| 1 | #ifndef __PSXEVENTS_H__ |
| 2 | #define __PSXEVENTS_H__ |
| 3 | |
| 4 | #include "psxcommon.h" |
| 5 | |
| 6 | enum { |
| 7 | PSXINT_SIO = 0, // sioInterrupt |
| 8 | PSXINT_CDR, // cdrInterrupt |
| 9 | PSXINT_CDREAD, // cdrPlayReadInterrupt |
| 10 | PSXINT_GPUDMA, // gpuInterrupt |
| 11 | PSXINT_MDECOUTDMA, // mdec1Interrupt |
| 12 | PSXINT_SPUDMA, // spuInterrupt |
| 13 | PSXINT_SPU_IRQ, // spuDelayedIrq |
| 14 | PSXINT_MDECINDMA, // mdec0Interrupt |
| 15 | PSXINT_GPUOTCDMA, // gpuotcInterrupt |
| 16 | PSXINT_CDRDMA, // cdrDmaInterrupt |
| 17 | PSXINT_NEWDRC_CHECK, // (none) |
| 18 | PSXINT_RCNT, // psxRcntUpdate |
| 19 | PSXINT_CDRLID, // cdrLidSeekInterrupt |
| 20 | PSXINT_IRQ10, // irq10Interrupt |
| 21 | PSXINT_SPU_UPDATE, // spuUpdate |
| 22 | PSXINT_COUNT |
| 23 | }; |
| 24 | |
| 25 | extern u32 event_cycles[PSXINT_COUNT]; |
| 26 | extern u32 next_interupt; |
| 27 | extern int stop; |
| 28 | |
| 29 | #define set_event_raw_abs(e, abs) { \ |
| 30 | u32 abs_ = abs; \ |
| 31 | s32 di_ = next_interupt - abs_; \ |
| 32 | event_cycles[e] = abs_; \ |
| 33 | if (di_ > 0) { \ |
| 34 | /*printf("%u: next_interupt %u -> %u\n", psxRegs.cycle, next_interupt, abs_);*/ \ |
| 35 | next_interupt = abs_; \ |
| 36 | } \ |
| 37 | } |
| 38 | |
| 39 | #define set_event(e, c) do { \ |
| 40 | psxRegs.interrupt |= (1 << (e)); \ |
| 41 | psxRegs.intCycle[e].cycle = c; \ |
| 42 | psxRegs.intCycle[e].sCycle = psxRegs.cycle; \ |
| 43 | set_event_raw_abs(e, psxRegs.cycle + (c)) \ |
| 44 | } while (0) |
| 45 | |
| 46 | union psxCP0Regs_; |
| 47 | u32 schedule_timeslice(void); |
| 48 | void irq_test(union psxCP0Regs_ *cp0); |
| 49 | void gen_interupt(union psxCP0Regs_ *cp0); |
| 50 | void events_restore(void); |
| 51 | |
| 52 | #endif // __PSXEVENTS_H__ |