| 1 | /*************************************************************************** |
| 2 | * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team * |
| 3 | * * |
| 4 | * This program is free software; you can redistribute it and/or modify * |
| 5 | * it under the terms of the GNU General Public License as published by * |
| 6 | * the Free Software Foundation; either version 2 of the License, or * |
| 7 | * (at your option) any later version. * |
| 8 | * * |
| 9 | * This program is distributed in the hope that it will be useful, * |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
| 12 | * GNU General Public License for more details. * |
| 13 | * * |
| 14 | * You should have received a copy of the GNU General Public License * |
| 15 | * along with this program; if not, write to the * |
| 16 | * Free Software Foundation, Inc., * |
| 17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * |
| 18 | ***************************************************************************/ |
| 19 | |
| 20 | /* |
| 21 | * Functions for PSX hardware control. |
| 22 | */ |
| 23 | |
| 24 | #include "psxhw.h" |
| 25 | #include "psxevents.h" |
| 26 | #include "mdec.h" |
| 27 | #include "cdrom.h" |
| 28 | #include "gpu.h" |
| 29 | |
| 30 | void psxHwReset() { |
| 31 | memset(psxH, 0, 0x10000); |
| 32 | |
| 33 | mdecInit(); // initialize mdec decoder |
| 34 | cdrReset(); |
| 35 | psxRcntInit(); |
| 36 | HW_GPU_STATUS = SWAP32(0x10802000); |
| 37 | } |
| 38 | |
| 39 | void psxHwWriteIstat(u32 value) |
| 40 | { |
| 41 | u32 stat = psxHu16(0x1070) & value; |
| 42 | psxHu16ref(0x1070) = SWAPu16(stat); |
| 43 | |
| 44 | psxRegs.CP0.n.Cause &= ~0x400; |
| 45 | if (stat & psxHu16(0x1074)) |
| 46 | psxRegs.CP0.n.Cause |= 0x400; |
| 47 | } |
| 48 | |
| 49 | void psxHwWriteImask(u32 value) |
| 50 | { |
| 51 | u32 stat = psxHu16(0x1070); |
| 52 | psxHu16ref(0x1074) = SWAPu16(value); |
| 53 | if (stat & value) { |
| 54 | //if ((psxRegs.CP0.n.SR & 0x401) == 0x401) |
| 55 | // log_unhandled("irq on unmask @%08x\n", psxRegs.pc); |
| 56 | set_event(PSXINT_NEWDRC_CHECK, 1); |
| 57 | } |
| 58 | psxRegs.CP0.n.Cause &= ~0x400; |
| 59 | if (stat & value) |
| 60 | psxRegs.CP0.n.Cause |= 0x400; |
| 61 | } |
| 62 | |
| 63 | #define make_dma_func(n) \ |
| 64 | void psxHwWriteChcr##n(u32 value) \ |
| 65 | { \ |
| 66 | if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \ |
| 67 | log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \ |
| 68 | HW_DMA##n##_CHCR = SWAPu32(value); \ |
| 69 | if (value & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8u << (n * 4))) \ |
| 70 | psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), value); \ |
| 71 | } |
| 72 | |
| 73 | make_dma_func(0) |
| 74 | make_dma_func(1) |
| 75 | make_dma_func(2) |
| 76 | make_dma_func(3) |
| 77 | make_dma_func(4) |
| 78 | make_dma_func(6) |
| 79 | |
| 80 | void psxHwWriteDmaIcr32(u32 value) |
| 81 | { |
| 82 | u32 tmp = value & 0x00ff803f; |
| 83 | tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000; |
| 84 | if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000) |
| 85 | || tmp & HW_DMA_ICR_BUS_ERROR) { |
| 86 | if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT)) |
| 87 | psxHu32ref(0x1070) |= SWAP32(8); |
| 88 | tmp |= HW_DMA_ICR_IRQ_SENT; |
| 89 | } |
| 90 | HW_DMA_ICR = SWAPu32(tmp); |
| 91 | } |
| 92 | |
| 93 | void psxHwWriteGpuSR(u32 value) |
| 94 | { |
| 95 | u32 old_sr = HW_GPU_STATUS, new_sr; |
| 96 | GPU_writeStatus(value); |
| 97 | gpuSyncPluginSR(); |
| 98 | new_sr = HW_GPU_STATUS; |
| 99 | // "The Next Tetris" seems to rely on the field order after enable |
| 100 | if ((old_sr ^ new_sr) & new_sr & SWAP32(PSXGPU_ILACE)) |
| 101 | frame_counter |= 1; |
| 102 | } |
| 103 | |
| 104 | u32 psxHwReadGpuSR(void) |
| 105 | { |
| 106 | u32 v, c = psxRegs.cycle; |
| 107 | |
| 108 | // meh2, syncing for img bit, might want to avoid it.. |
| 109 | gpuSyncPluginSR(); |
| 110 | v = SWAP32(HW_GPU_STATUS); |
| 111 | v |= ((s32)(psxRegs.gpuIdleAfter - c) >> 31) & PSXGPU_nBUSY; |
| 112 | |
| 113 | // XXX: because of large timeslices can't use hSyncCount, using rough |
| 114 | // approximization instead. Perhaps better use hcounter code here or something. |
| 115 | if (hSyncCount < 240 && (v & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS) |
| 116 | v |= PSXGPU_LCF & (c << 20); |
| 117 | return v; |
| 118 | } |
| 119 | |
| 120 | u8 psxHwRead8(u32 add) { |
| 121 | u8 hard; |
| 122 | |
| 123 | switch (add & 0xffff) { |
| 124 | case 0x1040: hard = sioRead8(); break; |
| 125 | case 0x1800: hard = cdrRead0(); break; |
| 126 | case 0x1801: hard = cdrRead1(); break; |
| 127 | case 0x1802: hard = cdrRead2(); break; |
| 128 | case 0x1803: hard = cdrRead3(); break; |
| 129 | |
| 130 | case 0x1041: case 0x1042: case 0x1043: |
| 131 | case 0x1044: case 0x1045: |
| 132 | case 0x1046: case 0x1047: |
| 133 | case 0x1048: case 0x1049: |
| 134 | case 0x104a: case 0x104b: |
| 135 | case 0x104c: case 0x104d: |
| 136 | case 0x104e: case 0x104f: |
| 137 | case 0x1050: case 0x1051: |
| 138 | case 0x1054: case 0x1055: |
| 139 | case 0x1058: case 0x1059: |
| 140 | case 0x105a: case 0x105b: |
| 141 | case 0x105c: case 0x105d: |
| 142 | case 0x1100: case 0x1101: |
| 143 | case 0x1104: case 0x1105: |
| 144 | case 0x1108: case 0x1109: |
| 145 | case 0x1110: case 0x1111: |
| 146 | case 0x1114: case 0x1115: |
| 147 | case 0x1118: case 0x1119: |
| 148 | case 0x1120: case 0x1121: |
| 149 | case 0x1124: case 0x1125: |
| 150 | case 0x1128: case 0x1129: |
| 151 | case 0x1810: case 0x1811: |
| 152 | case 0x1812: case 0x1813: |
| 153 | case 0x1814: case 0x1815: |
| 154 | case 0x1816: case 0x1817: |
| 155 | case 0x1820: case 0x1821: |
| 156 | case 0x1822: case 0x1823: |
| 157 | case 0x1824: case 0x1825: |
| 158 | case 0x1826: case 0x1827: |
| 159 | log_unhandled("unhandled r8 %08x @%08x\n", add, psxRegs.pc); |
| 160 | // falthrough |
| 161 | default: |
| 162 | if (0x1f801c00 <= add && add < 0x1f802000) { |
| 163 | u16 val = SPU_readRegister(add & ~1, psxRegs.cycle); |
| 164 | hard = (add & 1) ? val >> 8 : val; |
| 165 | break; |
| 166 | } |
| 167 | hard = psxHu8(add); |
| 168 | } |
| 169 | |
| 170 | //printf("r8 %08x %02x @%08x\n", add, hard, psxRegs.pc); |
| 171 | return hard; |
| 172 | } |
| 173 | |
| 174 | u16 psxHwRead16(u32 add) { |
| 175 | unsigned short hard; |
| 176 | |
| 177 | switch (add & 0xffff) { |
| 178 | case 0x1040: hard = sioRead8(); break; |
| 179 | case 0x1044: hard = sioReadStat16(); break; |
| 180 | case 0x1048: hard = sioReadMode16(); break; |
| 181 | case 0x104a: hard = sioReadCtrl16(); break; |
| 182 | case 0x104e: hard = sioReadBaud16(); break; |
| 183 | case 0x1054: hard = 0x80; break; // Armored Core Link cable misdetection |
| 184 | case 0x1100: hard = psxRcntRcount0(); break; |
| 185 | case 0x1104: hard = psxRcntRmode(0); break; |
| 186 | case 0x1108: hard = psxRcntRtarget(0); break; |
| 187 | case 0x1110: hard = psxRcntRcount1(); break; |
| 188 | case 0x1114: hard = psxRcntRmode(1); break; |
| 189 | case 0x1118: hard = psxRcntRtarget(1); break; |
| 190 | case 0x1120: hard = psxRcntRcount2(); break; |
| 191 | case 0x1124: hard = psxRcntRmode(2); break; |
| 192 | case 0x1128: hard = psxRcntRtarget(2); break; |
| 193 | |
| 194 | case 0x1042: |
| 195 | case 0x1046: |
| 196 | case 0x104c: |
| 197 | case 0x1050: |
| 198 | case 0x1058: |
| 199 | case 0x105a: |
| 200 | case 0x105c: |
| 201 | case 0x1800: |
| 202 | case 0x1802: |
| 203 | case 0x1810: |
| 204 | case 0x1812: |
| 205 | case 0x1814: |
| 206 | case 0x1816: |
| 207 | case 0x1820: |
| 208 | case 0x1822: |
| 209 | case 0x1824: |
| 210 | case 0x1826: |
| 211 | log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc); |
| 212 | // falthrough |
| 213 | default: |
| 214 | if (0x1f801c00 <= add && add < 0x1f802000) { |
| 215 | hard = SPU_readRegister(add, psxRegs.cycle); |
| 216 | break; |
| 217 | } |
| 218 | hard = psxHu16(add); |
| 219 | } |
| 220 | |
| 221 | //printf("r16 %08x %04x @%08x\n", add, hard, psxRegs.pc); |
| 222 | return hard; |
| 223 | } |
| 224 | |
| 225 | u32 psxHwRead32(u32 add) { |
| 226 | u32 hard; |
| 227 | |
| 228 | switch (add & 0xffff) { |
| 229 | case 0x1040: hard = sioRead8(); break; |
| 230 | case 0x1044: hard = sioReadStat16(); break; |
| 231 | case 0x1100: hard = psxRcntRcount0(); break; |
| 232 | case 0x1104: hard = psxRcntRmode(0); break; |
| 233 | case 0x1108: hard = psxRcntRtarget(0); break; |
| 234 | case 0x1110: hard = psxRcntRcount1(); break; |
| 235 | case 0x1114: hard = psxRcntRmode(1); break; |
| 236 | case 0x1118: hard = psxRcntRtarget(1); break; |
| 237 | case 0x1120: hard = psxRcntRcount2(); break; |
| 238 | case 0x1124: hard = psxRcntRmode(2); break; |
| 239 | case 0x1128: hard = psxRcntRtarget(2); break; |
| 240 | case 0x1810: hard = GPU_readData(); break; |
| 241 | case 0x1814: hard = psxHwReadGpuSR(); break; |
| 242 | case 0x1820: hard = mdecRead0(); break; |
| 243 | case 0x1824: hard = mdecRead1(); break; |
| 244 | |
| 245 | case 0x1048: |
| 246 | case 0x104c: |
| 247 | case 0x1050: |
| 248 | case 0x1054: |
| 249 | case 0x1058: |
| 250 | case 0x105c: |
| 251 | case 0x1800: |
| 252 | log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc); |
| 253 | // falthrough |
| 254 | default: |
| 255 | if (0x1f801c00 <= add && add < 0x1f802000) { |
| 256 | hard = SPU_readRegister(add, psxRegs.cycle); |
| 257 | hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16; |
| 258 | break; |
| 259 | } |
| 260 | hard = psxHu32(add); |
| 261 | } |
| 262 | //printf("r32 %08x %08x @%08x\n", add, hard, psxRegs.pc); |
| 263 | return hard; |
| 264 | } |
| 265 | |
| 266 | void psxHwWrite8(u32 add, u32 value) { |
| 267 | switch (add & 0xffff) { |
| 268 | case 0x1040: sioWrite8(value); return; |
| 269 | case 0x10f6: |
| 270 | // nocash documents it as forced w32, but still games use this? |
| 271 | break; |
| 272 | case 0x1800: cdrWrite0(value); return; |
| 273 | case 0x1801: cdrWrite1(value); return; |
| 274 | case 0x1802: cdrWrite2(value); return; |
| 275 | case 0x1803: cdrWrite3(value); return; |
| 276 | case 0x2041: break; // "POST (external 7 segment display)" |
| 277 | |
| 278 | default: |
| 279 | if (0x1f801c00 <= add && add < 0x1f802000) { |
| 280 | log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc); |
| 281 | if (!(add & 1)) |
| 282 | SPU_writeRegister(add, value, psxRegs.cycle); |
| 283 | return; |
| 284 | } |
| 285 | else |
| 286 | log_unhandled("unhandled w8 %08x %08x @%08x\n", |
| 287 | add, value, psxRegs.pc); |
| 288 | } |
| 289 | psxHu8(add) = value; |
| 290 | } |
| 291 | |
| 292 | void psxHwWrite16(u32 add, u32 value) { |
| 293 | switch (add & 0xffff) { |
| 294 | case 0x1040: sioWrite8(value); return; |
| 295 | case 0x1044: sioWriteStat16(value); return; |
| 296 | case 0x1048: sioWriteMode16(value); return; |
| 297 | case 0x104a: sioWriteCtrl16(value); return; |
| 298 | case 0x104e: sioWriteBaud16(value); return; |
| 299 | case 0x1070: psxHwWriteIstat(value); return; |
| 300 | case 0x1074: psxHwWriteImask(value); return; |
| 301 | case 0x1100: psxRcntWcount(0, value); return; |
| 302 | case 0x1104: psxRcntWmode(0, value); return; |
| 303 | case 0x1108: psxRcntWtarget(0, value); return; |
| 304 | case 0x1110: psxRcntWcount(1, value); return; |
| 305 | case 0x1114: psxRcntWmode(1, value); return; |
| 306 | case 0x1118: psxRcntWtarget(1, value); return; |
| 307 | case 0x1120: psxRcntWcount(2, value); return; |
| 308 | case 0x1124: psxRcntWmode(2, value); return; |
| 309 | case 0x1128: psxRcntWtarget(2, value); return; |
| 310 | |
| 311 | // forced write32: |
| 312 | case 0x1088: // DMA0 chcr (MDEC in DMA) |
| 313 | case 0x108c: psxHwWriteChcr0(value); return; |
| 314 | case 0x1098: // DMA1 chcr (MDEC out DMA) |
| 315 | case 0x109c: psxHwWriteChcr1(value); return; |
| 316 | case 0x10a8: // DMA2 chcr (GPU DMA) |
| 317 | case 0x10ac: psxHwWriteChcr2(value); return; |
| 318 | case 0x10b8: // DMA3 chcr (CDROM DMA) |
| 319 | case 0x10bc: psxHwWriteChcr3(value); return; |
| 320 | case 0x10c8: // DMA4 chcr (SPU DMA) |
| 321 | case 0x10cc: psxHwWriteChcr4(value); return; |
| 322 | case 0x10e8: // DMA6 chcr (OT clear) |
| 323 | case 0x10ec: psxHwWriteChcr6(value); return; |
| 324 | case 0x10f4: psxHwWriteDmaIcr32(value); return; |
| 325 | |
| 326 | // forced write32 with no immediate effect: |
| 327 | case 0x1014: |
| 328 | case 0x1060: |
| 329 | case 0x1080: |
| 330 | case 0x1090: |
| 331 | case 0x10a0: |
| 332 | case 0x10b0: |
| 333 | case 0x10c0: |
| 334 | case 0x10d0: |
| 335 | case 0x10e0: |
| 336 | case 0x10f0: |
| 337 | psxHu32ref(add) = SWAPu32(value); |
| 338 | return; |
| 339 | |
| 340 | case 0x1800: |
| 341 | case 0x1802: |
| 342 | case 0x1810: |
| 343 | case 0x1812: |
| 344 | case 0x1814: |
| 345 | case 0x1816: |
| 346 | case 0x1820: |
| 347 | case 0x1822: |
| 348 | case 0x1824: |
| 349 | case 0x1826: |
| 350 | log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc); |
| 351 | break; |
| 352 | |
| 353 | default: |
| 354 | if (0x1f801c00 <= add && add < 0x1f802000) { |
| 355 | SPU_writeRegister(add, value, psxRegs.cycle); |
| 356 | return; |
| 357 | } |
| 358 | else if (0x1f801000 <= add && add < 0x1f801800) |
| 359 | log_unhandled("unhandled w16 %08x %08x @%08x\n", |
| 360 | add, value, psxRegs.pc); |
| 361 | } |
| 362 | psxHu16ref(add) = SWAPu16(value); |
| 363 | } |
| 364 | |
| 365 | void psxHwWrite32(u32 add, u32 value) { |
| 366 | switch (add & 0xffff) { |
| 367 | case 0x1040: sioWrite8(value); return; |
| 368 | case 0x1070: psxHwWriteIstat(value); return; |
| 369 | case 0x1074: psxHwWriteImask(value); return; |
| 370 | case 0x1088: // DMA0 chcr (MDEC in DMA) |
| 371 | case 0x108c: psxHwWriteChcr0(value); return; |
| 372 | case 0x1098: // DMA1 chcr (MDEC out DMA) |
| 373 | case 0x109c: psxHwWriteChcr1(value); return; |
| 374 | case 0x10a8: // DMA2 chcr (GPU DMA) |
| 375 | case 0x10ac: psxHwWriteChcr2(value); return; |
| 376 | case 0x10b8: // DMA3 chcr (CDROM DMA) |
| 377 | case 0x10bc: psxHwWriteChcr3(value); return; |
| 378 | case 0x10c8: // DMA4 chcr (SPU DMA) |
| 379 | case 0x10cc: psxHwWriteChcr4(value); return; |
| 380 | case 0x10e8: // DMA6 chcr (OT clear) |
| 381 | case 0x10ec: psxHwWriteChcr6(value); return; |
| 382 | case 0x10f4: psxHwWriteDmaIcr32(value); return; |
| 383 | |
| 384 | case 0x1810: GPU_writeData(value); return; |
| 385 | case 0x1814: psxHwWriteGpuSR(value); return; |
| 386 | case 0x1820: mdecWrite0(value); break; |
| 387 | case 0x1824: mdecWrite1(value); break; |
| 388 | |
| 389 | case 0x1100: psxRcntWcount(0, value & 0xffff); return; |
| 390 | case 0x1104: psxRcntWmode(0, value); return; |
| 391 | case 0x1108: psxRcntWtarget(0, value & 0xffff); return; |
| 392 | case 0x1110: psxRcntWcount(1, value & 0xffff); return; |
| 393 | case 0x1114: psxRcntWmode(1, value); return; |
| 394 | case 0x1118: psxRcntWtarget(1, value & 0xffff); return; |
| 395 | case 0x1120: psxRcntWcount(2, value & 0xffff); return; |
| 396 | case 0x1124: psxRcntWmode(2, value); return; |
| 397 | case 0x1128: psxRcntWtarget(2, value & 0xffff); return; |
| 398 | |
| 399 | case 0x1044: |
| 400 | case 0x1048: |
| 401 | case 0x104c: |
| 402 | case 0x1050: |
| 403 | case 0x1054: |
| 404 | case 0x1058: |
| 405 | case 0x105c: |
| 406 | case 0x1800: |
| 407 | log_unhandled("unhandled w32 %08x %08x @%08x\n", add, value, psxRegs.pc); |
| 408 | break; |
| 409 | |
| 410 | default: |
| 411 | if (0x1f801c00 <= add && add < 0x1f802000) { |
| 412 | SPU_writeRegister(add, value&0xffff, psxRegs.cycle); |
| 413 | SPU_writeRegister(add + 2, value>>16, psxRegs.cycle); |
| 414 | return; |
| 415 | } |
| 416 | } |
| 417 | psxHu32ref(add) = SWAPu32(value); |
| 418 | } |
| 419 | |
| 420 | int psxHwFreeze(void *f, int Mode) { |
| 421 | return 0; |
| 422 | } |