| 1 | /*************************************************************************** |
| 2 | * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team * |
| 3 | * * |
| 4 | * This program is free software; you can redistribute it and/or modify * |
| 5 | * it under the terms of the GNU General Public License as published by * |
| 6 | * the Free Software Foundation; either version 2 of the License, or * |
| 7 | * (at your option) any later version. * |
| 8 | * * |
| 9 | * This program is distributed in the hope that it will be useful, * |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
| 12 | * GNU General Public License for more details. * |
| 13 | * * |
| 14 | * You should have received a copy of the GNU General Public License * |
| 15 | * along with this program; if not, write to the * |
| 16 | * Free Software Foundation, Inc., * |
| 17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * |
| 18 | ***************************************************************************/ |
| 19 | |
| 20 | /* |
| 21 | * PSX assembly interpreter. |
| 22 | */ |
| 23 | |
| 24 | #include "psxcommon.h" |
| 25 | #include "r3000a.h" |
| 26 | #include "gte.h" |
| 27 | #include "psxhle.h" |
| 28 | #include "psxinterpreter.h" |
| 29 | #include <stddef.h> |
| 30 | #include <assert.h> |
| 31 | //#include "debug.h" |
| 32 | #define ProcessDebug() |
| 33 | |
| 34 | static int branch = 0; |
| 35 | static int branch2 = 0; |
| 36 | static u32 branchPC; |
| 37 | |
| 38 | // These macros are used to assemble the repassembler functions |
| 39 | |
| 40 | #ifdef PSXCPU_LOG |
| 41 | #define debugI() PSXCPU_LOG("%s\n", disR3000AF(psxRegs.code, psxRegs.pc)); |
| 42 | #else |
| 43 | #define debugI() |
| 44 | #endif |
| 45 | |
| 46 | #ifdef __i386__ |
| 47 | #define INT_ATTR __attribute__((regparm(2))) |
| 48 | #else |
| 49 | #define INT_ATTR |
| 50 | #endif |
| 51 | #ifndef INVALID_PTR |
| 52 | #define INVALID_PTR NULL |
| 53 | #endif |
| 54 | |
| 55 | // Subsets |
| 56 | static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code); |
| 57 | static void (INT_ATTR *psxSPC[64])(psxRegisters *regs_, u32 code); |
| 58 | |
| 59 | static u32 INT_ATTR fetchNoCache(u8 **memRLUT, u32 pc) |
| 60 | { |
| 61 | u8 *base = memRLUT[pc >> 16]; |
| 62 | if (base == INVALID_PTR) |
| 63 | return 0; |
| 64 | u32 *code = (u32 *)(base + (pc & 0xfffc)); |
| 65 | return SWAP32(*code); |
| 66 | } |
| 67 | |
| 68 | /* |
| 69 | Formula One 2001 : |
| 70 | Use old CPU cache code when the RAM location is updated with new code (affects in-game racing) |
| 71 | */ |
| 72 | static struct cache_entry { |
| 73 | u32 tag; |
| 74 | u32 data[4]; |
| 75 | } ICache[256]; |
| 76 | |
| 77 | static u32 INT_ATTR fetchICache(u8 **memRLUT, u32 pc) |
| 78 | { |
| 79 | // cached? |
| 80 | if (pc < 0xa0000000) |
| 81 | { |
| 82 | // this is not how the hardware works but whatever |
| 83 | struct cache_entry *entry = &ICache[(pc & 0xff0) >> 4]; |
| 84 | |
| 85 | if (((entry->tag ^ pc) & 0xfffffff0) != 0 || pc < entry->tag) |
| 86 | { |
| 87 | const u8 *base = memRLUT[pc >> 16]; |
| 88 | const u32 *code; |
| 89 | if (base == INVALID_PTR) |
| 90 | return 0; |
| 91 | code = (u32 *)(base + (pc & 0xfff0)); |
| 92 | |
| 93 | entry->tag = pc; |
| 94 | // treat as 4 words, although other configurations are said to be possible |
| 95 | switch (pc & 0x0c) |
| 96 | { |
| 97 | case 0x00: entry->data[0] = SWAP32(code[0]); |
| 98 | case 0x04: entry->data[1] = SWAP32(code[1]); |
| 99 | case 0x08: entry->data[2] = SWAP32(code[2]); |
| 100 | case 0x0c: entry->data[3] = SWAP32(code[3]); |
| 101 | } |
| 102 | } |
| 103 | return entry->data[(pc & 0x0f) >> 2]; |
| 104 | } |
| 105 | |
| 106 | return fetchNoCache(memRLUT, pc); |
| 107 | } |
| 108 | |
| 109 | static u32 (INT_ATTR *fetch)(u8 **memRLUT, u32 pc) = fetchNoCache; |
| 110 | |
| 111 | // Make the timing events trigger faster as we are currently assuming everything |
| 112 | // takes one cycle, which is not the case on real hardware. |
| 113 | // FIXME: count cache misses, memory latencies, stalls to get rid of this |
| 114 | static inline void addCycle(void) |
| 115 | { |
| 116 | assert(psxRegs.subCycleStep >= 0x10000); |
| 117 | psxRegs.subCycle += psxRegs.subCycleStep; |
| 118 | psxRegs.cycle += psxRegs.subCycle >> 16; |
| 119 | psxRegs.subCycle &= 0xffff; |
| 120 | } |
| 121 | |
| 122 | static void delayRead(int reg, u32 bpc) { |
| 123 | u32 rold, rnew; |
| 124 | |
| 125 | // SysPrintf("delayRead at %x!\n", psxRegs.pc); |
| 126 | |
| 127 | rold = psxRegs.GPR.r[reg]; |
| 128 | psxBSC[psxRegs.code >> 26](&psxRegs, psxRegs.code); // branch delay load |
| 129 | rnew = psxRegs.GPR.r[reg]; |
| 130 | |
| 131 | psxRegs.pc = bpc; |
| 132 | |
| 133 | branch = 0; |
| 134 | |
| 135 | psxRegs.GPR.r[reg] = rold; |
| 136 | execI(); // first branch opcode |
| 137 | psxRegs.GPR.r[reg] = rnew; |
| 138 | |
| 139 | psxBranchTest(); |
| 140 | } |
| 141 | |
| 142 | static void delayWrite(int reg, u32 bpc) { |
| 143 | |
| 144 | /* SysPrintf("delayWrite at %x!\n", psxRegs.pc); |
| 145 | |
| 146 | SysPrintf("%s\n", disR3000AF(psxRegs.code, psxRegs.pc-4)); |
| 147 | SysPrintf("%s\n", disR3000AF(PSXMu32(bpc), bpc));*/ |
| 148 | |
| 149 | // no changes from normal behavior |
| 150 | |
| 151 | psxBSC[psxRegs.code >> 26](&psxRegs, psxRegs.code); |
| 152 | |
| 153 | branch = 0; |
| 154 | psxRegs.pc = bpc; |
| 155 | |
| 156 | psxBranchTest(); |
| 157 | } |
| 158 | |
| 159 | static void delayReadWrite(int reg, u32 bpc) { |
| 160 | |
| 161 | // SysPrintf("delayReadWrite at %x!\n", psxRegs.pc); |
| 162 | |
| 163 | // the branch delay load is skipped |
| 164 | |
| 165 | branch = 0; |
| 166 | psxRegs.pc = bpc; |
| 167 | |
| 168 | psxBranchTest(); |
| 169 | } |
| 170 | |
| 171 | /**** R3000A Instruction Macros ****/ |
| 172 | #define _PC_ regs_->pc // The next PC to be executed |
| 173 | |
| 174 | #define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register |
| 175 | #define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register |
| 176 | #define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register |
| 177 | #define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register |
| 178 | #define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register |
| 179 | #define _fSa_(code) ((code >> 6) & 0x1F) // The sa part of the instruction register |
| 180 | #define _fIm_(code) ((u16)code) // The immediate part of the instruction register |
| 181 | #define _fTarget_(code) (code & 0x03ffffff) // The target part of the instruction register |
| 182 | |
| 183 | #define _fImm_(code) ((s16)code) // sign-extended immediate |
| 184 | #define _fImmU_(code) (code&0xffff) // zero-extended immediate |
| 185 | |
| 186 | #define _Op_ _fOp_(code) |
| 187 | #define _Funct_ _fFunct_(code) |
| 188 | #define _Rd_ _fRd_(code) |
| 189 | #define _Rt_ _fRt_(code) |
| 190 | #define _Rs_ _fRs_(code) |
| 191 | #define _Sa_ _fSa_(code) |
| 192 | #define _Im_ _fIm_(code) |
| 193 | #define _Target_ _fTarget_(code) |
| 194 | |
| 195 | #define _Imm_ _fImm_(code) |
| 196 | #define _ImmU_ _fImmU_(code) |
| 197 | |
| 198 | #define _rRs_ regs_->GPR.r[_Rs_] // Rs register |
| 199 | #define _rRt_ regs_->GPR.r[_Rt_] // Rt register |
| 200 | #define _rRd_ regs_->GPR.r[_Rd_] // Rd register |
| 201 | #define _rSa_ regs_->GPR.r[_Sa_] // Sa register |
| 202 | #define _rFs_ regs_->CP0.r[_Rd_] // Fs register |
| 203 | |
| 204 | #define _rHi_ regs_->GPR.n.hi // The HI register |
| 205 | #define _rLo_ regs_->GPR.n.lo // The LO register |
| 206 | |
| 207 | #define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction |
| 208 | #define _BranchTarget_ ((s16)_Im_ * 4 + _PC_) // Calculates the target during a branch instruction |
| 209 | |
| 210 | #define _SetLink(x) regs_->GPR.r[x] = _PC_ + 4; // Sets the return address in the link register |
| 211 | |
| 212 | #define OP(name) \ |
| 213 | static inline INT_ATTR void name(psxRegisters *regs_, u32 code) |
| 214 | |
| 215 | // this defines shall be used with the tmp |
| 216 | // of the next func (instead of _Funct_...) |
| 217 | #define _tFunct_ ((tmp ) & 0x3F) // The funct part of the instruction register |
| 218 | #define _tRd_ ((tmp >> 11) & 0x1F) // The rd part of the instruction register |
| 219 | #define _tRt_ ((tmp >> 16) & 0x1F) // The rt part of the instruction register |
| 220 | #define _tRs_ ((tmp >> 21) & 0x1F) // The rs part of the instruction register |
| 221 | #define _tSa_ ((tmp >> 6) & 0x1F) // The sa part of the instruction register |
| 222 | |
| 223 | #define _i32(x) (s32)(x) |
| 224 | #define _u32(x) (u32)(x) |
| 225 | |
| 226 | static int psxTestLoadDelay(int reg, u32 tmp) { |
| 227 | if (tmp == 0) return 0; // NOP |
| 228 | switch (tmp >> 26) { |
| 229 | case 0x00: // SPECIAL |
| 230 | switch (_tFunct_) { |
| 231 | case 0x00: // SLL |
| 232 | case 0x02: case 0x03: // SRL/SRA |
| 233 | if (_tRd_ == reg && _tRt_ == reg) return 1; else |
| 234 | if (_tRt_ == reg) return 2; else |
| 235 | if (_tRd_ == reg) return 3; |
| 236 | break; |
| 237 | |
| 238 | case 0x08: // JR |
| 239 | if (_tRs_ == reg) return 2; |
| 240 | break; |
| 241 | case 0x09: // JALR |
| 242 | if (_tRd_ == reg && _tRs_ == reg) return 1; else |
| 243 | if (_tRs_ == reg) return 2; else |
| 244 | if (_tRd_ == reg) return 3; |
| 245 | break; |
| 246 | |
| 247 | // SYSCALL/BREAK just a break; |
| 248 | |
| 249 | case 0x20: case 0x21: case 0x22: case 0x23: |
| 250 | case 0x24: case 0x25: case 0x26: case 0x27: |
| 251 | case 0x2a: case 0x2b: // ADD/ADDU... |
| 252 | case 0x04: case 0x06: case 0x07: // SLLV... |
| 253 | if (_tRd_ == reg && (_tRt_ == reg || _tRs_ == reg)) return 1; else |
| 254 | if (_tRt_ == reg || _tRs_ == reg) return 2; else |
| 255 | if (_tRd_ == reg) return 3; |
| 256 | break; |
| 257 | |
| 258 | case 0x10: case 0x12: // MFHI/MFLO |
| 259 | if (_tRd_ == reg) return 3; |
| 260 | break; |
| 261 | case 0x11: case 0x13: // MTHI/MTLO |
| 262 | if (_tRs_ == reg) return 2; |
| 263 | break; |
| 264 | |
| 265 | case 0x18: case 0x19: |
| 266 | case 0x1a: case 0x1b: // MULT/DIV... |
| 267 | if (_tRt_ == reg || _tRs_ == reg) return 2; |
| 268 | break; |
| 269 | } |
| 270 | break; |
| 271 | |
| 272 | case 0x01: // REGIMM |
| 273 | switch (_tRt_) { |
| 274 | case 0x00: case 0x01: |
| 275 | case 0x10: case 0x11: // BLTZ/BGEZ... |
| 276 | // Xenogears - lbu v0 / beq v0 |
| 277 | // - no load delay (fixes battle loading) |
| 278 | break; |
| 279 | |
| 280 | if (_tRs_ == reg) return 2; |
| 281 | break; |
| 282 | } |
| 283 | break; |
| 284 | |
| 285 | // J would be just a break; |
| 286 | case 0x03: // JAL |
| 287 | if (31 == reg) return 3; |
| 288 | break; |
| 289 | |
| 290 | case 0x04: case 0x05: // BEQ/BNE |
| 291 | // Xenogears - lbu v0 / beq v0 |
| 292 | // - no load delay (fixes battle loading) |
| 293 | break; |
| 294 | |
| 295 | if (_tRs_ == reg || _tRt_ == reg) return 2; |
| 296 | break; |
| 297 | |
| 298 | case 0x06: case 0x07: // BLEZ/BGTZ |
| 299 | // Xenogears - lbu v0 / beq v0 |
| 300 | // - no load delay (fixes battle loading) |
| 301 | break; |
| 302 | |
| 303 | if (_tRs_ == reg) return 2; |
| 304 | break; |
| 305 | |
| 306 | case 0x08: case 0x09: case 0x0a: case 0x0b: |
| 307 | case 0x0c: case 0x0d: case 0x0e: // ADDI/ADDIU... |
| 308 | if (_tRt_ == reg && _tRs_ == reg) return 1; else |
| 309 | if (_tRs_ == reg) return 2; else |
| 310 | if (_tRt_ == reg) return 3; |
| 311 | break; |
| 312 | |
| 313 | case 0x0f: // LUI |
| 314 | if (_tRt_ == reg) return 3; |
| 315 | break; |
| 316 | |
| 317 | case 0x10: // COP0 |
| 318 | switch (_tFunct_) { |
| 319 | case 0x00: // MFC0 |
| 320 | if (_tRt_ == reg) return 3; |
| 321 | break; |
| 322 | case 0x02: // CFC0 |
| 323 | if (_tRt_ == reg) return 3; |
| 324 | break; |
| 325 | case 0x04: // MTC0 |
| 326 | if (_tRt_ == reg) return 2; |
| 327 | break; |
| 328 | case 0x06: // CTC0 |
| 329 | if (_tRt_ == reg) return 2; |
| 330 | break; |
| 331 | // RFE just a break; |
| 332 | } |
| 333 | break; |
| 334 | |
| 335 | case 0x12: // COP2 |
| 336 | switch (_tFunct_) { |
| 337 | case 0x00: |
| 338 | switch (_tRs_) { |
| 339 | case 0x00: // MFC2 |
| 340 | if (_tRt_ == reg) return 3; |
| 341 | break; |
| 342 | case 0x02: // CFC2 |
| 343 | if (_tRt_ == reg) return 3; |
| 344 | break; |
| 345 | case 0x04: // MTC2 |
| 346 | if (_tRt_ == reg) return 2; |
| 347 | break; |
| 348 | case 0x06: // CTC2 |
| 349 | if (_tRt_ == reg) return 2; |
| 350 | break; |
| 351 | } |
| 352 | break; |
| 353 | // RTPS... break; |
| 354 | } |
| 355 | break; |
| 356 | |
| 357 | case 0x22: case 0x26: // LWL/LWR |
| 358 | if (_tRt_ == reg) return 3; else |
| 359 | if (_tRs_ == reg) return 2; |
| 360 | break; |
| 361 | |
| 362 | case 0x20: case 0x21: case 0x23: |
| 363 | case 0x24: case 0x25: // LB/LH/LW/LBU/LHU |
| 364 | if (_tRt_ == reg && _tRs_ == reg) return 1; else |
| 365 | if (_tRs_ == reg) return 2; else |
| 366 | if (_tRt_ == reg) return 3; |
| 367 | break; |
| 368 | |
| 369 | case 0x28: case 0x29: case 0x2a: |
| 370 | case 0x2b: case 0x2e: // SB/SH/SWL/SW/SWR |
| 371 | if (_tRt_ == reg || _tRs_ == reg) return 2; |
| 372 | break; |
| 373 | |
| 374 | case 0x32: case 0x3a: // LWC2/SWC2 |
| 375 | if (_tRs_ == reg) return 2; |
| 376 | break; |
| 377 | } |
| 378 | |
| 379 | return 0; |
| 380 | } |
| 381 | |
| 382 | static void psxDelayTest(int reg, u32 bpc) { |
| 383 | u32 tmp = fetch(psxMemRLUT, bpc); |
| 384 | branch = 1; |
| 385 | |
| 386 | switch (psxTestLoadDelay(reg, tmp)) { |
| 387 | case 1: |
| 388 | delayReadWrite(reg, bpc); return; |
| 389 | case 2: |
| 390 | delayRead(reg, bpc); return; |
| 391 | case 3: |
| 392 | delayWrite(reg, bpc); return; |
| 393 | } |
| 394 | psxBSC[psxRegs.code >> 26](&psxRegs, psxRegs.code); |
| 395 | |
| 396 | branch = 0; |
| 397 | psxRegs.pc = bpc; |
| 398 | |
| 399 | psxBranchTest(); |
| 400 | } |
| 401 | |
| 402 | static u32 psxBranchNoDelay(psxRegisters *regs_) { |
| 403 | u32 temp, code; |
| 404 | |
| 405 | regs_->code = code = fetch(psxMemRLUT, regs_->pc); |
| 406 | switch (_Op_) { |
| 407 | case 0x00: // SPECIAL |
| 408 | switch (_Funct_) { |
| 409 | case 0x08: // JR |
| 410 | return _u32(_rRs_); |
| 411 | case 0x09: // JALR |
| 412 | temp = _u32(_rRs_); |
| 413 | if (_Rd_) { _SetLink(_Rd_); } |
| 414 | return temp; |
| 415 | } |
| 416 | break; |
| 417 | case 0x01: // REGIMM |
| 418 | switch (_Rt_) { |
| 419 | case 0x00: // BLTZ |
| 420 | if (_i32(_rRs_) < 0) |
| 421 | return _BranchTarget_; |
| 422 | break; |
| 423 | case 0x01: // BGEZ |
| 424 | if (_i32(_rRs_) >= 0) |
| 425 | return _BranchTarget_; |
| 426 | break; |
| 427 | case 0x08: // BLTZAL |
| 428 | if (_i32(_rRs_) < 0) { |
| 429 | _SetLink(31); |
| 430 | return _BranchTarget_; |
| 431 | } |
| 432 | break; |
| 433 | case 0x09: // BGEZAL |
| 434 | if (_i32(_rRs_) >= 0) { |
| 435 | _SetLink(31); |
| 436 | return _BranchTarget_; |
| 437 | } |
| 438 | break; |
| 439 | } |
| 440 | break; |
| 441 | case 0x02: // J |
| 442 | return _JumpTarget_; |
| 443 | case 0x03: // JAL |
| 444 | _SetLink(31); |
| 445 | return _JumpTarget_; |
| 446 | case 0x04: // BEQ |
| 447 | if (_i32(_rRs_) == _i32(_rRt_)) |
| 448 | return _BranchTarget_; |
| 449 | break; |
| 450 | case 0x05: // BNE |
| 451 | if (_i32(_rRs_) != _i32(_rRt_)) |
| 452 | return _BranchTarget_; |
| 453 | break; |
| 454 | case 0x06: // BLEZ |
| 455 | if (_i32(_rRs_) <= 0) |
| 456 | return _BranchTarget_; |
| 457 | break; |
| 458 | case 0x07: // BGTZ |
| 459 | if (_i32(_rRs_) > 0) |
| 460 | return _BranchTarget_; |
| 461 | break; |
| 462 | } |
| 463 | |
| 464 | return (u32)-1; |
| 465 | } |
| 466 | |
| 467 | static int psxDelayBranchExec(u32 tar) { |
| 468 | execI(); |
| 469 | |
| 470 | branch = 0; |
| 471 | psxRegs.pc = tar; |
| 472 | addCycle(); |
| 473 | psxBranchTest(); |
| 474 | return 1; |
| 475 | } |
| 476 | |
| 477 | static int psxDelayBranchTest(u32 tar1) { |
| 478 | u32 tar2, tmp1, tmp2; |
| 479 | |
| 480 | tar2 = psxBranchNoDelay(&psxRegs); |
| 481 | if (tar2 == (u32)-1) |
| 482 | return 0; |
| 483 | |
| 484 | debugI(); |
| 485 | |
| 486 | /* |
| 487 | * Branch in delay slot: |
| 488 | * - execute 1 instruction at tar1 |
| 489 | * - jump to tar2 (target of branch in delay slot; this branch |
| 490 | * has no normal delay slot, instruction at tar1 was fetched instead) |
| 491 | */ |
| 492 | psxRegs.pc = tar1; |
| 493 | tmp1 = psxBranchNoDelay(&psxRegs); |
| 494 | if (tmp1 == (u32)-1) { |
| 495 | return psxDelayBranchExec(tar2); |
| 496 | } |
| 497 | debugI(); |
| 498 | addCycle(); |
| 499 | |
| 500 | /* |
| 501 | * Got a branch at tar1: |
| 502 | * - execute 1 instruction at tar2 |
| 503 | * - jump to target of that branch (tmp1) |
| 504 | */ |
| 505 | psxRegs.pc = tar2; |
| 506 | tmp2 = psxBranchNoDelay(&psxRegs); |
| 507 | if (tmp2 == (u32)-1) { |
| 508 | return psxDelayBranchExec(tmp1); |
| 509 | } |
| 510 | debugI(); |
| 511 | addCycle(); |
| 512 | |
| 513 | /* |
| 514 | * Got a branch at tar2: |
| 515 | * - execute 1 instruction at tmp1 |
| 516 | * - jump to target of that branch (tmp2) |
| 517 | */ |
| 518 | psxRegs.pc = tmp1; |
| 519 | return psxDelayBranchExec(tmp2); |
| 520 | } |
| 521 | |
| 522 | static void doBranch(u32 tar) { |
| 523 | u32 tmp, code; |
| 524 | |
| 525 | branch2 = branch = 1; |
| 526 | branchPC = tar; |
| 527 | |
| 528 | // check for branch in delay slot |
| 529 | if (psxDelayBranchTest(tar)) |
| 530 | return; |
| 531 | |
| 532 | psxRegs.code = code = fetch(psxMemRLUT, psxRegs.pc); |
| 533 | |
| 534 | debugI(); |
| 535 | |
| 536 | psxRegs.pc += 4; |
| 537 | addCycle(); |
| 538 | |
| 539 | // check for load delay |
| 540 | tmp = psxRegs.code >> 26; |
| 541 | switch (tmp) { |
| 542 | case 0x10: // COP0 |
| 543 | switch (_Rs_) { |
| 544 | case 0x00: // MFC0 |
| 545 | case 0x02: // CFC0 |
| 546 | psxDelayTest(_Rt_, branchPC); |
| 547 | return; |
| 548 | } |
| 549 | break; |
| 550 | case 0x12: // COP2 |
| 551 | switch (_Funct_) { |
| 552 | case 0x00: |
| 553 | switch (_Rs_) { |
| 554 | case 0x00: // MFC2 |
| 555 | case 0x02: // CFC2 |
| 556 | psxDelayTest(_Rt_, branchPC); |
| 557 | return; |
| 558 | } |
| 559 | break; |
| 560 | } |
| 561 | break; |
| 562 | case 0x32: // LWC2 |
| 563 | psxDelayTest(_Rt_, branchPC); |
| 564 | return; |
| 565 | default: |
| 566 | if (tmp >= 0x20 && tmp <= 0x26) { // LB/LH/LWL/LW/LBU/LHU/LWR |
| 567 | psxDelayTest(_Rt_, branchPC); |
| 568 | return; |
| 569 | } |
| 570 | break; |
| 571 | } |
| 572 | |
| 573 | psxBSC[psxRegs.code >> 26](&psxRegs, psxRegs.code); |
| 574 | |
| 575 | branch = 0; |
| 576 | psxRegs.pc = branchPC; |
| 577 | |
| 578 | psxBranchTest(); |
| 579 | } |
| 580 | |
| 581 | /********************************************************* |
| 582 | * Arithmetic with immediate operand * |
| 583 | * Format: OP rt, rs, immediate * |
| 584 | *********************************************************/ |
| 585 | OP(psxADDI) { if (!_Rt_) return; _rRt_ = _u32(_rRs_) + _Imm_ ; } // Rt = Rs + Im (Exception on Integer Overflow) |
| 586 | OP(psxADDIU) { if (!_Rt_) return; _rRt_ = _u32(_rRs_) + _Imm_ ; } // Rt = Rs + Im |
| 587 | OP(psxANDI) { if (!_Rt_) return; _rRt_ = _u32(_rRs_) & _ImmU_; } // Rt = Rs And Im |
| 588 | OP(psxORI) { if (!_Rt_) return; _rRt_ = _u32(_rRs_) | _ImmU_; } // Rt = Rs Or Im |
| 589 | OP(psxXORI) { if (!_Rt_) return; _rRt_ = _u32(_rRs_) ^ _ImmU_; } // Rt = Rs Xor Im |
| 590 | OP(psxSLTI) { if (!_Rt_) return; _rRt_ = _i32(_rRs_) < _Imm_ ; } // Rt = Rs < Im (Signed) |
| 591 | OP(psxSLTIU) { if (!_Rt_) return; _rRt_ = _u32(_rRs_) < ((u32)_Imm_); } // Rt = Rs < Im (Unsigned) |
| 592 | |
| 593 | /********************************************************* |
| 594 | * Register arithmetic * |
| 595 | * Format: OP rd, rs, rt * |
| 596 | *********************************************************/ |
| 597 | OP(psxADD) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) + _u32(_rRt_); } // Rd = Rs + Rt (Exception on Integer Overflow) |
| 598 | OP(psxADDU) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) + _u32(_rRt_); } // Rd = Rs + Rt |
| 599 | OP(psxSUB) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) - _u32(_rRt_); } // Rd = Rs - Rt (Exception on Integer Overflow) |
| 600 | OP(psxSUBU) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) - _u32(_rRt_); } // Rd = Rs - Rt |
| 601 | OP(psxAND) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) & _u32(_rRt_); } // Rd = Rs And Rt |
| 602 | OP(psxOR) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) | _u32(_rRt_); } // Rd = Rs Or Rt |
| 603 | OP(psxXOR) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) ^ _u32(_rRt_); } // Rd = Rs Xor Rt |
| 604 | OP(psxNOR) { if (!_Rd_) return; _rRd_ =~(_u32(_rRs_) | _u32(_rRt_)); }// Rd = Rs Nor Rt |
| 605 | OP(psxSLT) { if (!_Rd_) return; _rRd_ = _i32(_rRs_) < _i32(_rRt_); } // Rd = Rs < Rt (Signed) |
| 606 | OP(psxSLTU) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) < _u32(_rRt_); } // Rd = Rs < Rt (Unsigned) |
| 607 | |
| 608 | /********************************************************* |
| 609 | * Register mult/div & Register trap logic * |
| 610 | * Format: OP rs, rt * |
| 611 | *********************************************************/ |
| 612 | OP(psxDIV) { |
| 613 | if (!_rRt_) { |
| 614 | _rHi_ = _rRs_; |
| 615 | if (_rRs_ & 0x80000000) { |
| 616 | _rLo_ = 1; |
| 617 | } else { |
| 618 | _rLo_ = 0xFFFFFFFF; |
| 619 | } |
| 620 | } |
| 621 | #if !defined(__arm__) && !defined(__aarch64__) |
| 622 | else if (_rRs_ == 0x80000000 && _rRt_ == 0xFFFFFFFF) { |
| 623 | _rLo_ = 0x80000000; |
| 624 | _rHi_ = 0; |
| 625 | } |
| 626 | #endif |
| 627 | else { |
| 628 | _rLo_ = _i32(_rRs_) / _i32(_rRt_); |
| 629 | _rHi_ = _i32(_rRs_) % _i32(_rRt_); |
| 630 | } |
| 631 | } |
| 632 | |
| 633 | OP(psxDIV_stall) { |
| 634 | regs_->muldivBusyCycle = regs_->cycle + 37; |
| 635 | psxDIV(regs_, code); |
| 636 | } |
| 637 | |
| 638 | OP(psxDIVU) { |
| 639 | if (_rRt_ != 0) { |
| 640 | _rLo_ = _rRs_ / _rRt_; |
| 641 | _rHi_ = _rRs_ % _rRt_; |
| 642 | } |
| 643 | else { |
| 644 | _rLo_ = 0xffffffff; |
| 645 | _rHi_ = _rRs_; |
| 646 | } |
| 647 | } |
| 648 | |
| 649 | OP(psxDIVU_stall) { |
| 650 | regs_->muldivBusyCycle = regs_->cycle + 37; |
| 651 | psxDIVU(regs_, code); |
| 652 | } |
| 653 | |
| 654 | OP(psxMULT) { |
| 655 | u64 res = (s64)_i32(_rRs_) * _i32(_rRt_); |
| 656 | |
| 657 | regs_->GPR.n.lo = (u32)res; |
| 658 | regs_->GPR.n.hi = (u32)(res >> 32); |
| 659 | } |
| 660 | |
| 661 | OP(psxMULT_stall) { |
| 662 | // approximate, but maybe good enough |
| 663 | u32 rs = _rRs_; |
| 664 | u32 lz = __builtin_clz(((rs ^ ((s32)rs >> 21)) | 1)); |
| 665 | u32 c = 7 + (2 - (lz / 11)) * 4; |
| 666 | regs_->muldivBusyCycle = regs_->cycle + c; |
| 667 | psxMULT(regs_, code); |
| 668 | } |
| 669 | |
| 670 | OP(psxMULTU) { |
| 671 | u64 res = (u64)_u32(_rRs_) * _u32(_rRt_); |
| 672 | |
| 673 | regs_->GPR.n.lo = (u32)(res & 0xffffffff); |
| 674 | regs_->GPR.n.hi = (u32)((res >> 32) & 0xffffffff); |
| 675 | } |
| 676 | |
| 677 | OP(psxMULTU_stall) { |
| 678 | // approximate, but maybe good enough |
| 679 | u32 lz = __builtin_clz(_rRs_ | 1); |
| 680 | u32 c = 7 + (2 - (lz / 11)) * 4; |
| 681 | regs_->muldivBusyCycle = regs_->cycle + c; |
| 682 | psxMULTU(regs_, code); |
| 683 | } |
| 684 | |
| 685 | /********************************************************* |
| 686 | * Register branch logic * |
| 687 | * Format: OP rs, offset * |
| 688 | *********************************************************/ |
| 689 | #define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_); |
| 690 | #define RepZBranchLinki32(op) { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } } |
| 691 | |
| 692 | OP(psxBGEZ) { RepZBranchi32(>=) } // Branch if Rs >= 0 |
| 693 | OP(psxBGEZAL) { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link |
| 694 | OP(psxBGTZ) { RepZBranchi32(>) } // Branch if Rs > 0 |
| 695 | OP(psxBLEZ) { RepZBranchi32(<=) } // Branch if Rs <= 0 |
| 696 | OP(psxBLTZ) { RepZBranchi32(<) } // Branch if Rs < 0 |
| 697 | OP(psxBLTZAL) { RepZBranchLinki32(<) } // Branch if Rs < 0 and link |
| 698 | |
| 699 | /********************************************************* |
| 700 | * Shift arithmetic with constant shift * |
| 701 | * Format: OP rd, rt, sa * |
| 702 | *********************************************************/ |
| 703 | OP(psxSLL) { if (!_Rd_) return; _rRd_ = _u32(_rRt_) << _Sa_; } // Rd = Rt << sa |
| 704 | OP(psxSRA) { if (!_Rd_) return; _rRd_ = _i32(_rRt_) >> _Sa_; } // Rd = Rt >> sa (arithmetic) |
| 705 | OP(psxSRL) { if (!_Rd_) return; _rRd_ = _u32(_rRt_) >> _Sa_; } // Rd = Rt >> sa (logical) |
| 706 | |
| 707 | /********************************************************* |
| 708 | * Shift arithmetic with variant register shift * |
| 709 | * Format: OP rd, rt, rs * |
| 710 | *********************************************************/ |
| 711 | OP(psxSLLV) { if (!_Rd_) return; _rRd_ = _u32(_rRt_) << (_u32(_rRs_) & 0x1F); } // Rd = Rt << rs |
| 712 | OP(psxSRAV) { if (!_Rd_) return; _rRd_ = _i32(_rRt_) >> (_u32(_rRs_) & 0x1F); } // Rd = Rt >> rs (arithmetic) |
| 713 | OP(psxSRLV) { if (!_Rd_) return; _rRd_ = _u32(_rRt_) >> (_u32(_rRs_) & 0x1F); } // Rd = Rt >> rs (logical) |
| 714 | |
| 715 | /********************************************************* |
| 716 | * Load higher 16 bits of the first word in GPR with imm * |
| 717 | * Format: OP rt, immediate * |
| 718 | *********************************************************/ |
| 719 | OP(psxLUI) { if (!_Rt_) return; _rRt_ = code << 16; } // Upper halfword of Rt = Im |
| 720 | |
| 721 | /********************************************************* |
| 722 | * Move from HI/LO to GPR * |
| 723 | * Format: OP rd * |
| 724 | *********************************************************/ |
| 725 | OP(psxMFHI) { if (!_Rd_) return; _rRd_ = _rHi_; } // Rd = Hi |
| 726 | OP(psxMFLO) { if (!_Rd_) return; _rRd_ = _rLo_; } // Rd = Lo |
| 727 | |
| 728 | static void mflohiCheckStall(psxRegisters *regs_) |
| 729 | { |
| 730 | u32 left = regs_->muldivBusyCycle - regs_->cycle; |
| 731 | if (left <= 37) { |
| 732 | //printf("muldiv stall %u\n", left); |
| 733 | regs_->cycle = regs_->muldivBusyCycle; |
| 734 | } |
| 735 | } |
| 736 | |
| 737 | OP(psxMFHI_stall) { mflohiCheckStall(regs_); psxMFHI(regs_, code); } |
| 738 | OP(psxMFLO_stall) { mflohiCheckStall(regs_); psxMFLO(regs_, code); } |
| 739 | |
| 740 | /********************************************************* |
| 741 | * Move to GPR to HI/LO & Register jump * |
| 742 | * Format: OP rs * |
| 743 | *********************************************************/ |
| 744 | OP(psxMTHI) { _rHi_ = _rRs_; } // Hi = Rs |
| 745 | OP(psxMTLO) { _rLo_ = _rRs_; } // Lo = Rs |
| 746 | |
| 747 | /********************************************************* |
| 748 | * Special purpose instructions * |
| 749 | * Format: OP * |
| 750 | *********************************************************/ |
| 751 | OP(psxBREAK) { |
| 752 | regs_->pc -= 4; |
| 753 | psxException(0x24, branch, ®s_->CP0); |
| 754 | } |
| 755 | |
| 756 | OP(psxSYSCALL) { |
| 757 | regs_->pc -= 4; |
| 758 | psxException(0x20, branch, ®s_->CP0); |
| 759 | } |
| 760 | |
| 761 | static inline void psxTestSWInts(psxRegisters *regs_) { |
| 762 | if (regs_->CP0.n.Cause & regs_->CP0.n.Status & 0x0300 && |
| 763 | regs_->CP0.n.Status & 0x1) { |
| 764 | regs_->CP0.n.Cause &= ~0x7c; |
| 765 | psxException(regs_->CP0.n.Cause, branch, ®s_->CP0); |
| 766 | } |
| 767 | } |
| 768 | |
| 769 | OP(psxRFE) { |
| 770 | // SysPrintf("psxRFE\n"); |
| 771 | regs_->CP0.n.Status = (regs_->CP0.n.Status & 0xfffffff0) | |
| 772 | ((regs_->CP0.n.Status & 0x3c) >> 2); |
| 773 | psxTestSWInts(regs_); |
| 774 | } |
| 775 | |
| 776 | /********************************************************* |
| 777 | * Register branch logic * |
| 778 | * Format: OP rs, rt, offset * |
| 779 | *********************************************************/ |
| 780 | #define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) doBranch(_BranchTarget_); |
| 781 | |
| 782 | OP(psxBEQ) { RepBranchi32(==) } // Branch if Rs == Rt |
| 783 | OP(psxBNE) { RepBranchi32(!=) } // Branch if Rs != Rt |
| 784 | |
| 785 | /********************************************************* |
| 786 | * Jump to target * |
| 787 | * Format: OP target * |
| 788 | *********************************************************/ |
| 789 | OP(psxJ) { doBranch(_JumpTarget_); } |
| 790 | OP(psxJAL) { _SetLink(31); doBranch(_JumpTarget_); } |
| 791 | |
| 792 | /********************************************************* |
| 793 | * Register jump * |
| 794 | * Format: OP rs, rd * |
| 795 | *********************************************************/ |
| 796 | OP(psxJR) { |
| 797 | doBranch(_rRs_ & ~3); |
| 798 | psxJumpTest(); |
| 799 | } |
| 800 | |
| 801 | OP(psxJALR) { |
| 802 | u32 temp = _u32(_rRs_); |
| 803 | if (_Rd_) { _SetLink(_Rd_); } |
| 804 | doBranch(temp & ~3); |
| 805 | } |
| 806 | |
| 807 | /********************************************************* |
| 808 | * Load and store for GPR * |
| 809 | * Format: OP rt, offset(base) * |
| 810 | *********************************************************/ |
| 811 | |
| 812 | #define _oB_ (regs_->GPR.r[_Rs_] + _Imm_) |
| 813 | |
| 814 | OP(psxLB) { u32 v = (s8)psxMemRead8(_oB_); if (_Rt_) _rRt_ = v; } |
| 815 | OP(psxLBU) { u32 v = psxMemRead8(_oB_); if (_Rt_) _rRt_ = v; } |
| 816 | OP(psxLH) { u32 v = (s16)psxMemRead16(_oB_); if (_Rt_) _rRt_ = v; } |
| 817 | OP(psxLHU) { u32 v = psxMemRead16(_oB_); if (_Rt_) _rRt_ = v; } |
| 818 | OP(psxLW) { u32 v = psxMemRead32(_oB_); if (_Rt_) _rRt_ = v; } |
| 819 | |
| 820 | OP(psxLWL) { |
| 821 | static const u32 LWL_MASK[4] = { 0xffffff, 0xffff, 0xff, 0 }; |
| 822 | static const u32 LWL_SHIFT[4] = { 24, 16, 8, 0 }; |
| 823 | u32 addr = _oB_; |
| 824 | u32 shift = addr & 3; |
| 825 | u32 mem = psxMemRead32(addr & ~3); |
| 826 | |
| 827 | if (!_Rt_) return; |
| 828 | _rRt_ = (_u32(_rRt_) & LWL_MASK[shift]) | (mem << LWL_SHIFT[shift]); |
| 829 | |
| 830 | /* |
| 831 | Mem = 1234. Reg = abcd |
| 832 | |
| 833 | 0 4bcd (mem << 24) | (reg & 0x00ffffff) |
| 834 | 1 34cd (mem << 16) | (reg & 0x0000ffff) |
| 835 | 2 234d (mem << 8) | (reg & 0x000000ff) |
| 836 | 3 1234 (mem ) | (reg & 0x00000000) |
| 837 | */ |
| 838 | } |
| 839 | |
| 840 | OP(psxLWR) { |
| 841 | static const u32 LWR_MASK[4] = { 0, 0xff000000, 0xffff0000, 0xffffff00 }; |
| 842 | static const u32 LWR_SHIFT[4] = { 0, 8, 16, 24 }; |
| 843 | u32 addr = _oB_; |
| 844 | u32 shift = addr & 3; |
| 845 | u32 mem = psxMemRead32(addr & ~3); |
| 846 | |
| 847 | if (!_Rt_) return; |
| 848 | _rRt_ = (_u32(_rRt_) & LWR_MASK[shift]) | (mem >> LWR_SHIFT[shift]); |
| 849 | |
| 850 | /* |
| 851 | Mem = 1234. Reg = abcd |
| 852 | |
| 853 | 0 1234 (mem ) | (reg & 0x00000000) |
| 854 | 1 a123 (mem >> 8) | (reg & 0xff000000) |
| 855 | 2 ab12 (mem >> 16) | (reg & 0xffff0000) |
| 856 | 3 abc1 (mem >> 24) | (reg & 0xffffff00) |
| 857 | */ |
| 858 | } |
| 859 | |
| 860 | OP(psxSB) { psxMemWrite8 (_oB_, _rRt_ & 0xff); } |
| 861 | OP(psxSH) { psxMemWrite16(_oB_, _rRt_ & 0xffff); } |
| 862 | OP(psxSW) { psxMemWrite32(_oB_, _rRt_); } |
| 863 | |
| 864 | OP(psxSWL) { |
| 865 | static const u32 SWL_MASK[4] = { 0xffffff00, 0xffff0000, 0xff000000, 0 }; |
| 866 | static const u32 SWL_SHIFT[4] = { 24, 16, 8, 0 }; |
| 867 | u32 addr = _oB_; |
| 868 | u32 shift = addr & 3; |
| 869 | u32 mem = psxMemRead32(addr & ~3); |
| 870 | |
| 871 | psxMemWrite32(addr & ~3, (_u32(_rRt_) >> SWL_SHIFT[shift]) | |
| 872 | ( mem & SWL_MASK[shift]) ); |
| 873 | /* |
| 874 | Mem = 1234. Reg = abcd |
| 875 | |
| 876 | 0 123a (reg >> 24) | (mem & 0xffffff00) |
| 877 | 1 12ab (reg >> 16) | (mem & 0xffff0000) |
| 878 | 2 1abc (reg >> 8) | (mem & 0xff000000) |
| 879 | 3 abcd (reg ) | (mem & 0x00000000) |
| 880 | */ |
| 881 | } |
| 882 | |
| 883 | OP(psxSWR) { |
| 884 | static const u32 SWR_MASK[4] = { 0, 0xff, 0xffff, 0xffffff }; |
| 885 | static const u32 SWR_SHIFT[4] = { 0, 8, 16, 24 }; |
| 886 | u32 addr = _oB_; |
| 887 | u32 shift = addr & 3; |
| 888 | u32 mem = psxMemRead32(addr & ~3); |
| 889 | |
| 890 | psxMemWrite32(addr & ~3, (_u32(_rRt_) << SWR_SHIFT[shift]) | |
| 891 | ( mem & SWR_MASK[shift]) ); |
| 892 | |
| 893 | /* |
| 894 | Mem = 1234. Reg = abcd |
| 895 | |
| 896 | 0 abcd (reg ) | (mem & 0x00000000) |
| 897 | 1 bcd4 (reg << 8) | (mem & 0x000000ff) |
| 898 | 2 cd34 (reg << 16) | (mem & 0x0000ffff) |
| 899 | 3 d234 (reg << 24) | (mem & 0x00ffffff) |
| 900 | */ |
| 901 | } |
| 902 | |
| 903 | /********************************************************* |
| 904 | * Moves between GPR and COPx * |
| 905 | * Format: OP rt, fs * |
| 906 | *********************************************************/ |
| 907 | OP(psxMFC0) { if (!_Rt_) return; _rRt_ = _rFs_; } |
| 908 | OP(psxCFC0) { if (!_Rt_) return; _rRt_ = _rFs_; } |
| 909 | |
| 910 | void MTC0(psxRegisters *regs_, int reg, u32 val) { |
| 911 | // SysPrintf("MTC0 %d: %x\n", reg, val); |
| 912 | switch (reg) { |
| 913 | case 12: // Status |
| 914 | if ((regs_->CP0.n.Status ^ val) & (1 << 16)) |
| 915 | psxMemOnIsolate((val >> 16) & 1); |
| 916 | regs_->CP0.n.Status = val; |
| 917 | psxTestSWInts(regs_); |
| 918 | break; |
| 919 | |
| 920 | case 13: // Cause |
| 921 | regs_->CP0.n.Cause &= ~0x0300; |
| 922 | regs_->CP0.n.Cause |= val & 0x0300; |
| 923 | psxTestSWInts(regs_); |
| 924 | break; |
| 925 | |
| 926 | default: |
| 927 | regs_->CP0.r[reg] = val; |
| 928 | break; |
| 929 | } |
| 930 | } |
| 931 | |
| 932 | OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); } |
| 933 | OP(psxCTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); } |
| 934 | |
| 935 | /********************************************************* |
| 936 | * Unknow instruction (would generate an exception) * |
| 937 | * Format: ? * |
| 938 | *********************************************************/ |
| 939 | static inline void psxNULL_(void) { |
| 940 | #ifdef PSXCPU_LOG |
| 941 | PSXCPU_LOG("psx: Unimplemented op %x\n", psxRegs.code); |
| 942 | #endif |
| 943 | } |
| 944 | |
| 945 | OP(psxNULL) { psxNULL_(); } |
| 946 | void gteNULL(struct psxCP2Regs *regs) { psxNULL_(); } |
| 947 | |
| 948 | OP(psxSPECIAL) { |
| 949 | psxSPC[_Funct_](regs_, code); |
| 950 | } |
| 951 | |
| 952 | OP(psxCOP0) { |
| 953 | switch (_Rs_) { |
| 954 | case 0x00: psxMFC0(regs_, code); break; |
| 955 | case 0x02: psxCFC0(regs_, code); break; |
| 956 | case 0x04: psxMTC0(regs_, code); break; |
| 957 | case 0x06: psxCTC0(regs_, code); break; |
| 958 | case 0x10: psxRFE(regs_, code); break; |
| 959 | default: psxNULL_(); break; |
| 960 | } |
| 961 | } |
| 962 | |
| 963 | OP(psxCOP2) { |
| 964 | psxCP2[_Funct_](®s_->CP2); |
| 965 | } |
| 966 | |
| 967 | OP(psxCOP2_stall) { |
| 968 | u32 f = _Funct_; |
| 969 | gteCheckStall(f); |
| 970 | psxCP2[f](®s_->CP2); |
| 971 | } |
| 972 | |
| 973 | OP(gteMFC2) { |
| 974 | if (!_Rt_) return; |
| 975 | regs_->GPR.r[_Rt_] = MFC2(®s_->CP2, _Rd_); |
| 976 | } |
| 977 | |
| 978 | OP(gteCFC2) { |
| 979 | if (!_Rt_) return; |
| 980 | regs_->GPR.r[_Rt_] = regs_->CP2C.r[_Rd_]; |
| 981 | } |
| 982 | |
| 983 | OP(gteMTC2) { |
| 984 | MTC2(®s_->CP2, regs_->GPR.r[_Rt_], _Rd_); |
| 985 | } |
| 986 | |
| 987 | OP(gteCTC2) { |
| 988 | CTC2(®s_->CP2, regs_->GPR.r[_Rt_], _Rd_); |
| 989 | } |
| 990 | |
| 991 | OP(gteLWC2) { |
| 992 | MTC2(®s_->CP2, psxMemRead32(_oB_), _Rt_); |
| 993 | } |
| 994 | |
| 995 | OP(gteSWC2) { |
| 996 | psxMemWrite32(_oB_, MFC2(®s_->CP2, _Rt_)); |
| 997 | } |
| 998 | |
| 999 | OP(gteLWC2_stall) { |
| 1000 | gteCheckStall(0); |
| 1001 | gteLWC2(regs_, code); |
| 1002 | } |
| 1003 | |
| 1004 | OP(gteSWC2_stall) { |
| 1005 | gteCheckStall(0); |
| 1006 | gteSWC2(regs_, code); |
| 1007 | } |
| 1008 | |
| 1009 | static void psxBASIC(struct psxCP2Regs *cp2regs) { |
| 1010 | psxRegisters *regs_ = (void *)((char *)cp2regs - offsetof(psxRegisters, CP2)); |
| 1011 | u32 code = regs_->code; |
| 1012 | assert(regs_ == &psxRegs); |
| 1013 | switch (_Rs_) { |
| 1014 | case 0x00: gteMFC2(regs_, code); break; |
| 1015 | case 0x02: gteCFC2(regs_, code); break; |
| 1016 | case 0x04: gteMTC2(regs_, code); break; |
| 1017 | case 0x06: gteCTC2(regs_, code); break; |
| 1018 | default: psxNULL_(); break; |
| 1019 | } |
| 1020 | } |
| 1021 | |
| 1022 | OP(psxREGIMM) { |
| 1023 | switch (_Rt_) { |
| 1024 | case 0x00: psxBLTZ(regs_, code); break; |
| 1025 | case 0x01: psxBGEZ(regs_, code); break; |
| 1026 | case 0x10: psxBLTZAL(regs_, code); break; |
| 1027 | case 0x11: psxBGEZAL(regs_, code); break; |
| 1028 | default: psxNULL_(); break; |
| 1029 | } |
| 1030 | } |
| 1031 | |
| 1032 | OP(psxHLE) { |
| 1033 | uint32_t hleCode = code & 0x03ffffff; |
| 1034 | if (hleCode >= (sizeof(psxHLEt) / sizeof(psxHLEt[0]))) { |
| 1035 | psxNULL_(); |
| 1036 | } else { |
| 1037 | psxHLEt[hleCode](); |
| 1038 | } |
| 1039 | } |
| 1040 | |
| 1041 | static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code) = { |
| 1042 | psxSPECIAL, psxREGIMM, psxJ , psxJAL , psxBEQ , psxBNE , psxBLEZ, psxBGTZ, |
| 1043 | psxADDI , psxADDIU , psxSLTI, psxSLTIU, psxANDI, psxORI , psxXORI, psxLUI , |
| 1044 | psxCOP0 , psxNULL , psxCOP2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, |
| 1045 | psxNULL , psxNULL , psxNULL, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, |
| 1046 | psxLB , psxLH , psxLWL , psxLW , psxLBU , psxLHU , psxLWR , psxNULL, |
| 1047 | psxSB , psxSH , psxSWL , psxSW , psxNULL, psxNULL, psxSWR , psxNULL, |
| 1048 | psxNULL , psxNULL , gteLWC2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, |
| 1049 | psxNULL , psxNULL , gteSWC2, psxHLE , psxNULL, psxNULL, psxNULL, psxNULL |
| 1050 | }; |
| 1051 | |
| 1052 | static void (INT_ATTR *psxSPC[64])(psxRegisters *regs_, u32 code) = { |
| 1053 | psxSLL , psxNULL , psxSRL , psxSRA , psxSLLV , psxNULL , psxSRLV, psxSRAV, |
| 1054 | psxJR , psxJALR , psxNULL, psxNULL, psxSYSCALL, psxBREAK, psxNULL, psxNULL, |
| 1055 | psxMFHI, psxMTHI , psxMFLO, psxMTLO, psxNULL , psxNULL , psxNULL, psxNULL, |
| 1056 | psxMULT, psxMULTU, psxDIV , psxDIVU, psxNULL , psxNULL , psxNULL, psxNULL, |
| 1057 | psxADD , psxADDU , psxSUB , psxSUBU, psxAND , psxOR , psxXOR , psxNOR , |
| 1058 | psxNULL, psxNULL , psxSLT , psxSLTU, psxNULL , psxNULL , psxNULL, psxNULL, |
| 1059 | psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL, |
| 1060 | psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL |
| 1061 | }; |
| 1062 | |
| 1063 | void (*psxCP2[64])(struct psxCP2Regs *regs) = { |
| 1064 | psxBASIC, gteRTPS , gteNULL , gteNULL, gteNULL, gteNULL , gteNCLIP, gteNULL, // 00 |
| 1065 | gteNULL , gteNULL , gteNULL , gteNULL, gteOP , gteNULL , gteNULL , gteNULL, // 08 |
| 1066 | gteDPCS , gteINTPL, gteMVMVA, gteNCDS, gteCDP , gteNULL , gteNCDT , gteNULL, // 10 |
| 1067 | gteNULL , gteNULL , gteNULL , gteNCCS, gteCC , gteNULL , gteNCS , gteNULL, // 18 |
| 1068 | gteNCT , gteNULL , gteNULL , gteNULL, gteNULL, gteNULL , gteNULL , gteNULL, // 20 |
| 1069 | gteSQR , gteDCPL , gteDPCT , gteNULL, gteNULL, gteAVSZ3, gteAVSZ4, gteNULL, // 28 |
| 1070 | gteRTPT , gteNULL , gteNULL , gteNULL, gteNULL, gteNULL , gteNULL , gteNULL, // 30 |
| 1071 | gteNULL , gteNULL , gteNULL , gteNULL, gteNULL, gteGPF , gteGPL , gteNCCT // 38 |
| 1072 | }; |
| 1073 | |
| 1074 | /////////////////////////////////////////// |
| 1075 | |
| 1076 | static int intInit() { |
| 1077 | return 0; |
| 1078 | } |
| 1079 | |
| 1080 | static void intReset() { |
| 1081 | } |
| 1082 | |
| 1083 | static inline void execI_(u8 **memRLUT, psxRegisters *regs_) { |
| 1084 | regs_->code = fetch(memRLUT, regs_->pc); |
| 1085 | |
| 1086 | debugI(); |
| 1087 | |
| 1088 | if (Config.Debug) ProcessDebug(); |
| 1089 | |
| 1090 | regs_->pc += 4; |
| 1091 | addCycle(); |
| 1092 | |
| 1093 | psxBSC[regs_->code >> 26](regs_, regs_->code); |
| 1094 | } |
| 1095 | |
| 1096 | static void intExecute() { |
| 1097 | psxRegisters *regs_ = &psxRegs; |
| 1098 | u8 **memRLUT = psxMemRLUT; |
| 1099 | extern int stop; |
| 1100 | |
| 1101 | while (!stop) |
| 1102 | execI_(memRLUT, regs_); |
| 1103 | } |
| 1104 | |
| 1105 | void intExecuteBlock() { |
| 1106 | psxRegisters *regs_ = &psxRegs; |
| 1107 | u8 **memRLUT = psxMemRLUT; |
| 1108 | |
| 1109 | branch2 = 0; |
| 1110 | while (!branch2) |
| 1111 | execI_(memRLUT, regs_); |
| 1112 | } |
| 1113 | |
| 1114 | static void intClear(u32 Addr, u32 Size) { |
| 1115 | } |
| 1116 | |
| 1117 | static void intNotify(enum R3000Anote note, void *data) { |
| 1118 | switch (note) { |
| 1119 | case R3000ACPU_NOTIFY_CACHE_ISOLATED: // Armored Core? |
| 1120 | case R3000ACPU_NOTIFY_AFTER_LOAD: |
| 1121 | memset(&ICache, 0xff, sizeof(ICache)); |
| 1122 | break; |
| 1123 | case R3000ACPU_NOTIFY_CACHE_UNISOLATED: |
| 1124 | case R3000ACPU_NOTIFY_BEFORE_SAVE: |
| 1125 | break; |
| 1126 | } |
| 1127 | } |
| 1128 | |
| 1129 | void intApplyConfig() { |
| 1130 | int cycle_mult; |
| 1131 | |
| 1132 | assert(psxBSC[18] == psxCOP2 || psxBSC[18] == psxCOP2_stall); |
| 1133 | assert(psxBSC[50] == gteLWC2 || psxBSC[50] == gteLWC2_stall); |
| 1134 | assert(psxBSC[58] == gteSWC2 || psxBSC[58] == gteSWC2_stall); |
| 1135 | assert(psxSPC[16] == psxMFHI || psxSPC[16] == psxMFHI_stall); |
| 1136 | assert(psxSPC[18] == psxMFLO || psxSPC[18] == psxMFLO_stall); |
| 1137 | assert(psxSPC[24] == psxMULT || psxSPC[24] == psxMULT_stall); |
| 1138 | assert(psxSPC[25] == psxMULTU || psxSPC[25] == psxMULTU_stall); |
| 1139 | assert(psxSPC[26] == psxDIV || psxSPC[26] == psxDIV_stall); |
| 1140 | assert(psxSPC[27] == psxDIVU || psxSPC[27] == psxDIVU_stall); |
| 1141 | |
| 1142 | if (Config.DisableStalls) { |
| 1143 | psxBSC[18] = psxCOP2; |
| 1144 | psxBSC[50] = gteLWC2; |
| 1145 | psxBSC[58] = gteSWC2; |
| 1146 | psxSPC[16] = psxMFHI; |
| 1147 | psxSPC[18] = psxMFLO; |
| 1148 | psxSPC[24] = psxMULT; |
| 1149 | psxSPC[25] = psxMULTU; |
| 1150 | psxSPC[26] = psxDIV; |
| 1151 | psxSPC[27] = psxDIVU; |
| 1152 | } else { |
| 1153 | psxBSC[18] = psxCOP2_stall; |
| 1154 | psxBSC[50] = gteLWC2_stall; |
| 1155 | psxBSC[58] = gteSWC2_stall; |
| 1156 | psxSPC[16] = psxMFHI_stall; |
| 1157 | psxSPC[18] = psxMFLO_stall; |
| 1158 | psxSPC[24] = psxMULT_stall; |
| 1159 | psxSPC[25] = psxMULTU_stall; |
| 1160 | psxSPC[26] = psxDIV_stall; |
| 1161 | psxSPC[27] = psxDIVU_stall; |
| 1162 | } |
| 1163 | |
| 1164 | // dynarec may occasionally call the interpreter, in such a case the |
| 1165 | // cache won't work (cache only works right if all fetches go through it) |
| 1166 | if (!Config.icache_emulation || psxCpu != &psxInt) |
| 1167 | fetch = fetchNoCache; |
| 1168 | else |
| 1169 | fetch = fetchICache; |
| 1170 | |
| 1171 | cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT |
| 1172 | ? Config.cycle_multiplier_override : Config.cycle_multiplier; |
| 1173 | psxRegs.subCycleStep = 0x10000 * cycle_mult / 100; |
| 1174 | } |
| 1175 | |
| 1176 | static void intShutdown() { |
| 1177 | } |
| 1178 | |
| 1179 | // single step (may do several ops in case of a branch) |
| 1180 | void execI() { |
| 1181 | execI_(psxMemRLUT, &psxRegs); |
| 1182 | } |
| 1183 | |
| 1184 | R3000Acpu psxInt = { |
| 1185 | intInit, |
| 1186 | intReset, |
| 1187 | intExecute, |
| 1188 | intExecuteBlock, |
| 1189 | intClear, |
| 1190 | intNotify, |
| 1191 | intApplyConfig, |
| 1192 | intShutdown |
| 1193 | }; |