| 1 | /*************************************************************************** |
| 2 | * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team * |
| 3 | * * |
| 4 | * This program is free software; you can redistribute it and/or modify * |
| 5 | * it under the terms of the GNU General Public License as published by * |
| 6 | * the Free Software Foundation; either version 2 of the License, or * |
| 7 | * (at your option) any later version. * |
| 8 | * * |
| 9 | * This program is distributed in the hope that it will be useful, * |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
| 12 | * GNU General Public License for more details. * |
| 13 | * * |
| 14 | * You should have received a copy of the GNU General Public License * |
| 15 | * along with this program; if not, write to the * |
| 16 | * Free Software Foundation, Inc., * |
| 17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * |
| 18 | ***************************************************************************/ |
| 19 | |
| 20 | #ifndef __R3000A_H__ |
| 21 | #define __R3000A_H__ |
| 22 | |
| 23 | #ifdef __cplusplus |
| 24 | extern "C" { |
| 25 | #endif |
| 26 | |
| 27 | #include "psxcommon.h" |
| 28 | #include "psxmem.h" |
| 29 | #include "psxcounters.h" |
| 30 | #include "psxbios.h" |
| 31 | |
| 32 | enum { |
| 33 | R3000ACPU_NOTIFY_CACHE_ISOLATED = 0, |
| 34 | R3000ACPU_NOTIFY_CACHE_UNISOLATED = 1, |
| 35 | R3000ACPU_NOTIFY_DMA3_EXE_LOAD = 2 |
| 36 | }; |
| 37 | |
| 38 | typedef struct { |
| 39 | int (*Init)(); |
| 40 | void (*Reset)(); |
| 41 | void (*Execute)(); /* executes up to a break */ |
| 42 | void (*ExecuteBlock)(); /* executes up to a jump */ |
| 43 | void (*Clear)(u32 Addr, u32 Size); |
| 44 | void (*Notify)(int note, void *data); |
| 45 | void (*ApplyConfig)(); |
| 46 | void (*Shutdown)(); |
| 47 | } R3000Acpu; |
| 48 | |
| 49 | extern R3000Acpu *psxCpu; |
| 50 | extern R3000Acpu psxInt; |
| 51 | extern R3000Acpu psxRec; |
| 52 | |
| 53 | typedef union { |
| 54 | #if defined(__BIGENDIAN__) |
| 55 | struct { u8 h3, h2, h, l; } b; |
| 56 | struct { s8 h3, h2, h, l; } sb; |
| 57 | struct { u16 h, l; } w; |
| 58 | struct { s16 h, l; } sw; |
| 59 | #else |
| 60 | struct { u8 l, h, h2, h3; } b; |
| 61 | struct { u16 l, h; } w; |
| 62 | struct { s8 l, h, h2, h3; } sb; |
| 63 | struct { s16 l, h; } sw; |
| 64 | #endif |
| 65 | } PAIR; |
| 66 | |
| 67 | typedef union { |
| 68 | struct { |
| 69 | u32 r0, at, v0, v1, a0, a1, a2, a3, |
| 70 | t0, t1, t2, t3, t4, t5, t6, t7, |
| 71 | s0, s1, s2, s3, s4, s5, s6, s7, |
| 72 | t8, t9, k0, k1, gp, sp, s8, ra, lo, hi; |
| 73 | } n; |
| 74 | u32 r[34]; /* Lo, Hi in r[32] and r[33] */ |
| 75 | PAIR p[34]; |
| 76 | } psxGPRRegs; |
| 77 | |
| 78 | typedef union { |
| 79 | struct { |
| 80 | u32 Index, Random, EntryLo0, EntryLo1, |
| 81 | Context, PageMask, Wired, Reserved0, |
| 82 | BadVAddr, Count, EntryHi, Compare, |
| 83 | Status, Cause, EPC, PRid, |
| 84 | Config, LLAddr, WatchLO, WatchHI, |
| 85 | XContext, Reserved1, Reserved2, Reserved3, |
| 86 | Reserved4, Reserved5, ECC, CacheErr, |
| 87 | TagLo, TagHi, ErrorEPC, Reserved6; |
| 88 | } n; |
| 89 | u32 r[32]; |
| 90 | PAIR p[32]; |
| 91 | } psxCP0Regs; |
| 92 | |
| 93 | typedef struct { |
| 94 | short x, y; |
| 95 | } SVector2D; |
| 96 | |
| 97 | typedef struct { |
| 98 | short z, pad; |
| 99 | } SVector2Dz; |
| 100 | |
| 101 | typedef struct { |
| 102 | short x, y, z, pad; |
| 103 | } SVector3D; |
| 104 | |
| 105 | typedef struct { |
| 106 | short x, y, z, pad; |
| 107 | } LVector3D; |
| 108 | |
| 109 | typedef struct { |
| 110 | unsigned char r, g, b, c; |
| 111 | } CBGR; |
| 112 | |
| 113 | typedef struct { |
| 114 | short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad; |
| 115 | } SMatrix3D; |
| 116 | |
| 117 | typedef union { |
| 118 | struct { |
| 119 | SVector3D v0, v1, v2; |
| 120 | CBGR rgb; |
| 121 | s32 otz; |
| 122 | s32 ir0, ir1, ir2, ir3; |
| 123 | SVector2D sxy0, sxy1, sxy2, sxyp; |
| 124 | SVector2Dz sz0, sz1, sz2, sz3; |
| 125 | CBGR rgb0, rgb1, rgb2; |
| 126 | s32 reserved; |
| 127 | s32 mac0, mac1, mac2, mac3; |
| 128 | u32 irgb, orgb; |
| 129 | s32 lzcs, lzcr; |
| 130 | } n; |
| 131 | u32 r[32]; |
| 132 | PAIR p[32]; |
| 133 | } psxCP2Data; |
| 134 | |
| 135 | typedef union { |
| 136 | struct { |
| 137 | SMatrix3D rMatrix; |
| 138 | s32 trX, trY, trZ; |
| 139 | SMatrix3D lMatrix; |
| 140 | s32 rbk, gbk, bbk; |
| 141 | SMatrix3D cMatrix; |
| 142 | s32 rfc, gfc, bfc; |
| 143 | s32 ofx, ofy; |
| 144 | s32 h; |
| 145 | s32 dqa, dqb; |
| 146 | s32 zsf3, zsf4; |
| 147 | s32 flag; |
| 148 | } n; |
| 149 | u32 r[32]; |
| 150 | PAIR p[32]; |
| 151 | } psxCP2Ctrl; |
| 152 | |
| 153 | enum { |
| 154 | PSXINT_SIO = 0, |
| 155 | PSXINT_CDR, |
| 156 | PSXINT_CDREAD, |
| 157 | PSXINT_GPUDMA, |
| 158 | PSXINT_MDECOUTDMA, |
| 159 | PSXINT_SPUDMA, |
| 160 | PSXINT_GPUBUSY, |
| 161 | PSXINT_MDECINDMA, |
| 162 | PSXINT_GPUOTCDMA, |
| 163 | PSXINT_CDRDMA, |
| 164 | PSXINT_NEWDRC_CHECK, |
| 165 | PSXINT_RCNT, |
| 166 | PSXINT_CDRLID, |
| 167 | PSXINT_CDRPLAY, |
| 168 | PSXINT_SPU_UPDATE, |
| 169 | PSXINT_COUNT |
| 170 | }; |
| 171 | |
| 172 | typedef struct psxCP2Regs { |
| 173 | psxCP2Data CP2D; /* Cop2 data registers */ |
| 174 | psxCP2Ctrl CP2C; /* Cop2 control registers */ |
| 175 | } psxCP2Regs; |
| 176 | |
| 177 | typedef struct { |
| 178 | psxGPRRegs GPR; /* General Purpose Registers */ |
| 179 | psxCP0Regs CP0; /* Coprocessor0 Registers */ |
| 180 | union { |
| 181 | struct { |
| 182 | psxCP2Data CP2D; /* Cop2 data registers */ |
| 183 | psxCP2Ctrl CP2C; /* Cop2 control registers */ |
| 184 | }; |
| 185 | psxCP2Regs CP2; |
| 186 | }; |
| 187 | u32 pc; /* Program counter */ |
| 188 | u32 code; /* The instruction */ |
| 189 | u32 cycle; |
| 190 | u32 interrupt; |
| 191 | struct { u32 sCycle, cycle; } intCycle[32]; |
| 192 | u32 gteBusyCycle; |
| 193 | u32 muldivBusyCycle; |
| 194 | // warning: changing anything in psxRegisters requires update of all |
| 195 | // asm in libpcsxcore/new_dynarec/, but this member can be replaced |
| 196 | u32 reserved[2]; |
| 197 | } psxRegisters; |
| 198 | |
| 199 | extern boolean writeok; |
| 200 | |
| 201 | extern psxRegisters psxRegs; |
| 202 | |
| 203 | /* new_dynarec stuff */ |
| 204 | extern u32 event_cycles[PSXINT_COUNT]; |
| 205 | extern u32 next_interupt; |
| 206 | |
| 207 | void lightrec_plugin_prepare_save_state(void); |
| 208 | void lightrec_plugin_prepare_load_state(void); |
| 209 | |
| 210 | void new_dyna_before_save(void); |
| 211 | void new_dyna_after_save(void); |
| 212 | void new_dyna_freeze(void *f, int mode); |
| 213 | |
| 214 | #define new_dyna_set_event(e, c) { \ |
| 215 | s32 c_ = c; \ |
| 216 | u32 abs_ = psxRegs.cycle + c_; \ |
| 217 | s32 odi_ = next_interupt - psxRegs.cycle; \ |
| 218 | event_cycles[e] = abs_; \ |
| 219 | if (c_ < odi_) { \ |
| 220 | /*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \ |
| 221 | next_interupt = abs_; \ |
| 222 | } \ |
| 223 | } |
| 224 | |
| 225 | #if defined(__BIGENDIAN__) |
| 226 | |
| 227 | #define _i32(x) *(s32 *)&x |
| 228 | #define _u32(x) x |
| 229 | |
| 230 | #define _i16(x) (((short *)&x)[1]) |
| 231 | #define _u16(x) (((unsigned short *)&x)[1]) |
| 232 | |
| 233 | #define _i8(x) (((char *)&x)[3]) |
| 234 | #define _u8(x) (((unsigned char *)&x)[3]) |
| 235 | |
| 236 | #else |
| 237 | |
| 238 | #define _i32(x) *(s32 *)&x |
| 239 | #define _u32(x) x |
| 240 | |
| 241 | #define _i16(x) *(short *)&x |
| 242 | #define _u16(x) *(unsigned short *)&x |
| 243 | |
| 244 | #define _i8(x) *(char *)&x |
| 245 | #define _u8(x) *(unsigned char *)&x |
| 246 | |
| 247 | #endif |
| 248 | |
| 249 | /**** R3000A Instruction Macros ****/ |
| 250 | #define _PC_ psxRegs.pc // The next PC to be executed |
| 251 | |
| 252 | #define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register |
| 253 | #define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register |
| 254 | #define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register |
| 255 | #define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register |
| 256 | #define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register |
| 257 | #define _fSa_(code) ((code >> 6) & 0x1F) // The sa part of the instruction register |
| 258 | #define _fIm_(code) ((u16)code) // The immediate part of the instruction register |
| 259 | #define _fTarget_(code) (code & 0x03ffffff) // The target part of the instruction register |
| 260 | |
| 261 | #define _fImm_(code) ((s16)code) // sign-extended immediate |
| 262 | #define _fImmU_(code) (code&0xffff) // zero-extended immediate |
| 263 | |
| 264 | #define _Op_ _fOp_(psxRegs.code) |
| 265 | #define _Funct_ _fFunct_(psxRegs.code) |
| 266 | #define _Rd_ _fRd_(psxRegs.code) |
| 267 | #define _Rt_ _fRt_(psxRegs.code) |
| 268 | #define _Rs_ _fRs_(psxRegs.code) |
| 269 | #define _Sa_ _fSa_(psxRegs.code) |
| 270 | #define _Im_ _fIm_(psxRegs.code) |
| 271 | #define _Target_ _fTarget_(psxRegs.code) |
| 272 | |
| 273 | #define _Imm_ _fImm_(psxRegs.code) |
| 274 | #define _ImmU_ _fImmU_(psxRegs.code) |
| 275 | |
| 276 | #define _rRs_ psxRegs.GPR.r[_Rs_] // Rs register |
| 277 | #define _rRt_ psxRegs.GPR.r[_Rt_] // Rt register |
| 278 | #define _rRd_ psxRegs.GPR.r[_Rd_] // Rd register |
| 279 | #define _rSa_ psxRegs.GPR.r[_Sa_] // Sa register |
| 280 | #define _rFs_ psxRegs.CP0.r[_Rd_] // Fs register |
| 281 | |
| 282 | #define _c2dRs_ psxRegs.CP2D.r[_Rs_] // Rs cop2 data register |
| 283 | #define _c2dRt_ psxRegs.CP2D.r[_Rt_] // Rt cop2 data register |
| 284 | #define _c2dRd_ psxRegs.CP2D.r[_Rd_] // Rd cop2 data register |
| 285 | #define _c2dSa_ psxRegs.CP2D.r[_Sa_] // Sa cop2 data register |
| 286 | |
| 287 | #define _rHi_ psxRegs.GPR.n.hi // The HI register |
| 288 | #define _rLo_ psxRegs.GPR.n.lo // The LO register |
| 289 | |
| 290 | #define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction |
| 291 | #define _BranchTarget_ ((s16)_Im_ * 4 + _PC_) // Calculates the target during a branch instruction |
| 292 | |
| 293 | #define _SetLink(x) psxRegs.GPR.r[x] = _PC_ + 4; // Sets the return address in the link register |
| 294 | |
| 295 | int psxInit(); |
| 296 | void psxReset(); |
| 297 | void psxShutdown(); |
| 298 | void psxException(u32 code, u32 bd); |
| 299 | void psxBranchTest(); |
| 300 | void psxExecuteBios(); |
| 301 | int psxTestLoadDelay(int reg, u32 tmp); |
| 302 | void psxDelayTest(int reg, u32 bpc); |
| 303 | void psxTestSWInts(); |
| 304 | void psxJumpTest(); |
| 305 | |
| 306 | #ifdef __cplusplus |
| 307 | } |
| 308 | #endif |
| 309 | #endif |