| 1 | |
| 2 | .text |
| 3 | |
| 4 | ! Master Vector Base Table at 0x06000000 |
| 5 | |
| 6 | .long mstart /* Cold Start PC */ |
| 7 | .long 0x06040000 /* Cold Start SP */ |
| 8 | .long mstart /* Manual Reset PC */ |
| 9 | .long 0x06040000 /* Manual Reset SP */ |
| 10 | .long master_e4 /* Illegal instruction */ |
| 11 | .long master_e5 /* reserved */ |
| 12 | .long master_e6 /* Invalid slot instruction */ |
| 13 | .long master_e7 /* reserved */ |
| 14 | .long master_e8 /* reserved */ |
| 15 | .long master_e9 /* CPU address error */ |
| 16 | .long master_e10 /* DMA address error */ |
| 17 | .long master_e11 /* NMI vector */ |
| 18 | .long master_e12 /* User break vector */ |
| 19 | .rept 19 |
| 20 | .long main_err /* reserved */ |
| 21 | .endr |
| 22 | .rept 32 |
| 23 | .long main_err /* TRAPA #32-63 */ |
| 24 | .endr |
| 25 | .long main_irq /* Level 1 IRQ */ |
| 26 | .long main_irq /* Level 2 & 3 IRQ's */ |
| 27 | .long main_irq /* Level 4 & 5 IRQ's */ |
| 28 | .long main_irq /* PWM interupt */ |
| 29 | .long main_irq /* Command interupt */ |
| 30 | .long main_irq /* H Blank interupt */ |
| 31 | .long main_irq /* V Blank interupt */ |
| 32 | .long main_irq /* Reset Button */ |
| 33 | .rept 56 |
| 34 | .long main_err /* peripherals */ |
| 35 | .endr |
| 36 | |
| 37 | ! Slave Vector Base Table at 0x06000200 |
| 38 | |
| 39 | .long sstart /* Cold Start PC */ |
| 40 | .long 0x0603f800 /* Cold Start SP */ |
| 41 | .long sstart /* Manual Reset PC */ |
| 42 | .long 0x0603f800 /* Manual Reset SP */ |
| 43 | .long slave_e4 /* Illegal instruction */ |
| 44 | .long slave_e5 /* reserved */ |
| 45 | .long slave_e6 /* Invalid slot instruction */ |
| 46 | .long slave_e7 /* reserved */ |
| 47 | .long slave_e8 /* reserved */ |
| 48 | .long slave_e9 /* CPU address error */ |
| 49 | .long slave_e10 /* DMA address error */ |
| 50 | .long slave_e11 /* NMI vector */ |
| 51 | .long slave_e12 /* User break vector */ |
| 52 | .rept 19 |
| 53 | .long slave_err /* reserved */ |
| 54 | .endr |
| 55 | .rept 32 |
| 56 | .long slave_err /* TRAPA #32-63 */ |
| 57 | .endr |
| 58 | .long slave_irq /* Level 1 IRQ */ |
| 59 | .long slave_irq /* Level 2 & 3 IRQ's */ |
| 60 | .long slave_irq /* Level 4 & 5 IRQ's */ |
| 61 | .long slave_irq /* PWM interupt */ |
| 62 | .long slave_irq /* Command interupt */ |
| 63 | .long slave_irq /* H Blank interupt */ |
| 64 | .long slave_irq /* V Blank interupt */ |
| 65 | .long slave_irq /* Reset Button */ |
| 66 | .rept 56 |
| 67 | .long slave_err /* peripherals */ |
| 68 | .endr |
| 69 | |
| 70 | ! trashes r0 |
| 71 | .macro mov_bc const ofs reg |
| 72 | mov #\const, r0 |
| 73 | .if \ofs == 0 |
| 74 | mov.b r0, @\reg |
| 75 | .else |
| 76 | mov.b r0, @(\ofs, \reg) |
| 77 | .endif |
| 78 | .endm |
| 79 | |
| 80 | ! Stacks set up by BIOS |
| 81 | |
| 82 | ! The main SH2 starts here at 0x06000400 |
| 83 | |
| 84 | mstart: |
| 85 | bra xstart |
| 86 | mov #0, r4 |
| 87 | |
| 88 | ! The slave SH2 starts here at 0x06000404 |
| 89 | |
| 90 | sstart: |
| 91 | mov #1, r4 |
| 92 | |
| 93 | xstart: |
| 94 | .if 0 |
| 95 | ! cache init - done by BIOS with single 0x11 write |
| 96 | mov.l l_cctl, r1 /* cache */ |
| 97 | mov_bc 0x00, 0, r1 /* disable */ |
| 98 | mov.b @r1, r0 /* dummy read */ |
| 99 | mov_bc 0x10, 0, r1 /* purge */ |
| 100 | mov.b @r1, r0 |
| 101 | mov_bc 0x01, 0, r1 /* enable */ |
| 102 | .endif |
| 103 | mov #0x10, r0 /* enable irqs, 0 causes endless irq */ |
| 104 | ldc r0, sr |
| 105 | mov.l l_main_c, r0 |
| 106 | jmp @r0 |
| 107 | nop |
| 108 | |
| 109 | main_irq: |
| 110 | mov.l r0, @-r15 |
| 111 | mov.l r1, @-r15 |
| 112 | mov.l l_irq_cnt, r1 /* counters in fb (0x2401ff00) */ |
| 113 | |
| 114 | do_irq_cmn: |
| 115 | mov.l r2, @-r15 |
| 116 | mov #0x80, r0 |
| 117 | mov.b r0, @(0, gbr) /* FM=1 */ |
| 118 | mov.b r0, @(0, gbr) /* flush write buf */ |
| 119 | stc sr, r0 /* SR holds IRQ level in I3-I0 */ |
| 120 | shlr2 r0 |
| 121 | shlr2 r0 |
| 122 | and #0x0e, r0 |
| 123 | mov r0, r2 |
| 124 | add r1, r0 |
| 125 | mov.w @r0, r1 |
| 126 | add #1, r1 |
| 127 | mov.w r1, @r0 |
| 128 | mova l_irq_ao, r0 |
| 129 | mov.w @(r0, r2), r0 |
| 130 | stc gbr, r1 |
| 131 | mov.w r0, @(r0, r1) /* ack */ |
| 132 | mov #0x80, r0 |
| 133 | mov.b r0, @(0, gbr) /* FM=1 and flush writebuf (alt: ~20 nops) */ |
| 134 | mov.l @r15+, r2 |
| 135 | mov.l @r15+, r1 |
| 136 | mov.l @r15+, r0 |
| 137 | rte |
| 138 | nop |
| 139 | |
| 140 | ! not used |
| 141 | .if 0 |
| 142 | main_irq_vres_: |
| 143 | mov.w r0, @(0x14, gbr) /* ack */ |
| 144 | mov.b @(7, gbr), r0 /* RV */ |
| 145 | tst #1, r0 |
| 146 | bt main_irq_ret |
| 147 | |
| 148 | ! Try to set FTOB pin that's wired to 32X hard reset. |
| 149 | ! Doesn't seem to be working right though, it somehow disturbs |
| 150 | ! 68k reset PC fetch which mysteriously ends up at range |
| 151 | ! 2c8 - 304 in multiples of 4, proportionally to reset delay |
| 152 | ! (0 - ~300 (?) sh2 cycles). Longer delay just hangs, presumably |
| 153 | ! at 880200? |
| 154 | mov.l l_frt, r1 |
| 155 | mov_bc 0xf1, 7, r1 /* TOCR sel OCRB, pin on B match */ |
| 156 | mov #0, r0 |
| 157 | mov.b r0, @(4, r1) /* OCRB H - output compare B */ |
| 158 | mov.b r0, @(5, r1) /* OCRB L */ |
| 159 | mov.b r0, @(2, r1) /* FRC H */ |
| 160 | mov.b r0, @(3, r1) /* FRC L */ |
| 161 | mov.b @(7, r1), r0 |
| 162 | ! sleep - docs say not to use |
| 163 | ! sleep |
| 164 | 0: |
| 165 | bra 0b |
| 166 | nop |
| 167 | |
| 168 | main_irq_ret: |
| 169 | mov.l @r15+, r0 |
| 170 | rte |
| 171 | nop |
| 172 | .endif |
| 173 | |
| 174 | .global _read_frt |
| 175 | _read_frt: |
| 176 | mov.l l_frt, r2 |
| 177 | mov.b @(2, r2), r0 |
| 178 | extu.b r0, r1 |
| 179 | mov.b @(3, r2), r0 |
| 180 | extu.b r0, r0 |
| 181 | shll8 r1 |
| 182 | rts |
| 183 | or r1, r0 |
| 184 | |
| 185 | ! dummy |
| 186 | .global _start |
| 187 | _start: |
| 188 | |
| 189 | main_err: |
| 190 | bra do_exc_master |
| 191 | mov #0xff, r0 |
| 192 | slave_err: |
| 193 | bra do_exc_slave |
| 194 | mov #0xff, r0 |
| 195 | |
| 196 | slave_irq: |
| 197 | mov.l r0, @-r15 |
| 198 | mov.l r1, @-r15 |
| 199 | mov.l l_irq_cnt, r1 /* counters in fb (0x2401ff00) */ |
| 200 | bra do_irq_cmn |
| 201 | add #0x10, r1 |
| 202 | |
| 203 | .align 2 |
| 204 | l_cctl: |
| 205 | .long 0xFFFFFE92 |
| 206 | l_frt: |
| 207 | .long 0xFFFFFE10 |
| 208 | l_main_c: |
| 209 | .long _main_c |
| 210 | l_irq_cnt: |
| 211 | .long 0x2401ff00 |
| 212 | l_irq_ao: |
| 213 | /* ?, ?, ?, pwm, cmd, h, v, rst */ |
| 214 | .word 0x0e, 0x0e, 0x0e, 0x1c, 0x1a, 0x18, 0x16, 0x14 |
| 215 | |
| 216 | .macro exc_master num |
| 217 | master_e\num: |
| 218 | bra do_exc_master |
| 219 | mov #\num, r0 |
| 220 | .endm |
| 221 | |
| 222 | .macro exc_slave num |
| 223 | slave_e\num: |
| 224 | bra do_exc_slave |
| 225 | mov #\num, r0 |
| 226 | .endm |
| 227 | |
| 228 | exc_master 4 |
| 229 | exc_master 5 |
| 230 | exc_master 6 |
| 231 | exc_master 7 |
| 232 | exc_master 8 |
| 233 | exc_master 9 |
| 234 | exc_master 10 |
| 235 | exc_master 11 |
| 236 | exc_master 12 |
| 237 | |
| 238 | exc_slave 4 |
| 239 | exc_slave 5 |
| 240 | exc_slave 6 |
| 241 | exc_slave 7 |
| 242 | exc_slave 8 |
| 243 | exc_slave 9 |
| 244 | exc_slave 10 |
| 245 | exc_slave 11 |
| 246 | exc_slave 12 |
| 247 | |
| 248 | do_exc_master: |
| 249 | mov.w r0, @(0x2c, gbr) |
| 250 | 0: |
| 251 | bra 0b |
| 252 | nop |
| 253 | |
| 254 | do_exc_slave: |
| 255 | mov.w r0, @(0x2e, gbr) |
| 256 | 0: |
| 257 | bra 0b |
| 258 | nop |
| 259 | |
| 260 | .global _spin |
| 261 | _spin: |
| 262 | dt r4 |
| 263 | bf _spin |
| 264 | rts |
| 265 | nop |
| 266 | |
| 267 | ! vim:ts=8:sw=8:expandtab |