| 1 | |
| 2 | .text |
| 3 | |
| 4 | ! Master Vector Base Table at 0x06000000 |
| 5 | |
| 6 | .long mstart /* Cold Start PC */ |
| 7 | .long 0x06040000 /* Cold Start SP */ |
| 8 | .long mstart /* Manual Reset PC */ |
| 9 | .long 0x06040000 /* Manual Reset SP */ |
| 10 | .long master_e4 /* Illegal instruction */ |
| 11 | .long master_e5 /* reserved */ |
| 12 | .long master_e6 /* Invalid slot instruction */ |
| 13 | .long master_e7 /* reserved */ |
| 14 | .long master_e8 /* reserved */ |
| 15 | .long master_e9 /* CPU address error */ |
| 16 | .long master_e10 /* DMA address error */ |
| 17 | .long master_e11 /* NMI vector */ |
| 18 | .long master_e12 /* User break vector */ |
| 19 | .rept 19 |
| 20 | .long master_err /* reserved */ |
| 21 | .endr |
| 22 | .rept 32 |
| 23 | .long master_err /* TRAPA #32-63 */ |
| 24 | .endr |
| 25 | .long master_irq0 /* Level 1 IRQ */ |
| 26 | .long master_irq1 /* Level 2 & 3 IRQ's */ |
| 27 | .long master_irq2 /* Level 4 & 5 IRQ's */ |
| 28 | .long master_irq3 /* PWM interupt */ |
| 29 | .long master_irq4 /* Command interupt */ |
| 30 | .long master_irq5 /* H Blank interupt */ |
| 31 | .long master_irq6 /* V Blank interupt */ |
| 32 | ! .long main_irq_vres |
| 33 | .long master_irq7 /* Reset Button */ |
| 34 | .rept 56 |
| 35 | .long master_err /* peripherals */ |
| 36 | .endr |
| 37 | |
| 38 | ! Slave Vector Base Table at 0x06000200 |
| 39 | |
| 40 | .long sstart /* Cold Start PC */ |
| 41 | .long 0x0603f800 /* Cold Start SP */ |
| 42 | .long sstart /* Manual Reset PC */ |
| 43 | .long 0x0603f800 /* Manual Reset SP */ |
| 44 | .long slave_e4 /* Illegal instruction */ |
| 45 | .long slave_e5 /* reserved */ |
| 46 | .long slave_e6 /* Invalid slot instruction */ |
| 47 | .long slave_e7 /* reserved */ |
| 48 | .long slave_e8 /* reserved */ |
| 49 | .long slave_e9 /* CPU address error */ |
| 50 | .long slave_e10 /* DMA address error */ |
| 51 | .long slave_e11 /* NMI vector */ |
| 52 | .long slave_e12 /* User break vector */ |
| 53 | .rept 19 |
| 54 | .long slave_err /* reserved */ |
| 55 | .endr |
| 56 | .rept 32 |
| 57 | .long slave_err /* TRAPA #32-63 */ |
| 58 | .endr |
| 59 | .long slave_irq0 /* Level 1 IRQ */ |
| 60 | .long slave_irq1 /* Level 2 & 3 IRQ's */ |
| 61 | .long slave_irq2 /* Level 4 & 5 IRQ's */ |
| 62 | .long slave_irq3 /* PWM interupt */ |
| 63 | .long slave_irq4 /* Command interupt */ |
| 64 | .long slave_irq5 /* H Blank interupt */ |
| 65 | .long slave_irq6 /* V Blank interupt */ |
| 66 | .long slave_irq7 /* Reset Button */ |
| 67 | .rept 56 |
| 68 | .long slave_err /* peripherals */ |
| 69 | .endr |
| 70 | |
| 71 | ! trashes r0 |
| 72 | .macro mov_bc const ofs reg |
| 73 | mov #\const, r0 |
| 74 | .if \ofs == 0 |
| 75 | mov.b r0, @\reg |
| 76 | .else |
| 77 | mov.b r0, @(\ofs, \reg) |
| 78 | .endif |
| 79 | .endm |
| 80 | |
| 81 | ! Stacks set up by BIOS |
| 82 | |
| 83 | ! The main SH2 starts here at 0x06000400 |
| 84 | |
| 85 | mstart: |
| 86 | bra xstart |
| 87 | mov #0, r4 |
| 88 | |
| 89 | ! The slave SH2 starts here at 0x06000404 |
| 90 | |
| 91 | sstart: |
| 92 | mov #1, r4 |
| 93 | |
| 94 | xstart: |
| 95 | .if 0 |
| 96 | ! cache init - done by BIOS with single 0x11 write |
| 97 | mov.l l_cctl, r1 /* cache */ |
| 98 | mov_bc 0x00, 0, r1 /* disable */ |
| 99 | mov.b @r1, r0 /* dummy read */ |
| 100 | mov_bc 0x10, 0, r1 /* purge */ |
| 101 | mov.b @r1, r0 |
| 102 | mov_bc 0x01, 0, r1 /* enable */ |
| 103 | .endif |
| 104 | mov #0x10, r0 /* enable irqs, 0 causes endless irq */ |
| 105 | ldc r0, sr |
| 106 | mov.l l_main_c, r0 |
| 107 | jmp @r0 |
| 108 | nop |
| 109 | |
| 110 | ! r0=vector_number |
| 111 | do_irq_master: |
| 112 | mov.b r0, @(0x2c, gbr) |
| 113 | mov.l r1, @-r15 |
| 114 | mov.l l_irq_cnt, r1 /* counters in fb (0x2401ff00) */ |
| 115 | |
| 116 | ! According to "32X Technical Information Attachment 1" FTOA pin must be toggled |
| 117 | ! or interrupts may be missed when multiple irqs trigger. We skip that here since |
| 118 | ! we test only 1 irq at a time. |
| 119 | do_irq_cmn: |
| 120 | mov.l r2, @-r15 |
| 121 | mov #0x80, r0 |
| 122 | mov.b r0, @(0, gbr) /* FM=1 */ |
| 123 | mov.b r0, @(0, gbr) /* flush write buf */ |
| 124 | stc sr, r0 /* SR holds IRQ level in I3-I0 */ |
| 125 | shlr2 r0 |
| 126 | shlr2 r0 |
| 127 | and #0x0e, r0 |
| 128 | mov r0, r2 |
| 129 | add r1, r0 |
| 130 | mov.w @r0, r1 |
| 131 | add #1, r1 |
| 132 | mov.w r1, @r0 |
| 133 | mova l_irq_ao, r0 |
| 134 | mov.w @(r0, r2), r0 |
| 135 | stc gbr, r1 |
| 136 | mov.w r0, @(r0, r1) /* ack */ |
| 137 | mov #0x80, r0 |
| 138 | mov.b r0, @(0, gbr) /* FM=1 and flush writebuf (alt: ~20 nops) */ |
| 139 | mov.l @r15+, r2 |
| 140 | mov.l @r15+, r1 |
| 141 | mov.l @r15+, r0 |
| 142 | rte |
| 143 | nop |
| 144 | |
| 145 | ! not used |
| 146 | .if 0 |
| 147 | main_irq_vres: |
| 148 | mov.w r0, @(0x14, gbr) /* ack */ |
| 149 | mov.b @(7, gbr), r0 /* RV */ |
| 150 | tst #1, r0 |
| 151 | bt main_irq_ret |
| 152 | |
| 153 | ! Try to set FTOB pin that's wired to 32X hard reset. |
| 154 | ! Doesn't seem to be working right though, it somehow disturbs |
| 155 | ! 68k reset PC fetch which mysteriously ends up at range |
| 156 | ! 2c8 - 304 in multiples of 4, proportionally to reset delay |
| 157 | ! (0 - ~300 (?) sh2 cycles). Longer delay just hangs, presumably |
| 158 | ! at 880200? |
| 159 | mov.l l_frt, r1 |
| 160 | mov_bc 0xf1, 7, r1 /* TOCR sel OCRB, pin on B match */ |
| 161 | mov #0, r0 |
| 162 | mov.b r0, @(4, r1) /* OCRB H - output compare B */ |
| 163 | mov.b r0, @(5, r1) /* OCRB L */ |
| 164 | mov.b r0, @(2, r1) /* FRC H */ |
| 165 | mov.b r0, @(3, r1) /* FRC L */ |
| 166 | mov.b @(3, r1), r0 |
| 167 | ! sleep - docs say not to use |
| 168 | ! sleep |
| 169 | 0: |
| 170 | bra 0b |
| 171 | nop |
| 172 | |
| 173 | main_irq_ret: |
| 174 | mov.l @r15+, r0 |
| 175 | rte |
| 176 | nop |
| 177 | .endif |
| 178 | |
| 179 | .global _read_frt |
| 180 | _read_frt: |
| 181 | mov.l l_frt, r2 |
| 182 | mov.b @(2, r2), r0 |
| 183 | extu.b r0, r1 |
| 184 | mov.b @(3, r2), r0 |
| 185 | extu.b r0, r0 |
| 186 | shll8 r1 |
| 187 | rts |
| 188 | or r1, r0 |
| 189 | |
| 190 | ! dummy |
| 191 | .global _start |
| 192 | _start: |
| 193 | |
| 194 | master_err: |
| 195 | bra do_exc_master |
| 196 | mov #0xff, r0 |
| 197 | slave_err: |
| 198 | bra do_exc_slave |
| 199 | mov #0xff, r0 |
| 200 | |
| 201 | ! r0=vector_number |
| 202 | do_irq_slave: |
| 203 | mov.b r0, @(0x2d, gbr) |
| 204 | mov.l r1, @-r15 |
| 205 | mov.l l_irq_cnt, r1 /* counters in fb (0x2401ff00) */ |
| 206 | bra do_irq_cmn |
| 207 | add #0x10, r1 |
| 208 | |
| 209 | .align 2 |
| 210 | l_cctl: |
| 211 | .long 0xFFFFFE92 |
| 212 | l_frt: |
| 213 | .long 0xFFFFFE10 |
| 214 | l_main_c: |
| 215 | .long _main_c |
| 216 | l_irq_cnt: |
| 217 | .long 0x2401ff00 |
| 218 | l_irq_ao: |
| 219 | /* ?, ?, ?, pwm, cmd, h, v, rst */ |
| 220 | .word 0x0e, 0x0e, 0x0e, 0x1c, 0x1a, 0x18, 0x16, 0x14 |
| 221 | |
| 222 | .macro exc_master num |
| 223 | master_e\num: |
| 224 | bra do_exc_master |
| 225 | mov #\num, r0 |
| 226 | .endm |
| 227 | |
| 228 | .macro exc_slave num |
| 229 | slave_e\num: |
| 230 | bra do_exc_slave |
| 231 | mov #\num, r0 |
| 232 | .endm |
| 233 | |
| 234 | .macro irq_master num |
| 235 | master_irq\num: |
| 236 | mov.l r0, @-r15 |
| 237 | bra do_irq_master |
| 238 | mov #\num, r0 |
| 239 | .endm |
| 240 | |
| 241 | .macro irq_slave num |
| 242 | slave_irq\num: |
| 243 | mov.l r0, @-r15 |
| 244 | bra do_irq_slave |
| 245 | mov #\num, r0 |
| 246 | .endm |
| 247 | |
| 248 | exc_master 4 |
| 249 | exc_master 5 |
| 250 | exc_master 6 |
| 251 | exc_master 7 |
| 252 | exc_master 8 |
| 253 | exc_master 9 |
| 254 | exc_master 10 |
| 255 | exc_master 11 |
| 256 | exc_master 12 |
| 257 | irq_master 0 |
| 258 | irq_master 1 |
| 259 | irq_master 2 |
| 260 | irq_master 3 |
| 261 | irq_master 4 |
| 262 | irq_master 5 |
| 263 | irq_master 6 |
| 264 | irq_master 7 |
| 265 | |
| 266 | exc_slave 4 |
| 267 | exc_slave 5 |
| 268 | exc_slave 6 |
| 269 | exc_slave 7 |
| 270 | exc_slave 8 |
| 271 | exc_slave 9 |
| 272 | exc_slave 10 |
| 273 | exc_slave 11 |
| 274 | exc_slave 12 |
| 275 | irq_slave 0 |
| 276 | irq_slave 1 |
| 277 | irq_slave 2 |
| 278 | irq_slave 3 |
| 279 | irq_slave 4 |
| 280 | irq_slave 5 |
| 281 | irq_slave 6 |
| 282 | irq_slave 7 |
| 283 | |
| 284 | do_exc_master: |
| 285 | mov.b r0, @(0x2e, gbr) |
| 286 | 0: |
| 287 | bra 0b |
| 288 | nop |
| 289 | |
| 290 | do_exc_slave: |
| 291 | mov.b r0, @(0x2f, gbr) |
| 292 | 0: |
| 293 | bra 0b |
| 294 | nop |
| 295 | |
| 296 | .global _spin |
| 297 | _spin: |
| 298 | dt r4 |
| 299 | bf _spin |
| 300 | rts |
| 301 | nop |
| 302 | |
| 303 | ! vim:ts=8:sw=8:expandtab |