| 1 | diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c |
| 2 | index 2d3348e8..a85d2cd4 100644 |
| 3 | --- a/libpcsxcore/new_dynarec/new_dynarec.c |
| 4 | +++ b/libpcsxcore/new_dynarec/new_dynarec.c |
| 5 | @@ -318,7 +318,7 @@ static struct compile_info |
| 6 | int new_dynarec_hacks_old; |
| 7 | int new_dynarec_did_compile; |
| 8 | |
| 9 | - #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x)) |
| 10 | + #define HACK_ENABLED(x) ((NDHACK_NO_STALLS) & (x)) |
| 11 | |
| 12 | extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 |
| 13 | extern int last_count; // last absolute target, often = next_interupt |
| 14 | @@ -598,6 +598,7 @@ static int cycle_multiplier_active; |
| 15 | |
| 16 | static int CLOCK_ADJUST(int x) |
| 17 | { |
| 18 | + return x * 2; |
| 19 | int m = cycle_multiplier_active; |
| 20 | int s = (x >> 31) | 1; |
| 21 | return (x * m + s * 50) / 100; |
| 22 | @@ -752,6 +753,9 @@ static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page) |
| 23 | // This is called from the recompiled JR/JALR instructions |
| 24 | static void noinline *get_addr(u_int vaddr, int can_compile) |
| 25 | { |
| 26 | +#ifdef DRC_DBG |
| 27 | +printf("get_addr %08x, pc=%08x\n", vaddr, psxRegs.pc); |
| 28 | +#endif |
| 29 | u_int start_page = get_page_prev(vaddr); |
| 30 | u_int i, page, end_page = get_page(vaddr); |
| 31 | void *found_clean = NULL; |
| 32 | @@ -7164,7 +7168,7 @@ static noinline void pass2_unneeded_regs(int istart,int iend,int r) |
| 33 | // R0 is always unneeded |
| 34 | u|=1; |
| 35 | // Save it |
| 36 | - unneeded_reg[i]=u; |
| 37 | + unneeded_reg[i]=1;//u; |
| 38 | gte_unneeded[i]=gte_u; |
| 39 | /* |
| 40 | printf("ur (%d,%d) %x: ",istart,iend,start+i*4); |
| 41 | @@ -8315,6 +8319,7 @@ static noinline void pass5a_preallocate1(void) |
| 42 | static noinline void pass5b_preallocate2(void) |
| 43 | { |
| 44 | int i, hr; |
| 45 | + return; |
| 46 | for(i=0;i<slen-1;i++) |
| 47 | { |
| 48 | if (!i || !dops[i-1].is_jump) |
| 49 | @@ -9124,6 +9129,14 @@ static int new_recompile_block(u_int addr) |
| 50 | load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP); |
| 51 | |
| 52 | ds = assemble(i, ®s[i], cinfo[i].ccadj); |
| 53 | +#ifdef DRC_DBG |
| 54 | + // write-out non-consts, consts are likely different because of get_final_value() |
| 55 | + if (regs[i].dirty & ~regs[i].loadedconst) { |
| 56 | + assem_debug("/ drc_dbg_wb\n"); |
| 57 | + wb_dirtys(regs[i].regmap, regs[i].dirty & ~regs[i].loadedconst); |
| 58 | + assem_debug("\\ drc_dbg_wb\n"); |
| 59 | + } |
| 60 | +#endif |
| 61 | |
| 62 | if (dops[i].is_ujump) |
| 63 | literal_pool(1024); |
| 64 | @@ -9316,6 +9329,10 @@ static int new_recompile_block(u_int addr) |
| 65 | |
| 66 | #ifdef ASSEM_PRINT |
| 67 | fflush(stdout); |
| 68 | +#endif |
| 69 | +#ifdef DRC_DBG |
| 70 | +printf("new_recompile_block done\n"); |
| 71 | +fflush(stdout); |
| 72 | #endif |
| 73 | stat_inc(stat_bc_direct); |
| 74 | return 0; |
| 75 | diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c |
| 76 | index 190f8fc7..5feb7a02 100644 |
| 77 | --- a/libpcsxcore/new_dynarec/pcsxmem.c |
| 78 | +++ b/libpcsxcore/new_dynarec/pcsxmem.c |
| 79 | @@ -289,6 +289,8 @@ static void write_biu(u32 value) |
| 80 | return; |
| 81 | } |
| 82 | |
| 83 | +extern u32 handler_cycle; |
| 84 | +handler_cycle = psxRegs.cycle; |
| 85 | memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle); |
| 86 | psxRegs.biuReg = value; |
| 87 | } |
| 88 | diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c |
| 89 | index 18bd6a4e..bc2eb3f6 100644 |
| 90 | --- a/libpcsxcore/psxcounters.c |
| 91 | +++ b/libpcsxcore/psxcounters.c |
| 92 | @@ -389,9 +389,12 @@ void psxRcntUpdate() |
| 93 | |
| 94 | /******************************************************************************/ |
| 95 | |
| 96 | +extern u32 handler_cycle; |
| 97 | + |
| 98 | void psxRcntWcount( u32 index, u32 value ) |
| 99 | { |
| 100 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); |
| 101 | +handler_cycle = psxRegs.cycle; |
| 102 | |
| 103 | _psxRcntWcount( index, value ); |
| 104 | psxRcntSet(); |
| 105 | @@ -400,6 +403,7 @@ void psxRcntWcount( u32 index, u32 value ) |
| 106 | void psxRcntWmode( u32 index, u32 value ) |
| 107 | { |
| 108 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); |
| 109 | +handler_cycle = psxRegs.cycle; |
| 110 | |
| 111 | _psxRcntWmode( index, value ); |
| 112 | _psxRcntWcount( index, 0 ); |
| 113 | @@ -411,6 +415,7 @@ void psxRcntWmode( u32 index, u32 value ) |
| 114 | void psxRcntWtarget( u32 index, u32 value ) |
| 115 | { |
| 116 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); |
| 117 | +handler_cycle = psxRegs.cycle; |
| 118 | |
| 119 | rcnts[index].target = value; |
| 120 | |
| 121 | @@ -423,6 +428,7 @@ void psxRcntWtarget( u32 index, u32 value ) |
| 122 | u32 psxRcntRcount( u32 index ) |
| 123 | { |
| 124 | u32 count; |
| 125 | +handler_cycle = psxRegs.cycle; |
| 126 | |
| 127 | count = _psxRcntRcount( index ); |
| 128 | |
| 129 | diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c |
| 130 | index e212d8a9..b98b694e 100644 |
| 131 | --- a/libpcsxcore/psxinterpreter.c |
| 132 | +++ b/libpcsxcore/psxinterpreter.c |
| 133 | @@ -237,7 +237,7 @@ static inline void addCycle(psxRegisters *regs) |
| 134 | { |
| 135 | assert(regs->subCycleStep >= 0x10000); |
| 136 | regs->subCycle += regs->subCycleStep; |
| 137 | - regs->cycle += regs->subCycle >> 16; |
| 138 | + regs->cycle += 2; //regs->subCycle >> 16; |
| 139 | regs->subCycle &= 0xffff; |
| 140 | } |
| 141 | |
| 142 | @@ -1341,8 +1341,14 @@ static void intShutdown() { |
| 143 | |
| 144 | // single step (may do several ops in case of a branch or load delay) |
| 145 | void execI(psxRegisters *regs) { |
| 146 | + extern int last_count; |
| 147 | + void do_insn_cmp(void); |
| 148 | + printf("execI %08x c %u, ni %u\n", regs->pc, regs->cycle, next_interupt); |
| 149 | + last_count = 0; |
| 150 | do { |
| 151 | execIbp(psxMemRLUT, regs); |
| 152 | + if (regs->dloadReg[0] || regs->dloadReg[1]) |
| 153 | + do_insn_cmp(); |
| 154 | } while (regs->dloadReg[0] || regs->dloadReg[1]); |
| 155 | } |
| 156 | |