3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
10 * a15102 ........ ......SM ? 4002 // intS intM
11 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
12 * a15106 ........ F....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
13 * a15108 (32bit DREQ src) 4008
14 * a1510c (32bit DREQ dst) 400c
15 * a15110 llllllll llllll00 4010 // DREQ Len
16 * a15112 (16bit FIFO reg) 4012
17 * a15114 0 (16bit VRES clr) 4014
18 * a15116 0 (16bit Vint clr) 4016
19 * a15118 0 (16bit Hint clr) 4018
20 * a1511a .......? .......C (16bit CMD clr) 401a // TV Cm
21 * a1511c 0 (16bit PWM clr) 401c
23 * a15120 (16 bytes comm) 2020
27 * iii. .cc. ..xx * // Internal, Cs, x
29 * sh2 map, wait/bus cycles (from docs):
31 * rom 0000000-0003fff 1 -
32 * sys reg 0004000-00040ff 1 1
33 * vdp reg 0004100-00041ff 5 5
34 * vdp pal 0004200-00043ff 5 5
35 * cart 2000000-23fffff 6-15
36 * dram/fb 4000000-401ffff 5-12 1-3
37 * fb ovr 4020000-403ffff
38 * sdram 6000000-603ffff 12 2 (cycles)
41 #include "../pico_int.h"
42 #include "../memory.h"
43 #include "../../cpu/sh2/compiler.h"
45 static const char str_mars[] = "MARS";
47 void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
48 struct Pico32xMem *Pico32xMem;
50 static void bank_switch(int b);
52 // addressing byte in 16bit reg
53 #define REG8IN16(ptr, offs) ((u8 *)ptr)[(offs) ^ 1]
56 #define POLL_THRESHOLD 3
63 static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
67 if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
68 && cycles - m68k_poll.cycles <= 64 && !SekNotPolling)
70 if (m68k_poll.cnt++ > POLL_THRESHOLD) {
71 if (!(Pico32x.emu_flags & flags)) {
72 elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
73 a, cycles - m68k_poll.cycles);
76 Pico32x.emu_flags |= flags;
84 m68k_poll.cycles = cycles;
89 void p32x_m68k_poll_event(u32 flags)
91 if (Pico32x.emu_flags & flags) {
92 elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
93 Pico32x.emu_flags & ~flags);
94 Pico32x.emu_flags &= ~flags;
97 m68k_poll.addr = m68k_poll.cnt = 0;
100 static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags, int maxcnt)
102 int cycles_left = sh2_cycles_left(sh2);
104 if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
105 if (sh2->poll_cnt++ > maxcnt) {
106 if (!(sh2->state & flags))
107 elprintf_sh2(sh2, EL_32X, "state: %02x->%02x",
108 sh2->state, sh2->state | flags);
112 pevt_log_sh2(sh2, EVT_POLL_START);
119 sh2->poll_cycles = cycles_left;
122 void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
124 if (sh2->state & flags) {
125 elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", sh2->state,
126 sh2->state & ~flags);
128 if (sh2->m68krcycles_done < m68k_cycles)
129 sh2->m68krcycles_done = m68k_cycles;
131 pevt_log_sh2_o(sh2, EVT_POLL_END);
134 sh2->state &= ~flags;
135 sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
138 static void sh2s_sync_on_read(SH2 *sh2)
141 if (sh2->poll_cnt != 0)
144 cycles = sh2_cycles_done(sh2);
146 p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3);
152 static int p32x_csum_faked;
153 static const u16 comm_fakevals[] = {
154 0x4d5f, 0x4f4b, // M_OK
155 0x535f, 0x4f4b, // S_OK
156 0x4D41, 0x5346, // MASF - Brutal Unleashed
157 0x5331, 0x4d31, // Darxide
160 0x0000, 0x0000, // eq for doom
161 0x0002, // Mortal Kombat
165 static u32 sh2_comm_faker(u32 a)
168 if (a == 0x28 && !p32x_csum_faked) {
170 return *(unsigned short *)(Pico.rom + 0x18e);
172 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
174 return comm_fakevals[f++];
178 // ------------------------------------------------------------------
181 static u32 p32x_reg_read16(u32 a)
186 if ((a & 0x30) == 0x20)
187 return sh2_comm_faker(a);
189 if ((a & 0x30) == 0x20) {
190 unsigned int cycles = SekCyclesDone();
191 int comreg = 1 << (a & 0x0f) / 2;
193 if (cycles - msh2.m68krcycles_done > 244
194 || (Pico32x.comm_dirty & comreg))
195 p32x_sync_sh2s(cycles);
197 if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
205 if (a == 2) { // INTM, INTS
206 unsigned int cycles = SekCyclesDone();
207 if (cycles - msh2.m68krcycles_done > 64)
208 p32x_sync_sh2s(cycles);
212 if ((a & 0x30) == 0x30)
213 return p32x_pwm_read16(a, NULL, SekCyclesDone());
216 return Pico32x.regs[a / 2];
219 static void dreq0_write(u16 *r, u32 d)
221 if (!(r[6 / 2] & P32XS_68S)) {
222 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
223 return; // ignored - tested
225 if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
226 Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
227 if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
228 r[6 / 2] |= P32XS_FULL;
229 // tested: len register decrements and 68S clears
230 // even if SH2s/DMAC aren't active..
232 if (r[0x10 / 2] == 0)
233 r[6 / 2] &= ~P32XS_68S;
235 if ((Pico32x.dmac0_fifo_ptr & 3) == 0) {
236 p32x_sync_sh2s(SekCyclesDone());
237 p32x_dreq0_trigger();
241 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO overflow!");
244 // writable bits tested
245 static void p32x_reg_write8(u32 a, u32 d)
247 u16 *r = Pico32x.regs;
250 // for things like bset on comm port
254 case 0x00: // adapter ctl: FM writable
255 REG8IN16(r, 0x00) = d & 0x80;
257 case 0x01: // adapter ctl: RES and ADEN writable
258 if ((d ^ r[0]) & d & P32XS_nRES)
260 REG8IN16(r, 0x01) &= ~(P32XS_nRES|P32XS_ADEN);
261 REG8IN16(r, 0x01) |= d & (P32XS_nRES|P32XS_ADEN);
263 case 0x02: // ignored, always 0
265 case 0x03: // irq ctl
266 if ((d ^ r[0x02 / 2]) & 3) {
267 int cycles = SekCyclesDone();
268 p32x_sync_sh2s(cycles);
270 p32x_update_cmd_irq(NULL, cycles);
273 case 0x04: // ignored, always 0
277 if (r[0x04 / 2] != d) {
282 case 0x06: // ignored, always 0
284 case 0x07: // DREQ ctl
285 REG8IN16(r, 0x07) &= ~(P32XS_68S|P32XS_DMA|P32XS_RV);
286 if (!(d & P32XS_68S)) {
287 Pico32x.dmac0_fifo_ptr = 0;
288 REG8IN16(r, 0x07) &= ~P32XS_FULL;
290 REG8IN16(r, 0x07) |= d & (P32XS_68S|P32XS_DMA|P32XS_RV);
292 case 0x08: // ignored, always 0
294 case 0x09: // DREQ src
295 REG8IN16(r, 0x09) = d;
298 REG8IN16(r, 0x0a) = d;
301 REG8IN16(r, 0x0b) = d & 0xfe;
303 case 0x0c: // ignored, always 0
305 case 0x0d: // DREQ dest
308 case 0x10: // DREQ len
312 REG8IN16(r, a) = d & 0xfc;
314 // DREQ FIFO - writes to odd addr go to fifo
315 // do writes to even work? Reads return 0
320 d = (REG8IN16(r, 0x12) << 8) | (d & 0xff);
321 REG8IN16(r, 0x12) = 0;
324 case 0x14: // ignored, always 0
331 case 0x1a: // what's this?
332 elprintf(EL_32X|EL_ANOMALY, "mystery w8 %02x %02x", a, d);
333 REG8IN16(r, a) = d & 0x01;
336 REG8IN16(r, a) = d & 0x01;
338 case 0x1c: // ignored, always 0
344 case 0x31: // PWM control
345 REG8IN16(r, a) &= ~0x0f;
346 REG8IN16(r, a) |= d & 0x0f;
349 case 0x32: // PWM cycle
350 REG8IN16(r, a) = d & 0x0f;
357 // PWM pulse regs.. Only writes to odd address send a value
358 // to FIFO; reads are 0 (except status bits)
367 d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
368 REG8IN16(r, a ^ 1) = 0;
370 case 0x3a: // ignored, always 0
378 p32x_pwm_write16(a & ~1, d, NULL, SekCyclesDone());
382 if ((a & 0x30) == 0x20) {
383 int cycles = SekCyclesDone();
386 if (REG8IN16(r, a) == d)
389 p32x_sync_sh2s(cycles);
392 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
393 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
394 comreg = 1 << (a & 0x0f) / 2;
395 Pico32x.comm_dirty |= comreg;
397 if (cycles - (int)msh2.m68krcycles_done > 120)
398 p32x_sync_sh2s(cycles);
403 static void p32x_reg_write16(u32 a, u32 d)
405 u16 *r = Pico32x.regs;
408 // for things like bset on comm port
412 case 0x00: // adapter ctl
413 if ((d ^ r[0]) & d & P32XS_nRES)
415 r[0] &= ~(P32XS_FM|P32XS_nRES|P32XS_ADEN);
416 r[0] |= d & (P32XS_FM|P32XS_nRES|P32XS_ADEN);
418 case 0x08: // DREQ src
424 case 0x0c: // DREQ dest
430 case 0x10: // DREQ len
433 case 0x12: // FIFO reg
436 case 0x1a: // TV + mystery bit
437 r[a / 2] = d & 0x0101;
439 case 0x30: // PWM control
440 d = (r[a / 2] & ~0x0f) | (d & 0x0f);
442 p32x_pwm_write16(a, d, NULL, SekCyclesDone());
447 if ((a & 0x30) == 0x20) {
448 int cycles = SekCyclesDone();
451 p32x_sync_sh2s(cycles);
454 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
455 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
456 comreg = 1 << (a & 0x0f) / 2;
457 Pico32x.comm_dirty |= comreg;
461 else if ((a & 0x30) == 0x30) {
462 p32x_pwm_write16(a, d, NULL, SekCyclesDone());
466 p32x_reg_write8(a + 1, d);
469 // ------------------------------------------------------------------
471 static u32 p32x_vdp_read16(u32 a)
476 d = Pico32x.vdp_regs[a / 2];
478 // tested: FEN seems to be randomly pulsing on hcnt 0x80-0xf0,
479 // most often at 0xb1-0xb5, even during vblank,
480 // what's the deal with that?
481 // we'll just fake it along with hblank for now
482 Pico32x.vdp_fbcr_fake++;
483 if (Pico32x.vdp_fbcr_fake & 4)
485 if ((Pico32x.vdp_fbcr_fake & 7) == 0)
491 static void p32x_vdp_write8(u32 a, u32 d)
493 u16 *r = Pico32x.vdp_regs;
496 // TODO: verify what's writeable
499 // priority inversion is handled in palette
500 if ((r[0] ^ d) & P32XV_PRI)
501 Pico32x.dirty_pal = 1;
502 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
504 case 0x03: // shift (for pp mode)
507 case 0x05: // fill len
512 Pico32x.pending_fb = d;
513 // if we are blanking and FS bit is changing
514 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
515 r[0x0a/2] ^= P32XV_FS;
516 Pico32xSwapDRAM(d ^ 1);
517 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
523 static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
526 if (a == 6) { // fill start
527 Pico32x.vdp_regs[6 / 2] = d;
530 if (a == 8) { // fill data
531 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
532 int len = Pico32x.vdp_regs[4 / 2] + 1;
534 a = Pico32x.vdp_regs[6 / 2];
537 a = (a & 0xff00) | ((a + 1) & 0xff);
539 Pico32x.vdp_regs[0x06 / 2] = a;
540 Pico32x.vdp_regs[0x08 / 2] = d;
541 if (sh2 != NULL && len > 4) {
542 Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
543 // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
544 p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
549 p32x_vdp_write8(a | 1, d);
552 // ------------------------------------------------------------------
555 static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
557 u16 *r = Pico32x.regs;
561 case 0x00: // adapter/irq ctl
562 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0]
563 | Pico32x.sh2irq_mask[sh2->is_slave];
564 case 0x04: // H count (often as comm too)
565 sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
566 sh2s_sync_on_read(sh2);
567 return Pico32x.sh2_regs[4 / 2];
569 return (r[a / 2] & ~P32XS_FULL) | 0x4000;
570 case 0x08: // DREQ src
572 case 0x0c: // DREQ dst
574 case 0x10: // DREQ len
576 case 0x12: // DREQ FIFO - does this work on hw?
577 if (Pico32x.dmac0_fifo_ptr > 0) {
578 Pico32x.dmac0_fifo_ptr--;
579 r[a / 2] = Pico32x.dmac_fifo[0];
580 memmove(&Pico32x.dmac_fifo[0], &Pico32x.dmac_fifo[1],
581 Pico32x.dmac0_fifo_ptr * 2);
593 if ((a & 0x30) == 0x20) {
594 sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
595 sh2s_sync_on_read(sh2);
598 if ((a & 0x30) == 0x30)
599 return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
601 elprintf_sh2(sh2, EL_32X|EL_ANOMALY,
602 "unhandled sysreg r16 [%02x] @%08x", a, sh2_pc(sh2));
606 static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
608 u16 *r = Pico32x.regs;
617 r[0] |= (d << 8) & P32XS_FM;
619 case 0x01: // HEN/irq masks
620 old = Pico32x.sh2irq_mask[sh2->is_slave];
622 p32x_pwm_sync_to_sh2(sh2);
624 Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x0f;
625 Pico32x.sh2_regs[0] &= ~0x80;
626 Pico32x.sh2_regs[0] |= d & 0x80;
629 p32x_pwm_schedule_sh2(sh2);
631 p32x_update_cmd_irq(sh2, 0);
633 p32x_schedule_hint(sh2, 0);
635 case 0x04: // ignored?
637 case 0x05: // H count
639 if (Pico32x.sh2_regs[4 / 2] != d) {
640 Pico32x.sh2_regs[4 / 2] = d;
641 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
642 sh2_cycles_done_m68k(sh2));
647 REG8IN16(r, a) = d & 0x0f;
650 case 0x31: // PWM control
651 REG8IN16(r, a) = d & 0x8f;
654 case 0x32: // PWM cycle
655 REG8IN16(r, a) = d & 0x0f;
662 // PWM pulse regs.. Only writes to odd address send a value
663 // to FIFO; reads are 0 (except status bits)
672 d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
673 REG8IN16(r, a ^ 1) = 0;
675 case 0x3a: // ignored, always 0?
683 p32x_pwm_write16(a & ~1, d, sh2, 0);
687 if ((a & 0x30) == 0x20) {
689 if (REG8IN16(r, a) == d)
693 p32x_m68k_poll_event(P32XF_68KCPOLL);
694 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
695 sh2_cycles_done_m68k(sh2));
696 comreg = 1 << (a & 0x0f) / 2;
697 Pico32x.comm_dirty |= comreg;
701 elprintf(EL_32X|EL_ANOMALY,
702 "unhandled sysreg w8 [%02x] %02x @%08x", a, d, sh2_pc(sh2));
705 static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
712 if ((a & 0x30) == 0x20) {
714 if (Pico32x.regs[a / 2] == d)
717 Pico32x.regs[a / 2] = d;
718 p32x_m68k_poll_event(P32XF_68KCPOLL);
719 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
720 sh2_cycles_done_m68k(sh2));
721 comreg = 1 << (a & 0x0f) / 2;
722 Pico32x.comm_dirty |= comreg;
726 else if ((a & 0x30) == 0x30) {
727 p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2));
733 Pico32x.regs[0] &= ~P32XS_FM;
734 Pico32x.regs[0] |= d & P32XS_FM;
737 Pico32x.sh2irqs &= ~P32XI_VRES;
740 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VINT;
743 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_HINT;
746 Pico32x.regs[2 / 2] &= ~(1 << sh2->is_slave);
747 p32x_update_cmd_irq(sh2, 0);
750 p32x_pwm_sync_to_sh2(sh2);
751 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_PWM;
752 p32x_pwm_schedule_sh2(sh2);
756 p32x_sh2reg_write8(a | 1, d, sh2);
760 p32x_update_irls(sh2, 0);
763 // ------------------------------------------------------------------
767 static u32 PicoRead8_32x_on(u32 a)
770 if ((a & 0xffc0) == 0x5100) { // a15100
771 d = p32x_reg_read16(a);
775 if ((a & 0xfc00) != 0x5000) {
776 if (PicoIn.AHW & PAHW_MCD)
777 return PicoRead8_mcd_io(a);
779 return PicoRead8_io(a);
782 if ((a & 0xfff0) == 0x5180) { // a15180
783 d = p32x_vdp_read16(a);
787 if ((a & 0xfe00) == 0x5200) { // a15200
788 d = Pico32xMem->pal[(a & 0x1ff) / 2];
792 if ((a & 0xfffc) == 0x30ec) { // a130ec
797 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
807 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
811 static u32 PicoRead16_32x_on(u32 a)
814 if ((a & 0xffc0) == 0x5100) { // a15100
815 d = p32x_reg_read16(a);
819 if ((a & 0xfc00) != 0x5000) {
820 if (PicoIn.AHW & PAHW_MCD)
821 return PicoRead16_mcd_io(a);
823 return PicoRead16_io(a);
826 if ((a & 0xfff0) == 0x5180) { // a15180
827 d = p32x_vdp_read16(a);
831 if ((a & 0xfe00) == 0x5200) { // a15200
832 d = Pico32xMem->pal[(a & 0x1ff) / 2];
836 if ((a & 0xfffc) == 0x30ec) { // a130ec
837 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
841 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
845 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
849 static void PicoWrite8_32x_on(u32 a, u32 d)
851 if ((a & 0xfc00) == 0x5000)
852 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
854 if ((a & 0xffc0) == 0x5100) { // a15100
855 p32x_reg_write8(a, d);
859 if ((a & 0xfc00) != 0x5000) {
860 if (PicoIn.AHW & PAHW_MCD)
861 PicoWrite8_mcd_io(a, d);
865 bank_switch(Pico32x.regs[4 / 2]);
869 if (!(Pico32x.regs[0] & P32XS_FM)) {
870 if ((a & 0xfff0) == 0x5180) { // a15180
871 p32x_vdp_write8(a, d);
876 if ((a & 0xfe00) == 0x5200) { // a15200
877 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
878 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
879 Pico32x.dirty_pal = 1;
884 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
887 static void PicoWrite16_32x_on(u32 a, u32 d)
889 if ((a & 0xfc00) == 0x5000)
890 elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
892 if ((a & 0xffc0) == 0x5100) { // a15100
893 p32x_reg_write16(a, d);
897 if ((a & 0xfc00) != 0x5000) {
898 if (PicoIn.AHW & PAHW_MCD)
899 PicoWrite16_mcd_io(a, d);
901 PicoWrite16_io(a, d);
903 bank_switch(Pico32x.regs[4 / 2]);
907 if (!(Pico32x.regs[0] & P32XS_FM)) {
908 if ((a & 0xfff0) == 0x5180) { // a15180
909 p32x_vdp_write16(a, d, NULL); // FIXME?
913 if ((a & 0xfe00) == 0x5200) { // a15200
914 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
915 Pico32x.dirty_pal = 1;
920 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
924 u32 PicoRead8_32x(u32 a)
928 if (PicoIn.opt & POPT_EN_32X) {
929 if ((a & 0xffc0) == 0x5100) { // a15100
930 // regs are always readable
931 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
935 if ((a & 0xfffc) == 0x30ec) { // a130ec
941 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
945 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
949 u32 PicoRead16_32x(u32 a)
953 if (PicoIn.opt & POPT_EN_32X) {
954 if ((a & 0xffc0) == 0x5100) { // a15100
955 d = Pico32x.regs[(a & 0x3f) / 2];
959 if ((a & 0xfffc) == 0x30ec) { // a130ec
960 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
965 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
969 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
973 void PicoWrite8_32x(u32 a, u32 d)
975 if ((PicoIn.opt & POPT_EN_32X) && (a & 0xffc0) == 0x5100) // a15100
977 u16 *r = Pico32x.regs;
979 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
982 if ((d ^ r[0]) & d & P32XS_ADEN) {
984 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
986 p32x_reg_write8(a, d); // forward for reset processing
991 // allow only COMM for now
992 if ((a & 0x30) == 0x20) {
999 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1002 void PicoWrite16_32x(u32 a, u32 d)
1004 if ((PicoIn.opt & POPT_EN_32X) && (a & 0xffc0) == 0x5100) // a15100
1006 u16 *r = Pico32x.regs;
1008 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1011 if ((d ^ r[0]) & d & P32XS_ADEN) {
1013 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
1015 p32x_reg_write16(a, d); // forward for reset processing
1020 // allow only COMM for now
1021 if ((a & 0x30) == 0x20)
1026 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1029 /* quirk: in both normal and overwrite areas only nonzero values go through */
1030 #define sh2_write8_dramN(n) \
1031 if ((d & 0xff) != 0) { \
1032 u8 *dram = (u8 *)Pico32xMem->dram[n]; \
1033 dram[(a & 0x1ffff) ^ 1] = d; \
1036 static void m68k_write8_dram0_ow(u32 a, u32 d)
1038 sh2_write8_dramN(0);
1041 static void m68k_write8_dram1_ow(u32 a, u32 d)
1043 sh2_write8_dramN(1);
1046 #define sh2_write16_dramN(n) \
1047 u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
1048 if (!(a & 0x20000)) { \
1053 if (!(d & 0xff00)) d |= *pd & 0xff00; \
1054 if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
1057 static void m68k_write16_dram0_ow(u32 a, u32 d)
1059 sh2_write16_dramN(0);
1062 static void m68k_write16_dram1_ow(u32 a, u32 d)
1064 sh2_write16_dramN(1);
1067 // -----------------------------------------------------------------
1069 // hint vector is writeable
1070 static void PicoWrite8_hint(u32 a, u32 d)
1072 if ((a & 0xfffc) == 0x0070) {
1073 Pico32xMem->m68k_rom[a ^ 1] = d;
1077 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x",
1078 a, d & 0xff, SekPc);
1081 static void PicoWrite16_hint(u32 a, u32 d)
1083 if ((a & 0xfffc) == 0x0070) {
1084 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
1088 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x",
1089 a, d & 0xffff, SekPc);
1092 // normally not writable, but somebody could make a RAM cart
1093 static void PicoWrite8_cart(u32 a, u32 d)
1095 elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1101 static void PicoWrite16_cart(u32 a, u32 d)
1103 elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1109 // same with bank, but save ram is sometimes here
1110 static u32 PicoRead8_bank(u32 a)
1112 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1113 return m68k_read8(a);
1116 static u32 PicoRead16_bank(u32 a)
1118 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1119 return m68k_read16(a);
1122 static void PicoWrite8_bank(u32 a, u32 d)
1124 if (!(Pico.m.sram_reg & SRR_MAPPED))
1125 elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x",
1126 a, d & 0xff, SekPc);
1128 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1132 static void PicoWrite16_bank(u32 a, u32 d)
1134 if (!(Pico.m.sram_reg & SRR_MAPPED))
1135 elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x",
1136 a, d & 0xffff, SekPc);
1138 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1142 static void bank_map_handler(void)
1144 cpu68k_map_set(m68k_read8_map, 0x900000, 0x9fffff, PicoRead8_bank, 1);
1145 cpu68k_map_set(m68k_read16_map, 0x900000, 0x9fffff, PicoRead16_bank, 1);
1148 static void bank_switch(int b)
1150 unsigned int rs, bank;
1152 if (Pico.m.ncart_in)
1156 if ((Pico.m.sram_reg & SRR_MAPPED) && bank == Pico.sv.start) {
1161 if (bank >= Pico.romsize) {
1162 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
1167 // 32X ROM (unbanked, XXX: consider mirroring?)
1168 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1172 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1173 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1175 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
1178 // -----------------------------------------------------------------
1180 // -----------------------------------------------------------------
1183 static u32 sh2_read8_unmapped(u32 a, SH2 *sh2)
1185 elprintf_sh2(sh2, EL_32X, "unmapped r8 [%08x] %02x @%06x",
1190 static u32 sh2_read8_cs0(u32 a, SH2 *sh2)
1194 sh2_burn_cycles(sh2, 1*2);
1196 // 0x3ffc0 is veridied
1197 if ((a & 0x3ffc0) == 0x4000) {
1198 d = p32x_sh2reg_read16(a, sh2);
1202 if ((a & 0x3fff0) == 0x4100) {
1203 d = p32x_vdp_read16(a);
1204 sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
1209 if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
1210 return Pico32xMem->sh2_rom_m.b[a ^ 1];
1211 if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
1212 return Pico32xMem->sh2_rom_s.b[a ^ 1];
1214 if ((a & 0x3fe00) == 0x4200) {
1215 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1219 return sh2_read8_unmapped(a, sh2);
1227 elprintf_sh2(sh2, EL_32X, "r8 [%08x] %02x @%06x",
1232 static u32 sh2_read8_da(u32 a, SH2 *sh2)
1234 return sh2->data_array[(a & 0xfff) ^ 1];
1238 static u32 sh2_read16_unmapped(u32 a, SH2 *sh2)
1240 elprintf_sh2(sh2, EL_32X, "unmapped r16 [%08x] %04x @%06x",
1245 static u32 sh2_read16_cs0(u32 a, SH2 *sh2)
1249 sh2_burn_cycles(sh2, 1*2);
1251 if ((a & 0x3ffc0) == 0x4000) {
1252 d = p32x_sh2reg_read16(a, sh2);
1253 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
1258 if ((a & 0x3fff0) == 0x4100) {
1259 d = p32x_vdp_read16(a);
1260 sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
1264 if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
1265 return Pico32xMem->sh2_rom_m.w[a / 2];
1266 if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
1267 return Pico32xMem->sh2_rom_s.w[a / 2];
1269 if ((a & 0x3fe00) == 0x4200) {
1270 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1274 return sh2_read16_unmapped(a, sh2);
1277 elprintf_sh2(sh2, EL_32X, "r16 [%08x] %04x @%06x",
1282 static u32 sh2_read16_da(u32 a, SH2 *sh2)
1284 return ((u16 *)sh2->data_array)[(a & 0xfff) / 2];
1288 static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
1293 static void REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, SH2 *sh2)
1295 elprintf_sh2(sh2, EL_32X, "unmapped w8 [%08x] %02x @%06x",
1296 a, d & 0xff, sh2_pc(sh2));
1299 static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
1301 elprintf_sh2(sh2, EL_32X, "w8 [%08x] %02x @%06x",
1302 a, d & 0xff, sh2_pc(sh2));
1304 if (Pico32x.regs[0] & P32XS_FM) {
1305 if ((a & 0x3fff0) == 0x4100) {
1307 p32x_vdp_write8(a, d);
1312 if ((a & 0x3ffc0) == 0x4000) {
1313 p32x_sh2reg_write8(a, d, sh2);
1317 sh2_write8_unmapped(a, d, sh2);
1320 static void REGPARM(3) sh2_write8_dram0(u32 a, u32 d, SH2 *sh2)
1322 sh2_write8_dramN(0);
1325 static void REGPARM(3) sh2_write8_dram1(u32 a, u32 d, SH2 *sh2)
1327 sh2_write8_dramN(1);
1330 static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
1332 u32 a1 = a & 0x3ffff;
1334 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1336 sh2_drc_wcheck_ram(a, t, sh2->is_slave);
1338 Pico32xMem->sdram[a1 ^ 1] = d;
1341 static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2)
1345 sh2_end_run(sh2, 32);
1347 sh2_write8_sdram(a, d, sh2);
1350 static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
1354 int id = sh2->is_slave;
1355 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1357 sh2_drc_wcheck_da(a, t, id);
1359 sh2->data_array[a1 ^ 1] = d;
1363 static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2)
1365 elprintf_sh2(sh2, EL_32X, "unmapped w16 [%08x] %04x @%06x",
1366 a, d & 0xffff, sh2_pc(sh2));
1369 static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
1371 if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1372 elprintf_sh2(sh2, EL_32X, "w16 [%08x] %04x @%06x",
1373 a, d & 0xffff, sh2_pc(sh2));
1375 if (Pico32x.regs[0] & P32XS_FM) {
1376 if ((a & 0x3fff0) == 0x4100) {
1378 p32x_vdp_write16(a, d, sh2);
1382 if ((a & 0x3fe00) == 0x4200) {
1383 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1384 Pico32x.dirty_pal = 1;
1389 if ((a & 0x3ffc0) == 0x4000) {
1390 p32x_sh2reg_write16(a, d, sh2);
1394 sh2_write16_unmapped(a, d, sh2);
1397 static void REGPARM(3) sh2_write16_dram0(u32 a, u32 d, SH2 *sh2)
1399 sh2_write16_dramN(0);
1402 static void REGPARM(3) sh2_write16_dram1(u32 a, u32 d, SH2 *sh2)
1404 sh2_write16_dramN(1);
1407 static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2)
1409 u32 a1 = a & 0x3ffff;
1411 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1413 sh2_drc_wcheck_ram(a, t, sh2->is_slave);
1415 ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
1418 static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2)
1422 int id = sh2->is_slave;
1423 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1425 sh2_drc_wcheck_da(a, t, id);
1427 ((u16 *)sh2->data_array)[a1 / 2] = d;
1431 typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2);
1432 typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2);
1434 #define SH2MAP_ADDR2OFFS_R(a) \
1435 ((u32)(a) >> SH2_READ_SHIFT)
1437 #define SH2MAP_ADDR2OFFS_W(a) \
1438 ((u32)(a) >> SH2_WRITE_SHIFT)
1440 u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
1442 const sh2_memmap *sh2_map = sh2->read8_map;
1445 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1447 if (map_flag_set(p))
1448 return ((sh2_read_handler *)(p << 1))(a, sh2);
1450 return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
1453 u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
1455 const sh2_memmap *sh2_map = sh2->read16_map;
1458 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1460 if (map_flag_set(p))
1461 return ((sh2_read_handler *)(p << 1))(a, sh2);
1463 return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1466 u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
1468 const sh2_memmap *sh2_map = sh2->read16_map;
1469 sh2_read_handler *handler;
1473 offs = SH2MAP_ADDR2OFFS_R(a);
1476 if (!map_flag_set(p)) {
1477 // XXX: maybe 32bit access instead with ror?
1478 u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1479 return (pd[0] << 16) | pd[1];
1482 if (offs == SH2MAP_ADDR2OFFS_R(0xffffc000))
1483 return sh2_peripheral_read32(a, sh2);
1485 handler = (sh2_read_handler *)(p << 1);
1486 return (handler(a, sh2) << 16) | handler(a + 2, sh2);
1489 void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
1491 const void **sh2_wmap = sh2->write8_tab;
1492 sh2_write_handler *wh;
1494 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1498 void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
1500 const void **sh2_wmap = sh2->write16_tab;
1501 sh2_write_handler *wh;
1503 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1507 void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
1509 const void **sh2_wmap = sh2->write16_tab;
1510 sh2_write_handler *wh;
1513 offs = SH2MAP_ADDR2OFFS_W(a);
1515 if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
1516 sh2_peripheral_write32(a, d, sh2);
1520 wh = sh2_wmap[offs];
1521 wh(a, d >> 16, sh2);
1525 // -----------------------------------------------------------------
1527 static void z80_md_bank_write_32x(unsigned int a, unsigned char d)
1529 unsigned int addr68k;
1531 addr68k = Pico.m.z80_bank68k << 15;
1532 addr68k += a & 0x7fff;
1533 if ((addr68k & 0xfff000) == 0xa15000)
1534 Pico32x.emu_flags |= P32XF_Z80_32X_IO;
1536 elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, d);
1537 m68k_write8(addr68k, d);
1540 // -----------------------------------------------------------------
1542 static const u16 msh2_code[] = {
1543 // trap instructions
1544 0xaffe, // 200 bra <self>
1546 // have to wait a bit until m68k initial program finishes clearing stuff
1547 // to avoid races with game SH2 code, like in Tempo
1548 0xd406, // 204 mov.l @(_m_ok,pc), r4
1549 0xc400, // 206 mov.b @(h'0,gbr),r0
1550 0xc801, // 208 tst #1, r0
1551 0x8b0f, // 20a bf cd_start
1552 0xd105, // 20c mov.l @(_cnt,pc), r1
1553 0xd206, // 20e mov.l @(_start,pc), r2
1554 0x71ff, // 210 add #-1, r1
1555 0x4115, // 212 cmp/pl r1
1556 0x89fc, // 214 bt -2
1557 0x6043, // 216 mov r4, r0
1558 0xc208, // 218 mov.l r0, @(h'20,gbr)
1559 0x6822, // 21a mov.l @r2, r8
1560 0x482b, // 21c jmp @r8
1562 ('M'<<8)|'_', ('O'<<8)|'K', // 220 _m_ok
1563 0x0001, 0x0000, // 224 _cnt
1564 0x2200, 0x03e0, // master start pointer in ROM
1566 0xd20d, // 22c mov.l @(__cd_,pc), r2
1567 0xc608, // 22e mov.l @(h'20,gbr), r0
1568 0x3200, // 230 cmp/eq r0, r2
1569 0x8bfc, // 232 bf #-2
1570 0xe000, // 234 mov #0, r0
1571 0xcf80, // 236 or.b #0x80,@(r0,gbr)
1572 0xd80b, // 238 mov.l @(_start_cd,pc), r8 // 24000018
1573 0xd30c, // 23a mov.l @(_max_len,pc), r3
1574 0x5b84, // 23c mov.l @(h'10,r8), r11 // master vbr
1575 0x5a82, // 23e mov.l @(8,r8), r10 // entry
1576 0x5081, // 240 mov.l @(4,r8), r0 // len
1577 0x5980, // 242 mov.l @(0,r8), r9 // dst
1578 0x3036, // 244 cmp/hi r3,r0
1579 0x8b00, // 246 bf #1
1580 0x6033, // 248 mov r3,r0
1581 0x7820, // 24a add #0x20, r8
1583 0x6286, // 24c mov.l @r8+, r2
1584 0x2922, // 24e mov.l r2, @r9
1585 0x7904, // 250 add #4, r9
1586 0x70fc, // 252 add #-4, r0
1587 0x8800, // 254 cmp/eq #0, r0
1588 0x8bf9, // 256 bf #-5
1590 0x4b2e, // 258 ldc r11, vbr
1591 0x6043, // 25a mov r4, r0 // M_OK
1592 0xc208, // 25c mov.l r0, @(h'20,gbr)
1593 0x4a2b, // 25e jmp @r10
1595 0x0009, // 262 nop // pad
1596 ('_'<<8)|'C', ('D'<<8)|'_', // 264 __cd_
1597 0x2400, 0x0018, // 268 _start_cd
1598 0x0001, 0xffe0, // 26c _max_len
1601 static const u16 ssh2_code[] = {
1602 0xaffe, // 200 bra <self>
1604 // code to wait for master, in case authentic master BIOS is used
1605 0xd106, // 204 mov.l @(_m_ok,pc), r1
1606 0xd208, // 206 mov.l @(_start,pc), r2
1607 0xc608, // 208 mov.l @(h'20,gbr), r0
1608 0x3100, // 20a cmp/eq r0, r1
1609 0x8bfc, // 20c bf #-2
1610 0xc400, // 20e mov.b @(h'0,gbr),r0
1611 0xc801, // 210 tst #1, r0
1612 0xd004, // 212 mov.l @(_s_ok,pc), r0
1613 0x8b0a, // 214 bf cd_start
1614 0xc209, // 216 mov.l r0, @(h'24,gbr)
1615 0x6822, // 218 mov.l @r2, r8
1616 0x482b, // 21a jmp @r8
1619 ('M'<<8)|'_', ('O'<<8)|'K', // 220
1620 ('S'<<8)|'_', ('O'<<8)|'K', // 224
1621 0x2200, 0x03e4, // slave start pointer in ROM
1623 0xd803, // 22c mov.l @(_start_cd,pc), r8 // 24000018
1624 0x5b85, // 22e mov.l @(h'14,r8), r11 // slave vbr
1625 0x5a83, // 230 mov.l @(h'0c,r8), r10 // entry
1626 0x4b2e, // 232 ldc r11, vbr
1627 0xc209, // 234 mov.l r0, @(h'24,gbr) // write S_OK
1628 0x4a2b, // 236 jmp @r10
1631 0x2400, 0x0018, // 23c _start_cd
1634 #define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16))
1635 static void get_bios(void)
1642 if (p32x_bios_g != NULL) {
1643 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1644 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
1648 ps = (u16 *)Pico32xMem->m68k_rom;
1650 for (i = 1; i < 0xc0/4; i++)
1651 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1654 for (i = 0xc0/2; i < 0x100/2; i++)
1658 ps[0xc0/2] = 0x46fc;
1659 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1660 ps[0xfe/2] = 0x60fe; // jump to self
1662 ps[0xfe/2] = 0x4e75; // rts
1665 // fill remaining m68k_rom page with game ROM
1666 memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
1667 Pico.rom + sizeof(Pico32xMem->m68k_rom),
1668 sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
1671 if (p32x_bios_m != NULL) {
1672 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1673 Byteswap(&Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1676 pl = (u32 *)&Pico32xMem->sh2_rom_m;
1678 // fill exception vector table to our trap address
1679 for (i = 0; i < 128; i++)
1680 pl[i] = HWSWAP(0x200);
1683 pl[0] = pl[2] = HWSWAP(0x204);
1685 pl[1] = pl[3] = HWSWAP(0x6040000);
1688 memcpy(&Pico32xMem->sh2_rom_m.b[0x200], msh2_code, sizeof(msh2_code));
1692 if (p32x_bios_s != NULL) {
1693 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1694 Byteswap(&Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1697 pl = (u32 *)&Pico32xMem->sh2_rom_s;
1699 // fill exception vector table to our trap address
1700 for (i = 0; i < 128; i++)
1701 pl[i] = HWSWAP(0x200);
1704 pl[0] = pl[2] = HWSWAP(0x204);
1706 pl[1] = pl[3] = HWSWAP(0x603f800);
1709 memcpy(&Pico32xMem->sh2_rom_s.b[0x200], ssh2_code, sizeof(ssh2_code));
1713 #define MAP_MEMORY(m) ((uptr)(m) >> 1)
1714 #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
1716 static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80];
1717 // for writes we are using handlers only
1718 static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
1720 void Pico32xSwapDRAM(int b)
1722 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1723 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1724 cpu68k_map_set(m68k_read8_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1725 cpu68k_map_set(m68k_read16_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1726 cpu68k_map_set(m68k_write8_map, 0x840000, 0x87ffff,
1727 b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1);
1728 cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff,
1729 b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
1732 sh2_read8_map[0x04/2].addr = sh2_read8_map[0x24/2].addr =
1733 sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
1735 sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
1736 sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
1739 void PicoMemSetup32x(void)
1744 Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
1745 if (Pico32xMem == NULL) {
1746 elprintf(EL_STATUS, "OOM");
1752 // cartridge area becomes unmapped
1753 // XXX: we take the easy way and don't unmap ROM,
1754 // so that we can avoid handling the RV bit.
1755 // m68k_map_unmap(0x000000, 0x3fffff);
1757 if (!Pico.m.ncart_in) {
1759 rs = sizeof(Pico32xMem->m68k_rom_bank);
1760 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1761 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1762 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1763 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1765 // 32X ROM (unbanked, XXX: consider mirroring?)
1766 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1769 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1770 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1771 cpu68k_map_set(m68k_write8_map, 0x880000, 0x880000 + rs - 1, PicoWrite8_cart, 1);
1772 cpu68k_map_set(m68k_write16_map, 0x880000, 0x880000 + rs - 1, PicoWrite16_cart, 1);
1774 // setup FAME fetchmap
1775 PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
1776 for (rs = 0x88; rs < 0x90; rs++)
1777 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
1782 cpu68k_map_set(m68k_write8_map, 0x900000, 0x9fffff, PicoWrite8_bank, 1);
1783 cpu68k_map_set(m68k_write16_map, 0x900000, 0x9fffff, PicoWrite16_bank, 1);
1787 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1788 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1789 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1790 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1792 // SH2 maps: A31,A30,A29,CS1,CS0
1793 // all unmapped by default
1794 for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
1795 sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
1796 sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
1799 for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
1800 sh2_write8_map[i] = sh2_write8_unmapped;
1801 sh2_write16_map[i] = sh2_write16_unmapped;
1805 for (i = 0x40; i <= 0x5f; i++) {
1806 sh2_write8_map[i >> 1] =
1807 sh2_write16_map[i >> 1] = sh2_write_ignore;
1811 sh2_read8_map[0x00/2].addr = sh2_read8_map[0x20/2].addr = MAP_HANDLER(sh2_read8_cs0);
1812 sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0);
1813 sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
1814 sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
1816 sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr =
1817 sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
1818 sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask =
1819 sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME
1820 // CS2 - DRAM - done by Pico32xSwapDRAM()
1821 sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask =
1822 sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff;
1824 sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
1825 sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
1826 sh2_write8_map[0x06/2] = sh2_write8_sdram;
1827 sh2_write8_map[0x26/2] = sh2_write8_sdram_wt;
1828 sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
1829 sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask =
1830 sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03ffff;
1832 sh2_read8_map[0xc0/2].addr = MAP_HANDLER(sh2_read8_da);
1833 sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da);
1834 sh2_write8_map[0xc0/2] = sh2_write8_da;
1835 sh2_write16_map[0xc0/2] = sh2_write16_da;
1837 sh2_read8_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read8);
1838 sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16);
1839 sh2_write8_map[0xff/2] = sh2_peripheral_write8;
1840 sh2_write16_map[0xff/2] = sh2_peripheral_write16;
1842 // map DRAM area, both 68k and SH2
1845 msh2.read8_map = ssh2.read8_map = sh2_read8_map;
1846 msh2.read16_map = ssh2.read16_map = sh2_read16_map;
1847 msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
1848 msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
1850 sh2_drc_mem_setup(&msh2);
1851 sh2_drc_mem_setup(&ssh2);
1854 z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write_32x, 1);
1857 void Pico32xMemStateLoaded(void)
1859 bank_switch(Pico32x.regs[4 / 2]);
1860 Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
1861 memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
1862 Pico32x.dirty_pal = 1;
1864 Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
1865 memset(&m68k_poll, 0, sizeof(m68k_poll));
1867 msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
1869 ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
1871 sh2_drc_flush_all();
1874 // vim:shiftwidth=2:ts=2:expandtab