3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
10 * a15102 ........ ......SM ? 4002 // intS intM
11 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
12 * a15106 ........ F....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
13 * a15108 (32bit DREQ src) 4008
14 * a1510c (32bit DREQ dst) 400c
15 * a15110 llllllll llllll00 4010 // DREQ Len
16 * a15112 (16bit FIFO reg) 4012
17 * a15114 0 (16bit VRES clr) 4014
18 * a15116 0 (16bit Vint clr) 4016
19 * a15118 0 (16bit Hint clr) 4018
20 * a1511a .......? .......C (16bit CMD clr) 401a // TV Cm
21 * a1511c 0 (16bit PWM clr) 401c
23 * a15120 (16 bytes comm) 2020
27 * iii. .cc. ..xx * // Internal, Cs, x
29 * sh2 map, wait/bus cycles (from docs):
31 * rom 0000000-0003fff 1 -
32 * sys reg 0004000-00040ff 1 1
33 * vdp reg 0004100-00041ff 5 5
34 * vdp pal 0004200-00043ff 5 5
35 * cart 2000000-23fffff 6-15
36 * dram/fb 4000000-401ffff 5-12 1-3
37 * fb ovr 4020000-403ffff
38 * sdram 6000000-603ffff 12 2 (cycles)
41 #include "../pico_int.h"
42 #include "../memory.h"
43 #include "../../cpu/sh2/compiler.h"
45 static const char str_mars[] = "MARS";
47 void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
48 struct Pico32xMem *Pico32xMem;
50 static void bank_switch_rom_68k(int b);
52 static void (*m68k_write8_io)(u32 a, u32 d);
53 static void (*m68k_write16_io)(u32 a, u32 d);
55 // addressing byte in 16bit reg
56 #define REG8IN16(ptr, offs) ((u8 *)ptr)[(offs) ^ 1]
59 #define POLL_THRESHOLD 3
66 static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
70 if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
71 && cycles - m68k_poll.cycles <= 64 && !SekNotPolling)
73 if (m68k_poll.cnt++ > POLL_THRESHOLD) {
74 if (!(Pico32x.emu_flags & flags)) {
75 elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
76 a, cycles - m68k_poll.cycles);
79 Pico32x.emu_flags |= flags;
87 m68k_poll.cycles = cycles;
92 void p32x_m68k_poll_event(u32 flags)
94 if (Pico32x.emu_flags & flags) {
95 elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
96 Pico32x.emu_flags & ~flags);
97 Pico32x.emu_flags &= ~flags;
100 m68k_poll.addr = m68k_poll.cnt = 0;
103 static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags, int maxcnt)
105 int cycles_left = sh2_cycles_left(sh2);
107 if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
108 if (sh2->poll_cnt++ > maxcnt) {
109 if (!(sh2->state & flags))
110 elprintf_sh2(sh2, EL_32X, "state: %02x->%02x",
111 sh2->state, sh2->state | flags);
115 pevt_log_sh2(sh2, EVT_POLL_START);
122 sh2->poll_cycles = cycles_left;
125 void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
127 if (sh2->state & flags) {
128 elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", sh2->state,
129 sh2->state & ~flags);
131 if (sh2->m68krcycles_done < m68k_cycles)
132 sh2->m68krcycles_done = m68k_cycles;
134 pevt_log_sh2_o(sh2, EVT_POLL_END);
137 sh2->state &= ~flags;
138 sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
141 static void sh2s_sync_on_read(SH2 *sh2)
144 if (sh2->poll_cnt != 0)
147 cycles = sh2_cycles_done(sh2);
149 p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3);
155 static int p32x_csum_faked;
156 static const u16 comm_fakevals[] = {
157 0x4d5f, 0x4f4b, // M_OK
158 0x535f, 0x4f4b, // S_OK
159 0x4D41, 0x5346, // MASF - Brutal Unleashed
160 0x5331, 0x4d31, // Darxide
163 0x0000, 0x0000, // eq for doom
164 0x0002, // Mortal Kombat
168 static u32 sh2_comm_faker(u32 a)
171 if (a == 0x28 && !p32x_csum_faked) {
173 return *(unsigned short *)(Pico.rom + 0x18e);
175 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
177 return comm_fakevals[f++];
181 // ------------------------------------------------------------------
184 static u32 p32x_reg_read16(u32 a)
189 if ((a & 0x30) == 0x20)
190 return sh2_comm_faker(a);
192 if ((a & 0x30) == 0x20) {
193 unsigned int cycles = SekCyclesDone();
194 int comreg = 1 << (a & 0x0f) / 2;
196 if (cycles - msh2.m68krcycles_done > 244
197 || (Pico32x.comm_dirty & comreg))
198 p32x_sync_sh2s(cycles);
200 if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
208 if (a == 2) { // INTM, INTS
209 unsigned int cycles = SekCyclesDone();
210 if (cycles - msh2.m68krcycles_done > 64)
211 p32x_sync_sh2s(cycles);
215 if ((a & 0x30) == 0x30)
216 return p32x_pwm_read16(a, NULL, SekCyclesDone());
219 return Pico32x.regs[a / 2];
222 static void dreq0_write(u16 *r, u32 d)
224 if (!(r[6 / 2] & P32XS_68S)) {
225 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
226 return; // ignored - tested
228 if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
229 Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
230 if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
231 r[6 / 2] |= P32XS_FULL;
232 // tested: len register decrements and 68S clears
233 // even if SH2s/DMAC aren't active..
235 if (r[0x10 / 2] == 0)
236 r[6 / 2] &= ~P32XS_68S;
238 if ((Pico32x.dmac0_fifo_ptr & 3) == 0) {
239 p32x_sync_sh2s(SekCyclesDone());
240 p32x_dreq0_trigger();
244 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO overflow!");
247 // writable bits tested
248 static void p32x_reg_write8(u32 a, u32 d)
250 u16 *r = Pico32x.regs;
253 // for things like bset on comm port
257 case 0x00: // adapter ctl: FM writable
258 REG8IN16(r, 0x00) = d & 0x80;
260 case 0x01: // adapter ctl: RES and ADEN writable
261 if ((d ^ r[0]) & d & P32XS_nRES)
263 REG8IN16(r, 0x01) &= ~(P32XS_nRES|P32XS_ADEN);
264 REG8IN16(r, 0x01) |= d & (P32XS_nRES|P32XS_ADEN);
266 case 0x02: // ignored, always 0
268 case 0x03: // irq ctl
269 if ((d ^ r[0x02 / 2]) & 3) {
270 int cycles = SekCyclesDone();
271 p32x_sync_sh2s(cycles);
273 p32x_update_cmd_irq(NULL, cycles);
276 case 0x04: // ignored, always 0
280 if (r[0x04 / 2] != d) {
282 bank_switch_rom_68k(d);
285 case 0x06: // ignored, always 0
287 case 0x07: // DREQ ctl
288 REG8IN16(r, 0x07) &= ~(P32XS_68S|P32XS_DMA|P32XS_RV);
289 if (!(d & P32XS_68S)) {
290 Pico32x.dmac0_fifo_ptr = 0;
291 REG8IN16(r, 0x07) &= ~P32XS_FULL;
293 REG8IN16(r, 0x07) |= d & (P32XS_68S|P32XS_DMA|P32XS_RV);
295 case 0x08: // ignored, always 0
297 case 0x09: // DREQ src
298 REG8IN16(r, 0x09) = d;
301 REG8IN16(r, 0x0a) = d;
304 REG8IN16(r, 0x0b) = d & 0xfe;
306 case 0x0c: // ignored, always 0
308 case 0x0d: // DREQ dest
311 case 0x10: // DREQ len
315 REG8IN16(r, a) = d & 0xfc;
317 // DREQ FIFO - writes to odd addr go to fifo
318 // do writes to even work? Reads return 0
323 d = (REG8IN16(r, 0x12) << 8) | (d & 0xff);
324 REG8IN16(r, 0x12) = 0;
327 case 0x14: // ignored, always 0
334 case 0x1a: // what's this?
335 elprintf(EL_32X|EL_ANOMALY, "mystery w8 %02x %02x", a, d);
336 REG8IN16(r, a) = d & 0x01;
339 REG8IN16(r, a) = d & 0x01;
341 case 0x1c: // ignored, always 0
347 case 0x31: // PWM control
348 REG8IN16(r, a) &= ~0x0f;
349 REG8IN16(r, a) |= d & 0x0f;
352 case 0x32: // PWM cycle
353 REG8IN16(r, a) = d & 0x0f;
360 // PWM pulse regs.. Only writes to odd address send a value
361 // to FIFO; reads are 0 (except status bits)
370 d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
371 REG8IN16(r, a ^ 1) = 0;
373 case 0x3a: // ignored, always 0
381 p32x_pwm_write16(a & ~1, d, NULL, SekCyclesDone());
385 if ((a & 0x30) == 0x20) {
386 int cycles = SekCyclesDone();
389 if (REG8IN16(r, a) == d)
392 p32x_sync_sh2s(cycles);
395 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
396 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
397 comreg = 1 << (a & 0x0f) / 2;
398 Pico32x.comm_dirty |= comreg;
400 if (cycles - (int)msh2.m68krcycles_done > 120)
401 p32x_sync_sh2s(cycles);
406 static void p32x_reg_write16(u32 a, u32 d)
408 u16 *r = Pico32x.regs;
411 // for things like bset on comm port
415 case 0x00: // adapter ctl
416 if ((d ^ r[0]) & d & P32XS_nRES)
418 r[0] &= ~(P32XS_FM|P32XS_nRES|P32XS_ADEN);
419 r[0] |= d & (P32XS_FM|P32XS_nRES|P32XS_ADEN);
421 case 0x08: // DREQ src
427 case 0x0c: // DREQ dest
433 case 0x10: // DREQ len
436 case 0x12: // FIFO reg
439 case 0x1a: // TV + mystery bit
440 r[a / 2] = d & 0x0101;
442 case 0x30: // PWM control
443 d = (r[a / 2] & ~0x0f) | (d & 0x0f);
445 p32x_pwm_write16(a, d, NULL, SekCyclesDone());
450 if ((a & 0x30) == 0x20) {
451 int cycles = SekCyclesDone();
454 p32x_sync_sh2s(cycles);
457 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
458 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
459 comreg = 1 << (a & 0x0f) / 2;
460 Pico32x.comm_dirty |= comreg;
464 else if ((a & 0x30) == 0x30) {
465 p32x_pwm_write16(a, d, NULL, SekCyclesDone());
469 p32x_reg_write8(a + 1, d);
472 // ------------------------------------------------------------------
474 static u32 p32x_vdp_read16(u32 a)
479 d = Pico32x.vdp_regs[a / 2];
481 // tested: FEN seems to be randomly pulsing on hcnt 0x80-0xf0,
482 // most often at 0xb1-0xb5, even during vblank,
483 // what's the deal with that?
484 // we'll just fake it along with hblank for now
485 Pico32x.vdp_fbcr_fake++;
486 if (Pico32x.vdp_fbcr_fake & 4)
488 if ((Pico32x.vdp_fbcr_fake & 7) == 0)
494 static void p32x_vdp_write8(u32 a, u32 d)
496 u16 *r = Pico32x.vdp_regs;
499 // TODO: verify what's writeable
502 // priority inversion is handled in palette
503 if ((r[0] ^ d) & P32XV_PRI)
504 Pico32x.dirty_pal = 1;
505 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
507 case 0x03: // shift (for pp mode)
510 case 0x05: // fill len
515 Pico32x.pending_fb = d;
516 // if we are blanking and FS bit is changing
517 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
518 r[0x0a/2] ^= P32XV_FS;
519 Pico32xSwapDRAM(d ^ 1);
520 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
526 static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
529 if (a == 6) { // fill start
530 Pico32x.vdp_regs[6 / 2] = d;
533 if (a == 8) { // fill data
534 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
535 int len = Pico32x.vdp_regs[4 / 2] + 1;
537 a = Pico32x.vdp_regs[6 / 2];
540 a = (a & 0xff00) | ((a + 1) & 0xff);
542 Pico32x.vdp_regs[0x06 / 2] = a;
543 Pico32x.vdp_regs[0x08 / 2] = d;
544 if (sh2 != NULL && len > 4) {
545 Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
546 // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
547 p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
552 p32x_vdp_write8(a | 1, d);
555 // ------------------------------------------------------------------
558 static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
560 u16 *r = Pico32x.regs;
564 case 0x00: // adapter/irq ctl
565 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0]
566 | Pico32x.sh2irq_mask[sh2->is_slave];
567 case 0x04: // H count (often as comm too)
568 sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
569 sh2s_sync_on_read(sh2);
570 return Pico32x.sh2_regs[4 / 2];
572 return (r[a / 2] & ~P32XS_FULL) | 0x4000;
573 case 0x08: // DREQ src
575 case 0x0c: // DREQ dst
577 case 0x10: // DREQ len
579 case 0x12: // DREQ FIFO - does this work on hw?
580 if (Pico32x.dmac0_fifo_ptr > 0) {
581 Pico32x.dmac0_fifo_ptr--;
582 r[a / 2] = Pico32x.dmac_fifo[0];
583 memmove(&Pico32x.dmac_fifo[0], &Pico32x.dmac_fifo[1],
584 Pico32x.dmac0_fifo_ptr * 2);
596 if ((a & 0x30) == 0x20) {
597 sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
598 sh2s_sync_on_read(sh2);
601 if ((a & 0x30) == 0x30)
602 return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
604 elprintf_sh2(sh2, EL_32X|EL_ANOMALY,
605 "unhandled sysreg r16 [%02x] @%08x", a, sh2_pc(sh2));
609 static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
611 u16 *r = Pico32x.regs;
620 r[0] |= (d << 8) & P32XS_FM;
622 case 0x01: // HEN/irq masks
623 old = Pico32x.sh2irq_mask[sh2->is_slave];
625 p32x_pwm_sync_to_sh2(sh2);
627 Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x0f;
628 Pico32x.sh2_regs[0] &= ~0x80;
629 Pico32x.sh2_regs[0] |= d & 0x80;
632 p32x_pwm_schedule_sh2(sh2);
634 p32x_update_cmd_irq(sh2, 0);
636 p32x_schedule_hint(sh2, 0);
638 case 0x04: // ignored?
640 case 0x05: // H count
642 if (Pico32x.sh2_regs[4 / 2] != d) {
643 Pico32x.sh2_regs[4 / 2] = d;
644 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
645 sh2_cycles_done_m68k(sh2));
650 REG8IN16(r, a) = d & 0x0f;
653 case 0x31: // PWM control
654 REG8IN16(r, a) = d & 0x8f;
657 case 0x32: // PWM cycle
658 REG8IN16(r, a) = d & 0x0f;
665 // PWM pulse regs.. Only writes to odd address send a value
666 // to FIFO; reads are 0 (except status bits)
675 d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
676 REG8IN16(r, a ^ 1) = 0;
678 case 0x3a: // ignored, always 0?
686 p32x_pwm_write16(a & ~1, d, sh2, 0);
690 if ((a & 0x30) == 0x20) {
692 if (REG8IN16(r, a) == d)
696 p32x_m68k_poll_event(P32XF_68KCPOLL);
697 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
698 sh2_cycles_done_m68k(sh2));
699 comreg = 1 << (a & 0x0f) / 2;
700 Pico32x.comm_dirty |= comreg;
704 elprintf(EL_32X|EL_ANOMALY,
705 "unhandled sysreg w8 [%02x] %02x @%08x", a, d, sh2_pc(sh2));
708 static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
715 if ((a & 0x30) == 0x20) {
717 if (Pico32x.regs[a / 2] == d)
720 Pico32x.regs[a / 2] = d;
721 p32x_m68k_poll_event(P32XF_68KCPOLL);
722 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
723 sh2_cycles_done_m68k(sh2));
724 comreg = 1 << (a & 0x0f) / 2;
725 Pico32x.comm_dirty |= comreg;
729 else if ((a & 0x30) == 0x30) {
730 p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2));
736 Pico32x.regs[0] &= ~P32XS_FM;
737 Pico32x.regs[0] |= d & P32XS_FM;
740 Pico32x.sh2irqs &= ~P32XI_VRES;
743 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VINT;
746 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_HINT;
749 Pico32x.regs[2 / 2] &= ~(1 << sh2->is_slave);
750 p32x_update_cmd_irq(sh2, 0);
753 p32x_pwm_sync_to_sh2(sh2);
754 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_PWM;
755 p32x_pwm_schedule_sh2(sh2);
759 p32x_sh2reg_write8(a | 1, d, sh2);
763 p32x_update_irls(sh2, 0);
766 // ------------------------------------------------------------------
770 static u32 PicoRead8_32x_on(u32 a)
773 if ((a & 0xffc0) == 0x5100) { // a15100
774 d = p32x_reg_read16(a);
778 if ((a & 0xfc00) != 0x5000) {
779 if (PicoIn.AHW & PAHW_MCD)
780 return PicoRead8_mcd_io(a);
782 return PicoRead8_io(a);
785 if ((a & 0xfff0) == 0x5180) { // a15180
786 d = p32x_vdp_read16(a);
790 if ((a & 0xfe00) == 0x5200) { // a15200
791 d = Pico32xMem->pal[(a & 0x1ff) / 2];
795 if ((a & 0xfffc) == 0x30ec) { // a130ec
800 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
810 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
814 static u32 PicoRead16_32x_on(u32 a)
817 if ((a & 0xffc0) == 0x5100) { // a15100
818 d = p32x_reg_read16(a);
822 if ((a & 0xfc00) != 0x5000) {
823 if (PicoIn.AHW & PAHW_MCD)
824 return PicoRead16_mcd_io(a);
826 return PicoRead16_io(a);
829 if ((a & 0xfff0) == 0x5180) { // a15180
830 d = p32x_vdp_read16(a);
834 if ((a & 0xfe00) == 0x5200) { // a15200
835 d = Pico32xMem->pal[(a & 0x1ff) / 2];
839 if ((a & 0xfffc) == 0x30ec) { // a130ec
840 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
844 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
848 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
852 static void PicoWrite8_32x_on(u32 a, u32 d)
854 if ((a & 0xfc00) == 0x5000)
855 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
857 if ((a & 0xffc0) == 0x5100) { // a15100
858 p32x_reg_write8(a, d);
862 if ((a & 0xfc00) != 0x5000) {
863 m68k_write8_io(a, d);
867 if (!(Pico32x.regs[0] & P32XS_FM)) {
868 if ((a & 0xfff0) == 0x5180) { // a15180
869 p32x_vdp_write8(a, d);
874 if ((a & 0xfe00) == 0x5200) { // a15200
875 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
876 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
877 Pico32x.dirty_pal = 1;
882 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
885 static void PicoWrite8_32x_on_io(u32 a, u32 d)
889 bank_switch_rom_68k(Pico32x.regs[4 / 2]);
892 static void PicoWrite8_32x_on_io_cd(u32 a, u32 d)
894 PicoWrite8_mcd_io(a, d);
896 bank_switch_rom_68k(Pico32x.regs[4 / 2]);
899 static void PicoWrite8_32x_on_io_ssf2(u32 a, u32 d)
901 carthw_ssf2_write8(a, d);
902 if ((a & ~0x0e) == 0xa130f1)
903 bank_switch_rom_68k(Pico32x.regs[4 / 2]);
906 static void PicoWrite16_32x_on(u32 a, u32 d)
908 if ((a & 0xfc00) == 0x5000)
909 elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
911 if ((a & 0xffc0) == 0x5100) { // a15100
912 p32x_reg_write16(a, d);
916 if ((a & 0xfc00) != 0x5000) {
917 m68k_write16_io(a, d);
921 if (!(Pico32x.regs[0] & P32XS_FM)) {
922 if ((a & 0xfff0) == 0x5180) { // a15180
923 p32x_vdp_write16(a, d, NULL); // FIXME?
927 if ((a & 0xfe00) == 0x5200) { // a15200
928 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
929 Pico32x.dirty_pal = 1;
934 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
937 static void PicoWrite16_32x_on_io(u32 a, u32 d)
939 PicoWrite16_io(a, d);
941 bank_switch_rom_68k(Pico32x.regs[4 / 2]);
944 static void PicoWrite16_32x_on_io_cd(u32 a, u32 d)
946 PicoWrite16_mcd_io(a, d);
948 bank_switch_rom_68k(Pico32x.regs[4 / 2]);
951 static void PicoWrite16_32x_on_io_ssf2(u32 a, u32 d)
953 PicoWrite16_io(a, d);
954 if ((a & ~0x0f) == 0xa130f0) {
955 carthw_ssf2_write8(a + 1, d);
956 bank_switch_rom_68k(Pico32x.regs[4 / 2]);
961 u32 PicoRead8_32x(u32 a)
965 if (PicoIn.opt & POPT_EN_32X) {
966 if ((a & 0xffc0) == 0x5100) { // a15100
967 // regs are always readable
968 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
972 if ((a & 0xfffc) == 0x30ec) { // a130ec
978 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
982 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
986 u32 PicoRead16_32x(u32 a)
990 if (PicoIn.opt & POPT_EN_32X) {
991 if ((a & 0xffc0) == 0x5100) { // a15100
992 d = Pico32x.regs[(a & 0x3f) / 2];
996 if ((a & 0xfffc) == 0x30ec) { // a130ec
997 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
1002 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
1006 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
1010 void PicoWrite8_32x(u32 a, u32 d)
1012 if ((PicoIn.opt & POPT_EN_32X) && (a & 0xffc0) == 0x5100) // a15100
1014 u16 *r = Pico32x.regs;
1016 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1019 if ((d ^ r[0]) & d & P32XS_ADEN) {
1021 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
1023 p32x_reg_write8(a, d); // forward for reset processing
1028 // allow only COMM for now
1029 if ((a & 0x30) == 0x20) {
1036 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1039 void PicoWrite16_32x(u32 a, u32 d)
1041 if ((PicoIn.opt & POPT_EN_32X) && (a & 0xffc0) == 0x5100) // a15100
1043 u16 *r = Pico32x.regs;
1045 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1048 if ((d ^ r[0]) & d & P32XS_ADEN) {
1050 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
1052 p32x_reg_write16(a, d); // forward for reset processing
1057 // allow only COMM for now
1058 if ((a & 0x30) == 0x20)
1063 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1066 /* quirk: in both normal and overwrite areas only nonzero values go through */
1067 #define sh2_write8_dramN(n) \
1068 if ((d & 0xff) != 0) { \
1069 u8 *dram = (u8 *)Pico32xMem->dram[n]; \
1070 dram[(a & 0x1ffff) ^ 1] = d; \
1073 static void m68k_write8_dram0_ow(u32 a, u32 d)
1075 sh2_write8_dramN(0);
1078 static void m68k_write8_dram1_ow(u32 a, u32 d)
1080 sh2_write8_dramN(1);
1083 #define sh2_write16_dramN(n) \
1084 u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
1085 if (!(a & 0x20000)) { \
1090 if (!(d & 0xff00)) d |= *pd & 0xff00; \
1091 if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
1094 static void m68k_write16_dram0_ow(u32 a, u32 d)
1096 sh2_write16_dramN(0);
1099 static void m68k_write16_dram1_ow(u32 a, u32 d)
1101 sh2_write16_dramN(1);
1104 // -----------------------------------------------------------------
1106 // hint vector is writeable
1107 static void PicoWrite8_hint(u32 a, u32 d)
1109 if ((a & 0xfffc) == 0x0070) {
1110 Pico32xMem->m68k_rom[a ^ 1] = d;
1114 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x",
1115 a, d & 0xff, SekPc);
1118 static void PicoWrite16_hint(u32 a, u32 d)
1120 if ((a & 0xfffc) == 0x0070) {
1121 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
1125 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x",
1126 a, d & 0xffff, SekPc);
1129 // normally not writable, but somebody could make a RAM cart
1130 static void PicoWrite8_cart(u32 a, u32 d)
1132 elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1138 static void PicoWrite16_cart(u32 a, u32 d)
1140 elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1146 // same with bank, but save ram is sometimes here
1147 static u32 PicoRead8_bank(u32 a)
1149 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1150 return m68k_read8(a);
1153 static u32 PicoRead16_bank(u32 a)
1155 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1156 return m68k_read16(a);
1159 static void PicoWrite8_bank(u32 a, u32 d)
1161 if (!(Pico.m.sram_reg & SRR_MAPPED))
1162 elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x",
1163 a, d & 0xff, SekPc);
1165 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1169 static void PicoWrite16_bank(u32 a, u32 d)
1171 if (!(Pico.m.sram_reg & SRR_MAPPED))
1172 elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x",
1173 a, d & 0xffff, SekPc);
1175 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1179 static void bank_map_handler(void)
1181 cpu68k_map_set(m68k_read8_map, 0x900000, 0x9fffff, PicoRead8_bank, 1);
1182 cpu68k_map_set(m68k_read16_map, 0x900000, 0x9fffff, PicoRead16_bank, 1);
1185 static void bank_switch_rom_68k(int b)
1187 unsigned int rs, bank, bank2;
1189 if (Pico.m.ncart_in)
1193 if ((Pico.m.sram_reg & SRR_MAPPED) && bank == Pico.sv.start) {
1198 if (bank >= Pico.romsize) {
1199 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
1204 // 32X ROM (XXX: consider mirroring?)
1205 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1206 if (!carthw_ssf2_active) {
1210 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1211 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1212 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
1216 bank2 = carthw_ssf2_banks[bank + 0] << 19;
1217 cpu68k_map_set(m68k_read8_map, 0x900000, 0x97ffff, Pico.rom + bank2, 0);
1218 cpu68k_map_set(m68k_read16_map, 0x900000, 0x97ffff, Pico.rom + bank2, 0);
1219 bank2 = carthw_ssf2_banks[bank + 1] << 19;
1220 cpu68k_map_set(m68k_read8_map, 0x980000, 0x9fffff, Pico.rom + bank2, 0);
1221 cpu68k_map_set(m68k_read16_map, 0x980000, 0x9fffff, Pico.rom + bank2, 0);
1225 // -----------------------------------------------------------------
1227 // -----------------------------------------------------------------
1230 static u32 sh2_read8_unmapped(u32 a, SH2 *sh2)
1232 elprintf_sh2(sh2, EL_32X, "unmapped r8 [%08x] %02x @%06x",
1237 static u32 sh2_read8_cs0(u32 a, SH2 *sh2)
1241 sh2_burn_cycles(sh2, 1*2);
1243 // 0x3ffc0 is veridied
1244 if ((a & 0x3ffc0) == 0x4000) {
1245 d = p32x_sh2reg_read16(a, sh2);
1249 if ((a & 0x3fff0) == 0x4100) {
1250 d = p32x_vdp_read16(a);
1251 sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
1256 if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
1257 return Pico32xMem->sh2_rom_m.b[a ^ 1];
1258 if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
1259 return Pico32xMem->sh2_rom_s.b[a ^ 1];
1261 if ((a & 0x3fe00) == 0x4200) {
1262 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1266 return sh2_read8_unmapped(a, sh2);
1274 elprintf_sh2(sh2, EL_32X, "r8 [%08x] %02x @%06x",
1279 static u32 sh2_read8_da(u32 a, SH2 *sh2)
1281 return sh2->data_array[(a & 0xfff) ^ 1];
1285 static u32 sh2_read8_rom(u32 a, SH2 *sh2)
1287 u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
1288 return Pico.rom[(bank + (a & 0x7ffff)) ^ 1];
1292 static u32 sh2_read16_unmapped(u32 a, SH2 *sh2)
1294 elprintf_sh2(sh2, EL_32X, "unmapped r16 [%08x] %04x @%06x",
1299 static u32 sh2_read16_cs0(u32 a, SH2 *sh2)
1303 sh2_burn_cycles(sh2, 1*2);
1305 if ((a & 0x3ffc0) == 0x4000) {
1306 d = p32x_sh2reg_read16(a, sh2);
1307 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
1312 if ((a & 0x3fff0) == 0x4100) {
1313 d = p32x_vdp_read16(a);
1314 sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
1318 if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
1319 return Pico32xMem->sh2_rom_m.w[a / 2];
1320 if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
1321 return Pico32xMem->sh2_rom_s.w[a / 2];
1323 if ((a & 0x3fe00) == 0x4200) {
1324 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1328 return sh2_read16_unmapped(a, sh2);
1331 elprintf_sh2(sh2, EL_32X, "r16 [%08x] %04x @%06x",
1336 static u32 sh2_read16_da(u32 a, SH2 *sh2)
1338 return ((u16 *)sh2->data_array)[(a & 0xfff) / 2];
1341 static u32 sh2_read16_rom(u32 a, SH2 *sh2)
1343 u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
1344 return *(u16 *)(Pico.rom + bank + (a & 0x7fffe));
1348 static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
1353 static void REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, SH2 *sh2)
1355 elprintf_sh2(sh2, EL_32X, "unmapped w8 [%08x] %02x @%06x",
1356 a, d & 0xff, sh2_pc(sh2));
1359 static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
1361 elprintf_sh2(sh2, EL_32X, "w8 [%08x] %02x @%06x",
1362 a, d & 0xff, sh2_pc(sh2));
1364 if (Pico32x.regs[0] & P32XS_FM) {
1365 if ((a & 0x3fff0) == 0x4100) {
1367 p32x_vdp_write8(a, d);
1372 if ((a & 0x3ffc0) == 0x4000) {
1373 p32x_sh2reg_write8(a, d, sh2);
1377 sh2_write8_unmapped(a, d, sh2);
1380 static void REGPARM(3) sh2_write8_dram0(u32 a, u32 d, SH2 *sh2)
1382 sh2_write8_dramN(0);
1385 static void REGPARM(3) sh2_write8_dram1(u32 a, u32 d, SH2 *sh2)
1387 sh2_write8_dramN(1);
1390 static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
1392 u32 a1 = a & 0x3ffff;
1394 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1396 sh2_drc_wcheck_ram(a, t, sh2->is_slave);
1398 Pico32xMem->sdram[a1 ^ 1] = d;
1401 static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2)
1405 sh2_end_run(sh2, 32);
1407 sh2_write8_sdram(a, d, sh2);
1410 static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
1414 int id = sh2->is_slave;
1415 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1417 sh2_drc_wcheck_da(a, t, id);
1419 sh2->data_array[a1 ^ 1] = d;
1423 static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2)
1425 elprintf_sh2(sh2, EL_32X, "unmapped w16 [%08x] %04x @%06x",
1426 a, d & 0xffff, sh2_pc(sh2));
1429 static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
1431 if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1432 elprintf_sh2(sh2, EL_32X, "w16 [%08x] %04x @%06x",
1433 a, d & 0xffff, sh2_pc(sh2));
1435 if (Pico32x.regs[0] & P32XS_FM) {
1436 if ((a & 0x3fff0) == 0x4100) {
1438 p32x_vdp_write16(a, d, sh2);
1442 if ((a & 0x3fe00) == 0x4200) {
1443 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1444 Pico32x.dirty_pal = 1;
1449 if ((a & 0x3ffc0) == 0x4000) {
1450 p32x_sh2reg_write16(a, d, sh2);
1454 sh2_write16_unmapped(a, d, sh2);
1457 static void REGPARM(3) sh2_write16_dram0(u32 a, u32 d, SH2 *sh2)
1459 sh2_write16_dramN(0);
1462 static void REGPARM(3) sh2_write16_dram1(u32 a, u32 d, SH2 *sh2)
1464 sh2_write16_dramN(1);
1467 static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2)
1469 u32 a1 = a & 0x3ffff;
1471 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1473 sh2_drc_wcheck_ram(a, t, sh2->is_slave);
1475 ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
1478 static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2)
1482 int id = sh2->is_slave;
1483 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1485 sh2_drc_wcheck_da(a, t, id);
1487 ((u16 *)sh2->data_array)[a1 / 2] = d;
1491 typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2);
1492 typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2);
1494 #define SH2MAP_ADDR2OFFS_R(a) \
1495 ((u32)(a) >> SH2_READ_SHIFT)
1497 #define SH2MAP_ADDR2OFFS_W(a) \
1498 ((u32)(a) >> SH2_WRITE_SHIFT)
1500 u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
1502 const sh2_memmap *sh2_map = sh2->read8_map;
1505 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1507 if (map_flag_set(p))
1508 return ((sh2_read_handler *)(p << 1))(a, sh2);
1510 return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
1513 u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
1515 const sh2_memmap *sh2_map = sh2->read16_map;
1518 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1520 if (map_flag_set(p))
1521 return ((sh2_read_handler *)(p << 1))(a, sh2);
1523 return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1526 u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
1528 const sh2_memmap *sh2_map = sh2->read16_map;
1529 sh2_read_handler *handler;
1533 offs = SH2MAP_ADDR2OFFS_R(a);
1536 if (!map_flag_set(p)) {
1537 // XXX: maybe 32bit access instead with ror?
1538 u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1539 return (pd[0] << 16) | pd[1];
1542 if (offs == SH2MAP_ADDR2OFFS_R(0xffffc000))
1543 return sh2_peripheral_read32(a, sh2);
1545 handler = (sh2_read_handler *)(p << 1);
1546 return (handler(a, sh2) << 16) | handler(a + 2, sh2);
1549 void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
1551 const void **sh2_wmap = sh2->write8_tab;
1552 sh2_write_handler *wh;
1554 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1558 void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
1560 const void **sh2_wmap = sh2->write16_tab;
1561 sh2_write_handler *wh;
1563 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1567 void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
1569 const void **sh2_wmap = sh2->write16_tab;
1570 sh2_write_handler *wh;
1573 offs = SH2MAP_ADDR2OFFS_W(a);
1575 if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
1576 sh2_peripheral_write32(a, d, sh2);
1580 wh = sh2_wmap[offs];
1581 wh(a, d >> 16, sh2);
1585 // -----------------------------------------------------------------
1587 static void z80_md_bank_write_32x(unsigned int a, unsigned char d)
1589 unsigned int addr68k;
1591 addr68k = Pico.m.z80_bank68k << 15;
1592 addr68k += a & 0x7fff;
1593 if ((addr68k & 0xfff000) == 0xa15000)
1594 Pico32x.emu_flags |= P32XF_Z80_32X_IO;
1596 elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, d);
1597 m68k_write8(addr68k, d);
1600 // -----------------------------------------------------------------
1602 static const u16 msh2_code[] = {
1603 // trap instructions
1604 0xaffe, // 200 bra <self>
1606 // have to wait a bit until m68k initial program finishes clearing stuff
1607 // to avoid races with game SH2 code, like in Tempo
1608 0xd406, // 204 mov.l @(_m_ok,pc), r4
1609 0xc400, // 206 mov.b @(h'0,gbr),r0
1610 0xc801, // 208 tst #1, r0
1611 0x8b0f, // 20a bf cd_start
1612 0xd105, // 20c mov.l @(_cnt,pc), r1
1613 0xd206, // 20e mov.l @(_start,pc), r2
1614 0x71ff, // 210 add #-1, r1
1615 0x4115, // 212 cmp/pl r1
1616 0x89fc, // 214 bt -2
1617 0x6043, // 216 mov r4, r0
1618 0xc208, // 218 mov.l r0, @(h'20,gbr)
1619 0x6822, // 21a mov.l @r2, r8
1620 0x482b, // 21c jmp @r8
1622 ('M'<<8)|'_', ('O'<<8)|'K', // 220 _m_ok
1623 0x0001, 0x0000, // 224 _cnt
1624 0x2200, 0x03e0, // master start pointer in ROM
1626 0xd20d, // 22c mov.l @(__cd_,pc), r2
1627 0xc608, // 22e mov.l @(h'20,gbr), r0
1628 0x3200, // 230 cmp/eq r0, r2
1629 0x8bfc, // 232 bf #-2
1630 0xe000, // 234 mov #0, r0
1631 0xcf80, // 236 or.b #0x80,@(r0,gbr)
1632 0xd80b, // 238 mov.l @(_start_cd,pc), r8 // 24000018
1633 0xd30c, // 23a mov.l @(_max_len,pc), r3
1634 0x5b84, // 23c mov.l @(h'10,r8), r11 // master vbr
1635 0x5a82, // 23e mov.l @(8,r8), r10 // entry
1636 0x5081, // 240 mov.l @(4,r8), r0 // len
1637 0x5980, // 242 mov.l @(0,r8), r9 // dst
1638 0x3036, // 244 cmp/hi r3,r0
1639 0x8b00, // 246 bf #1
1640 0x6033, // 248 mov r3,r0
1641 0x7820, // 24a add #0x20, r8
1643 0x6286, // 24c mov.l @r8+, r2
1644 0x2922, // 24e mov.l r2, @r9
1645 0x7904, // 250 add #4, r9
1646 0x70fc, // 252 add #-4, r0
1647 0x8800, // 254 cmp/eq #0, r0
1648 0x8bf9, // 256 bf #-5
1650 0x4b2e, // 258 ldc r11, vbr
1651 0x6043, // 25a mov r4, r0 // M_OK
1652 0xc208, // 25c mov.l r0, @(h'20,gbr)
1653 0x4a2b, // 25e jmp @r10
1655 0x0009, // 262 nop // pad
1656 ('_'<<8)|'C', ('D'<<8)|'_', // 264 __cd_
1657 0x2400, 0x0018, // 268 _start_cd
1658 0x0001, 0xffe0, // 26c _max_len
1661 static const u16 ssh2_code[] = {
1662 0xaffe, // 200 bra <self>
1664 // code to wait for master, in case authentic master BIOS is used
1665 0xd106, // 204 mov.l @(_m_ok,pc), r1
1666 0xd208, // 206 mov.l @(_start,pc), r2
1667 0xc608, // 208 mov.l @(h'20,gbr), r0
1668 0x3100, // 20a cmp/eq r0, r1
1669 0x8bfc, // 20c bf #-2
1670 0xc400, // 20e mov.b @(h'0,gbr),r0
1671 0xc801, // 210 tst #1, r0
1672 0xd004, // 212 mov.l @(_s_ok,pc), r0
1673 0x8b0a, // 214 bf cd_start
1674 0xc209, // 216 mov.l r0, @(h'24,gbr)
1675 0x6822, // 218 mov.l @r2, r8
1676 0x482b, // 21a jmp @r8
1679 ('M'<<8)|'_', ('O'<<8)|'K', // 220
1680 ('S'<<8)|'_', ('O'<<8)|'K', // 224
1681 0x2200, 0x03e4, // slave start pointer in ROM
1683 0xd803, // 22c mov.l @(_start_cd,pc), r8 // 24000018
1684 0x5b85, // 22e mov.l @(h'14,r8), r11 // slave vbr
1685 0x5a83, // 230 mov.l @(h'0c,r8), r10 // entry
1686 0x4b2e, // 232 ldc r11, vbr
1687 0xc209, // 234 mov.l r0, @(h'24,gbr) // write S_OK
1688 0x4a2b, // 236 jmp @r10
1691 0x2400, 0x0018, // 23c _start_cd
1694 #define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16))
1695 static void get_bios(void)
1702 if (p32x_bios_g != NULL) {
1703 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1704 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
1707 static const u16 andb[] = { 0x0239, 0x00fe, 0x00a1, 0x5107 };
1708 static const u16 p_d4[] = {
1709 0x48e7, 0x8040, // movem.l d0/a1, -(sp)
1710 0x227c, 0x00a1, 0x30f1, // movea.l #0xa130f1, a1
1711 0x7007, // moveq.l #7, d0
1712 0x12d8, //0: move.b (a0)+, (a1)+
1713 0x5289, // addq.l #1, a1
1714 0x51c8, 0xfffa, // dbra d0, 0b
1715 0x0239, 0x00fe, 0x00a1, // and.b #0xfe, (0xa15107).l
1717 0x4cdf, 0x0201 // movem.l (sp)+, d0/a1
1721 ps = (u16 *)Pico32xMem->m68k_rom;
1723 for (i = 1; i < 0xc0/4; i++)
1724 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1728 for (i = 0xc0/2; i < 0x100/2; i++)
1731 // c0: don't need to care about RV - not emulated
1732 ps[0xc8/2] = 0x1280; // move.b d0, (a1)
1733 memcpy(ps + 0xca/2, andb, sizeof(andb)); // and.b #0xfe, (a15107)
1734 ps[0xd2/2] = 0x4e75; // rts
1736 memcpy(ps + 0xd4/2, p_d4, sizeof(p_d4));
1737 ps[0xfe/2] = 0x4e75; // rts
1739 // fill remaining m68k_rom page with game ROM
1740 memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
1741 Pico.rom + sizeof(Pico32xMem->m68k_rom),
1742 sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
1745 if (p32x_bios_m != NULL) {
1746 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1747 Byteswap(&Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1750 pl = (u32 *)&Pico32xMem->sh2_rom_m;
1752 // fill exception vector table to our trap address
1753 for (i = 0; i < 128; i++)
1754 pl[i] = HWSWAP(0x200);
1757 pl[0] = pl[2] = HWSWAP(0x204);
1759 pl[1] = pl[3] = HWSWAP(0x6040000);
1762 memcpy(&Pico32xMem->sh2_rom_m.b[0x200], msh2_code, sizeof(msh2_code));
1766 if (p32x_bios_s != NULL) {
1767 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1768 Byteswap(&Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1771 pl = (u32 *)&Pico32xMem->sh2_rom_s;
1773 // fill exception vector table to our trap address
1774 for (i = 0; i < 128; i++)
1775 pl[i] = HWSWAP(0x200);
1778 pl[0] = pl[2] = HWSWAP(0x204);
1780 pl[1] = pl[3] = HWSWAP(0x603f800);
1783 memcpy(&Pico32xMem->sh2_rom_s.b[0x200], ssh2_code, sizeof(ssh2_code));
1787 #define MAP_MEMORY(m) ((uptr)(m) >> 1)
1788 #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
1790 static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80];
1791 // for writes we are using handlers only
1792 static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
1794 void Pico32xSwapDRAM(int b)
1796 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1797 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1798 cpu68k_map_set(m68k_read8_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1799 cpu68k_map_set(m68k_read16_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1800 cpu68k_map_set(m68k_write8_map, 0x840000, 0x87ffff,
1801 b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1);
1802 cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff,
1803 b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
1806 sh2_read8_map[0x04/2].addr = sh2_read8_map[0x24/2].addr =
1807 sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
1809 sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
1810 sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
1813 static void bank_switch_rom_sh2(void)
1815 if (!carthw_ssf2_active) {
1817 sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr =
1818 sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
1821 sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr = MAP_HANDLER(sh2_read8_rom);
1822 sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_HANDLER(sh2_read16_rom);
1826 void PicoMemSetup32x(void)
1831 Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
1832 if (Pico32xMem == NULL) {
1833 elprintf(EL_STATUS, "OOM");
1839 // cartridge area becomes unmapped
1840 // XXX: we take the easy way and don't unmap ROM,
1841 // so that we can avoid handling the RV bit.
1842 // m68k_map_unmap(0x000000, 0x3fffff);
1844 if (!Pico.m.ncart_in) {
1846 rs = sizeof(Pico32xMem->m68k_rom_bank);
1847 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1848 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1849 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1850 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1852 // 32X ROM (unbanked, XXX: consider mirroring?)
1853 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1856 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1857 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1858 cpu68k_map_set(m68k_write8_map, 0x880000, 0x880000 + rs - 1, PicoWrite8_cart, 1);
1859 cpu68k_map_set(m68k_write16_map, 0x880000, 0x880000 + rs - 1, PicoWrite16_cart, 1);
1862 bank_switch_rom_68k(0);
1863 cpu68k_map_set(m68k_write8_map, 0x900000, 0x9fffff, PicoWrite8_bank, 1);
1864 cpu68k_map_set(m68k_write16_map, 0x900000, 0x9fffff, PicoWrite16_bank, 1);
1868 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1869 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1870 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1871 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1873 // TODO: cd + carthw
1874 if (PicoIn.AHW & PAHW_MCD) {
1875 m68k_write8_io = PicoWrite8_32x_on_io_cd;
1876 m68k_write16_io = PicoWrite16_32x_on_io_cd;
1878 else if (carthw_ssf2_active) {
1879 m68k_write8_io = PicoWrite8_32x_on_io_ssf2;
1880 m68k_write16_io = PicoWrite16_32x_on_io_ssf2;
1883 m68k_write8_io = PicoWrite8_32x_on_io;
1884 m68k_write16_io = PicoWrite16_32x_on_io;
1887 // SH2 maps: A31,A30,A29,CS1,CS0
1888 // all unmapped by default
1889 for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
1890 sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
1891 sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
1894 for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
1895 sh2_write8_map[i] = sh2_write8_unmapped;
1896 sh2_write16_map[i] = sh2_write16_unmapped;
1900 for (i = 0x40; i <= 0x5f; i++) {
1901 sh2_write8_map[i >> 1] =
1902 sh2_write16_map[i >> 1] = sh2_write_ignore;
1906 sh2_read8_map[0x00/2].addr = sh2_read8_map[0x20/2].addr = MAP_HANDLER(sh2_read8_cs0);
1907 sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0);
1908 sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
1909 sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
1911 bank_switch_rom_sh2();
1912 sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask =
1913 sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME
1914 // CS2 - DRAM - done by Pico32xSwapDRAM()
1915 sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask =
1916 sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff;
1918 sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
1919 sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
1920 sh2_write8_map[0x06/2] = sh2_write8_sdram;
1921 sh2_write8_map[0x26/2] = sh2_write8_sdram_wt;
1922 sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
1923 sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask =
1924 sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03ffff;
1926 sh2_read8_map[0xc0/2].addr = MAP_HANDLER(sh2_read8_da);
1927 sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da);
1928 sh2_write8_map[0xc0/2] = sh2_write8_da;
1929 sh2_write16_map[0xc0/2] = sh2_write16_da;
1931 sh2_read8_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read8);
1932 sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16);
1933 sh2_write8_map[0xff/2] = sh2_peripheral_write8;
1934 sh2_write16_map[0xff/2] = sh2_peripheral_write16;
1936 // map DRAM area, both 68k and SH2
1939 msh2.read8_map = ssh2.read8_map = sh2_read8_map;
1940 msh2.read16_map = ssh2.read16_map = sh2_read16_map;
1941 msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
1942 msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
1944 sh2_drc_mem_setup(&msh2);
1945 sh2_drc_mem_setup(&ssh2);
1948 z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write_32x, 1);
1951 void p32x_update_banks(void)
1953 bank_switch_rom_68k(Pico32x.regs[4 / 2]);
1954 bank_switch_rom_sh2();
1955 if (Pico32x.emu_flags & P32XF_DRC_ROM_C)
1956 sh2_drc_flush_all();
1959 void Pico32xMemStateLoaded(void)
1961 bank_switch_rom_68k(Pico32x.regs[4 / 2]);
1962 Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
1963 memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
1964 Pico32x.dirty_pal = 1;
1966 Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
1967 memset(&m68k_poll, 0, sizeof(m68k_poll));
1969 msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
1971 ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
1973 sh2_drc_flush_all();
1976 // vim:shiftwidth=2:ts=2:expandtab