2 * SH2 peripherals/"system on chip"
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
8 * rough fffffe00-ffffffff map:
9 * e00-e05 SCI serial communication interface
10 * e10-e1a FRT free-running timer
11 * e60-e68 VCRx irq vectors
12 * e71-e72 DRCR dma selection
13 * e80-e83 WDT watchdog timer
14 * e91 SBYCR standby control
15 * e92 CCR cache control
17 * ee2 IPRA irq priorities
18 * ee4 VCRWDT WDT irq vectors
20 * f40-f7b UBC user break controller
22 * fe0-ffb BSC bus state controller
25 #include "../pico_int.h"
26 #include "../memory.h"
30 unsigned int sar, dar; // src, dst addr
31 unsigned int tcr; // transfer count
32 unsigned int chcr; // chan ctl
33 // -- dm dm sm sm ts ts ar am al ds dl tb ta ie te de
34 // ts - transfer size: 1, 2, 4, 16 bytes
35 // ar - auto request if 1, else dreq signal
39 #define DMA_AR (1 << 9)
40 #define DMA_IE (1 << 2)
41 #define DMA_TE (1 << 1)
42 #define DMA_DE (1 << 0)
46 struct dma_chan chan[2];
48 unsigned int unknown0;
50 unsigned int unknown1;
53 // pr - priority: chan0 > chan1 or round-robin
55 // nmif - nmi occurred
56 // dme - DMA master enable
57 #define DMA_DME (1 << 0)
60 static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
62 char *regs = (void *)Pico32xMem->sh2_peri_regs[sh2->is_slave];
63 struct dmac *dmac = (void *)(regs + 0x180);
64 int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
65 int vector = (chan == &dmac->chan[0]) ?
66 dmac->vcrdma0 : dmac->vcrdma1;
68 elprintf(EL_32XP, "dmac irq %d %d", level, vector);
69 sh2_internal_irq(sh2, level, vector & 0x7f);
72 static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
74 chan->chcr |= DMA_TE; // DMA has ended normally
76 p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT());
77 if (chan->chcr & DMA_IE)
78 dmac_te_irq(sh2, chan);
81 static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
85 size = (chan->chcr >> 10) & 3;
88 d = p32x_sh2_read8(chan->sar, sh2);
89 p32x_sh2_write8(chan->dar, d, sh2);
91 d = p32x_sh2_read16(chan->sar, sh2);
92 p32x_sh2_write16(chan->dar, d, sh2);
95 d = p32x_sh2_read32(chan->sar, sh2);
96 p32x_sh2_write32(chan->dar, d, sh2);
99 d = p32x_sh2_read32(chan->sar + 0x00, sh2);
100 p32x_sh2_write32(chan->dar + 0x00, d, sh2);
101 d = p32x_sh2_read32(chan->sar + 0x04, sh2);
102 p32x_sh2_write32(chan->dar + 0x04, d, sh2);
103 d = p32x_sh2_read32(chan->sar + 0x08, sh2);
104 p32x_sh2_write32(chan->dar + 0x08, d, sh2);
105 d = p32x_sh2_read32(chan->sar + 0x0c, sh2);
106 p32x_sh2_write32(chan->dar + 0x0c, d, sh2);
107 chan->sar += 16; // always?
108 if (chan->chcr & (1 << 15))
110 if (chan->chcr & (1 << 14))
118 if (chan->chcr & (1 << 15))
120 if (chan->chcr & (1 << 14))
122 if (chan->chcr & (1 << 13))
124 if (chan->chcr & (1 << 12))
128 // DMA trigger by SH2 register write
129 static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
131 elprintf(EL_32XP, "sh2 DMA %08x->%08x, cnt %d, chcr %04x @%06x",
132 chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
133 chan->tcr &= 0xffffff;
135 if (chan->chcr & DMA_AR) {
136 // auto-request transfer
137 while ((int)chan->tcr > 0)
138 dmac_transfer_one(sh2, chan);
139 dmac_transfer_complete(sh2, chan);
143 // DREQ0 is only sent after first 4 words are written.
144 // we do multiple of 4 words to avoid messing up alignment
145 if (chan->sar == 0x20004012) {
146 if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) {
147 elprintf(EL_32XP, "68k -> sh2 DMA");
148 p32x_dreq0_trigger();
153 elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: "
154 "%08x->%08x, cnt %d, chcr %04x @%06x",
155 chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
158 // timer state - FIXME
159 static int timer_cycles[2];
160 static int timer_tick_cycles[2];
163 void p32x_timers_recalc(void)
169 for (i = 0; i < 2; i++) {
170 tmp = PREG8(Pico32xMem->sh2_peri_regs[i], 0x80) & 7;
171 // Sclk cycles per timer tick
173 cycles = 0x20 << tmp;
176 timer_tick_cycles[i] = cycles;
178 elprintf(EL_32XP, "WDT cycles[%d] = %d", i, cycles);
182 void p32x_timers_do(unsigned int m68k_slice)
184 unsigned int cycles = m68k_slice * 3;
188 for (i = 0; i < 2; i++) {
189 void *pregs = Pico32xMem->sh2_peri_regs[i];
190 if (PREG8(pregs, 0x80) & 0x20) { // TME
191 timer_cycles[i] += cycles;
192 cnt = PREG8(pregs, 0x81);
193 while (timer_cycles[i] >= timer_tick_cycles[i]) {
194 timer_cycles[i] -= timer_tick_cycles[i];
198 int level = PREG8(pregs, 0xe3) >> 4;
199 int vector = PREG8(pregs, 0xe4) & 0x7f;
200 elprintf(EL_32XP, "%csh2 WDT irq (%d, %d)",
201 i ? 's' : 'm', level, vector);
202 sh2_internal_irq(&sh2s[i], level, vector);
205 PREG8(pregs, 0x81) = cnt;
210 // ------------------------------------------------------------------
211 // SH2 internal peripheral memhandlers
212 // we keep them in little endian format
214 u32 sh2_peripheral_read8(u32 a, int id)
216 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
222 elprintf(EL_32XP, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
226 u32 sh2_peripheral_read16(u32 a, int id)
228 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
234 elprintf(EL_32XP, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
238 u32 sh2_peripheral_read32(u32 a, int id)
242 d = Pico32xMem->sh2_peri_regs[id][a / 4];
244 elprintf(EL_32XP, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
248 int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id)
250 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
251 elprintf(EL_32XP, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
257 if ((a == 2 && (d & 0x20)) || // transmiter enabled
258 (a == 4 && !(d & 0x80))) { // valid data in TDR
259 void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
260 if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
261 int level = PREG8(oregs, 0x60) >> 4;
262 int vector = PREG8(oregs, 0x63) & 0x7f;
263 elprintf(EL_32XP, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
264 sh2_internal_irq(&sh2s[id ^ 1], level, vector);
271 int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
273 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
274 elprintf(EL_32XP, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
280 if ((d & 0xff00) == 0xa500) { // WTCSR
282 p32x_timers_recalc();
284 if ((d & 0xff00) == 0x5a00) // WTCNT
293 void sh2_peripheral_write32(u32 a, u32 d, int id)
295 u32 *r = Pico32xMem->sh2_peri_regs[id];
296 elprintf(EL_32XP, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
302 // division unit (TODO: verify):
303 case 0x104: // DVDNT: divident L, starts divide
304 elprintf(EL_32XP, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
306 signed int divisor = r[0x100 / 4];
307 r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
308 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
311 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
314 elprintf(EL_32XP, "%csh2 divide %08x%08x / %08x @%08x",
315 id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
317 signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
318 signed int divisor = r[0x100 / 4];
319 // XXX: undocumented mirroring to 0x118,0x11c?
320 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
322 r[0x11c / 4] = r[0x114 / 4] = divident;
324 if ((unsigned long long)divident + 1 > 1) {
325 //elprintf(EL_32XP, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id));
326 r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
330 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
334 // perhaps starting a DMA?
335 if (a == 0x1b0 || a == 0x18c || a == 0x19c) {
336 struct dmac *dmac = (void *)&Pico32xMem->sh2_peri_regs[id][0x180 / 4];
337 if (!(dmac->dmaor & DMA_DME))
340 if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
341 dmac_trigger(&sh2s[id], &dmac->chan[0]);
342 if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
343 dmac_trigger(&sh2s[id], &dmac->chan[1]);
348 static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
350 unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
353 // debug/sanity checks
354 if (chan->tcr != *dreqlen)
355 elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0 and len differ: %d != %d",
356 chan->tcr, *dreqlen);
357 // note: DACK is not connected, single addr mode should not be used
358 if ((chan->chcr & 0x3f08) != 0x0400)
359 elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
360 if (chan->sar != 0x20004012)
361 elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x\n", chan->sar);
363 // HACK: assume bus is busy and SH2 is halted
364 sh2->state |= SH2_STATE_SLEEP;
366 for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
367 elprintf(EL_32XP, "dmaw [%08x] %04x, left %d",
368 chan->dar, Pico32x.dmac_fifo[i], *dreqlen);
369 p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
375 if (Pico32x.dmac0_fifo_ptr != i)
376 memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i],
377 (Pico32x.dmac0_fifo_ptr - i) * 2);
378 Pico32x.dmac0_fifo_ptr -= i;
380 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
382 Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
384 dmac_transfer_complete(sh2, chan);
386 sh2_end_run(sh2, 16);
389 static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
391 // debug/sanity checks
392 if ((chan->chcr & 0xc308) != 0x0000)
393 elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr);
394 if ((chan->dar & ~0xf) != 0x20004030)
395 elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar);
397 dmac_transfer_one(sh2, chan);
399 dmac_transfer_complete(sh2, chan);
402 void p32x_dreq0_trigger(void)
404 struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
405 struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
407 elprintf(EL_32XP, "dreq0_trigger");
408 if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
409 dreq0_do(&msh2, &mdmac->chan[0]);
411 if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) {
412 dreq0_do(&ssh2, &sdmac->chan[0]);
416 void p32x_dreq1_trigger(void)
418 struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
419 struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
422 elprintf(EL_32XP, "dreq1_trigger");
423 if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) {
424 dreq1_do(&msh2, &mdmac->chan[1]);
427 if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) {
428 dreq1_do(&ssh2, &sdmac->chan[1]);
433 elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
436 // vim:shiftwidth=2:ts=2:expandtab