Pico/carthw/svp/compiler.c

   1
   2 #include "../../PicoInt.h"
   3 #include "compiler.h"
   4
   5 #define u32 unsigned int
   6
   7 static u32 *block_table[0x5090/2];
   8 static u32 *block_table_iram[15][0x800/2];
   9 static u32 *tcache_ptr = NULL;
  10
  11 static int nblocks = 0;
  12 static int n_in_ops = 0;
  13
  14 extern ssp1601_t *ssp;
  15
  16 #define rPC    ssp->gr[SSP_PC].h
  17 #define rPMC   ssp->gr[SSP_PMC]
  18
  19 #define SSP_FLAG_Z (1<<0xd)
  20 #define SSP_FLAG_N (1<<0xf)
  21
  22 #ifndef ARM
  23 #define DUMP_BLOCK 0x0c9a
  24 unsigned int tcache[512*1024];
  25 void ssp_drc_next(void){}
  26 void ssp_drc_next_patch(void){}
  27 void ssp_drc_end(void){}
  28 #endif
  29
  30 #include "gen_arm.c"
  31
  32 // -----------------------------------------------------
  33
  34 static int get_inc(int mode)
  35 {
  36         int inc = (mode >> 11) & 7;
  37         if (inc != 0) {
  38                 if (inc != 7) inc--;
  39                 inc = 1 << inc; // 0 1 2 4 8 16 32 128
  40                 if (mode & 0x8000) inc = -inc; // decrement mode
  41         }
  42         return inc;
  43 }
  44
  45 static u32 ssp_pm_read(int reg)
  46 {
  47         u32 d = 0, mode;
  48
  49         if (ssp->emu_status & SSP_PMC_SET)
  50         {
  51                 ssp->pmac_read[reg] = rPMC.v;
  52                 ssp->emu_status &= ~SSP_PMC_SET;
  53                 return 0;
  54         }
  55
  56         // just in case
  57         ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
  58
  59         mode = ssp->pmac_read[reg]>>16;
  60         if      ((mode & 0xfff0) == 0x0800) // ROM
  61         {
  62                 d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff];
  63                 ssp->pmac_read[reg] += 1;
  64         }
  65         else if ((mode & 0x47ff) == 0x0018) // DRAM
  66         {
  67                 unsigned short *dram = (unsigned short *)svp->dram;
  68                 int inc = get_inc(mode);
  69                 d = dram[ssp->pmac_read[reg]&0xffff];
  70                 ssp->pmac_read[reg] += inc;
  71         }
  72
  73         // PMC value corresponds to last PMR accessed
  74         rPMC.v = ssp->pmac_read[reg];
  75
  76         return d;
  77 }
  78
  79 #define overwrite_write(dst, d) \
  80 { \
  81         if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
  82         if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
  83         if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
  84         if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
  85 }
  86
  87 static void ssp_pm_write(u32 d, int reg)
  88 {
  89         unsigned short *dram;
  90         int mode, addr;
  91
  92         if (ssp->emu_status & SSP_PMC_SET)
  93         {
  94                 ssp->pmac_write[reg] = rPMC.v;
  95                 ssp->emu_status &= ~SSP_PMC_SET;
  96                 return;
  97         }
  98
  99         // just in case
 100         ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
 101
 102         dram = (unsigned short *)svp->dram;
 103         mode = ssp->pmac_write[reg]>>16;
 104         addr = ssp->pmac_write[reg]&0xffff;
 105         if      ((mode & 0x43ff) == 0x0018) // DRAM
 106         {
 107                 int inc = get_inc(mode);
 108                 if (mode & 0x0400) {
 109                        overwrite_write(dram[addr], d);
 110                 } else dram[addr] = d;
 111                 ssp->pmac_write[reg] += inc;
 112         }
 113         else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
 114         {
 115                 if (mode & 0x0400) {
 116                        overwrite_write(dram[addr], d);
 117                 } else dram[addr] = d;
 118                 ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
 119         }
 120         else if ((mode & 0x47ff) == 0x001c) // IRAM
 121         {
 122                 int inc = get_inc(mode);
 123                 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
 124                 ssp->pmac_write[reg] += inc;
 125                 ssp->drc.iram_dirty = 1;
 126         }
 127
 128         rPMC.v = ssp->pmac_write[reg];
 129 }
 130
 131
 132 // -----------------------------------------------------
 133
 134 // 14 IRAM blocks
 135 static unsigned char iram_context_map[] =
 136 {
 137          0, 0, 0, 0, 1, 0, 0, 0, // 04
 138          0, 0, 0, 0, 0, 0, 2, 0, // 0e
 139          0, 0, 0, 0, 0, 3, 0, 4, // 15 17
 140          5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d
 141          8, 9, 0, 0, 0,10, 0, 0, // 20 21 25
 142          0, 0, 0, 0, 0, 0, 0, 0,
 143          0, 0,11, 0, 0,12, 0, 0, // 32 35
 144         13,14, 0, 0, 0, 0, 0, 0  // 38 39
 145 };
 146
 147 int ssp_get_iram_context(void)
 148 {
 149         unsigned char *ir = (unsigned char *)svp->iram_rom;
 150         int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
 151         val1 = iram_context_map[(val>>1)&0x3f];
 152
 153         if (val1 == 0) {
 154                 printf("val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
 155                 //debug_dump2file(name, svp->iram_rom, 0x800);
 156                 exit(1);
 157         }
 158 //      elprintf(EL_ANOMALY, "iram_context: %02i", val1);
 159         return val1;
 160 }
 161
 162 // -----------------------------------------------------
 163
 164 /* regs with known values */
 165 static struct
 166 {
 167         ssp_reg_t gr[8];
 168         unsigned char r[8];
 169         unsigned int pmac_read[5];
 170         unsigned int pmac_write[5];
 171         ssp_reg_t pmc;
 172         unsigned int emu_status;
 173 } known_regs;
 174
 175 #define KRREG_X     (1 << SSP_X)
 176 #define KRREG_Y     (1 << SSP_Y)
 177 #define KRREG_A     (1 << SSP_A)        /* AH only */
 178 #define KRREG_ST    (1 << SSP_ST)
 179 #define KRREG_STACK (1 << SSP_STACK)
 180 #define KRREG_PC    (1 << SSP_PC)
 181 #define KRREG_P     (1 << SSP_P)
 182 #define KRREG_PR0   (1 << 8)
 183 #define KRREG_PR4   (1 << 12)
 184 #define KRREG_AL    (1 << 16)
 185 #define KRREG_PMCM  (1 << 18)           /* only mode word of PMC */
 186 #define KRREG_PMC   (1 << 19)
 187 #define KRREG_PM0R  (1 << 20)
 188 #define KRREG_PM1R  (1 << 21)
 189 #define KRREG_PM2R  (1 << 22)
 190 #define KRREG_PM3R  (1 << 23)
 191 #define KRREG_PM4R  (1 << 24)
 192 #define KRREG_PM0W  (1 << 25)
 193 #define KRREG_PM1W  (1 << 26)
 194 #define KRREG_PM2W  (1 << 27)
 195 #define KRREG_PM3W  (1 << 28)
 196 #define KRREG_PM4W  (1 << 29)
 197
 198 /* bitfield of known register values */
 199 static u32 known_regb = 0;
 200
 201 /* known vals, which need to be flushed
 202  * (only ST, P, r0-r7, PMCx, PMxR, PMxW)
 203  * ST means flags are being held in ARM PSR
 204  * P means that it needs to be recalculated
 205  */
 206 static u32 dirty_regb = 0;
 207
 208 /* known values of host regs.
 209  * -1            - unknown
 210  * 000000-00ffff - 16bit value
 211  * 100000-10ffff - base reg (r7) + 16bit val
 212  * 0r0000        - means reg (low) eq gr[r].h, r != AL
 213  */
 214 static int hostreg_r[4];
 215
 216 static void hostreg_clear(void)
 217 {
 218         int i;
 219         for (i = 0; i < 4; i++)
 220                 hostreg_r[i] = -1;
 221 }
 222
 223 static void hostreg_sspreg_changed(int sspreg)
 224 {
 225         int i;
 226         for (i = 0; i < 4; i++)
 227                 if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1;
 228 }
 229
 230
 231 #define PROGRAM(x)   ((unsigned short *)svp->iram_rom)[x]
 232 #define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
 233
 234 static void tr_unhandled(void)
 235 {
 236         FILE *f = fopen("tcache.bin", "wb");
 237         fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
 238         fclose(f);
 239         printf("unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
 240         exit(1);
 241 }
 242
 243 /* update P, if needed. Trashes r0 */
 244 static void tr_flush_dirty_P(void)
 245 {
 246         // TODO: const regs
 247         if (!(dirty_regb & KRREG_P)) return;
 248         EOP_MOV_REG_ASR(10, 4, 16);             // mov  r10, r4, asr #16
 249         EOP_MOV_REG_LSL( 0, 4, 16);             // mov  r0,  r4, lsl #16
 250         EOP_MOV_REG_ASR( 0, 0, 15);             // mov  r0,  r0, asr #15
 251         EOP_MUL(10, 0, 10);                     // mul  r10, r0, r10
 252         dirty_regb &= ~KRREG_P;
 253         hostreg_r[0] = -1;
 254 }
 255
 256 /* write dirty pr to host reg. Nothing is trashed */
 257 static void tr_flush_dirty_pr(int r)
 258 {
 259         int ror = 0, reg;
 260
 261         if (!(dirty_regb & (1 << (r+8)))) return;
 262
 263         switch (r&3) {
 264                 case 0: ror =    0; break;
 265                 case 1: ror = 24/2; break;
 266                 case 2: ror = 16/2; break;
 267         }
 268         reg = (r < 4) ? 8 : 9;
 269         EOP_BIC_IMM(reg,reg,ror,0xff);
 270         if (known_regs.r[r] != 0)
 271                 EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
 272         dirty_regb &= ~(1 << (r+8));
 273 }
 274
 275 /* write all dirty pr0-pr7 to host regs. Nothing is trashed */
 276 static void tr_flush_dirty_prs(void)
 277 {
 278         int i, ror = 0, reg;
 279         int dirty = dirty_regb >> 8;
 280         /* r0-r7 */
 281         for (i = 0; dirty && i < 8; i++, dirty >>= 1)
 282         {
 283                 if (!(dirty&1)) continue;
 284                 switch (i&3) {
 285                         case 0: ror =    0; break;
 286                         case 1: ror = 24/2; break;
 287                         case 2: ror = 16/2; break;
 288                 }
 289                 reg = (i < 4) ? 8 : 9;
 290                 EOP_BIC_IMM(reg,reg,ror,0xff);
 291                 if (known_regs.r[i] != 0)
 292                         EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
 293         }
 294         dirty_regb &= ~0xff00;
 295 }
 296
 297 /* write dirty pr and "forget" it. Nothing is trashed. */
 298 static void tr_release_pr(int r)
 299 {
 300         tr_flush_dirty_pr(r);
 301         known_regb &= ~(1 << (r+8));
 302 }
 303
 304 /* fush ARM PSR to r6. Trashes r1 */
 305 static void tr_flush_dirty_ST(void)
 306 {
 307         if (!(dirty_regb & KRREG_ST)) return;
 308         EOP_BIC_IMM(6,6,0,0x0f);
 309         EOP_MRS(1);
 310         EOP_ORR_REG_LSR(6,6,1,28);
 311         dirty_regb &= ~KRREG_ST;
 312         hostreg_r[1] = -1;
 313 }
 314
 315 /* inverse of above. Trashes r1 */
 316 static void tr_make_dirty_ST(void)
 317 {
 318         if (dirty_regb & KRREG_ST) return;
 319         if (known_regb & KRREG_ST) {
 320                 int flags = 0;
 321                 if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8;
 322                 if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4;
 323                 EOP_MSR_IMM(4/2, flags);
 324         } else {
 325                 EOP_MOV_REG_LSL(1, 6, 28);
 326                 EOP_MSR_REG(1);
 327                 hostreg_r[1] = -1;
 328         }
 329         dirty_regb |= KRREG_ST;
 330 }
 331
 332 /* load 16bit val into host reg r0-r3. Nothing is trashed */
 333 static void tr_mov16(int r, int val)
 334 {
 335         if (hostreg_r[r] != val) {
 336                 emit_mov_const(A_COND_AL, r, val);
 337                 hostreg_r[r] = val;
 338         }
 339 }
 340
 341 static void tr_mov16_cond(int cond, int r, int val)
 342 {
 343         emit_mov_const(cond, r, val);
 344         hostreg_r[r] = -1;
 345 }
 346
 347 /* trashes r1 */
 348 static void tr_flush_dirty_pmcrs(void)
 349 {
 350         u32 i, val = (u32)-1;
 351         if (!(dirty_regb & 0x3ff80000)) return;
 352
 353         if (dirty_regb & KRREG_PMC) {
 354                 val = known_regs.pmc.v;
 355                 emit_mov_const(A_COND_AL, 1, val);
 356                 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
 357
 358                 if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
 359                         printf("!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
 360                         tr_unhandled();
 361                 }
 362         }
 363         for (i = 0; i < 5; i++)
 364         {
 365                 if (dirty_regb & (1 << (20+i))) {
 366                         if (val != known_regs.pmac_read[i]) {
 367                                 val = known_regs.pmac_read[i];
 368                                 emit_mov_const(A_COND_AL, 1, val);
 369                         }
 370                         EOP_STR_IMM(1,7,0x454+i*4); // pmac_read
 371                 }
 372                 if (dirty_regb & (1 << (25+i))) {
 373                         if (val != known_regs.pmac_write[i]) {
 374                                 val = known_regs.pmac_write[i];
 375                                 emit_mov_const(A_COND_AL, 1, val);
 376                         }
 377                         EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write
 378                 }
 379         }
 380         dirty_regb &= ~0x3ff80000;
 381         hostreg_r[1] = -1;
 382 }
 383
 384 /* read bank word to r0 (upper bits zero). Thrashes r1. */
 385 static void tr_bank_read(int addr) /* word addr 0-0x1ff */
 386 {
 387         int breg = 7;
 388         if (addr > 0x7f) {
 389                 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
 390                         EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1);  // add  r1, r7, ((op&0x180)<<1)
 391                         hostreg_r[1] = 0x100000|((addr&0x180)<<1);
 392                 }
 393                 breg = 1;
 394         }
 395         EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1);    // ldrh r0, [r1, (op&0x7f)<<1]
 396         hostreg_r[0] = -1;
 397 }
 398
 399 /* write r0 to bank. Trashes r1. */
 400 static void tr_bank_write(int addr)
 401 {
 402         int breg = 7;
 403         if (addr > 0x7f) {
 404                 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
 405                         EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1);  // add  r1, r7, ((op&0x180)<<1)
 406                         hostreg_r[1] = 0x100000|((addr&0x180)<<1);
 407                 }
 408                 breg = 1;
 409         }
 410         EOP_STRH_IMM(0,breg,(addr&0x7f)<<1);            // strh r0, [r1, (op&0x7f)<<1]
 411 }
 412
 413 /* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
 414 static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
 415 {
 416         int modulo_shift = -1;  /* unknown */
 417
 418         if (mod == 0) return;
 419
 420         if (!need_modulo || mod == 1) // +!
 421                 modulo_shift = 8;
 422         else if (need_modulo && (known_regb & KRREG_ST)) {
 423                 modulo_shift = known_regs.gr[SSP_ST].h & 7;
 424                 if (modulo_shift == 0) modulo_shift = 8;
 425         }
 426
 427         if (modulo_shift == -1)
 428         {
 429                 int reg = (r < 4) ? 8 : 9;
 430                 tr_release_pr(r);
 431                 if (dirty_regb & KRREG_ST) {
 432                         // avoid flushing ARM flags
 433                         EOP_AND_IMM(1, 6, 0, 0x70);
 434                         EOP_SUB_IMM(1, 1, 0, 0x10);
 435                         EOP_AND_IMM(1, 1, 0, 0x70);
 436                         EOP_ADD_IMM(1, 1, 0, 0x10);
 437                 } else {
 438                         EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands  r1, r6, #0x70
 439                         EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
 440                 }
 441                 EOP_MOV_REG_LSR(1, 1, 4);               // mov r1, r1, lsr #4
 442                 EOP_RSB_IMM(2, 1, 0, 8);                // rsb r1, r1, #8
 443                 EOP_MOV_IMM(3, 8/2, count);             // mov r3, #0x01000000
 444                 if (r&3)
 445                         EOP_ADD_IMM(1, 1, 0, (r&3)*8);  // add r1, r1, #(r&3)*8
 446                 EOP_MOV_REG2_ROR(reg,reg,1);            // mov reg, reg, ror r1
 447                 if (mod == 2)
 448                      EOP_SUB_REG2_LSL(reg,reg,3,2);     // sub reg, reg, #0x01000000 << r2
 449                 else EOP_ADD_REG2_LSL(reg,reg,3,2);
 450                 EOP_RSB_IMM(1, 1, 0, 32);               // rsb r1, r1, #32
 451                 EOP_MOV_REG2_ROR(reg,reg,1);            // mov reg, reg, ror r1
 452                 hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
 453         }
 454         else if (known_regb & (1 << (r + 8)))
 455         {
 456                 int modulo = (1 << modulo_shift) - 1;
 457                 if (mod == 2)
 458                      known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
 459                 else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
 460         }
 461         else
 462         {
 463                 int reg = (r < 4) ? 8 : 9;
 464                 int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
 465                 EOP_MOV_REG_ROR(reg,reg,ror);
 466                 // {add|sub} reg, reg, #1<<shift
 467                 EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
 468                 EOP_MOV_REG_ROR(reg,reg,32-ror);
 469         }
 470 }
 471
 472 /* handle writes r0 to (rX). Trashes r1.
 473  * fortunately we can ignore modulo increment modes for writes. */
 474 static void tr_rX_write(int op)
 475 {
 476         if ((op&3) == 3)
 477         {
 478                 int mod = (op>>2) & 3; // direct addressing
 479                 tr_bank_write((op & 0x100) + mod);
 480         }
 481         else
 482         {
 483                 int r = (op&3) | ((op>>6)&4);
 484                 if (known_regb & (1 << (r + 8))) {
 485                         tr_bank_write((op&0x100) | known_regs.r[r]);
 486                 } else {
 487                         int reg = (r < 4) ? 8 : 9;
 488                         int ror = ((4 - (r&3))*8) & 0x1f;
 489                         EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 490                         if (r >= 4)
 491                                 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 492                         if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 493                         else     EOP_ADD_REG_LSL(1,7,1,1);
 494                         EOP_STRH_SIMPLE(0,1);                           // strh r0, [r1]
 495                         hostreg_r[1] = -1;
 496                 }
 497                 tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
 498         }
 499 }
 500
 501 /* read (rX) to r0. Trashes r1-r3. */
 502 static void tr_rX_read(int r, int mod)
 503 {
 504         if ((r&3) == 3)
 505         {
 506                 tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
 507         }
 508         else
 509         {
 510                 if (known_regb & (1 << (r + 8))) {
 511                         tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
 512                 } else {
 513                         int reg = (r < 4) ? 8 : 9;
 514                         int ror = ((4 - (r&3))*8) & 0x1f;
 515                         EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 516                         if (r >= 4)
 517                                 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 518                         if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 519                         else     EOP_ADD_REG_LSL(1,7,1,1);
 520                         EOP_LDRH_SIMPLE(0,1);                           // ldrh r0, [r1]
 521                         hostreg_r[0] = hostreg_r[1] = -1;
 522                 }
 523                 tr_ptrr_mod(r, mod, 1, 1);
 524         }
 525 }
 526
 527 /* read ((rX)) to r0. Trashes r1,r2. */
 528 static void tr_rX_read2(int op)
 529 {
 530         int r = (op&3) | ((op>>6)&4); // src
 531
 532         if ((r&3) == 3) {
 533                 tr_bank_read((op&0x100) | ((op>>2)&3));
 534         } else if (known_regb & (1 << (r+8))) {
 535                 tr_bank_read((op&0x100) | known_regs.r[r]);
 536         } else {
 537                 int reg = (r < 4) ? 8 : 9;
 538                 int ror = ((4 - (r&3))*8) & 0x1f;
 539                 EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 540                 if (r >= 4)
 541                         EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 542                 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 543                 else     EOP_ADD_REG_LSL(1,7,1,1);
 544                 EOP_LDRH_SIMPLE(0,1);                           // ldrh r0, [r1]
 545         }
 546         EOP_LDR_IMM(2,7,0x48c);                                 // ptr_iram_rom
 547         EOP_ADD_REG_LSL(2,2,0,1);                               // add  r2, r2, r0, lsl #1
 548         EOP_ADD_IMM(0,0,0,1);                                   // add  r0, r0, #1
 549         if ((r&3) == 3) {
 550                 tr_bank_write((op&0x100) | ((op>>2)&3));
 551         } else if (known_regb & (1 << (r+8))) {
 552                 tr_bank_write((op&0x100) | known_regs.r[r]);
 553         } else {
 554                 EOP_STRH_SIMPLE(0,1);                           // strh r0, [r1]
 555                 hostreg_r[1] = -1;
 556         }
 557         EOP_LDRH_SIMPLE(0,2);                                   // ldrh r0, [r2]
 558         hostreg_r[0] = hostreg_r[2] = -1;
 559 }
 560
 561 /* get ARM cond which would mean that SSP cond is satisfied. No trash. */
 562 static int tr_cond_check(int op)
 563 {
 564         int f = (op & 0x100) >> 8;
 565         switch (op&0xf0) {
 566                 case 0x00: return A_COND_AL;    /* always true */
 567                 case 0x50:                      /* Z matches f(?) bit */
 568                         if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
 569                         EOP_TST_IMM(6, 0, 4);
 570                         return f ? A_COND_NE : A_COND_EQ;
 571                 case 0x70:                      /* N matches f(?) bit */
 572                         if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
 573                         EOP_TST_IMM(6, 0, 8);
 574                         return f ? A_COND_NE : A_COND_EQ;
 575                 default:
 576                         printf("unimplemented cond?\n");
 577                         tr_unhandled();
 578                         return 0;
 579         }
 580 }
 581
 582 static int tr_neg_cond(int cond)
 583 {
 584         switch (cond) {
 585                 case A_COND_AL: printf("neg for AL?\n"); exit(1);
 586                 case A_COND_EQ: return A_COND_NE;
 587                 case A_COND_NE: return A_COND_EQ;
 588                 case A_COND_MI: return A_COND_PL;
 589                 case A_COND_PL: return A_COND_MI;
 590                 default:        printf("bad cond for neg\n"); exit(1);
 591         }
 592         return 0;
 593 }
 594
 595 static int tr_aop_ssp2arm(int op)
 596 {
 597         switch (op) {
 598                 case 1: return A_OP_SUB;
 599                 case 3: return A_OP_CMP;
 600                 case 4: return A_OP_ADD;
 601                 case 5: return A_OP_AND;
 602                 case 6: return A_OP_ORR;
 603                 case 7: return A_OP_EOR;
 604         }
 605
 606         tr_unhandled();
 607         return 0;
 608 }
 609
 610 // -----------------------------------------------------
 611
 612 //@ r4:  XXYY
 613 //@ r5:  A
 614 //@ r6:  STACK and emu flags
 615 //@ r7:  SSP context
 616 //@ r10: P
 617
 618 // read general reg to r0. Trashes r1
 619 static void tr_GR0_to_r0(int op)
 620 {
 621         tr_mov16(0, 0xffff);
 622 }
 623
 624 static void tr_X_to_r0(int op)
 625 {
 626         if (hostreg_r[0] != (SSP_X<<16)) {
 627                 EOP_MOV_REG_LSR(0, 4, 16);      // mov  r0, r4, lsr #16
 628                 hostreg_r[0] = SSP_X<<16;
 629         }
 630 }
 631
 632 static void tr_Y_to_r0(int op)
 633 {
 634         if (hostreg_r[0] != (SSP_Y<<16)) {
 635                 EOP_MOV_REG_SIMPLE(0, 4);       // mov  r0, r4
 636                 hostreg_r[0] = SSP_Y<<16;
 637         }
 638 }
 639
 640 static void tr_A_to_r0(int op)
 641 {
 642         if (hostreg_r[0] != (SSP_A<<16)) {
 643                 EOP_MOV_REG_LSR(0, 5, 16);      // mov  r0, r5, lsr #16  @ AH
 644                 hostreg_r[0] = SSP_A<<16;
 645         }
 646 }
 647
 648 static void tr_ST_to_r0(int op)
 649 {
 650         // VR doesn't need much accuracy here..
 651         EOP_MOV_REG_LSR(0, 6, 4);               // mov  r0, r6, lsr #4
 652         EOP_AND_IMM(0, 0, 0, 0x67);             // and  r0, r0, #0x67
 653         hostreg_r[0] = -1;
 654 }
 655
 656 static void tr_STACK_to_r0(int op)
 657 {
 658         // 448
 659         EOP_SUB_IMM(6, 6,  8/2, 0x20);          // sub  r6, r6, #1<<29
 660         EOP_ADD_IMM(1, 7, 24/2, 0x04);          // add  r1, r7, 0x400
 661         EOP_ADD_IMM(1, 1, 0, 0x48);             // add  r1, r1, 0x048
 662         EOP_ADD_REG_LSR(1, 1, 6, 28);           // add  r1, r1, r6, lsr #28
 663         EOP_LDRH_SIMPLE(0, 1);                  // ldrh r0, [r1]
 664         hostreg_r[0] = hostreg_r[1] = -1;
 665 }
 666
 667 static void tr_PC_to_r0(int op)
 668 {
 669         tr_mov16(0, known_regs.gr[SSP_PC].h);
 670 }
 671
 672 static void tr_P_to_r0(int op)
 673 {
 674         tr_flush_dirty_P();
 675         EOP_MOV_REG_LSR(0, 10, 16);             // mov  r0, r10, lsr #16
 676         hostreg_r[0] = -1;
 677 }
 678
 679 static void tr_AL_to_r0(int op)
 680 {
 681         if (op == 0x000f) {
 682                 if (known_regb & KRREG_PMC) {
 683                         known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
 684                 } else {
 685                         EOP_LDR_IMM(0,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 686                         EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
 687                         EOP_STR_IMM(0,7,0x484);
 688                 }
 689         }
 690
 691         if (hostreg_r[0] != (SSP_AL<<16)) {
 692                 EOP_MOV_REG_SIMPLE(0, 5);       // mov  r0, r5
 693                 hostreg_r[0] = SSP_AL<<16;
 694         }
 695 }
 696
 697 static void tr_PMX_to_r0(int reg)
 698 {
 699         if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
 700         {
 701                 known_regs.pmac_read[reg] = known_regs.pmc.v;
 702                 known_regs.emu_status &= ~SSP_PMC_SET;
 703                 known_regb |= 1 << (20+reg);
 704                 dirty_regb |= 1 << (20+reg);
 705                 return;
 706         }
 707
 708         if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg))))
 709         {
 710                 u32 pmcv = known_regs.pmac_read[reg];
 711                 int mode = pmcv>>16;
 712                 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
 713
 714                 if      ((mode & 0xfff0) == 0x0800)
 715                 {
 716                         EOP_LDR_IMM(1,7,0x488);         // rom_ptr
 717                         emit_mov_const(A_COND_AL, 0, (pmcv&0xfffff)<<1);
 718                         EOP_LDRH_REG(0,1,0);            // ldrh r0, [r1, r0]
 719                         known_regs.pmac_read[reg] += 1;
 720                 }
 721                 else if ((mode & 0x47ff) == 0x0018) // DRAM
 722                 {
 723                         int inc = get_inc(mode);
 724                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
 725                         emit_mov_const(A_COND_AL, 0, (pmcv&0xffff)<<1);
 726                         EOP_LDRH_REG(0,1,0);            // ldrh r0, [r1, r0]
 727                         if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
 728                         {
 729                                 int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
 730                                 tr_flush_dirty_ST();
 731                                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 732                                 EOP_TST_REG_SIMPLE(0,0);
 733                                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1);       // subeq r11, r11, #1024
 734                                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
 735                                 EOP_STR_IMM(1,7,0x484);                 // str r1, [r7, #0x484] // emu_status
 736                         }
 737                         known_regs.pmac_read[reg] += inc;
 738                 }
 739                 else
 740                 {
 741                         tr_unhandled();
 742                 }
 743                 known_regs.pmc.v = known_regs.pmac_read[reg];
 744                 //known_regb |= KRREG_PMC;
 745                 dirty_regb |= KRREG_PMC;
 746                 dirty_regb |= 1 << (20+reg);
 747                 hostreg_r[0] = hostreg_r[1] = -1;
 748                 return;
 749         }
 750
 751         known_regb &= ~KRREG_PMC;
 752         dirty_regb &= ~KRREG_PMC;
 753         known_regb &= ~(1 << (20+reg));
 754         dirty_regb &= ~(1 << (20+reg));
 755
 756         // call the C code to handle this
 757         tr_flush_dirty_ST();
 758         //tr_flush_dirty_pmcrs();
 759         tr_mov16(0, reg);
 760         emit_call(A_COND_AL, ssp_pm_read);
 761         hostreg_clear();
 762 }
 763
 764 static void tr_PM0_to_r0(int op)
 765 {
 766         tr_PMX_to_r0(0);
 767 }
 768
 769 static void tr_PM1_to_r0(int op)
 770 {
 771         tr_PMX_to_r0(1);
 772 }
 773
 774 static void tr_PM2_to_r0(int op)
 775 {
 776         tr_PMX_to_r0(2);
 777 }
 778
 779 static void tr_XST_to_r0(int op)
 780 {
 781         EOP_ADD_IMM(0, 7, 24/2, 4);     // add r0, r7, #0x400
 782         EOP_LDRH_IMM(0, 0, SSP_XST*4+2);
 783 }
 784
 785 static void tr_PM4_to_r0(int op)
 786 {
 787         tr_PMX_to_r0(4);
 788 }
 789
 790 static void tr_PMC_to_r0(int op)
 791 {
 792         if (known_regb & KRREG_PMC)
 793         {
 794                 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
 795                         known_regs.emu_status |= SSP_PMC_SET;
 796                         known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
 797                         // do nothing - this is handled elsewhere
 798                 } else {
 799                         tr_mov16(0, known_regs.pmc.l);
 800                         known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
 801                 }
 802         }
 803         else
 804         {
 805                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 806                 tr_flush_dirty_ST();
 807                 if (op != 0x000e)
 808                         EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4);
 809                 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
 810                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
 811                 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
 812                 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET);       // orrne r1, r1, #..
 813                 EOP_STR_IMM(1,7,0x484);
 814                 hostreg_r[0] = hostreg_r[1] = -1;
 815         }
 816 }
 817
 818
 819 typedef void (tr_read_func)(int op);
 820
 821 static tr_read_func *tr_read_funcs[16] =
 822 {
 823         tr_GR0_to_r0,
 824         tr_X_to_r0,
 825         tr_Y_to_r0,
 826         tr_A_to_r0,
 827         tr_ST_to_r0,
 828         tr_STACK_to_r0,
 829         tr_PC_to_r0,
 830         tr_P_to_r0,
 831         tr_PM0_to_r0,
 832         tr_PM1_to_r0,
 833         tr_PM2_to_r0,
 834         tr_XST_to_r0,
 835         tr_PM4_to_r0,
 836         (tr_read_func *)tr_unhandled,
 837         tr_PMC_to_r0,
 838         tr_AL_to_r0
 839 };
 840
 841
 842 // write r0 to general reg handlers. Trashes r1
 843 #define TR_WRITE_R0_TO_REG(reg) \
 844 { \
 845         hostreg_sspreg_changed(reg); \
 846         hostreg_r[0] = (reg)<<16; \
 847         if (const_val != -1) { \
 848                 known_regs.gr[reg].h = const_val; \
 849                 known_regb |= 1 << (reg); \
 850         } else { \
 851                 known_regb &= ~(1 << (reg)); \
 852         } \
 853 }
 854
 855 static void tr_r0_to_GR0(int const_val)
 856 {
 857         // do nothing
 858 }
 859
 860 static void tr_r0_to_X(int const_val)
 861 {
 862         EOP_MOV_REG_LSL(4, 4, 16);              // mov  r4, r4, lsl #16
 863         EOP_MOV_REG_LSR(4, 4, 16);              // mov  r4, r4, lsr #16
 864         EOP_ORR_REG_LSL(4, 4, 0, 16);           // orr  r4, r4, r0, lsl #16
 865         dirty_regb |= KRREG_P;                  // touching X or Y makes P dirty.
 866         TR_WRITE_R0_TO_REG(SSP_X);
 867 }
 868
 869 static void tr_r0_to_Y(int const_val)
 870 {
 871         EOP_MOV_REG_LSR(4, 4, 16);              // mov  r4, r4, lsr #16
 872         EOP_ORR_REG_LSL(4, 4, 0, 16);           // orr  r4, r4, r0, lsl #16
 873         EOP_MOV_REG_ROR(4, 4, 16);              // mov  r4, r4, ror #16
 874         dirty_regb |= KRREG_P;
 875         TR_WRITE_R0_TO_REG(SSP_Y);
 876 }
 877
 878 static void tr_r0_to_A(int const_val)
 879 {
 880         EOP_MOV_REG_LSL(5, 5, 16);              // mov  r5, r5, lsl #16
 881         EOP_MOV_REG_LSR(5, 5, 16);              // mov  r5, r5, lsr #16  @ AL
 882         EOP_ORR_REG_LSL(5, 5, 0, 16);           // orr  r5, r5, r0, lsl #16
 883         TR_WRITE_R0_TO_REG(SSP_A);
 884 }
 885
 886 static void tr_r0_to_ST(int const_val)
 887 {
 888         // VR doesn't need much accuracy here..
 889         EOP_AND_IMM(1, 0,   0, 0x67);           // and   r1, r0, #0x67
 890         EOP_AND_IMM(6, 6, 8/2, 0xe0);           // and   r6, r6, #7<<29     @ preserve STACK
 891         EOP_ORR_REG_LSL(6, 6, 1, 4);            // orr   r6, r6, r1, lsl #4
 892         TR_WRITE_R0_TO_REG(SSP_ST);
 893         hostreg_r[1] = -1;
 894         dirty_regb &= ~KRREG_ST;
 895 }
 896
 897 static void tr_r0_to_STACK(int const_val)
 898 {
 899         // 448
 900         EOP_ADD_IMM(1, 7, 24/2, 0x04);          // add  r1, r7, 0x400
 901         EOP_ADD_IMM(1, 1, 0, 0x48);             // add  r1, r1, 0x048
 902         EOP_ADD_REG_LSR(1, 1, 6, 28);           // add  r1, r1, r6, lsr #28
 903         EOP_STRH_SIMPLE(0, 1);                  // strh r0, [r1]
 904         EOP_ADD_IMM(6, 6,  8/2, 0x20);          // add  r6, r6, #1<<29
 905         hostreg_r[1] = -1;
 906 }
 907
 908 static void tr_r0_to_PC(int const_val)
 909 {
 910 /*
 911  * do nothing - dispatcher will take care of this
 912         EOP_MOV_REG_LSL(1, 0, 16);              // mov  r1, r0, lsl #16
 913         EOP_STR_IMM(1,7,0x400+6*4);             // str  r1, [r7, #(0x400+6*8)]
 914         hostreg_r[1] = -1;
 915 */
 916 }
 917
 918 static void tr_r0_to_AL(int const_val)
 919 {
 920         EOP_MOV_REG_LSR(5, 5, 16);              // mov  r5, r5, lsr #16
 921         EOP_ORR_REG_LSL(5, 5, 0, 16);           // orr  r5, r5, r0, lsl #16
 922         EOP_MOV_REG_ROR(5, 5, 16);              // mov  r5, r5, ror #16
 923         hostreg_sspreg_changed(SSP_AL);
 924         if (const_val != -1) {
 925                 known_regs.gr[SSP_A].l = const_val;
 926                 known_regb |= 1 << SSP_AL;
 927         } else
 928                 known_regb &= ~(1 << SSP_AL);
 929 }
 930
 931 static void tr_r0_to_PMX(int reg)
 932 {
 933         if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
 934         {
 935                 known_regs.pmac_write[reg] = known_regs.pmc.v;
 936                 known_regs.emu_status &= ~SSP_PMC_SET;
 937                 known_regb |= 1 << (25+reg);
 938                 dirty_regb |= 1 << (25+reg);
 939                 return;
 940         }
 941
 942         if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
 943         {
 944                 int mode, addr;
 945
 946                 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
 947
 948                 mode = known_regs.pmac_write[reg]>>16;
 949                 addr = known_regs.pmac_write[reg]&0xffff;
 950                 if      ((mode & 0x43ff) == 0x0018) // DRAM
 951                 {
 952                         int inc = get_inc(mode);
 953                         if (mode & 0x0400) tr_unhandled();
 954                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
 955                         emit_mov_const(A_COND_AL, 2, addr<<1);
 956                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
 957                         known_regs.pmac_write[reg] += inc;
 958                 }
 959                 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
 960                 {
 961                         if (mode & 0x0400) tr_unhandled();
 962                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
 963                         emit_mov_const(A_COND_AL, 2, addr<<1);
 964                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
 965                         known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
 966                 }
 967                 else if ((mode & 0x47ff) == 0x001c) // IRAM
 968                 {
 969                         int inc = get_inc(mode);
 970                         EOP_LDR_IMM(1,7,0x48c);         // iram_ptr
 971                         emit_mov_const(A_COND_AL, 2, (addr&0x3ff)<<1);
 972                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
 973                         EOP_MOV_IMM(1,0,1);
 974                         EOP_STR_IMM(1,7,0x494);         // iram_dirty
 975                         known_regs.pmac_write[reg] += inc;
 976                 }
 977                 else
 978                         tr_unhandled();
 979
 980                 known_regs.pmc.v = known_regs.pmac_write[reg];
 981                 //known_regb |= KRREG_PMC;
 982                 dirty_regb |= KRREG_PMC;
 983                 dirty_regb |= 1 << (25+reg);
 984                 hostreg_r[1] = hostreg_r[2] = -1;
 985                 return;
 986         }
 987
 988         known_regb &= ~KRREG_PMC;
 989         dirty_regb &= ~KRREG_PMC;
 990         known_regb &= ~(1 << (25+reg));
 991         dirty_regb &= ~(1 << (25+reg));
 992
 993         // call the C code to handle this
 994         tr_flush_dirty_ST();
 995         //tr_flush_dirty_pmcrs();
 996         tr_mov16(1, reg);
 997         emit_call(A_COND_AL, ssp_pm_write);
 998         hostreg_clear();
 999 }
1000
1001 static void tr_r0_to_PM0(int const_val)
1002 {
1003         tr_r0_to_PMX(0);
1004 }
1005
1006 static void tr_r0_to_PM1(int const_val)
1007 {
1008         tr_r0_to_PMX(1);
1009 }
1010
1011 static void tr_r0_to_PM2(int const_val)
1012 {
1013         tr_r0_to_PMX(2);
1014 }
1015
1016 static void tr_r0_to_PM4(int const_val)
1017 {
1018         tr_r0_to_PMX(4);
1019 }
1020
1021 static void tr_r0_to_PMC(int const_val)
1022 {
1023         if ((known_regb & KRREG_PMC) && const_val != -1)
1024         {
1025                 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
1026                         known_regs.emu_status |= SSP_PMC_SET;
1027                         known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1028                         known_regs.pmc.h = const_val;
1029                 } else {
1030                         known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
1031                         known_regs.pmc.l = const_val;
1032                 }
1033         }
1034         else
1035         {
1036                 tr_flush_dirty_ST();
1037                 if (known_regb & KRREG_PMC) {
1038                         emit_mov_const(A_COND_AL, 1, known_regs.pmc.v);
1039                         EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
1040                         known_regb &= ~KRREG_PMC;
1041                         dirty_regb &= ~KRREG_PMC;
1042                 }
1043                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
1044                 EOP_ADD_IMM(2,7,24/2,4);                // add r2, r7, #0x400
1045                 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
1046                 EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4);         // strxx r0, [r2, #SSP_PMC]
1047                 EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2);
1048                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
1049                 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
1050                 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET);       // orrne r1, r1, #..
1051                 EOP_STR_IMM(1,7,0x484);
1052                 hostreg_r[1] = hostreg_r[2] = -1;
1053         }
1054 }
1055
1056 typedef void (tr_write_func)(int const_val);
1057
1058 static tr_write_func *tr_write_funcs[16] =
1059 {
1060         tr_r0_to_GR0,
1061         tr_r0_to_X,
1062         tr_r0_to_Y,
1063         tr_r0_to_A,
1064         tr_r0_to_ST,
1065         tr_r0_to_STACK,
1066         tr_r0_to_PC,
1067         (tr_write_func *)tr_unhandled,
1068         tr_r0_to_PM0,
1069         tr_r0_to_PM1,
1070         tr_r0_to_PM2,
1071         (tr_write_func *)tr_unhandled,
1072         tr_r0_to_PM4,
1073         (tr_write_func *)tr_unhandled,
1074         tr_r0_to_PMC,
1075         tr_r0_to_AL
1076 };
1077
1078 static void tr_mac_load_XY(int op)
1079 {
1080         tr_rX_read(op&3, (op>>2)&3); // X
1081         EOP_MOV_REG_LSL(4, 0, 16);
1082         tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
1083         EOP_ORR_REG_SIMPLE(4, 0);
1084         dirty_regb |= KRREG_P;
1085         hostreg_sspreg_changed(SSP_X);
1086         hostreg_sspreg_changed(SSP_Y);
1087         known_regb &= ~KRREG_X;
1088         known_regb &= ~KRREG_Y;
1089 }
1090
1091 // -----------------------------------------------------
1092
1093 static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
1094 {
1095         u32 pmcv, tmpv;
1096         if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
1097
1098         // programming PMC:
1099         // ldi PMC, imm1
1100         // ldi PMC, imm2
1101         (*pc)++;
1102         pmcv = imm | (PROGRAM((*pc)++) << 16);
1103         known_regs.pmc.v = pmcv;
1104         known_regb |= KRREG_PMC;
1105         dirty_regb |= KRREG_PMC;
1106         known_regs.emu_status |= SSP_PMC_SET;
1107         n_in_ops++;
1108
1109         // check for possible reg programming
1110         tmpv = PROGRAM(*pc);
1111         if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
1112         {
1113                 int is_write = (tmpv & 0xff8f) == 0x80;
1114                 int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
1115                 if (reg > 4) tr_unhandled();
1116                 if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled();
1117                 known_regs.pmac_read[is_write ? reg + 5 : reg] = pmcv;
1118                 known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
1119                 dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
1120                 known_regs.emu_status &= ~SSP_PMC_SET;
1121                 (*pc)++;
1122                 n_in_ops++;
1123                 return 5;
1124         }
1125
1126         tr_unhandled();
1127         return 4;
1128 }
1129
1130 static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
1131
1132 static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
1133 {
1134         // ldi ST, 0
1135         // ldi PM0, 0
1136         // ldi PM0, 0
1137         // ldi ST, 60h
1138         unsigned short *pp;
1139         if (op != 0x0840 || imm != 0) return 0;
1140         pp = PROGRAM_P(*pc);
1141         if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
1142
1143         EOP_AND_IMM(6, 6, 8/2, 0xe0);           // and   r6, r6, #7<<29     @ preserve STACK
1144         EOP_ORR_IMM(6, 6, 24/2, 6);             // orr   r6, r6, 0x600
1145         hostreg_sspreg_changed(SSP_ST);
1146         known_regs.gr[SSP_ST].h = 0x60;
1147         known_regb |= 1 << SSP_ST;
1148         dirty_regb &= ~KRREG_ST;
1149         (*pc) += 3*2;
1150         n_in_ops += 3;
1151         return 4*2;
1152 }
1153
1154 static int tr_detect_rotate(unsigned int op, int *pc, int imm)
1155 {
1156         // @ 3DA2 and 426A
1157         // ld PMC, (r3|00)
1158         // ld (r3|00), PMC
1159         // ld -, AL
1160         if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0;
1161
1162         tr_bank_read(0);
1163         EOP_MOV_REG_LSL(0, 0, 4);
1164         EOP_ORR_REG_LSR(0, 0, 0, 16);
1165         tr_bank_write(0);
1166         (*pc) += 2;
1167         n_in_ops += 2;
1168         return 3;
1169 }
1170
1171 // -----------------------------------------------------
1172
1173 static int translate_op(unsigned int op, int *pc, int imm, int *end_cond, int *jump_pc)
1174 {
1175         u32 tmpv, tmpv2, tmpv3;
1176         int ret = 0;
1177         known_regs.gr[SSP_PC].h = *pc;
1178
1179         switch (op >> 9)
1180         {
1181                 // ld d, s
1182                 case 0x00:
1183                         if (op == 0) { ret++; break; } // nop
1184                         tmpv  = op & 0xf; // src
1185                         tmpv2 = (op >> 4) & 0xf; // dst
1186                         if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
1187                                 tr_flush_dirty_P();
1188                                 EOP_MOV_REG_SIMPLE(5, 10);
1189                                 hostreg_sspreg_changed(SSP_A);
1190                                 known_regb &= ~(KRREG_A|KRREG_AL);
1191                                 ret++; break;
1192                         }
1193                         tr_read_funcs[tmpv](op);
1194                         tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
1195                         if (tmpv2 == SSP_PC) {
1196                                 ret |= 0x10000;
1197                                 *end_cond = -A_COND_AL;
1198                         }
1199                         ret++; break;
1200
1201                 // ld d, (ri)
1202                 case 0x01: {
1203                         int r = (op&3) | ((op>>6)&4);
1204                         int mod = (op>>2)&3;
1205                         tmpv = (op >> 4) & 0xf; // dst
1206                         ret = tr_detect_rotate(op, pc, imm);
1207                         if (ret > 0) break;
1208                         if (tmpv != 0)
1209                              tr_rX_read(r, mod);
1210                         else tr_ptrr_mod(r, mod, 1, 1);
1211                         tr_write_funcs[tmpv](-1);
1212                         if (tmpv == SSP_PC) {
1213                                 ret |= 0x10000;
1214                                 *end_cond = -A_COND_AL;
1215                         }
1216                         ret++; break;
1217                 }
1218
1219                 // ld (ri), s
1220                 case 0x02:
1221                         tmpv = (op >> 4) & 0xf; // src
1222                         tr_read_funcs[tmpv](op);
1223                         tr_rX_write(op);
1224                         ret++; break;
1225
1226                 // ld a, adr
1227                 case 0x03:
1228                         tr_bank_read(op&0x1ff);
1229                         tr_r0_to_A(-1);
1230                         ret++; break;
1231
1232                 // ldi d, imm
1233                 case 0x04:
1234                         tmpv = (op & 0xf0) >> 4; // dst
1235                         ret = tr_detect_pm0_block(op, pc, imm);
1236                         if (ret > 0) break;
1237                         ret = tr_detect_set_pm(op, pc, imm);
1238                         if (ret > 0) break;
1239                         tr_mov16(0, imm);
1240                         tr_write_funcs[tmpv](imm);
1241                         if (tmpv == SSP_PC) {
1242                                 ret |= 0x10000;
1243                                 *jump_pc = imm;
1244                         }
1245                         ret += 2; break;
1246
1247                 // ld d, ((ri))
1248                 case 0x05:
1249                         tmpv2 = (op >> 4) & 0xf;  // dst
1250                         tr_rX_read2(op);
1251                         tr_write_funcs[tmpv2](-1);
1252                         if (tmpv2 == SSP_PC) {
1253                                 ret |= 0x10000;
1254                                 *end_cond = -A_COND_AL;
1255                         }
1256                         ret += 3; break;
1257
1258                 // ldi (ri), imm
1259                 case 0x06:
1260                         tr_mov16(0, imm);
1261                         tr_rX_write(op);
1262                         ret += 2; break;
1263
1264                 // ld adr, a
1265                 case 0x07:
1266                         tr_A_to_r0(op);
1267                         tr_bank_write(op&0x1ff);
1268                         ret++; break;
1269
1270                 // ld d, ri
1271                 case 0x09: {
1272                         int r;
1273                         r = (op&3) | ((op>>6)&4); // src
1274                         tmpv2 = (op >> 4) & 0xf;  // dst
1275                         if ((r&3) == 3) tr_unhandled();
1276
1277                         if (known_regb & (1 << (r+8))) {
1278                                 tr_mov16(0, known_regs.r[r]);
1279                                 tr_write_funcs[tmpv2](known_regs.r[r]);
1280                         } else {
1281                                 int reg = (r < 4) ? 8 : 9;
1282                                 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8);      // mov r0, r{7,8}, lsr #lsr
1283                                 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff);           // and r0, r{7,8}, <mask>
1284                                 hostreg_r[0] = -1;
1285                                 tr_write_funcs[tmpv2](-1);
1286                         }
1287                         ret++; break;
1288                 }
1289
1290                 // ld ri, s
1291                 case 0x0a: {
1292                         int r;
1293                         r = (op&3) | ((op>>6)&4); // dst
1294                         tmpv = (op >> 4) & 0xf;   // src
1295                         if ((r&3) == 3) tr_unhandled();
1296
1297                         if (known_regb & (1 << tmpv)) {
1298                                 known_regs.r[r] = known_regs.gr[tmpv].h;
1299                                 known_regb |= 1 << (r + 8);
1300                                 dirty_regb |= 1 << (r + 8);
1301                         } else {
1302                                 int reg = (r < 4) ? 8 : 9;
1303                                 int ror = ((4 - (r&3))*8) & 0x1f;
1304                                 tr_read_funcs[tmpv](op);
1305                                 EOP_BIC_IMM(reg, reg, ror/2, 0xff);             // bic r{7,8}, r{7,8}, <mask>
1306                                 EOP_AND_IMM(0, 0, 0, 0xff);                     // and r0, r0, 0xff
1307                                 EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8);          // orr r{7,8}, r{7,8}, r0, lsl #lsl
1308                                 hostreg_r[0] = -1;
1309                                 known_regb &= ~(1 << (r+8));
1310                                 dirty_regb &= ~(1 << (r+8));
1311                         }
1312                         ret++; break;
1313                 }
1314
1315                 // ldi ri, simm
1316                 case 0x0c ... 0x0f:
1317                         tmpv = (op>>8)&7;
1318                         known_regs.r[tmpv] = op;
1319                         known_regb |= 1 << (tmpv + 8);
1320                         dirty_regb |= 1 << (tmpv + 8);
1321                         ret++; break;
1322
1323                 // call cond, addr
1324                 case 0x24: {
1325                         u32 *jump_op = NULL;
1326                         tmpv = tr_cond_check(op);
1327                         if (tmpv != A_COND_AL) {
1328                                 jump_op = tcache_ptr;
1329                                 EOP_MOV_IMM(0, 0, 0); // placeholder for branch
1330                         }
1331                         tr_mov16(0, *pc);
1332                         tr_r0_to_STACK(*pc);
1333                         if (tmpv != A_COND_AL) {
1334                                 u32 *real_ptr = tcache_ptr;
1335                                 tcache_ptr = jump_op;
1336                                 EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2);
1337                                 tcache_ptr = real_ptr;
1338                         }
1339                         tr_mov16_cond(tmpv, 0, imm);
1340                         if (tmpv != A_COND_AL)
1341                                 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
1342                         tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
1343                         ret |= 0x10000;
1344                         *end_cond = tmpv;
1345                         *jump_pc = imm;
1346                         ret += 2; break;
1347                 }
1348
1349                 // ld d, (a)
1350                 case 0x25:
1351                         tmpv2 = (op >> 4) & 0xf;  // dst
1352                         tr_A_to_r0(op);
1353                         EOP_LDR_IMM(1,7,0x48c);                                 // ptr_iram_rom
1354                         EOP_ADD_REG_LSL(0,1,0,1);                               // add  r0, r1, r0, lsl #1
1355                         EOP_LDRH_SIMPLE(0,0);                                   // ldrh r0, [r0]
1356                         hostreg_r[0] = hostreg_r[1] = -1;
1357                         tr_write_funcs[tmpv2](-1);
1358                         if (tmpv2 == SSP_PC) {
1359                                 ret |= 0x10000;
1360                                 *end_cond = -A_COND_AL;
1361                         }
1362                         ret += 3; break;
1363
1364                 // bra cond, addr
1365                 case 0x26:
1366                         tmpv = tr_cond_check(op);
1367                         tr_mov16_cond(tmpv, 0, imm);
1368                         if (tmpv != A_COND_AL)
1369                                 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
1370                         tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
1371                         ret |= 0x10000;
1372                         *end_cond = tmpv;
1373                         *jump_pc = imm;
1374                         ret += 2; break;
1375
1376                 // mod cond, op
1377                 case 0x48: {
1378                         // check for repeats of this op
1379                         tmpv = 1; // count
1380                         while (PROGRAM(*pc) == op && (op & 7) != 6) {
1381                                 (*pc)++; tmpv++;
1382                                 n_in_ops++;
1383                         }
1384                         if ((op&0xf0) != 0) // !always
1385                                 tr_make_dirty_ST();
1386
1387                         tmpv2 = tr_cond_check(op);
1388                         switch (op & 7) {
1389                                 case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
1390                                 case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
1391                                 case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
1392                                 case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor  r1, r5, r5, asr #31
1393                                         EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
1394                                         hostreg_r[1] = -1; break; // abs
1395                                 default: tr_unhandled();
1396                         }
1397
1398                         hostreg_sspreg_changed(SSP_A);
1399                         dirty_regb |=  KRREG_ST;
1400                         known_regb &= ~KRREG_ST;
1401                         known_regb &= ~(KRREG_A|KRREG_AL);
1402                         ret += tmpv; break;
1403                 }
1404
1405                 // mpys?
1406                 case 0x1b:
1407                         tr_flush_dirty_P();
1408                         tr_mac_load_XY(op);
1409                         tr_make_dirty_ST();
1410                         EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
1411                         hostreg_sspreg_changed(SSP_A);
1412                         known_regb &= ~(KRREG_A|KRREG_AL);
1413                         dirty_regb |= KRREG_ST;
1414                         ret++; break;
1415
1416                 // mpya (rj), (ri), b
1417                 case 0x4b:
1418                         tr_flush_dirty_P();
1419                         tr_mac_load_XY(op);
1420                         tr_make_dirty_ST();
1421                         EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
1422                         hostreg_sspreg_changed(SSP_A);
1423                         known_regb &= ~(KRREG_A|KRREG_AL);
1424                         dirty_regb |= KRREG_ST;
1425                         ret++; break;
1426
1427                 // mld (rj), (ri), b
1428                 case 0x5b:
1429                         EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
1430                         hostreg_sspreg_changed(SSP_A);
1431                         known_regs.gr[SSP_A].v = 0;
1432                         known_regb |= (KRREG_A|KRREG_AL);
1433                         dirty_regb |= KRREG_ST;
1434                         tr_mac_load_XY(op);
1435                         ret++; break;
1436
1437                 // OP a, s
1438                 case 0x10:
1439                 case 0x30:
1440                 case 0x40:
1441                 case 0x50:
1442                 case 0x60:
1443                 case 0x70:
1444                         tmpv = op & 0xf; // src
1445                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1446                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1447                         if (tmpv == SSP_P) {
1448                                 tr_flush_dirty_P();
1449                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
1450                         } else if (tmpv == SSP_A) {
1451                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
1452                         } else {
1453                                 tr_read_funcs[tmpv](op);
1454                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
1455                         }
1456                         hostreg_sspreg_changed(SSP_A);
1457                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1458                         dirty_regb |= KRREG_ST;
1459                         ret++; break;
1460
1461                 // OP a, (ri)
1462                 case 0x11:
1463                 case 0x31:
1464                 case 0x41:
1465                 case 0x51:
1466                 case 0x61:
1467                 case 0x71:
1468                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1469                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1470                         tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
1471                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1472                         hostreg_sspreg_changed(SSP_A);
1473                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1474                         dirty_regb |= KRREG_ST;
1475                         ret++; break;
1476
1477                 // OP a, adr
1478                 case 0x13:
1479                 case 0x33:
1480                 case 0x43:
1481                 case 0x53:
1482                 case 0x63:
1483                 case 0x73:
1484                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1485                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1486                         tr_bank_read(op&0x1ff);
1487                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1488                         hostreg_sspreg_changed(SSP_A);
1489                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1490                         dirty_regb |= KRREG_ST;
1491                         ret++; break;
1492
1493                 // OP a, imm
1494                 case 0x14:
1495                 case 0x34:
1496                 case 0x44:
1497                 case 0x54:
1498                 case 0x64:
1499                 case 0x74:
1500                         tmpv = (op & 0xf0) >> 4;
1501                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1502                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1503                         tr_mov16(0, imm);
1504                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1505                         hostreg_sspreg_changed(SSP_A);
1506                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1507                         dirty_regb |= KRREG_ST;
1508                         ret += 2; break;
1509
1510                 // OP a, ((ri))
1511                 case 0x15:
1512                 case 0x35:
1513                 case 0x45:
1514                 case 0x55:
1515                 case 0x65:
1516                 case 0x75:
1517                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1518                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1519                         tr_rX_read2(op);
1520                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1521                         hostreg_sspreg_changed(SSP_A);
1522                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1523                         dirty_regb |= KRREG_ST;
1524                         ret += 3; break;
1525
1526                 // OP a, ri
1527                 case 0x19:
1528                 case 0x39:
1529                 case 0x49:
1530                 case 0x59:
1531                 case 0x69:
1532                 case 0x79: {
1533                         int r;
1534                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1535                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1536                         r = (op&3) | ((op>>6)&4); // src
1537                         if ((r&3) == 3) tr_unhandled();
1538
1539                         if (known_regb & (1 << (r+8))) {
1540                                 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]);  // OPs r5, r5, #val<<16
1541                         } else {
1542                                 int reg = (r < 4) ? 8 : 9;
1543                                 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8);      // mov r0, r{7,8}, lsr #lsr
1544                                 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff);           // and r0, r{7,8}, <mask>
1545                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1546                                 hostreg_r[0] = -1;
1547                         }
1548                         hostreg_sspreg_changed(SSP_A);
1549                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1550                         dirty_regb |= KRREG_ST;
1551                         ret++; break;
1552                 }
1553
1554                 // OP simm
1555                 case 0x1c:
1556                 case 0x3c:
1557                 case 0x4c:
1558                 case 0x5c:
1559                 case 0x6c:
1560                 case 0x7c:
1561                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1562                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1563                         EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff);        // OPs r5, r5, #val<<16
1564                         hostreg_sspreg_changed(SSP_A);
1565                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1566                         dirty_regb |= KRREG_ST;
1567                         ret++; break;
1568         }
1569
1570         n_in_ops++;
1571
1572         return ret;
1573 }
1574
1575 static void emit_block_prologue(void)
1576 {
1577         // check if there are enough cycles..
1578         // note: r0 must contain PC of current block
1579         EOP_CMP_IMM(11,0,0);                    // cmp r11, #0
1580         emit_call(A_COND_LE, ssp_drc_end);
1581 }
1582
1583 /* cond:
1584  * >0: direct (un)conditional jump
1585  * <0: indirect jump
1586  */
1587 static void emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
1588 {
1589         if (cycles > 0xff) { printf("large cycle count: %i\n", cycles); cycles = 0xff; }
1590         EOP_SUB_IMM(11,11,0,cycles);            // sub r11, r11, #cycles
1591
1592         if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) {
1593                 // indirect jump, or rom -> iram jump, must use dispatcher
1594                 emit_jump(A_COND_AL, ssp_drc_next);
1595         }
1596         else if (cond == A_COND_AL) {
1597                 u32 *target = (pc < 0x400) ? block_table_iram[ssp->drc.iram_context][pc] : block_table[pc];
1598                 if (target != NULL)
1599                         emit_jump(A_COND_AL, target);
1600                 else {
1601                         emit_jump(A_COND_AL, ssp_drc_next);
1602                         // cause the next block to be emitted over jump instrction
1603                         tcache_ptr--;
1604                 }
1605         }
1606         else {
1607                 u32 *target1 = (pc < 0x400) ? block_table_iram[ssp->drc.iram_context][pc] : block_table[pc];
1608                 u32 *target2 = (end_pc < 0x400) ? block_table_iram[ssp->drc.iram_context][end_pc] : block_table[end_pc];
1609                 if (target1 != NULL)
1610                      emit_jump(cond, target1);
1611                 else emit_call(cond, ssp_drc_next_patch);
1612                 if (target2 != NULL)
1613                      emit_jump(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
1614                 else emit_call(tr_neg_cond(cond), ssp_drc_next_patch);
1615         }
1616 }
1617
1618 void *ssp_translate_block(int pc)
1619 {
1620         unsigned int op, op1, imm, ccount = 0;
1621         unsigned int *block_start;
1622         int ret, end_cond = A_COND_AL, jump_pc = -1;
1623
1624         printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
1625         block_start = tcache_ptr;
1626         known_regb = 0;
1627         dirty_regb = KRREG_P;
1628         known_regs.emu_status = 0;
1629         hostreg_clear();
1630
1631         emit_block_prologue();
1632
1633         for (; ccount < 100;)
1634         {
1635                 op = PROGRAM(pc++);
1636                 op1 = op >> 9;
1637                 imm = (u32)-1;
1638
1639                 if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
1640                         imm = PROGRAM(pc++); // immediate
1641
1642                 ret = translate_op(op, &pc, imm, &end_cond, &jump_pc);
1643                 if (ret <= 0)
1644                 {
1645                         printf("NULL func! op=%08x (%02x)\n", op, op1);
1646                         exit(1);
1647                 }
1648
1649                 ccount += ret & 0xffff;
1650                 if (ret & 0x10000) break;
1651         }
1652
1653         if (ccount >= 100) {
1654                 end_cond = A_COND_AL;
1655                 jump_pc = pc;
1656                 emit_mov_const(A_COND_AL, 0, pc);
1657         }
1658
1659         tr_flush_dirty_prs();
1660         tr_flush_dirty_ST();
1661         tr_flush_dirty_pmcrs();
1662         emit_block_epilogue(ccount, end_cond, jump_pc, pc);
1663
1664         if (tcache_ptr - tcache > TCACHE_SIZE/4) {
1665                 printf("tcache overflow!\n");
1666                 fflush(stdout);
1667                 exit(1);
1668         }
1669
1670         // stats
1671         nblocks++;
1672         printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (tcache_ptr - tcache)*4,
1673                 (double)(tcache_ptr - tcache) / (double)n_in_ops);
1674
1675 #ifdef DUMP_BLOCK
1676         {
1677                 FILE *f = fopen("tcache.bin", "wb");
1678                 fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
1679                 fclose(f);
1680         }
1681         exit(0);
1682 #endif
1683
1684         handle_caches();
1685
1686         return block_start;
1687 }
1688
1689
1690
1691 // -----------------------------------------------------
1692
1693 static void ssp1601_state_load(void)
1694 {
1695         ssp->drc.iram_dirty = 1;
1696         ssp->drc.iram_context = 0;
1697 }
1698
1699 int ssp1601_dyn_startup(void)
1700 {
1701         memset(tcache, 0, TCACHE_SIZE);
1702         memset(block_table, 0, sizeof(block_table));
1703         memset(block_table_iram, 0, sizeof(block_table_iram));
1704         tcache_ptr = tcache;
1705
1706         PicoLoadStateHook = ssp1601_state_load;
1707
1708 #ifdef ARM
1709         // hle'd blocks
1710         block_table[0x400] = (void *) ssp_hle_800;
1711         n_in_ops = 3; // # of hled ops
1712 #endif
1713
1714         return 0;
1715 }
1716
1717
1718 void ssp1601_dyn_reset(ssp1601_t *ssp)
1719 {
1720         // debug
1721         {
1722                 int i, u;
1723                 FILE *f = fopen("tcache.bin", "wb");
1724                 fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
1725                 fclose(f);
1726
1727                 for (i = 0; i < 0x5090/2; i++)
1728                         if (block_table[i])
1729                                 printf("%06x -> __:%04x\n", (block_table[i] - tcache)*4, i<<1);
1730                 for (u = 1; u < 15; u++)
1731                         for (i = 0; i < 0x800/2; i++)
1732                                 if (block_table_iram[u][i])
1733                                         printf("%06x -> %02i:%04x\n", (block_table_iram[u][i] - tcache)*4, u, i<<1);
1734         }
1735
1736         ssp1601_reset(ssp);
1737         ssp->drc.iram_dirty = 1;
1738         ssp->drc.iram_context = 0;
1739         // must do this here because ssp is not available @ startup()
1740         ssp->drc.ptr_rom = (u32) Pico.rom;
1741         ssp->drc.ptr_iram_rom = (u32) svp->iram_rom;
1742         ssp->drc.ptr_dram = (u32) svp->dram;
1743         ssp->drc.ptr_btable = (u32) block_table;
1744         ssp->drc.ptr_btable_iram = (u32) block_table_iram;
1745
1746         // prevent new versions of IRAM from appearing
1747         memset(svp->iram_rom, 0, 0x800);
1748 }
1749
1750 void ssp1601_dyn_run(int cycles)
1751 {
1752         if (ssp->emu_status & SSP_WAIT_MASK) return;
1753
1754 #ifdef DUMP_BLOCK
1755         ssp_translate_block(DUMP_BLOCK >> 1);
1756 #endif
1757 #ifdef ARM
1758         ssp_drc_entry(cycles);
1759 #endif
1760 }
1761