Pico/carthw/svp/compiler.c

   1
   2 #include "../../PicoInt.h"
   3 #include "compiler.h"
   4
   5 #define u32 unsigned int
   6
   7 static u32 *tcache_ptr = NULL;
   8
   9 static int nblocks = 0;
  10 static int n_in_ops = 0;
  11
  12 extern ssp1601_t *ssp;
  13
  14 #define rPC    ssp->gr[SSP_PC].h
  15 #define rPMC   ssp->gr[SSP_PMC]
  16
  17 #define SSP_FLAG_Z (1<<0xd)
  18 #define SSP_FLAG_N (1<<0xf)
  19
  20 #ifndef ARM
  21 #define DUMP_BLOCK 0x0c9a
  22 u32 *ssp_block_table[0x5090/2];
  23 u32 *ssp_block_table_iram[15][0x800/2];
  24 u32 tcache[SSP_TCACHE_SIZE/4];
  25 void ssp_drc_next(void){}
  26 void ssp_drc_next_patch(void){}
  27 void ssp_drc_end(void){}
  28 #endif
  29
  30 #include "gen_arm.c"
  31
  32 // -----------------------------------------------------
  33
  34 static int get_inc(int mode)
  35 {
  36         int inc = (mode >> 11) & 7;
  37         if (inc != 0) {
  38                 if (inc != 7) inc--;
  39                 inc = 1 << inc; // 0 1 2 4 8 16 32 128
  40                 if (mode & 0x8000) inc = -inc; // decrement mode
  41         }
  42         return inc;
  43 }
  44
  45 u32 ssp_pm_read(int reg)
  46 {
  47         u32 d = 0, mode;
  48
  49         if (ssp->emu_status & SSP_PMC_SET)
  50         {
  51                 ssp->pmac_read[reg] = rPMC.v;
  52                 ssp->emu_status &= ~SSP_PMC_SET;
  53                 return 0;
  54         }
  55
  56         // just in case
  57         ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
  58
  59         mode = ssp->pmac_read[reg]>>16;
  60         if      ((mode & 0xfff0) == 0x0800) // ROM
  61         {
  62                 d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff];
  63                 ssp->pmac_read[reg] += 1;
  64         }
  65         else if ((mode & 0x47ff) == 0x0018) // DRAM
  66         {
  67                 unsigned short *dram = (unsigned short *)svp->dram;
  68                 int inc = get_inc(mode);
  69                 d = dram[ssp->pmac_read[reg]&0xffff];
  70                 ssp->pmac_read[reg] += inc;
  71         }
  72
  73         // PMC value corresponds to last PMR accessed
  74         rPMC.v = ssp->pmac_read[reg];
  75
  76         return d;
  77 }
  78
  79 #define overwrite_write(dst, d) \
  80 { \
  81         if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
  82         if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
  83         if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
  84         if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
  85 }
  86
  87 void ssp_pm_write(u32 d, int reg)
  88 {
  89         unsigned short *dram;
  90         int mode, addr;
  91
  92         if (ssp->emu_status & SSP_PMC_SET)
  93         {
  94                 ssp->pmac_write[reg] = rPMC.v;
  95                 ssp->emu_status &= ~SSP_PMC_SET;
  96                 return;
  97         }
  98
  99         // just in case
 100         ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
 101
 102         dram = (unsigned short *)svp->dram;
 103         mode = ssp->pmac_write[reg]>>16;
 104         addr = ssp->pmac_write[reg]&0xffff;
 105         if      ((mode & 0x43ff) == 0x0018) // DRAM
 106         {
 107                 int inc = get_inc(mode);
 108                 if (mode & 0x0400) {
 109                        overwrite_write(dram[addr], d);
 110                 } else dram[addr] = d;
 111                 ssp->pmac_write[reg] += inc;
 112         }
 113         else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
 114         {
 115                 if (mode & 0x0400) {
 116                        overwrite_write(dram[addr], d);
 117                 } else dram[addr] = d;
 118                 ssp->pmac_write[reg] += (addr&1) ? 0x1f : 1;
 119         }
 120         else if ((mode & 0x47ff) == 0x001c) // IRAM
 121         {
 122                 int inc = get_inc(mode);
 123                 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
 124                 ssp->pmac_write[reg] += inc;
 125                 ssp->drc.iram_dirty = 1;
 126         }
 127
 128         rPMC.v = ssp->pmac_write[reg];
 129 }
 130
 131
 132 // -----------------------------------------------------
 133
 134 // 14 IRAM blocks
 135 static unsigned char iram_context_map[] =
 136 {
 137          0, 0, 0, 0, 1, 0, 0, 0, // 04
 138          0, 0, 0, 0, 0, 0, 2, 0, // 0e
 139          0, 0, 0, 0, 0, 3, 0, 4, // 15 17
 140          5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d
 141          8, 9, 0, 0, 0,10, 0, 0, // 20 21 25
 142          0, 0, 0, 0, 0, 0, 0, 0,
 143          0, 0,11, 0, 0,12, 0, 0, // 32 35
 144         13,14, 0, 0, 0, 0, 0, 0  // 38 39
 145 };
 146
 147 int ssp_get_iram_context(void)
 148 {
 149         unsigned char *ir = (unsigned char *)svp->iram_rom;
 150         int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
 151         val1 = iram_context_map[(val>>1)&0x3f];
 152
 153         if (val1 == 0) {
 154                 elprintf(EL_ANOMALY, "svp: iram ctx val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
 155                 //debug_dump2file(name, svp->iram_rom, 0x800);
 156                 //exit(1);
 157         }
 158         return val1;
 159 }
 160
 161 // -----------------------------------------------------
 162
 163 /* regs with known values */
 164 static struct
 165 {
 166         ssp_reg_t gr[8];
 167         unsigned char r[8];
 168         unsigned int pmac_read[5];
 169         unsigned int pmac_write[5];
 170         ssp_reg_t pmc;
 171         unsigned int emu_status;
 172 } known_regs;
 173
 174 #define KRREG_X     (1 << SSP_X)
 175 #define KRREG_Y     (1 << SSP_Y)
 176 #define KRREG_A     (1 << SSP_A)        /* AH only */
 177 #define KRREG_ST    (1 << SSP_ST)
 178 #define KRREG_STACK (1 << SSP_STACK)
 179 #define KRREG_PC    (1 << SSP_PC)
 180 #define KRREG_P     (1 << SSP_P)
 181 #define KRREG_PR0   (1 << 8)
 182 #define KRREG_PR4   (1 << 12)
 183 #define KRREG_AL    (1 << 16)
 184 #define KRREG_PMCM  (1 << 18)           /* only mode word of PMC */
 185 #define KRREG_PMC   (1 << 19)
 186 #define KRREG_PM0R  (1 << 20)
 187 #define KRREG_PM1R  (1 << 21)
 188 #define KRREG_PM2R  (1 << 22)
 189 #define KRREG_PM3R  (1 << 23)
 190 #define KRREG_PM4R  (1 << 24)
 191 #define KRREG_PM0W  (1 << 25)
 192 #define KRREG_PM1W  (1 << 26)
 193 #define KRREG_PM2W  (1 << 27)
 194 #define KRREG_PM3W  (1 << 28)
 195 #define KRREG_PM4W  (1 << 29)
 196
 197 /* bitfield of known register values */
 198 static u32 known_regb = 0;
 199
 200 /* known vals, which need to be flushed
 201  * (only ST, P, r0-r7, PMCx, PMxR, PMxW)
 202  * ST means flags are being held in ARM PSR
 203  * P means that it needs to be recalculated
 204  */
 205 static u32 dirty_regb = 0;
 206
 207 /* known values of host regs.
 208  * -1            - unknown
 209  * 000000-00ffff - 16bit value
 210  * 100000-10ffff - base reg (r7) + 16bit val
 211  * 0r0000        - means reg (low) eq gr[r].h, r != AL
 212  */
 213 static int hostreg_r[4];
 214
 215 static void hostreg_clear(void)
 216 {
 217         int i;
 218         for (i = 0; i < 4; i++)
 219                 hostreg_r[i] = -1;
 220 }
 221
 222 static void hostreg_sspreg_changed(int sspreg)
 223 {
 224         int i;
 225         for (i = 0; i < 4; i++)
 226                 if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1;
 227 }
 228
 229
 230 #define PROGRAM(x)   ((unsigned short *)svp->iram_rom)[x]
 231 #define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
 232
 233 void tr_unhandled(void)
 234 {
 235         //FILE *f = fopen("tcache.bin", "wb");
 236         //fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
 237         //fclose(f);
 238         elprintf(EL_ANOMALY, "unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
 239         //exit(1);
 240 }
 241
 242 /* update P, if needed. Trashes r0 */
 243 static void tr_flush_dirty_P(void)
 244 {
 245         // TODO: const regs
 246         if (!(dirty_regb & KRREG_P)) return;
 247         EOP_MOV_REG_ASR(10, 4, 16);             // mov  r10, r4, asr #16
 248         EOP_MOV_REG_LSL( 0, 4, 16);             // mov  r0,  r4, lsl #16
 249         EOP_MOV_REG_ASR( 0, 0, 15);             // mov  r0,  r0, asr #15
 250         EOP_MUL(10, 0, 10);                     // mul  r10, r0, r10
 251         dirty_regb &= ~KRREG_P;
 252         hostreg_r[0] = -1;
 253 }
 254
 255 /* write dirty pr to host reg. Nothing is trashed */
 256 static void tr_flush_dirty_pr(int r)
 257 {
 258         int ror = 0, reg;
 259
 260         if (!(dirty_regb & (1 << (r+8)))) return;
 261
 262         switch (r&3) {
 263                 case 0: ror =    0; break;
 264                 case 1: ror = 24/2; break;
 265                 case 2: ror = 16/2; break;
 266         }
 267         reg = (r < 4) ? 8 : 9;
 268         EOP_BIC_IMM(reg,reg,ror,0xff);
 269         if (known_regs.r[r] != 0)
 270                 EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
 271         dirty_regb &= ~(1 << (r+8));
 272 }
 273
 274 /* write all dirty pr0-pr7 to host regs. Nothing is trashed */
 275 static void tr_flush_dirty_prs(void)
 276 {
 277         int i, ror = 0, reg;
 278         int dirty = dirty_regb >> 8;
 279         if ((dirty&7) == 7) {
 280                 emit_mov_const(A_COND_AL, 8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16));
 281                 dirty &= ~7;
 282         }
 283         if ((dirty&0x70) == 0x70) {
 284                 emit_mov_const(A_COND_AL, 9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16));
 285                 dirty &= ~0x70;
 286         }
 287         /* r0-r7 */
 288         for (i = 0; dirty && i < 8; i++, dirty >>= 1)
 289         {
 290                 if (!(dirty&1)) continue;
 291                 switch (i&3) {
 292                         case 0: ror =    0; break;
 293                         case 1: ror = 24/2; break;
 294                         case 2: ror = 16/2; break;
 295                 }
 296                 reg = (i < 4) ? 8 : 9;
 297                 EOP_BIC_IMM(reg,reg,ror,0xff);
 298                 if (known_regs.r[i] != 0)
 299                         EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
 300         }
 301         dirty_regb &= ~0xff00;
 302 }
 303
 304 /* write dirty pr and "forget" it. Nothing is trashed. */
 305 static void tr_release_pr(int r)
 306 {
 307         tr_flush_dirty_pr(r);
 308         known_regb &= ~(1 << (r+8));
 309 }
 310
 311 /* fush ARM PSR to r6. Trashes r1 */
 312 static void tr_flush_dirty_ST(void)
 313 {
 314         if (!(dirty_regb & KRREG_ST)) return;
 315         EOP_BIC_IMM(6,6,0,0x0f);
 316         EOP_MRS(1);
 317         EOP_ORR_REG_LSR(6,6,1,28);
 318         dirty_regb &= ~KRREG_ST;
 319         hostreg_r[1] = -1;
 320 }
 321
 322 /* inverse of above. Trashes r1 */
 323 static void tr_make_dirty_ST(void)
 324 {
 325         if (dirty_regb & KRREG_ST) return;
 326         if (known_regb & KRREG_ST) {
 327                 int flags = 0;
 328                 if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8;
 329                 if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4;
 330                 EOP_MSR_IMM(4/2, flags);
 331         } else {
 332                 EOP_MOV_REG_LSL(1, 6, 28);
 333                 EOP_MSR_REG(1);
 334                 hostreg_r[1] = -1;
 335         }
 336         dirty_regb |= KRREG_ST;
 337 }
 338
 339 /* load 16bit val into host reg r0-r3. Nothing is trashed */
 340 static void tr_mov16(int r, int val)
 341 {
 342         if (hostreg_r[r] != val) {
 343                 emit_mov_const(A_COND_AL, r, val);
 344                 hostreg_r[r] = val;
 345         }
 346 }
 347
 348 static void tr_mov16_cond(int cond, int r, int val)
 349 {
 350         emit_mov_const(cond, r, val);
 351         hostreg_r[r] = -1;
 352 }
 353
 354 /* trashes r1 */
 355 static void tr_flush_dirty_pmcrs(void)
 356 {
 357         u32 i, val = (u32)-1;
 358         if (!(dirty_regb & 0x3ff80000)) return;
 359
 360         if (dirty_regb & KRREG_PMC) {
 361                 val = known_regs.pmc.v;
 362                 emit_mov_const(A_COND_AL, 1, val);
 363                 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
 364
 365                 if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
 366                         elprintf(EL_ANOMALY, "!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
 367                         tr_unhandled();
 368                 }
 369         }
 370         for (i = 0; i < 5; i++)
 371         {
 372                 if (dirty_regb & (1 << (20+i))) {
 373                         if (val != known_regs.pmac_read[i]) {
 374                                 val = known_regs.pmac_read[i];
 375                                 emit_mov_const(A_COND_AL, 1, val);
 376                         }
 377                         EOP_STR_IMM(1,7,0x454+i*4); // pmac_read
 378                 }
 379                 if (dirty_regb & (1 << (25+i))) {
 380                         if (val != known_regs.pmac_write[i]) {
 381                                 val = known_regs.pmac_write[i];
 382                                 emit_mov_const(A_COND_AL, 1, val);
 383                         }
 384                         EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write
 385                 }
 386         }
 387         dirty_regb &= ~0x3ff80000;
 388         hostreg_r[1] = -1;
 389 }
 390
 391 /* read bank word to r0 (upper bits zero). Thrashes r1. */
 392 static void tr_bank_read(int addr) /* word addr 0-0x1ff */
 393 {
 394         int breg = 7;
 395         if (addr > 0x7f) {
 396                 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
 397                         EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1);  // add  r1, r7, ((op&0x180)<<1)
 398                         hostreg_r[1] = 0x100000|((addr&0x180)<<1);
 399                 }
 400                 breg = 1;
 401         }
 402         EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1);    // ldrh r0, [r1, (op&0x7f)<<1]
 403         hostreg_r[0] = -1;
 404 }
 405
 406 /* write r0 to bank. Trashes r1. */
 407 static void tr_bank_write(int addr)
 408 {
 409         int breg = 7;
 410         if (addr > 0x7f) {
 411                 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
 412                         EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1);  // add  r1, r7, ((op&0x180)<<1)
 413                         hostreg_r[1] = 0x100000|((addr&0x180)<<1);
 414                 }
 415                 breg = 1;
 416         }
 417         EOP_STRH_IMM(0,breg,(addr&0x7f)<<1);            // strh r0, [r1, (op&0x7f)<<1]
 418 }
 419
 420 /* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
 421 static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
 422 {
 423         int modulo_shift = -1;  /* unknown */
 424
 425         if (mod == 0) return;
 426
 427         if (!need_modulo || mod == 1) // +!
 428                 modulo_shift = 8;
 429         else if (need_modulo && (known_regb & KRREG_ST)) {
 430                 modulo_shift = known_regs.gr[SSP_ST].h & 7;
 431                 if (modulo_shift == 0) modulo_shift = 8;
 432         }
 433
 434         if (modulo_shift == -1)
 435         {
 436                 int reg = (r < 4) ? 8 : 9;
 437                 tr_release_pr(r);
 438                 if (dirty_regb & KRREG_ST) {
 439                         // avoid flushing ARM flags
 440                         EOP_AND_IMM(1, 6, 0, 0x70);
 441                         EOP_SUB_IMM(1, 1, 0, 0x10);
 442                         EOP_AND_IMM(1, 1, 0, 0x70);
 443                         EOP_ADD_IMM(1, 1, 0, 0x10);
 444                 } else {
 445                         EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands  r1, r6, #0x70
 446                         EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
 447                 }
 448                 EOP_MOV_REG_LSR(1, 1, 4);               // mov r1, r1, lsr #4
 449                 EOP_RSB_IMM(2, 1, 0, 8);                // rsb r1, r1, #8
 450                 EOP_MOV_IMM(3, 8/2, count);             // mov r3, #0x01000000
 451                 if (r&3)
 452                         EOP_ADD_IMM(1, 1, 0, (r&3)*8);  // add r1, r1, #(r&3)*8
 453                 EOP_MOV_REG2_ROR(reg,reg,1);            // mov reg, reg, ror r1
 454                 if (mod == 2)
 455                      EOP_SUB_REG2_LSL(reg,reg,3,2);     // sub reg, reg, #0x01000000 << r2
 456                 else EOP_ADD_REG2_LSL(reg,reg,3,2);
 457                 EOP_RSB_IMM(1, 1, 0, 32);               // rsb r1, r1, #32
 458                 EOP_MOV_REG2_ROR(reg,reg,1);            // mov reg, reg, ror r1
 459                 hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
 460         }
 461         else if (known_regb & (1 << (r + 8)))
 462         {
 463                 int modulo = (1 << modulo_shift) - 1;
 464                 if (mod == 2)
 465                      known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
 466                 else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
 467         }
 468         else
 469         {
 470                 int reg = (r < 4) ? 8 : 9;
 471                 int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
 472                 EOP_MOV_REG_ROR(reg,reg,ror);
 473                 // {add|sub} reg, reg, #1<<shift
 474                 EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
 475                 EOP_MOV_REG_ROR(reg,reg,32-ror);
 476         }
 477 }
 478
 479 /* handle writes r0 to (rX). Trashes r1.
 480  * fortunately we can ignore modulo increment modes for writes. */
 481 static void tr_rX_write(int op)
 482 {
 483         if ((op&3) == 3)
 484         {
 485                 int mod = (op>>2) & 3; // direct addressing
 486                 tr_bank_write((op & 0x100) + mod);
 487         }
 488         else
 489         {
 490                 int r = (op&3) | ((op>>6)&4);
 491                 if (known_regb & (1 << (r + 8))) {
 492                         tr_bank_write((op&0x100) | known_regs.r[r]);
 493                 } else {
 494                         int reg = (r < 4) ? 8 : 9;
 495                         int ror = ((4 - (r&3))*8) & 0x1f;
 496                         EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 497                         if (r >= 4)
 498                                 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 499                         if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 500                         else     EOP_ADD_REG_LSL(1,7,1,1);
 501                         EOP_STRH_SIMPLE(0,1);                           // strh r0, [r1]
 502                         hostreg_r[1] = -1;
 503                 }
 504                 tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
 505         }
 506 }
 507
 508 /* read (rX) to r0. Trashes r1-r3. */
 509 static void tr_rX_read(int r, int mod)
 510 {
 511         if ((r&3) == 3)
 512         {
 513                 tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
 514         }
 515         else
 516         {
 517                 if (known_regb & (1 << (r + 8))) {
 518                         tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
 519                 } else {
 520                         int reg = (r < 4) ? 8 : 9;
 521                         int ror = ((4 - (r&3))*8) & 0x1f;
 522                         EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 523                         if (r >= 4)
 524                                 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 525                         if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 526                         else     EOP_ADD_REG_LSL(1,7,1,1);
 527                         EOP_LDRH_SIMPLE(0,1);                           // ldrh r0, [r1]
 528                         hostreg_r[0] = hostreg_r[1] = -1;
 529                 }
 530                 tr_ptrr_mod(r, mod, 1, 1);
 531         }
 532 }
 533
 534 /* read ((rX)) to r0. Trashes r1,r2. */
 535 static void tr_rX_read2(int op)
 536 {
 537         int r = (op&3) | ((op>>6)&4); // src
 538
 539         if ((r&3) == 3) {
 540                 tr_bank_read((op&0x100) | ((op>>2)&3));
 541         } else if (known_regb & (1 << (r+8))) {
 542                 tr_bank_read((op&0x100) | known_regs.r[r]);
 543         } else {
 544                 int reg = (r < 4) ? 8 : 9;
 545                 int ror = ((4 - (r&3))*8) & 0x1f;
 546                 EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 547                 if (r >= 4)
 548                         EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 549                 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 550                 else     EOP_ADD_REG_LSL(1,7,1,1);
 551                 EOP_LDRH_SIMPLE(0,1);                           // ldrh r0, [r1]
 552         }
 553         EOP_LDR_IMM(2,7,0x48c);                                 // ptr_iram_rom
 554         EOP_ADD_REG_LSL(2,2,0,1);                               // add  r2, r2, r0, lsl #1
 555         EOP_ADD_IMM(0,0,0,1);                                   // add  r0, r0, #1
 556         if ((r&3) == 3) {
 557                 tr_bank_write((op&0x100) | ((op>>2)&3));
 558         } else if (known_regb & (1 << (r+8))) {
 559                 tr_bank_write((op&0x100) | known_regs.r[r]);
 560         } else {
 561                 EOP_STRH_SIMPLE(0,1);                           // strh r0, [r1]
 562                 hostreg_r[1] = -1;
 563         }
 564         EOP_LDRH_SIMPLE(0,2);                                   // ldrh r0, [r2]
 565         hostreg_r[0] = hostreg_r[2] = -1;
 566 }
 567
 568 // check if AL is going to be used later in block
 569 static int tr_predict_al_need(void)
 570 {
 571         int tmpv, tmpv2, op, pc = known_regs.gr[SSP_PC].h;
 572
 573         while (1)
 574         {
 575                 op = PROGRAM(pc);
 576                 switch (op >> 9)
 577                 {
 578                         // ld d, s
 579                         case 0x00:
 580                                 tmpv2 = (op >> 4) & 0xf; // dst
 581                                 tmpv  = op & 0xf; // src
 582                                 if ((tmpv2 == SSP_A && tmpv == SSP_P) || tmpv2 == SSP_AL) // ld A, P; ld AL, *
 583                                         return 0;
 584                                 break;
 585
 586                         // ld (ri), s
 587                         case 0x02:
 588                         // ld ri, s
 589                         case 0x0a:
 590                         // OP a, s
 591                         case 0x10: case 0x30: case 0x40: case 0x60: case 0x70:
 592                                 tmpv  = op & 0xf; // src
 593                                 if (tmpv == SSP_AL) // OP *, AL
 594                                         return 1;
 595                                 break;
 596
 597                         case 0x04:
 598                         case 0x06:
 599                         case 0x14:
 600                         case 0x34:
 601                         case 0x44:
 602                         case 0x64:
 603                         case 0x74: pc++; break;
 604
 605                         // call cond, addr
 606                         case 0x24:
 607                         // bra cond, addr
 608                         case 0x26:
 609                         // mod cond, op
 610                         case 0x48:
 611                         // mpys?
 612                         case 0x1b:
 613                         // mpya (rj), (ri), b
 614                         case 0x4b: return 1;
 615
 616                         // mld (rj), (ri), b
 617                         case 0x5b: return 0; // cleared anyway
 618
 619                         // and A, *
 620                         case 0x50:
 621                                 tmpv  = op & 0xf; // src
 622                                 if (tmpv == SSP_AL) return 1;
 623                         case 0x51: case 0x53: case 0x54: case 0x55: case 0x59: case 0x5c:
 624                                 return 0;
 625                 }
 626                 pc++;
 627         }
 628 }
 629
 630
 631 /* get ARM cond which would mean that SSP cond is satisfied. No trash. */
 632 static int tr_cond_check(int op)
 633 {
 634         int f = (op & 0x100) >> 8;
 635         switch (op&0xf0) {
 636                 case 0x00: return A_COND_AL;    /* always true */
 637                 case 0x50:                      /* Z matches f(?) bit */
 638                         if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
 639                         EOP_TST_IMM(6, 0, 4);
 640                         return f ? A_COND_NE : A_COND_EQ;
 641                 case 0x70:                      /* N matches f(?) bit */
 642                         if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
 643                         EOP_TST_IMM(6, 0, 8);
 644                         return f ? A_COND_NE : A_COND_EQ;
 645                 default:
 646                         elprintf(EL_ANOMALY, "unimplemented cond?\n");
 647                         tr_unhandled();
 648                         return 0;
 649         }
 650 }
 651
 652 static int tr_neg_cond(int cond)
 653 {
 654         switch (cond) {
 655                 case A_COND_AL: elprintf(EL_ANOMALY, "neg for AL?\n"); exit(1);
 656                 case A_COND_EQ: return A_COND_NE;
 657                 case A_COND_NE: return A_COND_EQ;
 658                 case A_COND_MI: return A_COND_PL;
 659                 case A_COND_PL: return A_COND_MI;
 660                 default:        elprintf(EL_ANOMALY, "bad cond for neg\n"); exit(1);
 661         }
 662         return 0;
 663 }
 664
 665 static int tr_aop_ssp2arm(int op)
 666 {
 667         switch (op) {
 668                 case 1: return A_OP_SUB;
 669                 case 3: return A_OP_CMP;
 670                 case 4: return A_OP_ADD;
 671                 case 5: return A_OP_AND;
 672                 case 6: return A_OP_ORR;
 673                 case 7: return A_OP_EOR;
 674         }
 675
 676         tr_unhandled();
 677         return 0;
 678 }
 679
 680 // -----------------------------------------------------
 681
 682 //@ r4:  XXYY
 683 //@ r5:  A
 684 //@ r6:  STACK and emu flags
 685 //@ r7:  SSP context
 686 //@ r10: P
 687
 688 // read general reg to r0. Trashes r1
 689 static void tr_GR0_to_r0(int op)
 690 {
 691         tr_mov16(0, 0xffff);
 692 }
 693
 694 static void tr_X_to_r0(int op)
 695 {
 696         if (hostreg_r[0] != (SSP_X<<16)) {
 697                 EOP_MOV_REG_LSR(0, 4, 16);      // mov  r0, r4, lsr #16
 698                 hostreg_r[0] = SSP_X<<16;
 699         }
 700 }
 701
 702 static void tr_Y_to_r0(int op)
 703 {
 704         if (hostreg_r[0] != (SSP_Y<<16)) {
 705                 EOP_MOV_REG_SIMPLE(0, 4);       // mov  r0, r4
 706                 hostreg_r[0] = SSP_Y<<16;
 707         }
 708 }
 709
 710 static void tr_A_to_r0(int op)
 711 {
 712         if (hostreg_r[0] != (SSP_A<<16)) {
 713                 EOP_MOV_REG_LSR(0, 5, 16);      // mov  r0, r5, lsr #16  @ AH
 714                 hostreg_r[0] = SSP_A<<16;
 715         }
 716 }
 717
 718 static void tr_ST_to_r0(int op)
 719 {
 720         // VR doesn't need much accuracy here..
 721         EOP_MOV_REG_LSR(0, 6, 4);               // mov  r0, r6, lsr #4
 722         EOP_AND_IMM(0, 0, 0, 0x67);             // and  r0, r0, #0x67
 723         hostreg_r[0] = -1;
 724 }
 725
 726 static void tr_STACK_to_r0(int op)
 727 {
 728         // 448
 729         EOP_SUB_IMM(6, 6,  8/2, 0x20);          // sub  r6, r6, #1<<29
 730         EOP_ADD_IMM(1, 7, 24/2, 0x04);          // add  r1, r7, 0x400
 731         EOP_ADD_IMM(1, 1, 0, 0x48);             // add  r1, r1, 0x048
 732         EOP_ADD_REG_LSR(1, 1, 6, 28);           // add  r1, r1, r6, lsr #28
 733         EOP_LDRH_SIMPLE(0, 1);                  // ldrh r0, [r1]
 734         hostreg_r[0] = hostreg_r[1] = -1;
 735 }
 736
 737 static void tr_PC_to_r0(int op)
 738 {
 739         tr_mov16(0, known_regs.gr[SSP_PC].h);
 740 }
 741
 742 static void tr_P_to_r0(int op)
 743 {
 744         tr_flush_dirty_P();
 745         EOP_MOV_REG_LSR(0, 10, 16);             // mov  r0, r10, lsr #16
 746         hostreg_r[0] = -1;
 747 }
 748
 749 static void tr_AL_to_r0(int op)
 750 {
 751         if (op == 0x000f) {
 752                 if (known_regb & KRREG_PMC) {
 753                         known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
 754                 } else {
 755                         EOP_LDR_IMM(0,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 756                         EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
 757                         EOP_STR_IMM(0,7,0x484);
 758                 }
 759         }
 760
 761         if (hostreg_r[0] != (SSP_AL<<16)) {
 762                 EOP_MOV_REG_SIMPLE(0, 5);       // mov  r0, r5
 763                 hostreg_r[0] = SSP_AL<<16;
 764         }
 765 }
 766
 767 static void tr_PMX_to_r0(int reg)
 768 {
 769         if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
 770         {
 771                 known_regs.pmac_read[reg] = known_regs.pmc.v;
 772                 known_regs.emu_status &= ~SSP_PMC_SET;
 773                 known_regb |= 1 << (20+reg);
 774                 dirty_regb |= 1 << (20+reg);
 775                 return;
 776         }
 777
 778         if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg))))
 779         {
 780                 u32 pmcv = known_regs.pmac_read[reg];
 781                 int mode = pmcv>>16;
 782                 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
 783
 784                 if      ((mode & 0xfff0) == 0x0800)
 785                 {
 786                         EOP_LDR_IMM(1,7,0x488);         // rom_ptr
 787                         emit_mov_const(A_COND_AL, 0, (pmcv&0xfffff)<<1);
 788                         EOP_LDRH_REG(0,1,0);            // ldrh r0, [r1, r0]
 789                         known_regs.pmac_read[reg] += 1;
 790                 }
 791                 else if ((mode & 0x47ff) == 0x0018) // DRAM
 792                 {
 793                         int inc = get_inc(mode);
 794                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
 795                         emit_mov_const(A_COND_AL, 0, (pmcv&0xffff)<<1);
 796                         EOP_LDRH_REG(0,1,0);            // ldrh r0, [r1, r0]
 797                         if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
 798                         {
 799                                 int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
 800                                 tr_flush_dirty_ST();
 801                                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 802                                 EOP_TST_REG_SIMPLE(0,0);
 803                                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1);       // subeq r11, r11, #1024
 804                                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
 805                                 EOP_STR_IMM(1,7,0x484);                 // str r1, [r7, #0x484] // emu_status
 806                         }
 807                         known_regs.pmac_read[reg] += inc;
 808                 }
 809                 else
 810                 {
 811                         tr_unhandled();
 812                 }
 813                 known_regs.pmc.v = known_regs.pmac_read[reg];
 814                 //known_regb |= KRREG_PMC;
 815                 dirty_regb |= KRREG_PMC;
 816                 dirty_regb |= 1 << (20+reg);
 817                 hostreg_r[0] = hostreg_r[1] = -1;
 818                 return;
 819         }
 820
 821         known_regb &= ~KRREG_PMC;
 822         dirty_regb &= ~KRREG_PMC;
 823         known_regb &= ~(1 << (20+reg));
 824         dirty_regb &= ~(1 << (20+reg));
 825
 826         // call the C code to handle this
 827         tr_flush_dirty_ST();
 828         //tr_flush_dirty_pmcrs();
 829         tr_mov16(0, reg);
 830         emit_call(A_COND_AL, ssp_pm_read);
 831         hostreg_clear();
 832 }
 833
 834 static void tr_PM0_to_r0(int op)
 835 {
 836         tr_PMX_to_r0(0);
 837 }
 838
 839 static void tr_PM1_to_r0(int op)
 840 {
 841         tr_PMX_to_r0(1);
 842 }
 843
 844 static void tr_PM2_to_r0(int op)
 845 {
 846         tr_PMX_to_r0(2);
 847 }
 848
 849 static void tr_XST_to_r0(int op)
 850 {
 851         EOP_ADD_IMM(0, 7, 24/2, 4);     // add r0, r7, #0x400
 852         EOP_LDRH_IMM(0, 0, SSP_XST*4+2);
 853 }
 854
 855 static void tr_PM4_to_r0(int op)
 856 {
 857         tr_PMX_to_r0(4);
 858 }
 859
 860 static void tr_PMC_to_r0(int op)
 861 {
 862         if (known_regb & KRREG_PMC)
 863         {
 864                 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
 865                         known_regs.emu_status |= SSP_PMC_SET;
 866                         known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
 867                         // do nothing - this is handled elsewhere
 868                 } else {
 869                         tr_mov16(0, known_regs.pmc.l);
 870                         known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
 871                 }
 872         }
 873         else
 874         {
 875                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 876                 tr_flush_dirty_ST();
 877                 if (op != 0x000e)
 878                         EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4);
 879                 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
 880                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
 881                 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
 882                 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET);       // orrne r1, r1, #..
 883                 EOP_STR_IMM(1,7,0x484);
 884                 hostreg_r[0] = hostreg_r[1] = -1;
 885         }
 886 }
 887
 888
 889 typedef void (tr_read_func)(int op);
 890
 891 static tr_read_func *tr_read_funcs[16] =
 892 {
 893         tr_GR0_to_r0,
 894         tr_X_to_r0,
 895         tr_Y_to_r0,
 896         tr_A_to_r0,
 897         tr_ST_to_r0,
 898         tr_STACK_to_r0,
 899         tr_PC_to_r0,
 900         tr_P_to_r0,
 901         tr_PM0_to_r0,
 902         tr_PM1_to_r0,
 903         tr_PM2_to_r0,
 904         tr_XST_to_r0,
 905         tr_PM4_to_r0,
 906         (tr_read_func *)tr_unhandled,
 907         tr_PMC_to_r0,
 908         tr_AL_to_r0
 909 };
 910
 911
 912 // write r0 to general reg handlers. Trashes r1
 913 #define TR_WRITE_R0_TO_REG(reg) \
 914 { \
 915         hostreg_sspreg_changed(reg); \
 916         hostreg_r[0] = (reg)<<16; \
 917         if (const_val != -1) { \
 918                 known_regs.gr[reg].h = const_val; \
 919                 known_regb |= 1 << (reg); \
 920         } else { \
 921                 known_regb &= ~(1 << (reg)); \
 922         } \
 923 }
 924
 925 static void tr_r0_to_GR0(int const_val)
 926 {
 927         // do nothing
 928 }
 929
 930 static void tr_r0_to_X(int const_val)
 931 {
 932         EOP_MOV_REG_LSL(4, 4, 16);              // mov  r4, r4, lsl #16
 933         EOP_MOV_REG_LSR(4, 4, 16);              // mov  r4, r4, lsr #16
 934         EOP_ORR_REG_LSL(4, 4, 0, 16);           // orr  r4, r4, r0, lsl #16
 935         dirty_regb |= KRREG_P;                  // touching X or Y makes P dirty.
 936         TR_WRITE_R0_TO_REG(SSP_X);
 937 }
 938
 939 static void tr_r0_to_Y(int const_val)
 940 {
 941         EOP_MOV_REG_LSR(4, 4, 16);              // mov  r4, r4, lsr #16
 942         EOP_ORR_REG_LSL(4, 4, 0, 16);           // orr  r4, r4, r0, lsl #16
 943         EOP_MOV_REG_ROR(4, 4, 16);              // mov  r4, r4, ror #16
 944         dirty_regb |= KRREG_P;
 945         TR_WRITE_R0_TO_REG(SSP_Y);
 946 }
 947
 948 static void tr_r0_to_A(int const_val)
 949 {
 950         if (tr_predict_al_need()) {
 951                 EOP_MOV_REG_LSL(5, 5, 16);      // mov  r5, r5, lsl #16
 952                 EOP_MOV_REG_LSR(5, 5, 16);      // mov  r5, r5, lsr #16  @ AL
 953                 EOP_ORR_REG_LSL(5, 5, 0, 16);   // orr  r5, r5, r0, lsl #16
 954         }
 955         else
 956                 EOP_MOV_REG_LSL(5, 0, 16);
 957         TR_WRITE_R0_TO_REG(SSP_A);
 958 }
 959
 960 static void tr_r0_to_ST(int const_val)
 961 {
 962         // VR doesn't need much accuracy here..
 963         EOP_AND_IMM(1, 0,   0, 0x67);           // and   r1, r0, #0x67
 964         EOP_AND_IMM(6, 6, 8/2, 0xe0);           // and   r6, r6, #7<<29     @ preserve STACK
 965         EOP_ORR_REG_LSL(6, 6, 1, 4);            // orr   r6, r6, r1, lsl #4
 966         TR_WRITE_R0_TO_REG(SSP_ST);
 967         hostreg_r[1] = -1;
 968         dirty_regb &= ~KRREG_ST;
 969 }
 970
 971 static void tr_r0_to_STACK(int const_val)
 972 {
 973         // 448
 974         EOP_ADD_IMM(1, 7, 24/2, 0x04);          // add  r1, r7, 0x400
 975         EOP_ADD_IMM(1, 1, 0, 0x48);             // add  r1, r1, 0x048
 976         EOP_ADD_REG_LSR(1, 1, 6, 28);           // add  r1, r1, r6, lsr #28
 977         EOP_STRH_SIMPLE(0, 1);                  // strh r0, [r1]
 978         EOP_ADD_IMM(6, 6,  8/2, 0x20);          // add  r6, r6, #1<<29
 979         hostreg_r[1] = -1;
 980 }
 981
 982 static void tr_r0_to_PC(int const_val)
 983 {
 984 /*
 985  * do nothing - dispatcher will take care of this
 986         EOP_MOV_REG_LSL(1, 0, 16);              // mov  r1, r0, lsl #16
 987         EOP_STR_IMM(1,7,0x400+6*4);             // str  r1, [r7, #(0x400+6*8)]
 988         hostreg_r[1] = -1;
 989 */
 990 }
 991
 992 static void tr_r0_to_AL(int const_val)
 993 {
 994         EOP_MOV_REG_LSR(5, 5, 16);              // mov  r5, r5, lsr #16
 995         EOP_ORR_REG_LSL(5, 5, 0, 16);           // orr  r5, r5, r0, lsl #16
 996         EOP_MOV_REG_ROR(5, 5, 16);              // mov  r5, r5, ror #16
 997         hostreg_sspreg_changed(SSP_AL);
 998         if (const_val != -1) {
 999                 known_regs.gr[SSP_A].l = const_val;
1000                 known_regb |= 1 << SSP_AL;
1001         } else
1002                 known_regb &= ~(1 << SSP_AL);
1003 }
1004
1005 static void tr_r0_to_PMX(int reg)
1006 {
1007         if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
1008         {
1009                 known_regs.pmac_write[reg] = known_regs.pmc.v;
1010                 known_regs.emu_status &= ~SSP_PMC_SET;
1011                 known_regb |= 1 << (25+reg);
1012                 dirty_regb |= 1 << (25+reg);
1013                 return;
1014         }
1015
1016         if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
1017         {
1018                 int mode, addr;
1019
1020                 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1021
1022                 mode = known_regs.pmac_write[reg]>>16;
1023                 addr = known_regs.pmac_write[reg]&0xffff;
1024                 if      ((mode & 0x43ff) == 0x0018) // DRAM
1025                 {
1026                         int inc = get_inc(mode);
1027                         if (mode & 0x0400) tr_unhandled();
1028                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
1029                         emit_mov_const(A_COND_AL, 2, addr<<1);
1030                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
1031                         known_regs.pmac_write[reg] += inc;
1032                 }
1033                 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
1034                 {
1035                         if (mode & 0x0400) tr_unhandled();
1036                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
1037                         emit_mov_const(A_COND_AL, 2, addr<<1);
1038                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
1039                         known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
1040                 }
1041                 else if ((mode & 0x47ff) == 0x001c) // IRAM
1042                 {
1043                         int inc = get_inc(mode);
1044                         EOP_LDR_IMM(1,7,0x48c);         // iram_ptr
1045                         emit_mov_const(A_COND_AL, 2, (addr&0x3ff)<<1);
1046                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
1047                         EOP_MOV_IMM(1,0,1);
1048                         EOP_STR_IMM(1,7,0x494);         // iram_dirty
1049                         known_regs.pmac_write[reg] += inc;
1050                 }
1051                 else
1052                         tr_unhandled();
1053
1054                 known_regs.pmc.v = known_regs.pmac_write[reg];
1055                 //known_regb |= KRREG_PMC;
1056                 dirty_regb |= KRREG_PMC;
1057                 dirty_regb |= 1 << (25+reg);
1058                 hostreg_r[1] = hostreg_r[2] = -1;
1059                 return;
1060         }
1061
1062         known_regb &= ~KRREG_PMC;
1063         dirty_regb &= ~KRREG_PMC;
1064         known_regb &= ~(1 << (25+reg));
1065         dirty_regb &= ~(1 << (25+reg));
1066
1067         // call the C code to handle this
1068         tr_flush_dirty_ST();
1069         //tr_flush_dirty_pmcrs();
1070         tr_mov16(1, reg);
1071         emit_call(A_COND_AL, ssp_pm_write);
1072         hostreg_clear();
1073 }
1074
1075 static void tr_r0_to_PM0(int const_val)
1076 {
1077         tr_r0_to_PMX(0);
1078 }
1079
1080 static void tr_r0_to_PM1(int const_val)
1081 {
1082         tr_r0_to_PMX(1);
1083 }
1084
1085 static void tr_r0_to_PM2(int const_val)
1086 {
1087         tr_r0_to_PMX(2);
1088 }
1089
1090 static void tr_r0_to_PM4(int const_val)
1091 {
1092         tr_r0_to_PMX(4);
1093 }
1094
1095 static void tr_r0_to_PMC(int const_val)
1096 {
1097         if ((known_regb & KRREG_PMC) && const_val != -1)
1098         {
1099                 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
1100                         known_regs.emu_status |= SSP_PMC_SET;
1101                         known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1102                         known_regs.pmc.h = const_val;
1103                 } else {
1104                         known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
1105                         known_regs.pmc.l = const_val;
1106                 }
1107         }
1108         else
1109         {
1110                 tr_flush_dirty_ST();
1111                 if (known_regb & KRREG_PMC) {
1112                         emit_mov_const(A_COND_AL, 1, known_regs.pmc.v);
1113                         EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
1114                         known_regb &= ~KRREG_PMC;
1115                         dirty_regb &= ~KRREG_PMC;
1116                 }
1117                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
1118                 EOP_ADD_IMM(2,7,24/2,4);                // add r2, r7, #0x400
1119                 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
1120                 EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4);         // strxx r0, [r2, #SSP_PMC]
1121                 EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2);
1122                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
1123                 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
1124                 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET);       // orrne r1, r1, #..
1125                 EOP_STR_IMM(1,7,0x484);
1126                 hostreg_r[1] = hostreg_r[2] = -1;
1127         }
1128 }
1129
1130 typedef void (tr_write_func)(int const_val);
1131
1132 static tr_write_func *tr_write_funcs[16] =
1133 {
1134         tr_r0_to_GR0,
1135         tr_r0_to_X,
1136         tr_r0_to_Y,
1137         tr_r0_to_A,
1138         tr_r0_to_ST,
1139         tr_r0_to_STACK,
1140         tr_r0_to_PC,
1141         (tr_write_func *)tr_unhandled,
1142         tr_r0_to_PM0,
1143         tr_r0_to_PM1,
1144         tr_r0_to_PM2,
1145         (tr_write_func *)tr_unhandled,
1146         tr_r0_to_PM4,
1147         (tr_write_func *)tr_unhandled,
1148         tr_r0_to_PMC,
1149         tr_r0_to_AL
1150 };
1151
1152 static void tr_mac_load_XY(int op)
1153 {
1154         tr_rX_read(op&3, (op>>2)&3); // X
1155         EOP_MOV_REG_LSL(4, 0, 16);
1156         tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
1157         EOP_ORR_REG_SIMPLE(4, 0);
1158         dirty_regb |= KRREG_P;
1159         hostreg_sspreg_changed(SSP_X);
1160         hostreg_sspreg_changed(SSP_Y);
1161         known_regb &= ~KRREG_X;
1162         known_regb &= ~KRREG_Y;
1163 }
1164
1165 // -----------------------------------------------------
1166
1167 static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
1168 {
1169         u32 pmcv, tmpv;
1170         if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
1171
1172         // programming PMC:
1173         // ldi PMC, imm1
1174         // ldi PMC, imm2
1175         (*pc)++;
1176         pmcv = imm | (PROGRAM((*pc)++) << 16);
1177         known_regs.pmc.v = pmcv;
1178         known_regb |= KRREG_PMC;
1179         dirty_regb |= KRREG_PMC;
1180         known_regs.emu_status |= SSP_PMC_SET;
1181         n_in_ops++;
1182
1183         // check for possible reg programming
1184         tmpv = PROGRAM(*pc);
1185         if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
1186         {
1187                 int is_write = (tmpv & 0xff8f) == 0x80;
1188                 int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
1189                 if (reg > 4) tr_unhandled();
1190                 if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled();
1191                 known_regs.pmac_read[is_write ? reg + 5 : reg] = pmcv;
1192                 known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
1193                 dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
1194                 known_regs.emu_status &= ~SSP_PMC_SET;
1195                 (*pc)++;
1196                 n_in_ops++;
1197                 return 5;
1198         }
1199
1200         tr_unhandled();
1201         return 4;
1202 }
1203
1204 static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
1205
1206 static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
1207 {
1208         // ldi ST, 0
1209         // ldi PM0, 0
1210         // ldi PM0, 0
1211         // ldi ST, 60h
1212         unsigned short *pp;
1213         if (op != 0x0840 || imm != 0) return 0;
1214         pp = PROGRAM_P(*pc);
1215         if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
1216
1217         EOP_AND_IMM(6, 6, 8/2, 0xe0);           // and   r6, r6, #7<<29     @ preserve STACK
1218         EOP_ORR_IMM(6, 6, 24/2, 6);             // orr   r6, r6, 0x600
1219         hostreg_sspreg_changed(SSP_ST);
1220         known_regs.gr[SSP_ST].h = 0x60;
1221         known_regb |= 1 << SSP_ST;
1222         dirty_regb &= ~KRREG_ST;
1223         (*pc) += 3*2;
1224         n_in_ops += 3;
1225         return 4*2;
1226 }
1227
1228 static int tr_detect_rotate(unsigned int op, int *pc, int imm)
1229 {
1230         // @ 3DA2 and 426A
1231         // ld PMC, (r3|00)
1232         // ld (r3|00), PMC
1233         // ld -, AL
1234         if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0;
1235
1236         tr_bank_read(0);
1237         EOP_MOV_REG_LSL(0, 0, 4);
1238         EOP_ORR_REG_LSR(0, 0, 0, 16);
1239         tr_bank_write(0);
1240         (*pc) += 2;
1241         n_in_ops += 2;
1242         return 3;
1243 }
1244
1245 // -----------------------------------------------------
1246
1247 static int translate_op(unsigned int op, int *pc, int imm, int *end_cond, int *jump_pc)
1248 {
1249         u32 tmpv, tmpv2, tmpv3;
1250         int ret = 0;
1251         known_regs.gr[SSP_PC].h = *pc;
1252
1253         switch (op >> 9)
1254         {
1255                 // ld d, s
1256                 case 0x00:
1257                         if (op == 0) { ret++; break; } // nop
1258                         tmpv  = op & 0xf; // src
1259                         tmpv2 = (op >> 4) & 0xf; // dst
1260                         if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
1261                                 tr_flush_dirty_P();
1262                                 EOP_MOV_REG_SIMPLE(5, 10);
1263                                 hostreg_sspreg_changed(SSP_A);
1264                                 known_regb &= ~(KRREG_A|KRREG_AL);
1265                                 ret++; break;
1266                         }
1267                         tr_read_funcs[tmpv](op);
1268                         tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
1269                         if (tmpv2 == SSP_PC) {
1270                                 ret |= 0x10000;
1271                                 *end_cond = -A_COND_AL;
1272                         }
1273                         ret++; break;
1274
1275                 // ld d, (ri)
1276                 case 0x01: {
1277                         int r = (op&3) | ((op>>6)&4);
1278                         int mod = (op>>2)&3;
1279                         tmpv = (op >> 4) & 0xf; // dst
1280                         ret = tr_detect_rotate(op, pc, imm);
1281                         if (ret > 0) break;
1282                         if (tmpv != 0)
1283                                 tr_rX_read(r, mod);
1284                         else {
1285                                 int cnt = 1;
1286                                 while (PROGRAM(*pc) == op) {
1287                                         (*pc)++; cnt++; ret++;
1288                                         n_in_ops++;
1289                                 }
1290                                 tr_ptrr_mod(r, mod, 1, cnt); // skip
1291                         }
1292                         tr_write_funcs[tmpv](-1);
1293                         if (tmpv == SSP_PC) {
1294                                 ret |= 0x10000;
1295                                 *end_cond = -A_COND_AL;
1296                         }
1297                         ret++; break;
1298                 }
1299
1300                 // ld (ri), s
1301                 case 0x02:
1302                         tmpv = (op >> 4) & 0xf; // src
1303                         tr_read_funcs[tmpv](op);
1304                         tr_rX_write(op);
1305                         ret++; break;
1306
1307                 // ld a, adr
1308                 case 0x03:
1309                         tr_bank_read(op&0x1ff);
1310                         tr_r0_to_A(-1);
1311                         ret++; break;
1312
1313                 // ldi d, imm
1314                 case 0x04:
1315                         tmpv = (op & 0xf0) >> 4; // dst
1316                         ret = tr_detect_pm0_block(op, pc, imm);
1317                         if (ret > 0) break;
1318                         ret = tr_detect_set_pm(op, pc, imm);
1319                         if (ret > 0) break;
1320                         tr_mov16(0, imm);
1321                         tr_write_funcs[tmpv](imm);
1322                         if (tmpv == SSP_PC) {
1323                                 ret |= 0x10000;
1324                                 *jump_pc = imm;
1325                         }
1326                         ret += 2; break;
1327
1328                 // ld d, ((ri))
1329                 case 0x05:
1330                         tmpv2 = (op >> 4) & 0xf;  // dst
1331                         tr_rX_read2(op);
1332                         tr_write_funcs[tmpv2](-1);
1333                         if (tmpv2 == SSP_PC) {
1334                                 ret |= 0x10000;
1335                                 *end_cond = -A_COND_AL;
1336                         }
1337                         ret += 3; break;
1338
1339                 // ldi (ri), imm
1340                 case 0x06:
1341                         tr_mov16(0, imm);
1342                         tr_rX_write(op);
1343                         ret += 2; break;
1344
1345                 // ld adr, a
1346                 case 0x07:
1347                         tr_A_to_r0(op);
1348                         tr_bank_write(op&0x1ff);
1349                         ret++; break;
1350
1351                 // ld d, ri
1352                 case 0x09: {
1353                         int r;
1354                         r = (op&3) | ((op>>6)&4); // src
1355                         tmpv2 = (op >> 4) & 0xf;  // dst
1356                         if ((r&3) == 3) tr_unhandled();
1357
1358                         if (known_regb & (1 << (r+8))) {
1359                                 tr_mov16(0, known_regs.r[r]);
1360                                 tr_write_funcs[tmpv2](known_regs.r[r]);
1361                         } else {
1362                                 int reg = (r < 4) ? 8 : 9;
1363                                 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8);      // mov r0, r{7,8}, lsr #lsr
1364                                 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff);           // and r0, r{7,8}, <mask>
1365                                 hostreg_r[0] = -1;
1366                                 tr_write_funcs[tmpv2](-1);
1367                         }
1368                         ret++; break;
1369                 }
1370
1371                 // ld ri, s
1372                 case 0x0a: {
1373                         int r;
1374                         r = (op&3) | ((op>>6)&4); // dst
1375                         tmpv = (op >> 4) & 0xf;   // src
1376                         if ((r&3) == 3) tr_unhandled();
1377
1378                         if (known_regb & (1 << tmpv)) {
1379                                 known_regs.r[r] = known_regs.gr[tmpv].h;
1380                                 known_regb |= 1 << (r + 8);
1381                                 dirty_regb |= 1 << (r + 8);
1382                         } else {
1383                                 int reg = (r < 4) ? 8 : 9;
1384                                 int ror = ((4 - (r&3))*8) & 0x1f;
1385                                 tr_read_funcs[tmpv](op);
1386                                 EOP_BIC_IMM(reg, reg, ror/2, 0xff);             // bic r{7,8}, r{7,8}, <mask>
1387                                 EOP_AND_IMM(0, 0, 0, 0xff);                     // and r0, r0, 0xff
1388                                 EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8);          // orr r{7,8}, r{7,8}, r0, lsl #lsl
1389                                 hostreg_r[0] = -1;
1390                                 known_regb &= ~(1 << (r+8));
1391                                 dirty_regb &= ~(1 << (r+8));
1392                         }
1393                         ret++; break;
1394                 }
1395
1396                 // ldi ri, simm
1397                 case 0x0c ... 0x0f:
1398                         tmpv = (op>>8)&7;
1399                         known_regs.r[tmpv] = op;
1400                         known_regb |= 1 << (tmpv + 8);
1401                         dirty_regb |= 1 << (tmpv + 8);
1402                         ret++; break;
1403
1404                 // call cond, addr
1405                 case 0x24: {
1406                         u32 *jump_op = NULL;
1407                         tmpv = tr_cond_check(op);
1408                         if (tmpv != A_COND_AL) {
1409                                 jump_op = tcache_ptr;
1410                                 EOP_MOV_IMM(0, 0, 0); // placeholder for branch
1411                         }
1412                         tr_mov16(0, *pc);
1413                         tr_r0_to_STACK(*pc);
1414                         if (tmpv != A_COND_AL) {
1415                                 u32 *real_ptr = tcache_ptr;
1416                                 tcache_ptr = jump_op;
1417                                 EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2);
1418                                 tcache_ptr = real_ptr;
1419                         }
1420                         tr_mov16_cond(tmpv, 0, imm);
1421                         if (tmpv != A_COND_AL)
1422                                 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
1423                         tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
1424                         ret |= 0x10000;
1425                         *end_cond = tmpv;
1426                         *jump_pc = imm;
1427                         ret += 2; break;
1428                 }
1429
1430                 // ld d, (a)
1431                 case 0x25:
1432                         tmpv2 = (op >> 4) & 0xf;  // dst
1433                         tr_A_to_r0(op);
1434                         EOP_LDR_IMM(1,7,0x48c);                                 // ptr_iram_rom
1435                         EOP_ADD_REG_LSL(0,1,0,1);                               // add  r0, r1, r0, lsl #1
1436                         EOP_LDRH_SIMPLE(0,0);                                   // ldrh r0, [r0]
1437                         hostreg_r[0] = hostreg_r[1] = -1;
1438                         tr_write_funcs[tmpv2](-1);
1439                         if (tmpv2 == SSP_PC) {
1440                                 ret |= 0x10000;
1441                                 *end_cond = -A_COND_AL;
1442                         }
1443                         ret += 3; break;
1444
1445                 // bra cond, addr
1446                 case 0x26:
1447                         tmpv = tr_cond_check(op);
1448                         tr_mov16_cond(tmpv, 0, imm);
1449                         if (tmpv != A_COND_AL)
1450                                 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
1451                         tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
1452                         ret |= 0x10000;
1453                         *end_cond = tmpv;
1454                         *jump_pc = imm;
1455                         ret += 2; break;
1456
1457                 // mod cond, op
1458                 case 0x48: {
1459                         // check for repeats of this op
1460                         tmpv = 1; // count
1461                         while (PROGRAM(*pc) == op && (op & 7) != 6) {
1462                                 (*pc)++; tmpv++;
1463                                 n_in_ops++;
1464                         }
1465                         if ((op&0xf0) != 0) // !always
1466                                 tr_make_dirty_ST();
1467
1468                         tmpv2 = tr_cond_check(op);
1469                         switch (op & 7) {
1470                                 case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
1471                                 case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
1472                                 case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
1473                                 case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor  r1, r5, r5, asr #31
1474                                         EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
1475                                         hostreg_r[1] = -1; break; // abs
1476                                 default: tr_unhandled();
1477                         }
1478
1479                         hostreg_sspreg_changed(SSP_A);
1480                         dirty_regb |=  KRREG_ST;
1481                         known_regb &= ~KRREG_ST;
1482                         known_regb &= ~(KRREG_A|KRREG_AL);
1483                         ret += tmpv; break;
1484                 }
1485
1486                 // mpys?
1487                 case 0x1b:
1488                         tr_flush_dirty_P();
1489                         tr_mac_load_XY(op);
1490                         tr_make_dirty_ST();
1491                         EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
1492                         hostreg_sspreg_changed(SSP_A);
1493                         known_regb &= ~(KRREG_A|KRREG_AL);
1494                         dirty_regb |= KRREG_ST;
1495                         ret++; break;
1496
1497                 // mpya (rj), (ri), b
1498                 case 0x4b:
1499                         tr_flush_dirty_P();
1500                         tr_mac_load_XY(op);
1501                         tr_make_dirty_ST();
1502                         EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
1503                         hostreg_sspreg_changed(SSP_A);
1504                         known_regb &= ~(KRREG_A|KRREG_AL);
1505                         dirty_regb |= KRREG_ST;
1506                         ret++; break;
1507
1508                 // mld (rj), (ri), b
1509                 case 0x5b:
1510                         EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
1511                         hostreg_sspreg_changed(SSP_A);
1512                         known_regs.gr[SSP_A].v = 0;
1513                         known_regb |= (KRREG_A|KRREG_AL);
1514                         dirty_regb |= KRREG_ST;
1515                         tr_mac_load_XY(op);
1516                         ret++; break;
1517
1518                 // OP a, s
1519                 case 0x10:
1520                 case 0x30:
1521                 case 0x40:
1522                 case 0x50:
1523                 case 0x60:
1524                 case 0x70:
1525                         tmpv = op & 0xf; // src
1526                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1527                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1528                         if (tmpv == SSP_P) {
1529                                 tr_flush_dirty_P();
1530                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
1531                         } else if (tmpv == SSP_A) {
1532                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
1533                         } else {
1534                                 tr_read_funcs[tmpv](op);
1535                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
1536                         }
1537                         hostreg_sspreg_changed(SSP_A);
1538                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1539                         dirty_regb |= KRREG_ST;
1540                         ret++; break;
1541
1542                 // OP a, (ri)
1543                 case 0x11:
1544                 case 0x31:
1545                 case 0x41:
1546                 case 0x51:
1547                 case 0x61:
1548                 case 0x71:
1549                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1550                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1551                         tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
1552                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1553                         hostreg_sspreg_changed(SSP_A);
1554                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1555                         dirty_regb |= KRREG_ST;
1556                         ret++; break;
1557
1558                 // OP a, adr
1559                 case 0x13:
1560                 case 0x33:
1561                 case 0x43:
1562                 case 0x53:
1563                 case 0x63:
1564                 case 0x73:
1565                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1566                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1567                         tr_bank_read(op&0x1ff);
1568                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1569                         hostreg_sspreg_changed(SSP_A);
1570                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1571                         dirty_regb |= KRREG_ST;
1572                         ret++; break;
1573
1574                 // OP a, imm
1575                 case 0x14:
1576                 case 0x34:
1577                 case 0x44:
1578                 case 0x54:
1579                 case 0x64:
1580                 case 0x74:
1581                         tmpv = (op & 0xf0) >> 4;
1582                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1583                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1584                         tr_mov16(0, imm);
1585                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1586                         hostreg_sspreg_changed(SSP_A);
1587                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1588                         dirty_regb |= KRREG_ST;
1589                         ret += 2; break;
1590
1591                 // OP a, ((ri))
1592                 case 0x15:
1593                 case 0x35:
1594                 case 0x45:
1595                 case 0x55:
1596                 case 0x65:
1597                 case 0x75:
1598                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1599                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1600                         tr_rX_read2(op);
1601                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1602                         hostreg_sspreg_changed(SSP_A);
1603                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1604                         dirty_regb |= KRREG_ST;
1605                         ret += 3; break;
1606
1607                 // OP a, ri
1608                 case 0x19:
1609                 case 0x39:
1610                 case 0x49:
1611                 case 0x59:
1612                 case 0x69:
1613                 case 0x79: {
1614                         int r;
1615                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1616                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1617                         r = (op&3) | ((op>>6)&4); // src
1618                         if ((r&3) == 3) tr_unhandled();
1619
1620                         if (known_regb & (1 << (r+8))) {
1621                                 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]);  // OPs r5, r5, #val<<16
1622                         } else {
1623                                 int reg = (r < 4) ? 8 : 9;
1624                                 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8);      // mov r0, r{7,8}, lsr #lsr
1625                                 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff);           // and r0, r{7,8}, <mask>
1626                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1627                                 hostreg_r[0] = -1;
1628                         }
1629                         hostreg_sspreg_changed(SSP_A);
1630                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1631                         dirty_regb |= KRREG_ST;
1632                         ret++; break;
1633                 }
1634
1635                 // OP simm
1636                 case 0x1c:
1637                 case 0x3c:
1638                 case 0x4c:
1639                 case 0x5c:
1640                 case 0x6c:
1641                 case 0x7c:
1642                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1643                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1644                         EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff);        // OPs r5, r5, #val<<16
1645                         hostreg_sspreg_changed(SSP_A);
1646                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1647                         dirty_regb |= KRREG_ST;
1648                         ret++; break;
1649         }
1650
1651         n_in_ops++;
1652
1653         return ret;
1654 }
1655
1656 static void emit_block_prologue(void)
1657 {
1658         // check if there are enough cycles..
1659         // note: r0 must contain PC of current block
1660         EOP_CMP_IMM(11,0,0);                    // cmp r11, #0
1661         emit_call(A_COND_LE, ssp_drc_end);
1662 }
1663
1664 /* cond:
1665  * >0: direct (un)conditional jump
1666  * <0: indirect jump
1667  */
1668 static void emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
1669 {
1670         if (cycles > 0xff) { elprintf(EL_ANOMALY, "large cycle count: %i\n", cycles); cycles = 0xff; }
1671         EOP_SUB_IMM(11,11,0,cycles);            // sub r11, r11, #cycles
1672
1673         if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) {
1674                 // indirect jump, or rom -> iram jump, must use dispatcher
1675                 emit_jump(A_COND_AL, ssp_drc_next);
1676         }
1677         else if (cond == A_COND_AL) {
1678                 u32 *target = (pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][pc] : ssp_block_table[pc];
1679                 if (target != NULL)
1680                         emit_jump(A_COND_AL, target);
1681                 else {
1682                         emit_jump(A_COND_AL, ssp_drc_next);
1683                         // cause the next block to be emitted over jump instrction
1684                         tcache_ptr--;
1685                 }
1686         }
1687         else {
1688                 u32 *target1 = (pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][pc] : ssp_block_table[pc];
1689                 u32 *target2 = (end_pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][end_pc] : ssp_block_table[end_pc];
1690                 if (target1 != NULL)
1691                      emit_jump(cond, target1);
1692                 else emit_call(cond, ssp_drc_next_patch);
1693                 if (target2 != NULL)
1694                      emit_jump(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
1695                 else emit_call(tr_neg_cond(cond), ssp_drc_next_patch);
1696         }
1697 }
1698
1699 void *ssp_translate_block(int pc)
1700 {
1701         unsigned int op, op1, imm, ccount = 0;
1702         unsigned int *block_start;
1703         int ret, end_cond = A_COND_AL, jump_pc = -1;
1704
1705         //printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
1706         block_start = tcache_ptr;
1707         known_regb = 0;
1708         dirty_regb = KRREG_P;
1709         known_regs.emu_status = 0;
1710         hostreg_clear();
1711
1712         emit_block_prologue();
1713
1714         for (; ccount < 100;)
1715         {
1716                 op = PROGRAM(pc++);
1717                 op1 = op >> 9;
1718                 imm = (u32)-1;
1719
1720                 if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
1721                         imm = PROGRAM(pc++); // immediate
1722
1723                 ret = translate_op(op, &pc, imm, &end_cond, &jump_pc);
1724                 if (ret <= 0)
1725                 {
1726                         elprintf(EL_ANOMALY, "NULL func! op=%08x (%02x)\n", op, op1);
1727                         //exit(1);
1728                 }
1729
1730                 ccount += ret & 0xffff;
1731                 if (ret & 0x10000) break;
1732         }
1733
1734         if (ccount >= 100) {
1735                 end_cond = A_COND_AL;
1736                 jump_pc = pc;
1737                 emit_mov_const(A_COND_AL, 0, pc);
1738         }
1739
1740         tr_flush_dirty_prs();
1741         tr_flush_dirty_ST();
1742         tr_flush_dirty_pmcrs();
1743         emit_block_epilogue(ccount, end_cond, jump_pc, pc);
1744
1745         if (tcache_ptr - tcache > SSP_TCACHE_SIZE/4) {
1746                 elprintf(EL_ANOMALY, "tcache overflow!\n");
1747                 fflush(stdout);
1748                 exit(1);
1749         }
1750
1751         // stats
1752         nblocks++;
1753         //printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (tcache_ptr - tcache)*4,
1754         //      (double)(tcache_ptr - tcache) / (double)n_in_ops);
1755
1756 #ifdef DUMP_BLOCK
1757         {
1758                 FILE *f = fopen("tcache.bin", "wb");
1759                 fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
1760                 fclose(f);
1761         }
1762         exit(0);
1763 #endif
1764
1765         handle_caches();
1766
1767         return block_start;
1768 }
1769
1770
1771
1772 // -----------------------------------------------------
1773
1774 static void ssp1601_state_load(void)
1775 {
1776         ssp->drc.iram_dirty = 1;
1777         ssp->drc.iram_context = 0;
1778 }
1779
1780 int ssp1601_dyn_startup(void)
1781 {
1782         memset(tcache, 0, SSP_TCACHE_SIZE);
1783         memset(ssp_block_table, 0, sizeof(ssp_block_table));
1784         memset(ssp_block_table_iram, 0, sizeof(ssp_block_table_iram));
1785         tcache_ptr = tcache;
1786
1787         PicoLoadStateHook = ssp1601_state_load;
1788
1789         n_in_ops = 0;
1790 #ifdef ARM
1791         // hle'd blocks
1792         ssp_block_table[0x800/2] = (void *) ssp_hle_800;
1793         ssp_block_table[0x902/2] = (void *) ssp_hle_902;
1794         ssp_block_table_iram[ 7][0x030/2] = (void *) ssp_hle_07_030;
1795         ssp_block_table_iram[ 7][0x036/2] = (void *) ssp_hle_07_036;
1796         ssp_block_table_iram[ 7][0x6d6/2] = (void *) ssp_hle_07_6d6;
1797         ssp_block_table_iram[11][0x12c/2] = (void *) ssp_hle_11_12c;
1798         ssp_block_table_iram[11][0x384/2] = (void *) ssp_hle_11_384;
1799         ssp_block_table_iram[11][0x38a/2] = (void *) ssp_hle_11_38a;
1800 #endif
1801
1802         return 0;
1803 }
1804
1805
1806 void ssp1601_dyn_reset(ssp1601_t *ssp)
1807 {
1808         ssp1601_reset(ssp);
1809         ssp->drc.iram_dirty = 1;
1810         ssp->drc.iram_context = 0;
1811         // must do this here because ssp is not available @ startup()
1812         ssp->drc.ptr_rom = (u32) Pico.rom;
1813         ssp->drc.ptr_iram_rom = (u32) svp->iram_rom;
1814         ssp->drc.ptr_dram = (u32) svp->dram;
1815         ssp->drc.ptr_btable = (u32) ssp_block_table;
1816         ssp->drc.ptr_btable_iram = (u32) ssp_block_table_iram;
1817
1818         // prevent new versions of IRAM from appearing
1819         memset(svp->iram_rom, 0, 0x800);
1820 }
1821
1822 void ssp1601_dyn_run(int cycles)
1823 {
1824         if (ssp->emu_status & SSP_WAIT_MASK) return;
1825
1826 #ifdef DUMP_BLOCK
1827         ssp_translate_block(DUMP_BLOCK >> 1);
1828 #endif
1829 #ifdef ARM
1830         ssp_drc_entry(cycles);
1831 #endif
1832 }
1833