Pico/carthw/svp/gen_arm.c

   1 #define EMIT(x) *tcache_ptr++ = x
   2
   3 #define A_R4M  (1 << 4)
   4 #define A_R5M  (1 << 5)
   5 #define A_R6M  (1 << 6)
   6 #define A_R7M  (1 << 7)
   7 #define A_R8M  (1 << 8)
   8 #define A_R9M  (1 << 9)
   9 #define A_R10M (1 << 10)
  10 #define A_R11M (1 << 11)
  11 #define A_R14M (1 << 14)
  12
  13 #define A_COND_AL 0xe
  14 #define A_COND_EQ 0x0
  15 #define A_COND_NE 0x1
  16 #define A_COND_MI 0x4
  17 #define A_COND_PL 0x5
  18 #define A_COND_LE 0xd
  19
  20 /* addressing mode 1 */
  21 #define A_AM1_LSL 0
  22 #define A_AM1_LSR 1
  23 #define A_AM1_ASR 2
  24 #define A_AM1_ROR 3
  25
  26 #define A_AM1_IMM(ror2,imm8)                  (((ror2)<<8) | (imm8) | 0x02000000)
  27 #define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
  28 #define A_AM1_REG_XREG(rs,shift_op,rm)        (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm))
  29
  30 /* data processing op */
  31 #define A_OP_AND 0x0
  32 #define A_OP_EOR 0x1
  33 #define A_OP_SUB 0x2
  34 #define A_OP_RSB 0x3
  35 #define A_OP_ADD 0x4
  36 #define A_OP_TST 0x8
  37 #define A_OP_CMP 0xa
  38 #define A_OP_ORR 0xc
  39 #define A_OP_MOV 0xd
  40 #define A_OP_BIC 0xe
  41
  42 #define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
  43         EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
  44
  45 #define EOP_C_DOP_IMM(     cond,op,s,rn,rd,ror2,imm8)             EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
  46 #define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
  47 #define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs,       shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs,       shift_op,rm))
  48
  49 #define EOP_MOV_IMM(rd,   ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
  50 #define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
  51 #define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
  52 #define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
  53 #define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
  54 #define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
  55 #define EOP_TST_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
  56 #define EOP_CMP_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
  57 #define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
  58
  59 #define EOP_MOV_REG(s,   rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
  60 #define EOP_ORR_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
  61 #define EOP_ADD_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
  62 #define EOP_TST_REG(  rn,   shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
  63
  64 #define EOP_MOV_REG2(s,   rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
  65 #define EOP_ADD_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
  66 #define EOP_SUB_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
  67
  68 #define EOP_MOV_REG_SIMPLE(rd,rm)           EOP_MOV_REG(0,rd,0,A_AM1_LSL,rm)
  69 #define EOP_MOV_REG_LSL(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSL,rm)
  70 #define EOP_MOV_REG_LSR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSR,rm)
  71 #define EOP_MOV_REG_ASR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ASR,rm)
  72 #define EOP_MOV_REG_ROR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ROR,rm)
  73
  74 #define EOP_ORR_REG_SIMPLE(rd,rm)           EOP_ORR_REG(0,rd,rd,0,A_AM1_LSL,rm)
  75 #define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
  76 #define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
  77 #define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ASR,rm)
  78 #define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ROR,rm)
  79
  80 #define EOP_ADD_REG_SIMPLE(rd,rm)           EOP_ADD_REG(0,rd,rd,0,A_AM1_LSL,rm)
  81 #define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
  82 #define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
  83
  84 #define EOP_TST_REG_SIMPLE(rn,rm)           EOP_TST_REG(  rn,   0,A_AM1_LSL,rm)
  85
  86 #define EOP_MOV_REG2_LSL(rd,   rm,rs)       EOP_MOV_REG2(0,   rd,rs,A_AM1_LSL,rm)
  87 #define EOP_MOV_REG2_ROR(rd,   rm,rs)       EOP_MOV_REG2(0,   rd,rs,A_AM1_ROR,rm)
  88 #define EOP_ADD_REG2_LSL(rd,rn,rm,rs)       EOP_ADD_REG2(0,rn,rd,rs,A_AM1_LSL,rm)
  89 #define EOP_SUB_REG2_LSL(rd,rn,rm,rs)       EOP_SUB_REG2(0,rn,rd,rs,A_AM1_LSL,rm)
  90
  91 /* addressing mode 2 */
  92 #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
  93         EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
  94
  95 /* addressing mode 3 */
  96 #define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
  97         EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
  98                         ((s)<<6) | ((h)<<5) | (immed_reg))
  99
 100 #define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf))
 101
 102 #define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm)       EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
 103
 104 /* ldr and str */
 105 #define EOP_LDR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
 106 #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
 107 #define EOP_LDR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
 108 #define EOP_STR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
 109 #define EOP_STR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
 110
 111 #define EOP_LDRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
 112 #define EOP_LDRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
 113 #define EOP_LDRH_REG(   rd,rn,rm)        EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
 114 #define EOP_STRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
 115 #define EOP_STRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
 116 #define EOP_STRH_REG(   rd,rn,rm)        EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)
 117
 118 /* ldm and stm */
 119 #define EOP_XXM(cond,p,u,s,w,l,rn,list) \
 120         EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
 121
 122 #define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
 123 #define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
 124
 125 /* branches */
 126 #define EOP_C_BX(cond,rm) \
 127         EMIT(((cond)<<28) | 0x012fff10 | (rm))
 128
 129 #define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
 130
 131 #define EOP_C_B(cond,l,signed_immed_24) \
 132         EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
 133
 134 #define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
 135 #define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
 136
 137 /* misc */
 138 #define EOP_C_MUL(cond,s,rd,rs,rm) \
 139         EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm))
 140
 141 #define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
 142
 143 #define EOP_C_MRS(cond,rd) \
 144         EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12))
 145
 146 #define EOP_C_MSR_IMM(cond,ror2,imm) \
 147         EMIT(((cond)<<28) | 0x0328f000 | ((ror2)<<8) | (imm)) // cpsr_f
 148
 149 #define EOP_C_MSR_REG(cond,rm) \
 150         EMIT(((cond)<<28) | 0x0128f000 | (rm)) // cpsr_f
 151
 152 #define EOP_MRS(rd)           EOP_C_MRS(A_COND_AL,rd)
 153 #define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
 154 #define EOP_MSR_REG(rm)       EOP_C_MSR_REG(A_COND_AL,rm)
 155
 156
 157 static void emit_mov_const(int cond, int d, unsigned int val)
 158 {
 159         int need_or = 0;
 160         if (val & 0xff000000) {
 161                 EOP_C_DOP_IMM(cond, A_OP_MOV, 0, 0, d, 8/2, (val>>24)&0xff);
 162                 need_or = 1;
 163         }
 164         if (val & 0x00ff0000) {
 165                 EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 16/2, (val>>16)&0xff);
 166                 need_or = 1;
 167         }
 168         if (val & 0x0000ff00) {
 169                 EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 24/2, (val>>8)&0xff);
 170                 need_or = 1;
 171         }
 172         if ((val &0x000000ff) || !need_or)
 173                 EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 0, val&0xff);
 174 }
 175
 176 static void check_offset_24(int val)
 177 {
 178         if (val >= (int)0xff000000 && val <= 0x00ffffff) return;
 179         printf("offset_24 overflow %08x\n", val);
 180         exit(1);
 181 }
 182
 183 static void emit_call(int cond, void *target)
 184 {
 185         int val = (unsigned int *)target - tcache_ptr - 2;
 186         check_offset_24(val);
 187
 188         EOP_C_B(cond,1,val & 0xffffff);                 // bl target
 189 }
 190
 191 static void emit_jump(int cond, void *target)
 192 {
 193         int val = (unsigned int *)target - tcache_ptr - 2;
 194         check_offset_24(val);
 195
 196         EOP_C_B(cond,0,val & 0xffffff);                 // b target
 197 }
 198
 199 static void handle_caches(void)
 200 {
 201 #ifdef ARM
 202         extern void flush_inval_caches(const void *start_addr, const void *end_addr);
 203         flush_inval_caches(tcache, tcache_ptr);
 204 #endif
 205 }
 206
 207