Pico/carthw/svp/gen_arm.c

   1 #define EMIT(x) *tcache_ptr++ = x
   2
   3 #define A_R4M  (1 << 4)
   4 #define A_R5M  (1 << 5)
   5 #define A_R6M  (1 << 6)
   6 #define A_R7M  (1 << 7)
   7 #define A_R8M  (1 << 8)
   8 #define A_R9M  (1 << 9)
   9 #define A_R10M (1 << 10)
  10 #define A_R11M (1 << 11)
  11 #define A_R14M (1 << 14)
  12
  13 #define A_COND_AL 0xe
  14
  15 /* addressing mode 1 */
  16 #define A_AM1_LSL 0
  17 #define A_AM1_LSR 1
  18 #define A_AM1_ASR 2
  19 #define A_AM1_ROR 3
  20
  21 #define A_AM1_IMM(ror2,imm8)                  (((ror2)<<8) | (imm8) | 0x02000000)
  22 #define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
  23
  24 /* data processing op */
  25 #define A_OP_ORR 0xc
  26 #define A_OP_MOV 0xd
  27
  28 #define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
  29         EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
  30
  31 #define EOP_C_DOP_IMM(cond,op,s,rn,rd,ror2,imm8)             EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
  32 #define EOP_C_DOP_REG(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
  33
  34 #define EOP_MOV_IMM(s,   rd,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,s, 0,rd,ror2,imm8)
  35 #define EOP_ORR_IMM(s,rn,rd,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,s,rn,rd,ror2,imm8)
  36
  37 #define EOP_MOV_REG(s,   rd,shift_imm,shift_op,rm) EOP_C_DOP_REG(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
  38
  39 #define EOP_MOV_REG_SIMPLE(rd,rm) EOP_MOV_REG(0,rd,0,A_AM1_LSL,rm)
  40
  41 /* ldr and str */
  42 #define EOP_C_XXR_IMM(cond,u,b,l,rn,rd,offset_12) \
  43         EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
  44
  45 #define EOP_LDR_IMM(   rd,rn,offset_12) EOP_C_XXR_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
  46 #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_XXR_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
  47 #define EOP_LDR_SIMPLE(rd,rn)           EOP_C_XXR_IMM(A_COND_AL,1,0,1,rn,rd,0)
  48 #define EOP_STR_IMM(   rd,rn,offset_12) EOP_C_XXR_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
  49 #define EOP_STR_SIMPLE(rd,rn)           EOP_C_XXR_IMM(A_COND_AL,1,0,0,rn,rd,0)
  50
  51 /* ldm and stm */
  52 #define EOP_XXM(cond,p,u,s,w,l,rn,list) \
  53         EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
  54
  55 #define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
  56 #define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
  57
  58 /* branches */
  59 #define EOP_C_BX(cond,rm) \
  60         EMIT(((cond)<<28) | 0x012fff10 | (rm))
  61
  62 #define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
  63
  64 #define EOP_C_B(cond,l,signed_immed_24) \
  65         EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
  66
  67 #define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
  68 #define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
  69
  70
  71 static void emit_mov_const(int d, unsigned int val)
  72 {
  73         int need_or = 0;
  74         if (val & 0xff000000) {
  75                 EOP_MOV_IMM(0, d,  8/2, (val>>24)&0xff);
  76                 need_or = 1;
  77         }
  78         if (val & 0x00ff0000) {
  79                 EOP_C_DOP_IMM(A_COND_AL,need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 16/2, (val>>16)&0xff);
  80                 need_or = 1;
  81         }
  82         if (val & 0x0000ff00) {
  83                 EOP_C_DOP_IMM(A_COND_AL,need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 24/2, (val>>8)&0xff);
  84                 need_or = 1;
  85         }
  86         if ((val &0x000000ff) || !need_or)
  87                 EOP_C_DOP_IMM(A_COND_AL,need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 0, val&0xff);
  88 }
  89
  90 /*
  91 static void check_offset_12(unsigned int val)
  92 {
  93         if (!(val & ~0xfff)) return;
  94         printf("offset_12 overflow %04x\n", val);
  95         exit(1);
  96 }
  97 */
  98
  99 static void check_offset_24(int val)
 100 {
 101         if (val >= (int)0xff000000 && val <= 0x00ffffff) return;
 102         printf("offset_24 overflow %08x\n", val);
 103         exit(1);
 104 }
 105
 106 static void emit_call(void *target)
 107 {
 108         int val = (unsigned int *)target - tcache_ptr - 2;
 109         check_offset_24(val);
 110
 111         EOP_BL(val & 0xffffff);                 // bl target
 112 }
 113
 114 static void emit_block_prologue(void)
 115 {
 116         // stack regs
 117         EOP_STMFD_ST(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M); // stmfd r13!, {r4-r11,lr}
 118         emit_call(regfile_load);
 119 }
 120
 121 static void emit_block_epilogue(int icount)
 122 {
 123         emit_call(regfile_store);
 124         EOP_LDMFD_ST(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M); // ldmfd r13!, {r4-r11,lr}
 125         emit_mov_const(0, icount);
 126         EOP_BX(14);                             // bx r14
 127 }
 128
 129 static void emit_pc_dump(int pc)
 130 {
 131         emit_mov_const(3, pc<<16);
 132         EOP_STR_IMM(3,7,0x400+6*4);             // str r3, [r7, #(0x400+6*8)]
 133 }
 134
 135 static void emit_interpreter_call(void *target)
 136 {
 137         emit_call(regfile_store);
 138         emit_call(target);
 139         emit_call(regfile_load);
 140 }
 141
 142 static void handle_caches()
 143 {
 144 #ifdef ARM
 145         extern void flush_inval_caches(const void *start_addr, const void *end_addr);
 146         flush_inval_caches(tcache, tcache_ptr);
 147 #else
 148 #error wth
 149 #endif
 150 }
 151
 152