Pico/carthw/svp/gen_arm.c

   1 #define EMIT(x) *tcache_ptr++ = x
   2
   3 #define A_R4M  (1 << 4)
   4 #define A_R5M  (1 << 5)
   5 #define A_R6M  (1 << 6)
   6 #define A_R7M  (1 << 7)
   7 #define A_R8M  (1 << 8)
   8 #define A_R9M  (1 << 9)
   9 #define A_R10M (1 << 10)
  10 #define A_R11M (1 << 11)
  11 #define A_R14M (1 << 14)
  12
  13 #define A_COND_AL 0xe
  14 #define A_COND_EQ 0x0
  15
  16 /* addressing mode 1 */
  17 #define A_AM1_LSL 0
  18 #define A_AM1_LSR 1
  19 #define A_AM1_ASR 2
  20 #define A_AM1_ROR 3
  21
  22 #define A_AM1_IMM(ror2,imm8)                  (((ror2)<<8) | (imm8) | 0x02000000)
  23 #define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
  24
  25 /* data processing op */
  26 #define A_OP_AND 0x0
  27 #define A_OP_SUB 0x2
  28 #define A_OP_ADD 0x4
  29 #define A_OP_TST 0x8
  30 #define A_OP_ORR 0xc
  31 #define A_OP_MOV 0xd
  32 #define A_OP_BIC 0xe
  33
  34 #define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
  35         EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
  36
  37 #define EOP_C_DOP_IMM(cond,op,s,rn,rd,ror2,imm8)             EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
  38 #define EOP_C_DOP_REG(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
  39
  40 #define EOP_MOV_IMM(rd,   ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
  41 #define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
  42 #define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
  43 #define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
  44 #define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
  45
  46 #define EOP_MOV_REG(s,   rd,shift_imm,shift_op,rm) EOP_C_DOP_REG(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
  47 #define EOP_ORR_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG(A_COND_AL,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
  48 #define EOP_ADD_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG(A_COND_AL,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
  49 #define EOP_TST_REG(  rn,   shift_imm,shift_op,rm) EOP_C_DOP_REG(A_COND_AL,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
  50
  51 #define EOP_MOV_REG_SIMPLE(rd,rm)           EOP_MOV_REG(0,rd,0,A_AM1_LSL,rm)
  52 #define EOP_MOV_REG_LSL(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSL,rm)
  53 #define EOP_MOV_REG_LSR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSR,rm)
  54 #define EOP_MOV_REG_ASR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ASR,rm)
  55 #define EOP_MOV_REG_ROR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ROR,rm)
  56
  57 #define EOP_ORR_REG_SIMPLE(rd,rm)           EOP_ORR_REG(0,rd,rd,0,A_AM1_LSL,rm)
  58 #define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
  59 #define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
  60 #define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ASR,rm)
  61 #define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ROR,rm)
  62
  63 #define EOP_ADD_REG_SIMPLE(rd,rm)           EOP_ADD_REG(0,rd,rd,0,A_AM1_LSL,rm)
  64 #define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
  65 #define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
  66
  67 #define EOP_TST_REG_SIMPLE(rn,rm)           EOP_TST_REG(  rn,   0,A_AM1_LSL,rm)
  68
  69 /* addressing mode 2 */
  70 #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
  71         EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
  72
  73 /* addressing mode 3 */
  74 #define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) \
  75         EMIT(((cond)<<28) | 0x01400090 | ((u)<<23) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (((offset_8)&0xf0)<<4) | \
  76                         ((s)<<6) | ((h)<<5) | ((offset_8)&0xf))
  77
  78 /* ldr and str */
  79 #define EOP_LDR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
  80 #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
  81 #define EOP_LDR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
  82 #define EOP_STR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
  83 #define EOP_STR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
  84
  85 #define EOP_LDRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
  86 #define EOP_LDRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
  87 #define EOP_STRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
  88 #define EOP_STRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
  89
  90 /* ldm and stm */
  91 #define EOP_XXM(cond,p,u,s,w,l,rn,list) \
  92         EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
  93
  94 #define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
  95 #define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
  96
  97 /* branches */
  98 #define EOP_C_BX(cond,rm) \
  99         EMIT(((cond)<<28) | 0x012fff10 | (rm))
 100
 101 #define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
 102
 103 #define EOP_C_B(cond,l,signed_immed_24) \
 104         EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
 105
 106 #define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
 107 #define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
 108
 109
 110 static void emit_mov_const(int d, unsigned int val)
 111 {
 112         int need_or = 0;
 113         if (val & 0xff000000) {
 114                 EOP_MOV_IMM(d,  8/2, (val>>24)&0xff);
 115                 need_or = 1;
 116         }
 117         if (val & 0x00ff0000) {
 118                 EOP_C_DOP_IMM(A_COND_AL,need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 16/2, (val>>16)&0xff);
 119                 need_or = 1;
 120         }
 121         if (val & 0x0000ff00) {
 122                 EOP_C_DOP_IMM(A_COND_AL,need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 24/2, (val>>8)&0xff);
 123                 need_or = 1;
 124         }
 125         if ((val &0x000000ff) || !need_or)
 126                 EOP_C_DOP_IMM(A_COND_AL,need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 0, val&0xff);
 127 }
 128
 129 /*
 130 static void check_offset_12(unsigned int val)
 131 {
 132         if (!(val & ~0xfff)) return;
 133         printf("offset_12 overflow %04x\n", val);
 134         exit(1);
 135 }
 136 */
 137
 138 static void check_offset_24(int val)
 139 {
 140         if (val >= (int)0xff000000 && val <= 0x00ffffff) return;
 141         printf("offset_24 overflow %08x\n", val);
 142         exit(1);
 143 }
 144
 145 static void emit_call(void *target)
 146 {
 147         int val = (unsigned int *)target - tcache_ptr - 2;
 148         check_offset_24(val);
 149
 150         EOP_BL(val & 0xffffff);                 // bl target
 151 }
 152
 153 static void emit_block_prologue(void)
 154 {
 155         // stack regs
 156         EOP_STMFD_ST(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M); // stmfd r13!, {r4-r11,lr}
 157         emit_call(regfile_load);
 158         EOP_MOV_IMM(11, 0, 0);                  // mov r11, #0
 159 }
 160
 161 static void emit_block_epilogue(int icount)
 162 {
 163         if (icount > 0xff) { printf("large icount: %i\n", icount); icount = 0xff; }
 164         emit_call(regfile_store);
 165         EOP_ADD_IMM(0,11,0,icount);             // add r0, r11, #icount
 166         EOP_LDMFD_ST(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M); // ldmfd r13!, {r4-r11,lr}
 167         EOP_BX(14);                             // bx r14
 168 }
 169
 170 static void emit_pc_dump(int pc)
 171 {
 172         emit_mov_const(3, pc<<16);
 173         EOP_STR_IMM(3,7,0x400+6*4);             // str r3, [r7, #(0x400+6*8)]
 174 }
 175
 176 static void emit_interpreter_call(void *target)
 177 {
 178         emit_call(regfile_store);
 179         emit_call(target);
 180         emit_call(regfile_load);
 181 }
 182
 183 static void handle_caches()
 184 {
 185 #ifdef ARM
 186         extern void flush_inval_caches(const void *start_addr, const void *end_addr);
 187         flush_inval_caches(tcache, tcache_ptr);
 188 #endif
 189 }
 190
 191