Pico/carthw/svp/gen_arm.c

   1 #define EMIT(x) *tcache_ptr++ = x
   2
   3 #define A_R4M  (1 << 4)
   4 #define A_R5M  (1 << 5)
   5 #define A_R6M  (1 << 6)
   6 #define A_R7M  (1 << 7)
   7 #define A_R8M  (1 << 8)
   8 #define A_R9M  (1 << 9)
   9 #define A_R10M (1 << 10)
  10 #define A_R11M (1 << 11)
  11 #define A_R14M (1 << 14)
  12
  13 #define A_COND_AL 0xe
  14
  15 /* addressing mode 1 */
  16 #define A_AM1_LSL 0
  17 #define A_AM1_LSR 1
  18 #define A_AM1_ASR 2
  19 #define A_AM1_ROR 3
  20
  21 #define A_AM1_IMM(ror2,imm8)                  (((ror2)<<8) | (imm8) | 0x02000000)
  22 #define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
  23
  24 /* data processing op */
  25 #define A_OP_ADD 0x4
  26 #define A_OP_ORR 0xc
  27 #define A_OP_MOV 0xd
  28
  29 #define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
  30         EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
  31
  32 #define EOP_C_DOP_IMM(cond,op,s,rn,rd,ror2,imm8)             EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
  33 #define EOP_C_DOP_REG(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
  34
  35 #define EOP_MOV_IMM(s,   rd,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,s, 0,rd,ror2,imm8)
  36 #define EOP_ORR_IMM(s,rn,rd,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,s,rn,rd,ror2,imm8)
  37 #define EOP_ADD_IMM(s,rn,rd,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,s,rn,rd,ror2,imm8)
  38
  39 #define EOP_MOV_REG(s,   rd,shift_imm,shift_op,rm) EOP_C_DOP_REG(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
  40 #define EOP_ORR_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG(A_COND_AL,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
  41
  42 #define EOP_MOV_REG_SIMPLE(rd,rm)        EOP_MOV_REG(0,rd,0,A_AM1_LSL,rm)
  43 #define EOP_MOV_REG_LSL(rd,rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSL,rm)
  44 #define EOP_MOV_REG_LSR(rd,rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSR,rm)
  45 #define EOP_MOV_REG_ASR(rd,rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ASR,rm)
  46 #define EOP_MOV_REG_ROR(rd,rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ROR,rm)
  47
  48 #define EOP_ORR_REG_SIMPLE(rd,rm)        EOP_ORR_REG(0,rd,rd,0,A_AM1_LSL,rm)
  49
  50 /* addressing mode 2 */
  51 #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
  52         EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
  53
  54 /* addressing mode 3 */
  55 #define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) \
  56         EMIT(((cond)<<28) | 0x01400090 | ((u)<<23) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (((offset_8)&0xf0)<<4) | \
  57                         ((s)<<6) | ((h)<<5) | ((offset_8)&0xf))
  58
  59 /* ldr and str */
  60 #define EOP_LDR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
  61 #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
  62 #define EOP_LDR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
  63 #define EOP_STR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
  64 #define EOP_STR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
  65
  66 #define EOP_LDRH_IMM(  rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
  67 #define EOP_STRH_IMM(  rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
  68
  69 /* ldm and stm */
  70 #define EOP_XXM(cond,p,u,s,w,l,rn,list) \
  71         EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
  72
  73 #define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
  74 #define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
  75
  76 /* branches */
  77 #define EOP_C_BX(cond,rm) \
  78         EMIT(((cond)<<28) | 0x012fff10 | (rm))
  79
  80 #define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
  81
  82 #define EOP_C_B(cond,l,signed_immed_24) \
  83         EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
  84
  85 #define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
  86 #define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
  87
  88
  89 static void emit_mov_const(int d, unsigned int val)
  90 {
  91         int need_or = 0;
  92         if (val & 0xff000000) {
  93                 EOP_MOV_IMM(0, d,  8/2, (val>>24)&0xff);
  94                 need_or = 1;
  95         }
  96         if (val & 0x00ff0000) {
  97                 EOP_C_DOP_IMM(A_COND_AL,need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 16/2, (val>>16)&0xff);
  98                 need_or = 1;
  99         }
 100         if (val & 0x0000ff00) {
 101                 EOP_C_DOP_IMM(A_COND_AL,need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 24/2, (val>>8)&0xff);
 102                 need_or = 1;
 103         }
 104         if ((val &0x000000ff) || !need_or)
 105                 EOP_C_DOP_IMM(A_COND_AL,need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 0, val&0xff);
 106 }
 107
 108 /*
 109 static void check_offset_12(unsigned int val)
 110 {
 111         if (!(val & ~0xfff)) return;
 112         printf("offset_12 overflow %04x\n", val);
 113         exit(1);
 114 }
 115 */
 116
 117 static void check_offset_24(int val)
 118 {
 119         if (val >= (int)0xff000000 && val <= 0x00ffffff) return;
 120         printf("offset_24 overflow %08x\n", val);
 121         exit(1);
 122 }
 123
 124 static void emit_call(void *target)
 125 {
 126         int val = (unsigned int *)target - tcache_ptr - 2;
 127         check_offset_24(val);
 128
 129         EOP_BL(val & 0xffffff);                 // bl target
 130 }
 131
 132 static void emit_block_prologue(void)
 133 {
 134         // stack regs
 135         EOP_STMFD_ST(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M); // stmfd r13!, {r4-r11,lr}
 136         emit_call(regfile_load);
 137 }
 138
 139 static void emit_block_epilogue(int icount)
 140 {
 141         emit_call(regfile_store);
 142         EOP_LDMFD_ST(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M); // ldmfd r13!, {r4-r11,lr}
 143         emit_mov_const(0, icount);
 144         EOP_BX(14);                             // bx r14
 145 }
 146
 147 static void emit_pc_dump(int pc)
 148 {
 149         emit_mov_const(3, pc<<16);
 150         EOP_STR_IMM(3,7,0x400+6*4);             // str r3, [r7, #(0x400+6*8)]
 151 }
 152
 153 static void emit_interpreter_call(void *target)
 154 {
 155         emit_call(regfile_store);
 156         emit_call(target);
 157         emit_call(regfile_load);
 158 }
 159
 160 static void handle_caches()
 161 {
 162 #ifdef ARM
 163         extern void flush_inval_caches(const void *start_addr, const void *end_addr);
 164         flush_inval_caches(tcache, tcache_ptr);
 165 #else
 166 #error wth
 167 #endif
 168 }
 169
 170