1 // basic, incomplete SSP160x (SSP1601?) interpreter
2 // with SVP memory controller emu
4 // (c) Copyright 2008, Grazvydas "notaz" Ignotas
5 // Free for non-commercial use.
7 // For commercial use, separate licencing terms must be obtained.
10 #include "../../PicoInt.h"
17 * desc: Constant register with all bits set (0xffff).
21 * desc: Generic register. When set, updates P (P = X * Y * 2)
25 * desc: Generic register. When set, updates P (P = X * Y * 2)
33 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
35 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
36 * modulo-increment and modulo-decrement. The value shows which
37 * power of 2 to use, i.e. 4 means modulo by 16.
38 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
40 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
41 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
42 * datasheet says these (5,6) bits correspond to hardware pins.
43 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
44 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
45 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
46 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
47 * a - GPI_0 Interrupt 0 enable/status?
48 * b - GPI_1 Interrupt 1 enable/status?
49 * c - L L flag. Carry?
51 * e - OV Overflow flag.
52 * f - N Negative flag.
53 * seen directly changing code sequences:
54 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
55 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
56 * ld ST, A ld ST, A ori 3
61 * desc: hw stack of 6 levels (according to datasheet)
65 * desc: Program counter.
69 * desc: multiply result register. P = X * Y * 2
70 * probably affected by MACS bit in ST.
72 * 8. "PM0" (PM from PMAR name from Tasco's docs)
74 * desc: Programmable Memory access register.
75 * On reset, or when one (both?) GP0 bits are clear,
76 * acts as status for XST, mapped at 015004 at 68k side:
77 * bit0: ssp has written something to XST (cleared when 015004 is read)
78 * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
82 * desc: Programmable Memory access register.
83 * This reg. is only used as PMAR.
87 * desc: Programmable Memory access register.
88 * This reg. is only used as PMAR.
92 * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
93 * Can be programmed as PMAR? (only seen in test mode code)
94 * Affects PM0 when written to?
98 * desc: Programmable Memory access register.
99 * This reg. is only used as PMAR. The most used PMAR by VR.
103 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
105 * desc: Programmable Memory access Control. Set using 2 16bit writes,
106 * first address, then mode word. After setting PMAC, PMAR sould
107 * be blind accessed (ld -, PMx or ld PMx, -) to program it for
108 * reading and writing respectively.
109 * Reading the register also shifts it's state (from "waiting for
110 * address" to "waiting for mode" and back). Reads always return
111 * address related to last PMx register accressed.
112 * (note: addresses do not wrap).
116 * desc: Accumulator Low. 16 least significant bits of accumulator.
117 * (normally reading acc (ld X, A) you get 16 most significant bits).
120 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
121 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
122 * which work similar to * and ** operators in C, only they use different memory banks and
123 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
124 * program memory at address read from (rX), and increments value in (rX).
126 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
127 * 3 modifiers can be applied (optional):
128 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
129 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
130 * +!: post-increment, unaffected by RPL (probably).
131 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
132 * ar probably invalid.
134 * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
135 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
136 * Samsung's old DSP page claims that).
137 * 1 of these 4 modifiers must be used (short form direct addressing?):
138 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
140 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
146 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
148 * mld (rj), (ri) [, b]
149 * operation: A = 0; P = (rj) * (ri)
150 * notes: based on IIR_4B.SC sample. flags? what is b???
152 * mpya (rj), (ri) [, b]
153 * name: multiply and add?
154 * operation: A += P; P = (rj) * (ri)
157 * name: multiply and subtract?
158 * notes: not used by VR code.
161 * mod cond, shr does arithmetic shift
163 * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
166 * 000000 - 1fffff ROM, accessable by both
167 * 200000 - 2fffff unused?
168 * 300000 - 31ffff DRAM, both
169 * 320000 - 38ffff unused?
170 * 390000 - 3907ff IRAM. can only be accessed by ssp?
171 * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
172 * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
174 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
175 * 30fe06 - also sync related.
176 * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
178 * + figure out if 'op A, P' is 32bit (nearly sure it is)
179 * * does mld, mpya load their operands into X and Y?
182 * Assumptions in this code
183 * P is not directly writeable
184 * flags correspond to full 32bit accumulator
185 * only Z and N status flags are emulated (others unused by SVP)
186 * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
189 #include "../../PicoInt.h"
191 #define u32 unsigned int
193 //#define USE_DEBUGGER
196 #define rX ssp->gr[SSP_X].h
197 #define rY ssp->gr[SSP_Y].h
198 #define rA ssp->gr[SSP_A].h
199 #define rST ssp->gr[SSP_ST].h // 4
200 #define rSTACK ssp->gr[SSP_STACK].h
201 #define rPC ssp->gr[SSP_PC].h
202 #define rP ssp->gr[SSP_P]
203 #define rPM0 ssp->gr[SSP_PM0].h // 8
204 #define rPM1 ssp->gr[SSP_PM1].h
205 #define rPM2 ssp->gr[SSP_PM2].h
206 #define rXST ssp->gr[SSP_XST].h
207 #define rPM4 ssp->gr[SSP_PM4].h // 12
209 #define rPMC ssp->gr[SSP_PMC] // will keep addr in .l, mode in .h
210 #define rAL ssp->gr[SSP_A].l
212 #define rA32 ssp->gr[SSP_A].v
215 #define IJind (((op>>6)&4)|(op&3))
217 #ifndef EMBED_INTERPRETER
218 #define GET_PC() (PC - (unsigned short *)svp->iram_rom)
219 #define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
220 #define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
223 #define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
224 #define REG_WRITE(r,d) { \
226 if (r1 >= 4) write_handlers[r1](d); \
227 else if (r1 > 0) ssp->gr[r1].h = d; \
231 #define SSP_FLAG_L (1<<0xc)
232 #define SSP_FLAG_Z (1<<0xd)
233 #define SSP_FLAG_V (1<<0xe)
234 #define SSP_FLAG_N (1<<0xf)
236 // update ZN according to 32bit ACC.
238 rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
239 if (!rA32) rST |= SSP_FLAG_Z; \
240 else rST |= (rA32>>16)&SSP_FLAG_N;
242 // it seems SVP code never checks for L and OV, so we leave them out.
243 // rST |= (t>>4)&SSP_FLAG_L;
245 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
246 if (!rA32) rST |= SSP_FLAG_Z; \
247 else rST |= (rA32>>16)&SSP_FLAG_N;
249 // standard cond processing.
250 // again, only Z and N is checked, as SVP doesn't seem to use any other conds.
253 case 0x00: cond = 1; break; /* always true */ \
254 case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
255 case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
256 default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
259 // ops with accumulator.
260 // how is low word really affected by these?
261 // nearly sure 'ld A' doesn't affect flags
265 #define OP_LDA32(x) \
268 #define OP_SUBA(x) { \
273 #define OP_SUBA32(x) { \
278 #define OP_CMPA(x) { \
279 u32 t = rA32 - ((x) << 16); \
280 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
281 if (!t) rST |= SSP_FLAG_Z; \
282 else rST |= (t>>16)&SSP_FLAG_N; \
285 #define OP_CMPA32(x) { \
286 u32 t = rA32 - (x); \
287 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
288 if (!t) rST |= SSP_FLAG_Z; \
289 else rST |= (t>>16)&SSP_FLAG_N; \
292 #define OP_ADDA(x) { \
297 #define OP_ADDA32(x) { \
306 #define OP_ANDA32(x) \
314 #define OP_ORA32(x) \
322 #define OP_EORA32(x) \
327 #define OP_CHECK32(OP) \
328 if ((op & 0x0f) == SSP_P) { /* A <- P */ \
329 read_P(); /* update P */ \
335 static ssp1601_t *ssp = NULL;
336 static unsigned short *PC;
340 static int running = 0;
341 static int last_iram = 0;
343 #ifdef EMBED_INTERPRETER
344 static int iram_dirty = 0;
347 // -----------------------------------------------------
348 // register i/o handlers
351 static u32 read_unknown(void)
353 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
357 static void write_unknown(u32 d)
359 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
363 static void write_ST(u32 d)
365 //if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
366 if ((rST ^ d) & 0x0f98) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
371 static u32 read_STACK(void)
374 if ((short)rSTACK < 0) {
376 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
378 return ssp->stack[rSTACK];
381 static void write_STACK(u32 d)
384 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
387 ssp->stack[rSTACK++] = d;
391 static u32 read_PC(void)
396 static void write_PC(u32 d)
403 static u32 read_P(void)
405 int m1 = (signed short)rX;
406 int m2 = (signed short)rY;
407 rP.v = (m1 * m2 * 2);
411 // -----------------------------------------------------
413 static int get_inc(int mode)
415 int inc = (mode >> 11) & 7;
418 inc = 1 << inc; // 0 1 2 4 8 16 32 128
419 if (mode & 0x8000) inc = -inc; // decrement mode
424 #define overwite_write(dst, d) \
426 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
427 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
428 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
429 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
432 static u32 pm_io(int reg, int write, u32 d)
434 if (ssp->emu_status & SSP_PMC_SET)
436 // this MUST be blind r or w
437 if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
438 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
439 reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
440 ssp->emu_status &= ~SSP_PMC_SET;
443 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
444 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
445 ssp->emu_status &= ~SSP_PMC_SET;
446 if ((rPMC.v & 0x7fffff) == 0x1c8000 || (rPMC.v & 0x7fffff) == 0x1c8240) {
447 elprintf(EL_SVP, "ssp IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
449 last_iram = (ssp->RAM1[0]-1)<<1;
456 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
457 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
458 reg, write ? 'w' : 'r', GET_PPC_OFFS());
459 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
462 if (reg == 4 || (rST & 0x60))
464 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
465 unsigned short *dram = (unsigned short *)svp->dram;
468 int mode = ssp->pmac_write[reg]>>16;
469 int addr = ssp->pmac_write[reg]&0xffff;
470 if ((mode & 0xb800) == 0xb800)
471 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode);
472 if ((mode & 0x43ff) == 0x0018) // DRAM
474 int inc = get_inc(mode);
475 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
476 reg, CADDR, d, inc, (mode>>10)&1);
478 overwite_write(dram[addr], d);
479 } else dram[addr] = d;
480 ssp->pmac_write[reg] += inc;
482 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
484 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
485 reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
487 overwite_write(dram[addr], d);
488 } else dram[addr] = d;
489 ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
491 else if ((mode & 0x47ff) == 0x001c) // IRAM
493 int inc = get_inc(mode);
494 if ((addr&0xfc00) != 0x8000)
495 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
496 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
497 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
498 ssp->pmac_write[reg] += inc;
499 #ifdef EMBED_INTERPRETER
505 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
506 reg, mode, CADDR, d, GET_PPC_OFFS());
511 int mode = ssp->pmac_read[reg]>>16;
512 int addr = ssp->pmac_read[reg]&0xffff;
513 if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
515 elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
516 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
517 ssp->pmac_read[reg] += 1;
518 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
520 else if ((mode & 0x47ff) == 0x0018) // DRAM
522 int inc = get_inc(mode);
523 elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr]);
525 ssp->pmac_read[reg] += inc;
529 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
530 reg, mode, CADDR, GET_PPC_OFFS());
535 // PMC value corresponds to last PMR accessed (not sure).
536 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
545 static u32 read_PM0(void)
547 u32 d = pm_io(0, 0, 0);
548 if (d != (u32)-1) return d;
549 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
551 #ifndef EMBED_INTERPRETER
552 if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
553 ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
560 static void write_PM0(u32 d)
562 u32 r = pm_io(0, 1, d);
563 if (r != (u32)-1) return;
564 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
569 static u32 read_PM1(void)
571 u32 d = pm_io(1, 0, 0);
572 if (d != (u32)-1) return d;
574 elprintf(EL_SVP|EL_ANOMALY, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
578 static void write_PM1(u32 d)
580 u32 r = pm_io(1, 1, d);
581 if (r != (u32)-1) return;
583 elprintf(EL_SVP|EL_ANOMALY, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
588 static u32 read_PM2(void)
590 u32 d = pm_io(2, 0, 0);
591 if (d != (u32)-1) return d;
593 elprintf(EL_SVP|EL_ANOMALY, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
597 static void write_PM2(u32 d)
599 u32 r = pm_io(2, 1, d);
600 if (r != (u32)-1) return;
602 elprintf(EL_SVP|EL_ANOMALY, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
607 static u32 read_XST(void)
610 u32 d = pm_io(3, 0, 0);
611 if (d != (u32)-1) return d;
613 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
617 static void write_XST(u32 d)
620 u32 r = pm_io(3, 1, d);
621 if (r != (u32)-1) return;
623 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
629 static u32 read_PM4(void)
631 u32 d = pm_io(4, 0, 0);
632 #ifndef EMBED_INTERPRETER
634 switch (GET_PPC_OFFS()) {
635 case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
636 case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
640 if (d != (u32)-1) return d;
642 elprintf(EL_SVP|EL_ANOMALY, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
646 static void write_PM4(u32 d)
648 u32 r = pm_io(4, 1, d);
649 if (r != (u32)-1) return;
651 elprintf(EL_SVP|EL_ANOMALY, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
656 static u32 read_PMC(void)
658 elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.l,
659 (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
660 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
661 //if (ssp->emu_status & SSP_PMC_SET)
662 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
663 ssp->emu_status |= SSP_PMC_SET;
664 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
665 return ((rPMC.l << 4) & 0xfff0) | ((rPMC.l >> 4) & 0xf);
667 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
672 static void write_PMC(u32 d)
674 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
675 //if (ssp->emu_status & SSP_PMC_SET)
676 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
677 ssp->emu_status |= SSP_PMC_SET;
678 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
680 elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.h, GET_PPC_OFFS());
682 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
684 elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.l, GET_PPC_OFFS());
689 static u32 read_AL(void)
691 if (*(PC-1) == 0x000f) {
692 elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
693 ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
698 static void write_AL(u32 d)
704 typedef u32 (*read_func_t)(void);
705 typedef void (*write_func_t)(u32 d);
707 static read_func_t read_handlers[16] =
709 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
710 read_unknown, // 4 ST
719 read_unknown, // 13 gr13
724 static write_func_t write_handlers[16] =
726 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
727 // write_unknown, // 4 ST
728 write_ST, // 4 ST (debug hook)
731 write_unknown, // 7 P
737 write_unknown, // 13 gr13
742 // -----------------------------------------------------
743 // pointer register handlers
746 #define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
748 static u32 ptr1_read_(int ri, int isj2, int modi3)
750 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
751 u32 mask, add = 0, t = ri | isj2 | modi3;
752 unsigned char *rp = NULL;
758 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
759 case 0x03: return ssp->RAM0[0];
762 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
763 case 0x07: return ssp->RAM1[0];
767 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
768 case 0x0b: return ssp->RAM0[1];
771 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
772 case 0x0f: return ssp->RAM1[1];
776 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
777 if (!(rST&7)) { (*rp)--; return t; }
778 add = -1; goto modulo;
779 case 0x13: return ssp->RAM0[2];
782 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
783 if (!(rST&7)) { (*rp)--; return t; }
784 add = -1; goto modulo;
785 case 0x17: return ssp->RAM1[2];
789 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
790 if (!(rST&7)) { (*rp)++; return t; }
791 add = 1; goto modulo;
792 case 0x1b: return ssp->RAM0[3];
795 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
796 if (!(rST&7)) { (*rp)++; return t; }
797 add = 1; goto modulo;
798 case 0x1f: return ssp->RAM1[3];
804 mask = (1 << (rST&7)) - 1;
805 *rp = (*rp & ~mask) | ((*rp + add) & mask);
809 static void ptr1_write(int op, u32 d)
811 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
817 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
818 case 0x03: ssp->RAM0[0] = d; return;
821 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
822 case 0x07: ssp->RAM1[0] = d; return;
830 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
831 case 0x0b: ssp->RAM0[1] = d; return;
837 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
838 case 0x0f: ssp->RAM1[1] = d; return;
842 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
843 case 0x13: ssp->RAM0[2] = d; return;
846 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
847 case 0x17: ssp->RAM1[2] = d; return;
849 case 0x1b: ssp->RAM0[3] = d; return;
850 case 0x1f: ssp->RAM1[3] = d; return;
854 static u32 ptr2_read(int op)
856 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
862 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
863 case 0x03: mv = ssp->RAM0[0]++; break;
866 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
867 case 0x07: mv = ssp->RAM1[0]++; break;
869 case 0x0b: mv = ssp->RAM0[1]++; break;
870 case 0x0f: mv = ssp->RAM1[1]++; break;
872 case 0x13: mv = ssp->RAM0[2]++; break;
873 case 0x17: mv = ssp->RAM1[2]++; break;
875 case 0x1b: mv = ssp->RAM0[3]++; break;
876 case 0x1f: mv = ssp->RAM1[3]++; break;
877 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
881 return ((unsigned short *)svp->iram_rom)[mv];
885 // -----------------------------------------------------
887 #if defined(USE_DEBUGGER) //|| defined(EMBED_INTERPRETER)
888 static void debug_dump2file(const char *fname, void *mem, int len)
890 FILE *f = fopen(fname, "wb");
891 unsigned short *p = mem;
894 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
895 fwrite(mem, 1, len, f);
897 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
898 printf("dumped to %s\n", fname);
901 printf("dump failed\n");
906 static void debug_dump(void)
908 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
909 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, rP.v);
910 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
911 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, rPMC.v);
912 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
913 rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
914 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
915 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
916 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
917 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
920 static void debug_dump_mem(void)
924 for (h = 0; h < 32; h++)
926 if (h == 16) printf("RAM1\n");
927 printf("%03x:", h*16);
928 for (i = 0; i < 16; i++)
929 printf(" %04x", ssp->RAM[h*16+i]);
934 static int bpts[10] = { 0, };
936 static void debug(unsigned int pc, unsigned int op)
938 static char buffo[64] = {0,};
939 char buff[64] = {0,};
943 for (i = 0; i < 10; i++)
944 if (pc != 0 && bpts[i] == pc) {
945 printf("breakpoint %i\n", i);
952 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
958 fgets(buff, sizeof(buff), stdin);
959 if (buff[0] == '\n') strcpy(buff, buffo);
960 else strcpy(buffo, buff);
965 case 'r': running = 1; return;
968 case 'x': debug_dump(); break;
969 case 'm': debug_dump_mem(); break;
971 char *baddr = buff + 2;
973 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
974 bpts[i] = strtol(baddr, NULL, 16) >> 1;
975 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
979 sprintf(buff, "iramrom_%04x.bin", last_iram);
980 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
981 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
983 default: printf("unknown command\n"); break;
987 #endif // USE_DEBUGGER
990 void ssp1601_reset(ssp1601_t *l_ssp)
994 ssp->gr[SSP_GR0].v = 0xffff0000;
996 rSTACK = 0; // ? using ascending stack
1001 void ssp1601_run(int cycles)
1003 #ifndef EMBED_INTERPRETER
1008 while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
1015 debug(GET_PC()-1, op);
1021 if (op == 0) break; // nop
1022 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
1023 // not sure. MAME claims that only hi word is transfered.
1024 read_P(); // update P
1029 tmpv = REG_READ(op & 0x0f);
1030 REG_WRITE((op & 0xf0) >> 4, tmpv);
1035 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1038 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
1041 case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1044 case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1047 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
1050 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
1053 case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1056 case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
1062 case 0x0f: rIJ[(op>>8)&7] = op; break;
1068 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
1074 case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1080 if (cond) { int new_PC = *PC++; write_PC(new_PC); }
1091 case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
1092 case 3: rA32 <<= 1; break; // shl
1093 case 6: rA32 = -(signed int)rA32; break; // neg
1094 case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
1095 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
1096 op&7, GET_PPC_OFFS());
1105 read_P(); // update P
1106 rA32 -= rP.v; // maybe only upper word?
1107 UPD_ACC_ZN // there checking flags after this
1108 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1109 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1112 // mpya (rj), (ri), b
1114 read_P(); // update P
1115 rA32 += rP.v; // confirmed to be 32bit
1117 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1118 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1121 // mld (rj), (ri), b
1125 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1126 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1130 case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1131 case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1132 case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1133 case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1134 case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1135 case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
1138 case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1139 case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1140 case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1141 case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1142 case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1143 case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1146 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1147 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1148 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1149 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1150 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1151 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1152 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1155 case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
1156 case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
1157 case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
1158 case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
1159 case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
1160 case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
1163 case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
1164 case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
1165 case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
1166 case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
1167 case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
1168 case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
1171 case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1172 case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1173 case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1174 case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1175 case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1176 case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1179 case 0x1c: OP_SUBA(op & 0xff); break;
1180 case 0x3c: OP_CMPA(op & 0xff); break;
1181 case 0x4c: OP_ADDA(op & 0xff); break;
1182 // MAME code only does LSB of top word, but this looks wrong to me.
1183 case 0x5c: OP_ANDA(op & 0xff); break;
1184 case 0x6c: OP_ORA (op & 0xff); break;
1185 case 0x7c: OP_EORA(op & 0xff); break;
1187 #ifdef EMBED_INTERPRETER
1188 case 0x7f: goto interp_end; /* pseudo op */
1191 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
1198 #ifdef EMBED_INTERPRETER
1201 read_P(); // update P
1203 if (ssp->gr[SSP_GR0].v != 0xffff0000)
1204 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);