1 // basic, incomplete SSP160x (SSP1601?) interpreter
5 * most names taken from MAME code
9 * desc: Constant register with all bits set (0xffff).
13 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
17 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
25 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
27 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
28 * modulo-increment and modulo-decrement. The value shows which
29 * power of 2 to use, i.e. 4 means modulo by 16.
30 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
32 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
33 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
34 * datasheet says these (5,6) bits correspond to hardware pins.
35 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
36 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
37 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
38 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
39 * a - GPI_0 Interrupt 0 enable/status?
40 * b - GPI_1 Interrupt 1 enable/status?
41 * c - L L flag. Carry?
43 * e - OV Overflow flag.
44 * f - N Negative flag.
45 * seen directly changing code sequences:
46 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
47 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
48 * ld ST, A ld ST, A ori 3
53 * desc: hw stack of 6 levels (according to datasheet)
57 * desc: Program counter.
61 * desc: multiply result register. Updated after mp* instructions,
62 * or writes to X or Y (P = X * Y * 2) ??
63 * probably affected by MACS bit in ST.
65 * 8. "PM0" (PM from PMAR name from Tasco's docs)
67 * desc: Programmable Memory access register.
68 * On reset, or when one (both?) GP0 bits are clear,
69 * acts as status for XST, mapped at 015004 at 68k side:
70 * bit0: ssp has written something to XST (cleared when 015004 is read)
71 * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
75 * desc: Programmable Memory access register.
76 * This reg. is only used as PMAR.
80 * desc: Programmable Memory access register.
81 * This reg. is only used as PMAR.
85 * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
86 * Can be programmed as PMAR? (only seen in test mode code)
87 * Affects PM0 when written to?
91 * desc: Programmable Memory access register.
92 * This reg. is only used as PMAR. The most used PMAR by VR.
96 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
98 * desc: Programmable Memory access Control. Set using 2 16bit writes,
99 * first address, then mode word. After setting PMAC, PMAR sould
100 * be accessed to program it.
104 * desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
105 * (normally reading acc (ld X, A) you get 16 most significant bits).
108 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
109 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
110 * which work similar to * and ** operators in C, only they use different memory banks and
111 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
112 * program memory at address read from (rX), and increments value in (rX).
114 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
115 * 3 modifiers can be applied (optional):
116 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
117 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
118 * +!: post-increment, unaffected by RPL (probably).
119 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
120 * ar probably invalid.
122 * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
123 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
124 * Samsung's old DSP page claims that).
125 * 1 of these 4 modifiers must be used (short form direct addressing?):
126 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
128 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
134 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
136 * mld (rj), (ri) [, b]
137 * operation: A = 0; P = (rj) * (ri)
138 * notes: based on IIR_4B.SC sample. flags? what is b???
139 * TODO: figure out if (rj) and (ri) get loaded in X and Y
141 * mpya (rj), (ri) [, b]
142 * name: multiply and add?
143 * operation: A += P; P = (rj) * (ri)
146 * name: multiply and subtract?
147 * notes: not used by VR code.
150 * mod cond, shr does arithmetic shift
152 * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
155 * 000000 - 1fffff ROM, accessable by both
156 * 200000 - 2fffff unused?
157 * 300000 - 31ffff DRAM, both
158 * 320000 - 38ffff unused?
159 * 390000 - 3907ff IRAM. can only be accessed by ssp?
160 * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
161 * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
163 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
164 * 30fe06 - also sync related.
165 * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
168 * + figure out if 'op A, P' is 32bit (nearly sure it is)
169 * * what exactly is AL?
170 * * does mld, mpya load their operands into X and Y?
174 * pressing all buttons while resetting game will kick into test mode
176 * Assumptions in this code
177 * P is not directly writeable
178 * flags correspond to full 32bit accumulator
179 * only Z and N status flags are emulated (others unused by SVP)
180 * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
181 * modifiers '+' and '+!' act the same (this is most likely wrong)
182 * 'ld d, (a)' loads from program ROM
185 #include "../../PicoInt.h"
187 #define u32 unsigned int
190 #define rX ssp->gr[SSP_X].h
191 #define rY ssp->gr[SSP_Y].h
192 #define rA ssp->gr[SSP_A].h
193 #define rST ssp->gr[SSP_ST].h // 4
194 #define rSTACK ssp->gr[SSP_STACK].h
195 #define rPC ssp->gr[SSP_PC].h
196 #define rP ssp->gr[SSP_P]
197 #define rPM0 ssp->gr[SSP_PM0].h // 8
198 #define rPM1 ssp->gr[SSP_PM1].h
199 #define rPM2 ssp->gr[SSP_PM2].h
200 #define rXST ssp->gr[SSP_XST].h
201 #define rPM4 ssp->gr[SSP_PM4].h // 12
203 #define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
204 #define rAL ssp->gr[SSP_A].l
206 #define rA32 ssp->gr[SSP_A].v
209 #define IJind (((op>>6)&4)|(op&3))
211 #define GET_PC() (PC - (unsigned short *)svp->iram_rom)
212 #define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
213 #define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
215 #define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
216 #define REG_WRITE(r,d) { \
218 if (r1 >= 4) write_handlers[r1](d); \
219 else if (r1 > 0) ssp->gr[r1].h = d; \
223 #define SSP_FLAG_L (1<<0xc)
224 #define SSP_FLAG_Z (1<<0xd)
225 #define SSP_FLAG_V (1<<0xe)
226 #define SSP_FLAG_N (1<<0xf)
228 // update ZN according to 32bit ACC.
230 rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
231 if (!rA32) rST |= SSP_FLAG_Z; \
232 else rST |= (rA32>>16)&SSP_FLAG_N;
234 // it seems SVP code never checks for L and OV, so we leave them out.
235 // rST |= (t>>4)&SSP_FLAG_L;
237 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
238 if (!rA32) rST |= SSP_FLAG_Z; \
239 else rST |= (rA32>>16)&SSP_FLAG_N;
242 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
243 if (!t) rST |= SSP_FLAG_Z; \
244 else rST |= t&SSP_FLAG_N; \
246 // standard cond processing.
247 // again, only Z and N is checked, as SVP doesn't seem to use any other conds.
250 case 0x00: cond = 1; break; /* always true */ \
251 case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
252 case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
253 default:elprintf(EL_SVP, "unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
256 // ops with accumulator.
257 // how is low word really affected by these?
258 // nearly sure 'ld A' doesn't affect flags
262 #define OP_LDA32(x) \
265 #define OP_SUBA(x) { \
266 u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
268 ssp->gr[SSP_A].h = t; \
271 #define OP_SUBA32(x) { \
272 ssp->gr[SSP_A].v -= (x); \
276 #define OP_CMPA(x) { \
277 u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
281 #define OP_CMPA32(x) { \
282 u32 t = ssp->gr[SSP_A].v - (x); \
283 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
284 if (!t) rST |= SSP_FLAG_Z; \
285 else rST |= (t>>16)&SSP_FLAG_N; \
288 #define OP_ADDA(x) { \
289 u32 t = (ssp->gr[SSP_A].v >> 16) + (x); \
291 ssp->gr[SSP_A].h = t; \
294 #define OP_ADDA32(x) { \
295 ssp->gr[SSP_A].v += (x); \
300 ssp->gr[SSP_A].v &= (x) << 16; \
303 #define OP_ANDA32(x) \
304 ssp->gr[SSP_A].v &= (x); \
308 ssp->gr[SSP_A].v |= (x) << 16; \
311 #define OP_ORA32(x) \
312 ssp->gr[SSP_A].v |= (x); \
316 ssp->gr[SSP_A].v ^= (x) << 16; \
319 #define OP_EORA32(x) \
320 ssp->gr[SSP_A].v ^= (x); \
324 #define OP_CHECK32(OP) \
325 if ((op & 0x0f) == SSP_P) { /* A <- P */ \
326 read_P(); /* update P */ \
327 OP(ssp->gr[SSP_P].v); \
332 static ssp1601_t *ssp = NULL;
333 static unsigned short *PC;
336 static int running = 0;
337 static int last_iram = 0;
339 // -----------------------------------------------------
340 // register i/o handlers
343 static u32 read_unknown(void)
345 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown read @ %04x", GET_PPC_OFFS());
349 static void write_unknown(u32 d)
351 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown write @ %04x", GET_PPC_OFFS());
355 static void write_ST(u32 d)
358 elprintf(EL_SVP, "ssp16: RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
365 static u32 read_STACK(void)
367 //elprintf(EL_SVP, "pop %i @ %04x", rSTACK, GET_PPC_OFFS());
369 if ((short)rSTACK < 0) {
371 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
373 return ssp->stack[rSTACK];
376 static void write_STACK(u32 d)
380 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
383 ssp->stack[rSTACK++] = d;
387 static u32 read_PC(void)
392 static void write_PC(u32 d)
399 static u32 read_P(void)
401 rP.v = (u32)rX * rY * 2;
405 // -----------------------------------------------------
407 static void iram_write(int addr, u32 d, int reg, int inc)
409 if ((addr&0xfc00) != 0x8000)
410 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
411 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
412 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
413 ssp->pmac_write[reg] += inc<<16;
416 int lil[32] = { 0, }, lilp = 0;
418 static void debug_dump2file(const char *fname, void *mem, int len);
420 #define overwite_write(dst, d) \
422 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
423 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
424 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
425 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
428 static u32 pm_io(int reg, int write, u32 d)
430 if (ssp->emu_status & SSP_PMC_SET)
432 // this MUST be blind r or w
433 if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
434 elprintf(EL_SVP|EL_ANOMALY, "FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
435 reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
436 ssp->emu_status &= ~SSP_PMC_SET;
439 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
440 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
441 ssp->emu_status &= ~SSP_PMC_SET;
442 if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
443 elprintf(EL_SVP, "IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
448 for (i = 0; i < 32; i++) {
449 if (lil[i] == last_iram) break;
452 sprintf(buff, "iramrom_%04x.bin", last_iram);
453 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
459 last_iram = (ssp->RAM1[0]-1)<<1;
465 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
466 elprintf(EL_SVP|EL_ANOMALY, "FIXME: PM%i (%c) with only addr set @ %04x",
467 reg, write ? 'w' : 'r', GET_PPC_OFFS());
468 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
471 // if (ssp->pmac_read[reg] != 0)
472 if (reg == 4 || (rST & 0x60))
474 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
475 unsigned short *dram = (unsigned short *)svp->dram;
478 /* TODO: 0c18 mode? */
479 int mode = ssp->pmac_write[reg]&0xffff;
480 int addr = ssp->pmac_write[reg]>>16;
482 case 0x0018: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x", reg, CADDR, d);
485 case 0x0418: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (overwr)", reg, CADDR, d);
486 overwite_write(dram[addr], d);
488 case 0x0818: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc 1)", reg, CADDR, d);
490 ssp->pmac_write[reg] += 1<<16;
492 case 0x081c: iram_write(addr, d, reg, 1); break; // checked: used by code @ 0902
493 case 0x101c: iram_write(addr, d, reg, 2); break; // checked: used by code @ 3b7c
494 case 0x4018: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc)", reg, CADDR, d);
496 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
498 case 0x4418: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (overwr, cell inc)", reg, CADDR, d);
499 overwite_write(dram[addr], d);
500 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
502 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
503 reg, mode, CADDR, d, GET_PPC_OFFS()); break;
508 int mode = ssp->pmac_read[reg]&0xffff;
509 int addr = ssp->pmac_read[reg]>>16;
510 if ((mode & 0xfff0) == 0x0800) { // ROM, inc 1, verified to be correct
511 elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
512 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
513 ssp->pmac_read[reg] += 1<<16;
514 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
519 case 0x0018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x", CADDR, dram[addr]);
520 d = dram[addr]; // checked
522 case 0x0818: elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc 1)", reg, CADDR, dram[addr]);
523 ssp->pmac_read[reg] += 1<<16;
526 case 0x3018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 32)", CADDR, dram[addr]);
527 ssp->pmac_read[reg] += 32<<16;
530 case 0xa818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 16)", CADDR, dram[addr]);
531 ssp->pmac_read[reg] -= 16<<16;
534 case 0xb818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 128?)", CADDR, dram[addr]);
535 ssp->pmac_read[reg] -= 128<<16;
538 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled read mode %04x, [%06x] @ %04x",
539 reg, mode, CADDR, GET_PPC_OFFS());
546 // PMC value corresponds to last PMR accessed (not sure).
547 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
556 static u32 read_PM0(void)
558 u32 d = pm_io(0, 0, 0);
559 if (d != (u32)-1) return d;
560 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
562 if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
563 ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
569 static void write_PM0(u32 d)
571 u32 r = pm_io(0, 1, d);
572 if (r != (u32)-1) return;
573 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
578 static u32 read_PM1(void)
580 u32 d = pm_io(1, 0, 0);
581 if (d != (u32)-1) return d;
583 elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
587 static void write_PM1(u32 d)
589 u32 r = pm_io(1, 1, d);
590 if (r != (u32)-1) return;
592 elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
597 static u32 read_PM2(void)
599 u32 d = pm_io(2, 0, 0);
600 if (d != (u32)-1) return d;
602 elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
606 static void write_PM2(u32 d)
608 u32 r = pm_io(2, 1, d);
609 if (r != (u32)-1) return;
611 elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
616 static u32 read_XST(void)
619 u32 d = pm_io(3, 0, 0);
620 if (d != (u32)-1) return d;
622 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
626 static void write_XST(u32 d)
629 u32 r = pm_io(3, 1, d);
630 if (r != (u32)-1) return;
632 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
638 static u32 read_PM4(void)
640 u32 d = pm_io(4, 0, 0);
642 switch (GET_PPC_OFFS()) {
643 case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
644 case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
647 if (d != (u32)-1) return d;
649 elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
653 static void write_PM4(u32 d)
655 u32 r = pm_io(4, 1, d);
656 if (r != (u32)-1) return;
658 elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
663 static u32 read_PMC(void)
665 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
666 if (ssp->emu_status & SSP_PMC_SET)
667 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
668 ssp->emu_status |= SSP_PMC_SET;
669 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
670 elprintf(EL_SVP, "PMC r m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
673 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
674 elprintf(EL_SVP, "PMC r a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
679 static void write_PMC(u32 d)
681 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
682 if (ssp->emu_status & SSP_PMC_SET)
683 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
684 ssp->emu_status |= SSP_PMC_SET;
685 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
687 elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
689 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
691 elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
696 static u32 read_AL(void)
698 // TODO: figure out what's up with those blind reads..
699 if (*(PC-1) == 0x000f) {
700 elprintf(EL_SVP|EL_ANOMALY, "ssp dummy PM assign %08x, ST=%04x @ %04x", rPMC.v, rST, GET_PPC_OFFS());
701 ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
703 //elprintf(EL_SVP, "ssp AL read, ST=%04x @ %04x", rST, GET_PPC_OFFS());
708 static void write_AL(u32 d)
710 //elprintf(EL_SVP, "ssp AL write %04x, ST=%04x @ %04x", d, rST, GET_PPC_OFFS());
715 typedef u32 (*read_func_t)(void);
716 typedef void (*write_func_t)(u32 d);
718 static read_func_t read_handlers[16] =
720 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
721 read_unknown, // 4 ST
730 read_unknown, // 13 gr13
735 static write_func_t write_handlers[16] =
737 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
738 // write_unknown, // 4 ST
739 write_ST, // 4 ST (debug hook)
742 write_unknown, // 7 P
748 write_unknown, // 13 gr13
753 // -----------------------------------------------------
754 // pointer register handlers
757 #define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
759 static u32 ptr1_read_(int ri, int isj2, int modi3)
761 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
762 u32 mask, add = 0, t = ri | isj2 | modi3;
763 unsigned char *rp = NULL;
769 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
770 case 0x03: return ssp->RAM0[0];
773 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
774 case 0x07: return ssp->RAM1[0];
778 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
779 case 0x0b: return ssp->RAM0[1];
782 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
783 case 0x0f: return ssp->RAM1[1];
787 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
788 if (!(rST&7)) { (*rp)--; return t; }
789 add = -1; goto modulo;
790 case 0x13: return ssp->RAM0[2];
793 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
794 if (!(rST&7)) { (*rp)--; return t; }
795 add = -1; goto modulo;
796 case 0x17: return ssp->RAM1[2];
800 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
801 if (!(rST&7)) { (*rp)++; return t; }
802 add = 1; goto modulo;
803 case 0x1b: return ssp->RAM0[3];
806 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
807 if (!(rST&7)) { (*rp)++; return t; }
808 add = 1; goto modulo;
809 case 0x1f: return ssp->RAM1[3];
815 mask = (1 << (rST&7)) - 1;
816 *rp = (*rp & ~mask) | ((*rp + add) & mask);
820 static void ptr1_write(int op, u32 d)
822 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
828 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
829 case 0x03: ssp->RAM0[0] = d; return;
832 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
833 case 0x07: ssp->RAM1[0] = d; return;
841 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
842 case 0x0b: ssp->RAM0[1] = d; return;
848 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
849 case 0x0f: ssp->RAM1[1] = d; return;
853 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
854 case 0x13: ssp->RAM0[2] = d; return;
857 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
858 case 0x17: ssp->RAM1[2] = d; return;
860 case 0x1b: ssp->RAM0[3] = d; return;
861 case 0x1f: ssp->RAM1[3] = d; return;
865 static u32 ptr2_read(int op)
867 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
873 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
874 case 0x03: mv = ssp->RAM0[0]++; break;
877 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
878 case 0x07: mv = ssp->RAM1[0]++; break;
880 case 0x0b: mv = ssp->RAM0[1]++; break;
881 case 0x0f: mv = ssp->RAM1[1]++; break;
883 case 0x13: mv = ssp->RAM0[2]++; break;
884 case 0x17: mv = ssp->RAM1[2]++; break;
886 case 0x1b: mv = ssp->RAM0[3]++; break;
887 case 0x1f: mv = ssp->RAM1[3]++; break;
888 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
892 return ((unsigned short *)svp->iram_rom)[mv];
896 // -----------------------------------------------------
898 void ssp1601_reset(ssp1601_t *l_ssp)
902 ssp->gr[SSP_GR0].v = 0xffff0000;
904 rSTACK = 0; // ? using ascending stack
909 static void debug_dump(void)
911 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
912 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
913 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
914 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
915 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
916 rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
917 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
918 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
919 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
920 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
923 static void debug_dump_mem(void)
927 for (h = 0; h < 32; h++)
929 if (h == 16) printf("RAM1\n");
930 printf("%03x:", h*16);
931 for (i = 0; i < 16; i++)
932 printf(" %04x", ssp->RAM[h*16+i]);
937 static void debug_dump2file(const char *fname, void *mem, int len)
939 FILE *f = fopen(fname, "wb");
940 unsigned short *p = mem;
943 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
944 fwrite(mem, 1, len, f);
946 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
947 printf("dumped to %s\n", fname);
950 printf("dump failed\n");
953 static int bpts[10] = { 0, };
955 static void debug(unsigned int pc, unsigned int op)
957 static char buffo[64] = {0,};
958 char buff[64] = {0,};
962 for (i = 0; i < 10; i++)
963 if (pc != 0 && bpts[i] == pc) {
964 printf("breakpoint %i\n", i);
971 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
977 fgets(buff, sizeof(buff), stdin);
978 if (buff[0] == '\n') strcpy(buff, buffo);
979 else strcpy(buffo, buff);
984 case 'r': running = 1; return;
987 case 'x': debug_dump(); break;
988 case 'm': debug_dump_mem(); break;
990 char *baddr = buff + 2;
992 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
993 bpts[i] = strtol(baddr, NULL, 16) >> 1;
994 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
998 sprintf(buff, "iramrom_%04x.bin", last_iram);
999 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
1000 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
1002 default: printf("unknown command\n"); break;
1007 void ssp1601_run(int cycles)
1012 //if (Pico.m.frame_count == 480) running = 0;
1014 while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
1020 debug(GET_PC()-1, op);
1025 if (op == 0) break; // nop
1026 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
1027 // not sure. MAME claims that only hi word is transfered.
1028 read_P(); // update P
1029 ssp->gr[SSP_A].v = ssp->gr[SSP_P].v;
1033 tmpv = REG_READ(op & 0x0f);
1034 REG_WRITE((op & 0xf0) >> 4, tmpv);
1039 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1042 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
1045 case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1048 case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1051 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
1054 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
1057 case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1060 case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
1066 case 0x0f: rIJ[(op>>8)&7] = op; break;
1072 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
1078 case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1084 if (cond) { int new_PC = *PC++; write_PC(new_PC); }
1095 case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
1096 case 3: rA32 <<= 1; break; // shl
1097 case 6: rA32 = -(signed int)rA32; break; // neg
1098 case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
1099 default: elprintf(EL_SVP, "ssp16: FIXME unhandled mod %i @ %04x", op&7, GET_PPC_OFFS());
1109 // very uncertain about this one. What about b?
1110 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
1111 read_P(); // update P
1112 ssp->gr[SSP_A].v -= ssp->gr[SSP_P].v; // maybe only upper word?
1113 // UPD_ACC_ZN // I've seen code checking flags after this
1114 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1115 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1118 // mpya (rj), (ri), b
1120 // dunno if this is correct. What about b?
1121 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
1122 read_P(); // update P
1123 ssp->gr[SSP_A].v += ssp->gr[SSP_P].v; // maybe only upper word?
1125 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1126 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1129 // mld (rj), (ri), b
1131 // dunno if this is correct. What about b?
1132 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
1133 ssp->gr[SSP_A].v = 0; // maybe only upper word?
1135 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1136 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1140 case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1141 case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1142 case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1143 case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1144 case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1145 case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
1148 case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1149 case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1150 case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1151 case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1152 case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1153 case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1156 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1157 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1158 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1159 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1160 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1161 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1162 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1165 case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
1166 case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
1167 case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
1168 case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
1169 case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
1170 case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
1173 case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
1174 case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
1175 case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
1176 case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
1177 case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
1178 case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
1181 case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1182 case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1183 case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1184 case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1185 case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1186 case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1189 case 0x1c: OP_SUBA(op & 0xff); break;
1190 case 0x3c: OP_CMPA(op & 0xff); break;
1191 case 0x4c: OP_ADDA(op & 0xff); break;
1192 // MAME code only does LSB of top word, but this looks wrong to me.
1193 case 0x5c: OP_ANDA(op & 0xff); break;
1194 case 0x6c: OP_ORA (op & 0xff); break;
1195 case 0x7c: OP_EORA(op & 0xff); break;
1198 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
1204 read_P(); // update P
1207 if (ssp->gr[SSP_GR0].v != 0xffff0000)
1208 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);