4 SSP_GR0, SSP_X, SSP_Y, SSP_A,
5 SSP_ST, SSP_STACK, SSP_PC, SSP_P,
6 SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
7 SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
22 unsigned short RAM[256*2]; // 2 internal RAM banks
24 unsigned short RAM0[256];
25 unsigned short RAM1[256];
28 ssp_reg_t gr[16]; // general registers
30 unsigned char r[8]; // BANK pointers
36 unsigned short stack[6];
37 unsigned int pmac_read[6]; // read modes/addrs for PM0-PM5
38 unsigned int pmac_write[6]; // write ...
40 #define SSP_PMC_HAVE_ADDR 0x0001 // address written to PMAC, waiting for mode
41 #define SSP_PMC_SET 0x0002 // PMAC is set
42 #define SSP_WAIT_PM0 0x2000 // bit1 in PM0
43 #define SSP_WAIT_30FE06 0x4000 // ssp tight loops on 30FE08 to become non-zero
44 #define SSP_WAIT_30FE08 0x8000 // same for 30FE06
45 #define SSP_WAIT_MASK 0xe000
46 unsigned int emu_status;
51 void ssp1601_reset(ssp1601_t *ssp);
52 void ssp1601_run(int cycles);