9 .global flush_inval_caches
10 .global ssp_regfile_load
11 .global ssp_regfile_store
16 @ translation cache buffer
19 .size tcache, TCACHE_SIZE
29 mov r2, #0x0 @ must be 0
34 @ SSP_GR0, SSP_X, SSP_Y, SSP_A,
35 @ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
36 @ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
37 @ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
42 @ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
56 ldmia r2, {r3,r4,r5,r6,r8}
59 orr r4, r3, r4, lsr #16 @ XXYY
62 mov r8, r8, lsl #13 @ sss0 *
67 orrne r8, r8, #0x4 @ sss0 * NZ..
68 orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
70 ldr r8, [r7, #0x440] @ r0-r2
71 ldr r9, [r7, #0x444] @ r4-r6
72 ldr r10,[r7, #(0x400+7*4)] @ P
77 str r10,[r7, #(0x400+7*4)] @ P
78 str r8, [r7, #0x440] @ r0-r2
79 str r9, [r7, #0x444] @ r4-r6
82 and r9, r9, #(7<<16) @ STACK
84 msr cpsr_flg, r3 @ to to ARM PSR
87 orrmi r6, r6, #0x80000000 @ N
88 orreq r6, r6, #0x20000000 @ Z
90 mov r3, r4, lsl #16 @ Y
92 mov r2, r2, lsl #16 @ X
95 stmia r8, {r2,r3,r5,r6,r9}
99 #define SSP_OFFS_GR 0x400
102 #define SSP_OFFS_EMUSTAT 0x484 // emu_status
103 #define SSP_OFFS_IRAM_DIRTY 0x494
104 #define SSP_OFFS_IRAM_CTX 0x498 // iram_context
105 #define SSP_OFFS_BLTAB 0x49c // block_table
106 #define SSP_OFFS_BLTAB_IRAM 0x4a0
107 #define SSP_OFFS_TMP0 0x4a4
108 #define SSP_WAIT_PM0 0x2000
112 stmfd sp!, {r4-r11, lr}
120 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
122 str r0, [r7, #SSP_OFFS_TMP0]
126 ldr r1, [r7, #SSP_OFFS_BLTAB]
127 ldr r1, [r1, r0, lsl #2]
130 bl ssp_translate_block
131 ldr r2, [r7, #SSP_OFFS_TMP0] @ entry PC
132 ldr r1, [r7, #SSP_OFFS_BLTAB]
133 str r0, [r1, r2, lsl #2]
137 ldr r1, [r7, #SSP_OFFS_IRAM_DIRTY]
139 ldreq r1, [r7, #SSP_OFFS_IRAM_CTX]
142 bl ssp_get_iram_context
144 str r1, [r7, #SSP_OFFS_IRAM_DIRTY]
146 str r1, [r7, #SSP_OFFS_IRAM_CTX]
147 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
150 ldr r2, [r7, #SSP_OFFS_BLTAB_IRAM]
151 add r2, r2, r1, lsl #12 @ block_tab_iram + iram_context * 0x800/2*4
152 add r2, r2, r0, lsl #2
156 str r2, [r7, #SSP_OFFS_TMP0]
157 bl ssp_translate_block
158 ldr r2, [r7, #SSP_OFFS_TMP0] @ &block_table_iram[iram_context][rPC]
165 ldmfd sp!, {r4-r11, lr}
175 @ stmfd sp!, {r4-r11, lr}
179 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
180 ldr r1, [r7, #SSP_OFFS_EMUSTAT]
182 orreq r1, r1, #SSP_WAIT_PM0
184 streq r1, [r7, #SSP_OFFS_EMUSTAT]
185 movne r0, #0x04000000
186 orrne r0, r0, #0x00040000
187 strne r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
192 @ ldmfd sp!, {r4-r11, lr}