3 @ Compiler helper functions and some SVP HLE code
5 @ (c) Copyright 2008, Grazvydas "notaz" Ignotas
6 @ Free for non-commercial use.
13 .global ssp_block_table
14 .global ssp_block_table_iram
16 .global flush_inval_caches
19 .global ssp_drc_next_patch
23 .global ssp_hle_07_030
24 .global ssp_hle_07_036
25 .global ssp_hle_07_6d6
26 .global ssp_hle_11_12c
27 .global ssp_hle_11_384
28 .global ssp_hle_11_38a
30 @ translation cache buffer + pointer table
33 .size tcache, SSP_TCACHE_SIZE
34 .size ssp_block_table, SSP_BLOCKTAB_SIZE
35 .size ssp_block_table_iram, SSP_BLOCKTAB_IRAM_SIZE
37 .space SSP_TCACHE_SIZE
39 .space SSP_BLOCKTAB_SIZE
41 .space SSP_BLOCKTAB_IRAM_SIZE
42 .space SSP_BLOCKTAB_ALIGN_SIZE
50 mov r2, #0x0 @ must be 0
55 @ SSP_GR0, SSP_X, SSP_Y, SSP_A,
56 @ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
57 @ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
58 @ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
63 @ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
71 #define SSP_OFFS_GR 0x400
76 #define SSP_OFFS_PM_WRITE 0x46c // pmac_write[]
77 #define SSP_OFFS_EMUSTAT 0x484 // emu_status
78 #define SSP_OFFS_IRAM_ROM 0x48c // ptr_iram_rom
79 #define SSP_OFFS_DRAM 0x490 // ptr_dram
80 #define SSP_OFFS_IRAM_DIRTY 0x494
81 #define SSP_OFFS_IRAM_CTX 0x498 // iram_context
82 #define SSP_OFFS_BLTAB 0x49c // block_table
83 #define SSP_OFFS_BLTAB_IRAM 0x4a0
84 #define SSP_OFFS_TMP0 0x4a4 // for entry PC
85 #define SSP_OFFS_TMP1 0x4a8
86 #define SSP_OFFS_TMP2 0x4ac
87 #define SSP_WAIT_PM0 0x2000
90 .macro ssp_drc_do_next patch_jump=0
92 str lr, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
96 str r0, [r7, #SSP_OFFS_TMP0]
100 ldr r2, [r7, #SSP_OFFS_BLTAB]
101 ldr r2, [r2, r0, lsl #2]
108 bl ssp_translate_block
110 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
111 ldr r1, [r7, #SSP_OFFS_BLTAB]
112 str r2, [r1, r0, lsl #2]
120 ldr r1, [r7, #SSP_OFFS_IRAM_DIRTY]
122 ldreq r1, [r7, #SSP_OFFS_IRAM_CTX]
123 beq 1f @ ssp_de_iram_ctx
125 bl ssp_get_iram_context
127 str r1, [r7, #SSP_OFFS_IRAM_DIRTY]
129 str r1, [r7, #SSP_OFFS_IRAM_CTX]
130 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
132 1: @ ssp_de_iram_ctx:
133 ldr r2, [r7, #SSP_OFFS_BLTAB_IRAM]
134 add r2, r2, r1, lsl #12 @ block_tab_iram + iram_context * 0x800/2*4
135 add r1, r2, r0, lsl #2
143 str r1, [r7, #SSP_OFFS_TMP1]
144 bl ssp_translate_block
146 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
147 ldr r1, [r7, #SSP_OFFS_TMP1] @ &block_table_iram[iram_context][rPC]
154 .endm @ ssp_drc_do_next
158 stmfd sp!, {r4-r11, lr}
165 ldmia r2, {r3,r4,r5,r6,r8}
168 orr r4, r3, r4, lsr #16 @ XXYY
170 and r8, r8, #0x0f0000
171 mov r8, r8, lsl #13 @ sss0 *
172 and r9, r6, #0x670000
176 orrne r8, r8, #0x4 @ sss0 * NZ..
177 orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
179 ldr r8, [r7, #0x440] @ r0-r2
180 ldr r9, [r7, #0x444] @ r4-r6
181 ldr r10,[r7, #(0x400+SSP_P*4)] @ P
183 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
195 ldr r1, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
197 moveq r3, #0xe1000000
198 orreq r3, r3, #0x00a00000 @ nop
205 streq r3, [r1, #-4] @ move the other cond up
206 moveq r3, #0xe1000000
207 orreq r3, r3, #0x00a00000
208 streq r3, [r1] @ fill it's place with nop
214 bic r3, r3, #1 @ L bit
215 orr r3, r3, r12,lsl #6
216 mov r3, r3, ror #8 @ patched branch instruction
220 str r2, [r7, #SSP_OFFS_TMP1]
223 bl flush_inval_caches
224 ldr r2, [r7, #SSP_OFFS_TMP1]
225 ldr r0, [r7, #SSP_OFFS_TMP0]
231 str r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
234 str r10,[r7, #(0x400+SSP_P*4)] @ P
235 str r8, [r7, #0x440] @ r0-r2
236 str r9, [r7, #0x444] @ r4-r6
239 and r9, r9, #(7<<16) @ STACK
241 msr cpsr_flg, r3 @ to to ARM PSR
244 orrmi r6, r6, #0x80000000 @ N
245 orreq r6, r6, #0x20000000 @ Z
247 mov r3, r4, lsl #16 @ Y
249 mov r2, r2, lsl #16 @ X
252 stmia r8, {r2,r3,r5,r6,r9}
255 ldmfd sp!, {r4-r11, lr}
264 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
265 ldr r1, [r7, #SSP_OFFS_EMUSTAT]
267 orreq r1, r1, #SSP_WAIT_PM0
269 streq r1, [r7, #SSP_OFFS_EMUSTAT]
276 .macro hle_flushflags
279 orr r6, r6, r1, lsr #28
283 sub r6, r6, #0x20000000
285 add r1, r1, #0x048 @ stack
286 add r1, r1, r6, lsr #28
296 ldr r3, [r7, #SSP_OFFS_IRAM_ROM]
297 add r2, r3, r0, lsl #1 @ (r7|00)
302 add r3, r3, r0, lsl #1 @ IRAM dest
303 ldrh r12,[r2], #2 @ length
304 bic r3, r3, #3 @ always seen aligned
305 @ orr r5, r5, #0x08000000
306 @ orr r5, r5, #0x00880000
307 @ sub r5, r5, r12, lsl #16
311 str r0, [r7, #SSP_OFFS_IRAM_DIRTY]
312 sub r11,r11,r12,lsl #1
313 sub r11,r11,r12 @ -= length*3
319 orr r0, r0, r1, lsl #16
327 ldr r0, [r7, #SSP_OFFS_IRAM_ROM]
331 strh r2, [r1] @ (r7|00)
335 orr r0, r0, #0x08000000
336 orr r0, r0, #0x001c8000
337 str r0, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
338 str r0, [r7, #(SSP_OFFS_PM_WRITE+4*4)]
341 subs r11,r11,#16 @ timeslice is likely to end
346 @ this one is car rendering related
347 .macro hle_11_12c_mla offs_in
348 ldrsh r5, [r7, #(\offs_in+0)]
349 ldrsh r0, [r7, #(\offs_in+2)]
350 ldrsh r1, [r7, #(\offs_in+4)]
352 ldrsh r12,[r7, #(\offs_in+6)]
355 add r5, r5, r12,lsl #11
358 add r1, r7, r8, lsr #23
379 mov r2, r2, asr #15 @ (r7|00) << 1
381 mov r3, r3, asr #15 @ (r7|01) << 1
383 mov r4, r4, asr #15 @ (r7|10) << 1
411 mov r2, #0 @ EFh, EEh
413 add r0, r7, #0x1c0 @ r0 (based)
419 eor r5, r5, r5, asr #31
420 add r5, r5, r5, lsr #31 @ abs(r5)
422 orrpl r2, r2, r1,lsl #16 @ EFh |= r4
427 orrpl r2, r2, r1,lsl #16 @ EFh |= r4
437 bpl ssp_hle_11_38x_loop
442 orr r8, r8, r0, lsr #1
448 sub r11,r11,#(9+30*4)
457 and r0, r8, #0xff @ assuming alignment
458 add r0, r7, r0, lsl #1
460 mov r1, r1, lsl #16 @ 106h << 16
461 mov r2, r2, lsl #16 @ 107h << 16
466 bmi ssp_hle_07_6d6_end
472 bmi ssp_hle_07_6d6_loop
474 b ssp_hle_07_6d6_loop
481 orr r1, r2, r1, lsr #16
491 orr r0, r0, r0, lsr #16
496 ldr r1, [r7, #0x1e0] @ F1h F0h
497 rsb r5, r1, r1, lsr #16
498 mov r5, r5, lsl #16 @ AL not needed
501 bmi hle_07_036_ending2
502 ldr r1, [r7, #0x1dc] @ EEh
509 strh r0, [r1, #0xea] @ F5h
510 ldr r0, [r7, #0x1e0] @ F0h
512 strh r0, [r1, #0xf0] @ F8h
513 add r2, r0, #0xc0 @ r2
514 add r2, r7, r2, lsl #1
520 @ will handle PMC later
521 ldr r0, [r7, #0x1e8] @ F5h << 16
522 ldr r1, [r7, #0x1f0] @ F8h
523 ldr r2, [r7, #0x1d4] @ EAh
525 add r0, r0, r1, lsl #16
526 sub r0, r2, r0, asr #18
528 rsbs r0, r0, #0x78 @ length
529 ble hle_07_036_ending1
534 ldr r1, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
535 ldr r2, [r7, #SSP_OFFS_DRAM]
537 add r1, r2, r1, lsr #15 @ addr (based)
538 ldrh r2, [r7, #0] @ pattern
539 ldrh r3, [r7, #6] @ mode
544 subnes r12,r12,#0x0400
547 orr r2, r2, r2, lsl #16
553 strneh r2, [r1], #0x3e @ align
566 strne r2, [r1], #0x40
569 b hle_07_036_end_copy
573 orreq r12,r12,#0x000f
575 orreq r12,r12,#0x00f0
577 orreq r12,r12,#0x0f00
579 orreq r12,r12,#0xf000
580 orrs r12,r12,r12,lsl #16
581 beq hle_07_036_no_ovrwr
588 strh r3, [r1], #0x3e @ align
611 ldr r2, [r7, #SSP_OFFS_DRAM]
613 sub r0, r1, r2 @ new addr
615 strh r0, [r3, #(0x6c+4*4)] @ SSP_OFFS_PM_WRITE+4*4 (low)
618 ldr r0, [r7, #0x1e0] @ F1h << 16
621 add r0, r0, #(0xc4<<16)
622 bic r8, r8, #0xff0000
624 add r0, r7, r0, lsr #15
630 ldr r1, [r7, #4] @ new mode
632 strh r1, [r2, #(0x6c+4*4+2)] @ SSP_OFFS_PM_WRITE+4*4 (high)
646 b ssp_drc_next @ let the dispatcher finish this