9 .global flush_inval_caches
12 .global ssp_drc_next_patch
16 .global ssp_hle_07_030
17 .global ssp_hle_07_036
18 .global ssp_hle_07_6d6
19 .global ssp_hle_11_12c
20 .global ssp_hle_11_384
21 .global ssp_hle_11_38a
23 @ translation cache buffer
26 .size tcache, TCACHE_SIZE
36 mov r2, #0x0 @ must be 0
41 @ SSP_GR0, SSP_X, SSP_Y, SSP_A,
42 @ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
43 @ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
44 @ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
49 @ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
57 #define SSP_OFFS_GR 0x400
62 #define SSP_OFFS_PM_WRITE 0x46c // pmac_write[]
63 #define SSP_OFFS_EMUSTAT 0x484 // emu_status
64 #define SSP_OFFS_IRAM_ROM 0x48c // ptr_iram_rom
65 #define SSP_OFFS_DRAM 0x490 // ptr_dram
66 #define SSP_OFFS_IRAM_DIRTY 0x494
67 #define SSP_OFFS_IRAM_CTX 0x498 // iram_context
68 #define SSP_OFFS_BLTAB 0x49c // block_table
69 #define SSP_OFFS_BLTAB_IRAM 0x4a0
70 #define SSP_OFFS_TMP0 0x4a4 // for entry PC
71 #define SSP_OFFS_TMP1 0x4a8
72 #define SSP_OFFS_TMP2 0x4ac
73 #define SSP_WAIT_PM0 0x2000
76 .macro ssp_drc_do_next patch_jump=0
78 str lr, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
82 str r0, [r7, #SSP_OFFS_TMP0]
86 ldr r2, [r7, #SSP_OFFS_BLTAB]
87 ldr r2, [r2, r0, lsl #2]
94 bl ssp_translate_block
96 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
97 ldr r1, [r7, #SSP_OFFS_BLTAB]
98 str r2, [r1, r0, lsl #2]
106 ldr r1, [r7, #SSP_OFFS_IRAM_DIRTY]
108 ldreq r1, [r7, #SSP_OFFS_IRAM_CTX]
109 beq 1f @ ssp_de_iram_ctx
111 bl ssp_get_iram_context
113 str r1, [r7, #SSP_OFFS_IRAM_DIRTY]
115 str r1, [r7, #SSP_OFFS_IRAM_CTX]
116 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
118 1: @ ssp_de_iram_ctx:
119 ldr r2, [r7, #SSP_OFFS_BLTAB_IRAM]
120 add r2, r2, r1, lsl #12 @ block_tab_iram + iram_context * 0x800/2*4
121 add r1, r2, r0, lsl #2
129 str r1, [r7, #SSP_OFFS_TMP1]
130 bl ssp_translate_block
132 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
133 ldr r1, [r7, #SSP_OFFS_TMP1] @ &block_table_iram[iram_context][rPC]
140 .endm @ ssp_drc_do_next
144 stmfd sp!, {r4-r11, lr}
151 ldmia r2, {r3,r4,r5,r6,r8}
154 orr r4, r3, r4, lsr #16 @ XXYY
156 and r8, r8, #0x0f0000
157 mov r8, r8, lsl #13 @ sss0 *
158 and r9, r6, #0x670000
162 orrne r8, r8, #0x4 @ sss0 * NZ..
163 orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
165 ldr r8, [r7, #0x440] @ r0-r2
166 ldr r9, [r7, #0x444] @ r4-r6
167 ldr r10,[r7, #(0x400+SSP_P*4)] @ P
169 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
181 ldr r1, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
183 moveq r3, #0xe1000000
184 orreq r3, r3, #0x00a00000 @ nop
191 streq r3, [r1, #-4] @ move the other cond up
192 moveq r3, #0xe1000000
193 orreq r3, r3, #0x00a00000
194 streq r3, [r1] @ fill it's place with nop
200 bic r3, r3, #1 @ L bit
201 orr r3, r3, r12,lsl #6
202 mov r3, r3, ror #8 @ patched branch instruction
206 str r2, [r7, #SSP_OFFS_TMP1]
209 bl flush_inval_caches
210 ldr r2, [r7, #SSP_OFFS_TMP1]
211 ldr r0, [r7, #SSP_OFFS_TMP0]
217 str r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
220 str r10,[r7, #(0x400+SSP_P*4)] @ P
221 str r8, [r7, #0x440] @ r0-r2
222 str r9, [r7, #0x444] @ r4-r6
225 and r9, r9, #(7<<16) @ STACK
227 msr cpsr_flg, r3 @ to to ARM PSR
230 orrmi r6, r6, #0x80000000 @ N
231 orreq r6, r6, #0x20000000 @ Z
233 mov r3, r4, lsl #16 @ Y
235 mov r2, r2, lsl #16 @ X
238 stmia r8, {r2,r3,r5,r6,r9}
241 ldmfd sp!, {r4-r11, lr}
250 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
251 ldr r1, [r7, #SSP_OFFS_EMUSTAT]
253 orreq r1, r1, #SSP_WAIT_PM0
255 streq r1, [r7, #SSP_OFFS_EMUSTAT]
262 .macro hle_flushflags
265 orr r6, r6, r1, lsr #28
269 sub r6, r6, #0x20000000
271 add r1, r1, #0x048 @ stack
272 add r1, r1, r6, lsr #28
282 ldr r3, [r7, #SSP_OFFS_IRAM_ROM]
283 add r2, r3, r0, lsl #1 @ (r7|00)
288 add r3, r3, r0, lsl #1 @ IRAM dest
289 ldrh r12,[r2], #2 @ length
290 bic r3, r3, #3 @ always seen aligned
291 @ orr r5, r5, #0x08000000
292 @ orr r5, r5, #0x00880000
293 @ sub r5, r5, r12, lsl #16
297 str r0, [r7, #SSP_OFFS_IRAM_DIRTY]
298 sub r11,r11,r12,lsl #1
299 sub r11,r11,r12 @ -= length*3
305 orr r0, r0, r1, lsl #16
313 ldr r0, [r7, #SSP_OFFS_IRAM_ROM]
317 strh r2, [r1] @ (r7|00)
321 orr r0, r0, #0x08000000
322 orr r0, r0, #0x001c8000
323 str r0, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
324 str r0, [r7, #(SSP_OFFS_PM_WRITE+4*4)]
327 subs r11,r11,#16 @ timeslice is likely to end
332 @ this one is car rendering related
333 .macro hle_11_12c_mla offs_in
334 ldrsh r5, [r7, #(\offs_in+0)]
335 ldrsh r0, [r7, #(\offs_in+2)]
336 ldrsh r1, [r7, #(\offs_in+4)]
338 ldrsh r12,[r7, #(\offs_in+6)]
341 add r5, r5, r12,lsl #11
344 add r1, r7, r8, lsr #23
365 mov r2, r2, asr #15 @ (r7|00) << 1
367 mov r3, r3, asr #15 @ (r7|01) << 1
369 mov r4, r4, asr #15 @ (r7|10) << 1
397 mov r2, #0 @ EFh, EEh
399 add r0, r7, #0x1c0 @ r0 (based)
405 eor r5, r5, r5, asr #31
406 add r5, r5, r5, lsr #31 @ abs(r5)
408 orrpl r2, r2, r1,lsl #16 @ EFh |= r4
413 orrpl r2, r2, r1,lsl #16 @ EFh |= r4
423 bpl ssp_hle_11_38x_loop
428 orr r8, r8, r0, lsr #1
434 sub r11,r11,#(9+30*4)
443 and r0, r8, #0xff @ assuming alignment
444 add r0, r7, r0, lsl #1
446 mov r1, r1, lsl #16 @ 106h << 16
447 mov r2, r2, lsl #16 @ 107h << 16
452 bmi ssp_hle_07_6d6_end
458 bmi ssp_hle_07_6d6_loop
460 b ssp_hle_07_6d6_loop
467 orr r1, r2, r1, lsr #16
477 orr r0, r0, r0, lsr #16
482 ldr r1, [r7, #0x1e0] @ F1h F0h
483 rsb r5, r1, r1, lsr #16
484 mov r5, r5, lsl #16 @ AL not needed
487 bmi hle_07_036_ending2
488 ldr r1, [r7, #0x1dc] @ EEh
495 strh r0, [r1, #0xea] @ F5h
496 ldr r0, [r7, #0x1e0] @ F0h
498 strh r0, [r1, #0xf0] @ F8h
499 add r2, r0, #0xc0 @ r2
500 add r2, r7, r2, lsl #1
506 @ will handle PMC later
507 ldr r0, [r7, #0x1e8] @ F5h << 16
508 ldr r1, [r7, #0x1f0] @ F8h
509 ldr r2, [r7, #0x1d4] @ EAh
511 add r0, r0, r1, lsl #16
512 sub r0, r2, r0, asr #18
514 rsbs r0, r0, #0x78 @ length
515 ble hle_07_036_ending1
520 ldr r1, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
521 ldr r2, [r7, #SSP_OFFS_DRAM]
523 add r1, r2, r1, lsr #15 @ addr (based)
524 ldrh r2, [r7, #0] @ pattern
525 ldrh r3, [r7, #6] @ mode
530 subnes r12,r12,#0x0400
533 orr r2, r2, r2, lsl #16
539 strneh r2, [r1], #0x3e @ align
552 strne r2, [r1], #0x40
555 b hle_07_036_end_copy
559 orreq r12,r12,#0x000f
561 orreq r12,r12,#0x00f0
563 orreq r12,r12,#0x0f00
565 orreq r12,r12,#0xf000
566 orrs r12,r12,r12,lsl #16
567 beq hle_07_036_no_ovrwr
574 strh r3, [r1], #0x3e @ align
597 ldr r2, [r7, #SSP_OFFS_DRAM]
599 sub r0, r1, r2 @ new addr
601 strh r0, [r3, #(0x6c+4*4)] @ SSP_OFFS_PM_WRITE+4*4 (low)
604 ldr r0, [r7, #0x1e0] @ F1h << 16
607 add r0, r0, #(0xc4<<16)
608 bic r8, r8, #0xff0000
610 add r0, r7, r0, lsr #15
616 ldr r1, [r7, #4] @ new mode
618 strh r1, [r2, #(0x6c+4*4+2)] @ SSP_OFFS_PM_WRITE+4*4 (high)
632 b ssp_drc_next @ let the dispatcher finish this