1 // This is part of Pico Library
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3 // (c) Copyright 2004 Dave, All rights reserved.
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4 // (c) Copyright 2007 notaz, All rights reserved.
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5 // Free for non-commercial use.
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7 // For commercial use, separate licencing terms must be obtained.
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9 // A68K no longer supported here
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11 //#define __debug_io
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13 #include "../PicoInt.h"
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15 #include "../sound/sound.h"
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16 #include "../sound/ym2612.h"
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17 #include "../sound/sn76496.h"
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21 typedef unsigned char u8;
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22 typedef unsigned short u16;
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23 typedef unsigned int u32;
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25 //#define __debug_io
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26 //#define __debug_io2
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27 //#define rdprintf dprintf
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28 #define rdprintf(...)
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30 // -----------------------------------------------------------------
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33 static u32 m68k_reg_read16(u32 a)
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37 // dprintf("m68k_regs r%2i: [%02x] @%06x", realsize&~1, a+(realsize&1), SekPc);
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41 d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens
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44 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);
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45 dprintf("m68k_regs r3: %02x @%06x", (u8)d, SekPc);
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48 d = Pico_mcd->s68k_regs[4]<<8;
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51 d = Pico_mcd->m.hint_vector;
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54 d = Read_CDC_Host(0);
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57 dprintf("m68k reserved read");
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60 dprintf("m68k stopwatch timer read");
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65 // comm flag/cmd/status (0xE-0x2F)
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66 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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70 dprintf("m68k_regs invalid read @ %02x", a);
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74 // dprintf("ret = %04x", d);
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78 static void m68k_reg_write8(u32 a, u32 d)
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81 // dprintf("m68k_regs w%2i: [%02x] %02x @%06x", realsize, a, d, SekPc);
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86 if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { dprintf("m68k: s68k irq 2"); SekInterruptS68k(2); }
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90 if (!(d&1)) Pico_mcd->m.state_flags |= 1; // reset pending, needed to be sure we fetch the right vectors on reset
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91 if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));
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92 if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);
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93 if ((Pico_mcd->m.state_flags&1) && (d&3)==1) {
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94 SekResetS68k(); // S68k comes out of RESET or BRQ state
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95 Pico_mcd->m.state_flags&=~1;
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96 dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);
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98 Pico_mcd->m.busreq = d;
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101 Pico_mcd->s68k_regs[2] = d; // really use s68k side register
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104 dprintf("m68k_regs w3: %02x @%06x", (u8)d, SekPc);
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106 if ((Pico_mcd->s68k_regs[3]>>6) != ((d>>6)&3))
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107 dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));
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108 //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);
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109 //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :
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110 // ((d&2) ? "word ram to s68k" : "word ram to m68k"));
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111 d |= Pico_mcd->s68k_regs[3]&0x1d;
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112 if (!(d & 4) && (d & 2)) d &= ~1; // return word RAM to s68k in 2M mode
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113 Pico_mcd->s68k_regs[3] = d; // really use s68k side register
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116 *((char *)&Pico_mcd->m.hint_vector+1) = d;
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117 Pico_mcd->bios[0x72 + 1] = d; // simple hint vector changer
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120 *(char *)&Pico_mcd->m.hint_vector = d;
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121 Pico_mcd->bios[0x72] = d;
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124 //dprintf("m68k: comm flag: %02x", d);
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126 //dprintf("s68k @ %06x", SekPcS68k);
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128 Pico_mcd->s68k_regs[0xe] = d;
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132 if ((a&0xf0) == 0x10) {
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133 Pico_mcd->s68k_regs[a] = d;
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137 dprintf("m68k: invalid write? [%02x] %02x", a, d);
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142 static u32 s68k_reg_read16(u32 a)
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146 // dprintf("s68k_regs r%2i: [%02x] @ %06x", realsize&~1, a+(realsize&1), SekPcS68k);
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150 d = ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state
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153 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0x1f);
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154 dprintf("s68k_regs r3: %02x @%06x", (u8)d, SekPc);
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157 d = CDC_Read_Reg();
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160 d = Read_CDC_Host(1); // Gens returns 0 here on byte reads
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163 dprintf("s68k stopwatch timer read");
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166 dprintf("s68k int3 timer read");
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168 case 0x34: // fader
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169 d = 0; // no busy bit
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173 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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177 // dprintf("ret = %04x", d);
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182 static void s68k_reg_write8(u32 a, u32 d)
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184 //dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);
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186 // TODO: review against Gens
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189 return; // only m68k can change WP
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191 dprintf("s68k_regs w3: %02x @%06x", (u8)d, SekPc);
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194 d |= Pico_mcd->s68k_regs[3]&0xc2;
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195 if ((d ^ Pico_mcd->s68k_regs[3]) & 5) d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit
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197 d |= Pico_mcd->s68k_regs[3]&0xc3;
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198 if (d&1) d &= ~2; // return word RAM to m68k in 2M mode
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202 dprintf("s68k CDC dest: %x", d&7);
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203 Pico_mcd->s68k_regs[4] = (Pico_mcd->s68k_regs[4]&0xC0) | (d&7); // CDC mode
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206 //dprintf("s68k CDC reg addr: %x", d&0xf);
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212 dprintf("s68k set CDC dma addr");
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215 dprintf("s68k set stopwatch timer");
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218 dprintf("s68k set int3 timer");
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220 case 0x33: // IRQ mask
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221 dprintf("s68k irq mask: %02x", d);
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222 if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {
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223 CDD_Export_Status();
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226 case 0x34: // fader
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227 Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;
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230 return; // d/m bit is unsetable
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232 u32 d_old = Pico_mcd->s68k_regs[0x37];
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233 Pico_mcd->s68k_regs[0x37] = d&7;
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234 if ((d&4) && !(d_old&4)) {
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235 CDD_Export_Status();
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240 Pico_mcd->s68k_regs[a] = (u8) d;
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241 CDD_Import_Command();
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245 if ((a&0x1f0) == 0x10 || a == 0x0e || (a >= 0x38 && a < 0x42))
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247 dprintf("m68k: invalid write @ %02x?", a);
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251 Pico_mcd->s68k_regs[a] = (u8) d;
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258 static int PadRead(int i)
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260 int pad=0,value=0,TH;
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261 pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU
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262 TH=Pico.ioports[i+1]&0x40;
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264 if(PicoOpt & 0x20) { // 6 button gamepad enabled
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265 int phase = Pico.m.padTHPhase[i];
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267 if(phase == 2 && !TH) {
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268 value=(pad&0xc0)>>2; // ?0SA 0000
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270 } else if(phase == 3 && TH) {
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271 value=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ
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273 } else if(phase == 3 && !TH) {
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274 value=((pad&0xc0)>>2)|0x0f; // ?0SA 1111
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279 if(TH) value=(pad&0x3f); // ?1CB RLDU
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280 else value=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU
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284 // orr the bits, which are set as output
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285 value |= Pico.ioports[i+1]&Pico.ioports[i+4];
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287 return value; // will mirror later
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290 static u8 z80Read8(u32 a)
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292 if(Pico.m.z80Run&1) return 0;
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297 // Z80 disabled, do some faking
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298 static u8 zerosent = 0;
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299 if(a == Pico.m.z80_lastaddr) { // probably polling something
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300 u8 d = Pico.m.z80_fakeval;
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301 if((d & 0xf) == 0xf && !zerosent) {
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302 d = 0; zerosent = 1;
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304 Pico.m.z80_fakeval++;
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309 Pico.m.z80_fakeval = 0;
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313 Pico.m.z80_lastaddr = (u16) a;
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314 return Pico.zram[a];
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318 // for nonstandard reads
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319 static u32 UnusualRead16(u32 a, int realsize)
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323 dprintf("unusual r%i: %06x @%06x", realsize&~1, (a&0xfffffe)+(realsize&1), SekPc);
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326 dprintf("ret = %04x", d);
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330 static u32 OtherRead16(u32 a, int realsize)
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334 if ((a&0xff0000)==0xa00000) {
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335 if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)
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336 if ((a&0x6000)==0x4000) { if(PicoOpt&1) d=YM2612Read(); else d=Pico.m.rotate++&3; goto end; } // 0x4000-0x5fff, Fudge if disabled
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337 d=0xffff; goto end;
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339 if ((a&0xffffe0)==0xa10000) { // I/O ports
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342 case 0: d=Pico.m.hardware; break; // Hardware value (Version register)
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343 case 1: d=PadRead(0); d|=Pico.ioports[1]&0x80; break;
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344 case 2: d=PadRead(1); d|=Pico.ioports[2]&0x80; break;
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345 default: d=Pico.ioports[a]; break; // IO ports can be used as RAM
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350 // |=0x80 for Shadow of the Beast & Super Offroad; rotate fakes next fetched instruction for Time Killers
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351 if (a==0xa11100) { d=((Pico.m.z80Run&1)<<8)|0x8000|Pico.m.rotate++; goto end; }
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353 if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; }
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355 if ((a&0xffffc0)==0xa12000) {
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356 d=m68k_reg_read16(a);
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360 d = UnusualRead16(a, realsize);
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366 //extern UINT32 mz80GetRegisterValue(void *, UINT32);
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368 static void OtherWrite8(u32 a,u32 d,int realsize)
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370 if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
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371 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram
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372 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound
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373 if ((a&0xffffe0)==0xa10000) { // I/O ports
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375 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
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378 Pico.m.padDelay[0] = 0;
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379 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
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382 Pico.m.padDelay[1] = 0;
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383 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
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386 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
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390 extern int z80startCycle, z80stopCycle;
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391 //int lineCycles=(488-SekCyclesLeft)&0x1ff;
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394 // hack: detect a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)
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395 if((PicoOpt&4) && Pico.m.z80Run==1) z80_run(20);
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396 z80stopCycle = SekCyclesDone();
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397 //z80ExtraCycles += (lineCycles>>1)-(lineCycles>>5); // only meaningful in PicoFrameHints()
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399 z80startCycle = SekCyclesDone();
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400 //if(Pico.m.scanline != -1)
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401 //z80ExtraCycles -= (lineCycles>>1)-(lineCycles>>5)+16;
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403 //dprintf("set_zrun: %i [%i|%i] zPC=%04x @%06x", d, Pico.m.scanline, SekCyclesDone(), mz80GetRegisterValue(NULL, 0), SekPc);
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404 Pico.m.z80Run=(u8)d; return;
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406 if (a==0xa11200) { if(!(d&1)) z80_reset(); return; }
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408 if ((a&0xff7f00)==0xa06000) // Z80 BANK register
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410 Pico.m.z80_bank68k>>=1;
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411 Pico.m.z80_bank68k|=(d&1)<<8;
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412 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
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416 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)(d|(d<<8))); return; } // Byte access gets mirrored
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418 if ((a&0xffffc0)==0xa12000) { m68k_reg_write8(a, d); return; }
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420 dprintf("strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);
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423 static void OtherWrite16(u32 a,u32 d)
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425 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; }
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426 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)
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428 if ((a&0xffffe0)==0xa10000) { // I/O ports
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430 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
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433 Pico.m.padDelay[0] = 0;
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434 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
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437 Pico.m.padDelay[1] = 0;
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438 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
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441 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
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444 if (a==0xa11100) { OtherWrite8(a, d>>8, 16); return; }
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445 if (a==0xa11200) { if(!(d&0x100)) z80_reset(); return; }
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447 OtherWrite8(a, d>>8, 16);
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448 OtherWrite8(a+1,d&0xff, 16);
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451 // -----------------------------------------------------------------
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452 // Read Rom and read Ram
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454 u8 PicoReadM68k8(u32 a)
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458 if ((a&0xe00000)==0xe00000) { d = *(u8 *)(Pico.ram+((a^1)&0xffff)); goto end; } // Ram
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462 if (a < 0x20000) { d = *(u8 *)(Pico_mcd->bios+(a^1)); goto end; } // bios
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465 if ((a&0xfe0000)==0x020000) {
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466 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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467 d = *(prg_bank+((a^1)&0x1ffff));
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472 if (a == 0x200000 && SekPc == 0xff0b66 && Pico.m.frame_count > 1000)
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476 unsigned short *ram = (unsigned short *) Pico.ram;
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477 // unswap and dump RAM
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478 for (i = 0; i < 0x10000/2; i++)
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479 ram[i] = (ram[i]>>8) | (ram[i]<<8);
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480 ff = fopen("ram.bin", "wb");
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481 fwrite(ram, 1, 0x10000, ff);
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488 if ((a&0xfc0000)==0x200000) {
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489 dprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);
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490 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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491 if (a >= 0x220000) {
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494 a=((a&0x1fffe)<<1)|(a&1);
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495 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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496 d = Pico_mcd->word_ram[a^1];
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499 // allow access in any mode, like Gens does
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500 d = Pico_mcd->word_ram[(a^1)&0x3ffff];
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502 dprintf("ret = %02x", (u8)d);
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506 if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram
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508 if ((a&0xffffc0)==0xa12000)
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509 rdprintf("m68k_regs r8: [%02x] @%06x", a&0x3f, SekPc);
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511 d=OtherRead16(a&~1, 8|(a&1)); if ((a&1)==0) d>>=8;
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513 if ((a&0xffffc0)==0xa12000)
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514 rdprintf("ret = %02x", (u8)d);
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519 dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);
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525 u16 PicoReadM68k16(u32 a)
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529 if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram
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533 if (a < 0x20000) { d = *(u16 *)(Pico_mcd->bios+a); goto end; } // bios
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536 if ((a&0xfe0000)==0x020000) {
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537 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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538 d = *(u16 *)(prg_bank+(a&0x1fffe));
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543 if ((a&0xfc0000)==0x200000) {
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544 dprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);
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545 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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546 if (a >= 0x220000) {
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549 a=((a&0x1fffe)<<1);
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550 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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551 d = *(u16 *)(Pico_mcd->word_ram+a);
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554 // allow access in any mode, like Gens does
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555 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
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557 dprintf("ret = %04x", d);
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561 if ((a&0xffffc0)==0xa12000)
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562 rdprintf("m68k_regs r16: [%02x] @%06x", a&0x3f, SekPc);
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564 d = (u16)OtherRead16(a, 16);
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566 if ((a&0xffffc0)==0xa12000)
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567 rdprintf("ret = %04x", d);
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572 dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
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578 u32 PicoReadM68k32(u32 a)
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582 if ((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); d = (pm[0]<<16)|pm[1]; goto end; } // Ram
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586 if (a < 0x20000) { u16 *pm=(u16 *)(Pico_mcd->bios+a); d = (pm[0]<<16)|pm[1]; goto end; } // bios
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589 if ((a&0xfe0000)==0x020000) {
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590 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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591 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
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592 d = (pm[0]<<16)|pm[1];
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597 if ((a&0xfc0000)==0x200000) {
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598 dprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);
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599 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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600 if (a >= 0x220000) {
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603 a=((a&0x1fffe)<<1);
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604 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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605 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;
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606 d |= *(u16 *)(Pico_mcd->word_ram+a+4);
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609 // allow access in any mode, like Gens does
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610 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
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612 dprintf("ret = %08x", d);
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616 if ((a&0xffffc0)==0xa12000)
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617 rdprintf("m68k_regs r32: [%02x] @%06x", a&0x3f, SekPc);
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619 d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);
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621 if ((a&0xffffc0)==0xa12000)
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622 rdprintf("ret = %08x", d);
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626 dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);
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632 // -----------------------------------------------------------------
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635 void PicoWriteM68k8(u32 a,u8 d)
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638 dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
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640 //if ((a&0xe0ffff)==0xe0a9ba+0x69c)
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641 // dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
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644 if ((a&0xe00000)==0xe00000) { // Ram
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645 *(u8 *)(Pico.ram+((a^1)&0xffff)) = d;
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652 if ((a&0xfe0000)==0x020000) {
\r
653 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
654 *(u8 *)(prg_bank+((a^1)&0x1ffff))=d;
\r
659 if ((a&0xfc0000)==0x200000) {
\r
660 dprintf("m68k_wram w8: [%06x] %02x @%06x", a, d, SekPc);
\r
661 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
662 if (a >= 0x220000) {
\r
665 a=((a&0x1fffe)<<1)|(a&1);
\r
666 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
667 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;
\r
670 // allow access in any mode, like Gens does
\r
671 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;
\r
676 if ((a&0xffffc0)==0xa12000)
\r
677 rdprintf("m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);
\r
679 OtherWrite8(a,d,8);
\r
683 void PicoWriteM68k16(u32 a,u16 d)
\r
686 dprintf("w16: %06x, %04x", a&0xffffff, d);
\r
688 // dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
\r
690 if ((a&0xe00000)==0xe00000) { // Ram
\r
691 *(u16 *)(Pico.ram+(a&0xfffe))=d;
\r
698 if ((a&0xfe0000)==0x020000) {
\r
699 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
700 *(u16 *)(prg_bank+(a&0x1fffe))=d;
\r
705 if ((a&0xfc0000)==0x200000) {
\r
706 dprintf("m68k_wram w16: [%06x] %04x @%06x", a, d, SekPc);
\r
707 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
708 if (a >= 0x220000) {
\r
711 a=((a&0x1fffe)<<1);
\r
712 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
713 *(u16 *)(Pico_mcd->word_ram+a)=d;
\r
716 // allow access in any mode, like Gens does
\r
717 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;
\r
722 if ((a&0xffffc0)==0xa12000)
\r
723 rdprintf("m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);
\r
729 void PicoWriteM68k32(u32 a,u32 d)
\r
732 dprintf("w32: %06x, %08x", a&0xffffff, d);
\r
735 if ((a&0xe00000)==0xe00000)
\r
738 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));
\r
739 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
746 if ((a&0xfe0000)==0x020000) {
\r
747 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
748 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
\r
749 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
754 if ((a&0xfc0000)==0x200000) {
\r
755 if (d != 0) // don't log clears
\r
756 dprintf("m68k_wram w32: [%06x] %08x @%06x", a, d, SekPc);
\r
757 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
758 if (a >= 0x220000) {
\r
761 a=((a&0x1fffe)<<1);
\r
762 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
763 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;
\r
764 *(u16 *)(Pico_mcd->word_ram+a+4) = d;
\r
767 // allow access in any mode, like Gens does
\r
768 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
769 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
774 if ((a&0xffffc0)==0xa12000)
\r
775 rdprintf("m68k_regs w32: [%02x] %08x @%06x", a&0x3f, d, SekPc);
\r
777 OtherWrite16(a, (u16)(d>>16));
\r
778 OtherWrite16(a+2,(u16)d);
\r
782 // -----------------------------------------------------------------
\r
785 u8 PicoReadS68k8(u32 a)
\r
793 d = *(Pico_mcd->prg_ram+(a^1));
\r
798 if ((a&0xfffe00) == 0xff8000) {
\r
800 rdprintf("s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);
\r
801 if (a >= 0x50 && a < 0x68)
\r
802 d = gfx_cd_read(a&~1);
\r
803 else d = s68k_reg_read16(a&~1);
\r
804 if ((a&1)==0) d>>=8;
\r
805 rdprintf("ret = %02x", (u8)d);
\r
809 // word RAM (2M area)
\r
810 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
811 dprintf("s68k_wram2M r8: [%06x] @%06x", a, SekPc);
\r
812 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
814 dprintf("(decode)");
\r
816 // allow access in any mode, like Gens does
\r
817 d = Pico_mcd->word_ram[(a^1)&0x3ffff];
\r
819 dprintf("ret = %02x", (u8)d);
\r
823 // word RAM (1M area)
\r
824 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
825 dprintf("s68k_wram1M r8: [%06x] @%06x", a, SekPc);
\r
826 a=((a&0x1fffe)<<1)|(a&1);
\r
827 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
828 d = Pico_mcd->word_ram[a^1];
\r
829 dprintf("ret = %02x", (u8)d);
\r
834 if ((a&0xff0000)==0xfe0000) {
\r
835 d = Pico_mcd->bram[(a>>1)&0x1fff];
\r
839 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
844 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
850 u16 PicoReadS68k16(u32 a)
\r
858 d = *(u16 *)(Pico_mcd->prg_ram+a);
\r
863 if ((a&0xfffe00) == 0xff8000) {
\r
865 rdprintf("s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);
\r
866 if (a >= 0x50 && a < 0x68)
\r
867 d = gfx_cd_read(a);
\r
868 else d = s68k_reg_read16(a);
\r
869 rdprintf("ret = %04x", d);
\r
873 // word RAM (2M area)
\r
874 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
875 dprintf("s68k_wram2M r16: [%06x] @%06x", a, SekPc);
\r
876 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
878 dprintf("(decode)");
\r
880 // allow access in any mode, like Gens does
\r
881 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
883 dprintf("ret = %04x", d);
\r
887 // word RAM (1M area)
\r
888 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
889 dprintf("s68k_wram1M r16: [%06x] @%06x", a, SekPc);
\r
890 a=((a&0x1fffe)<<1);
\r
891 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
892 d = *(u16 *)(Pico_mcd->word_ram+a);
\r
893 dprintf("ret = %04x", d);
\r
898 if ((a&0xff0000)==0xfe0000) {
\r
899 dprintf("s68k_bram r16: [%06x] @%06x", a, SekPc);
\r
901 d = Pico_mcd->bram[a++]; // Gens does little endian here, an so do we..
\r
902 d|= Pico_mcd->bram[a++] << 8;
\r
903 dprintf("ret = %04x", d);
\r
907 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
912 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
918 u32 PicoReadS68k32(u32 a)
\r
926 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
927 d = (pm[0]<<16)|pm[1];
\r
932 if ((a&0xfffe00) == 0xff8000) {
\r
934 rdprintf("s68k_regs r32: [%02x] @ %06x", a, SekPcS68k);
\r
935 if (a >= 0x50 && a < 0x68)
\r
936 d = (gfx_cd_read(a)<<16)|gfx_cd_read(a+2);
\r
937 else d = (s68k_reg_read16(a)<<16)|s68k_reg_read16(a+2);
\r
938 rdprintf("ret = %08x", d);
\r
942 // word RAM (2M area)
\r
943 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
944 dprintf("s68k_wram2M r32: [%06x] @%06x", a, SekPc);
\r
945 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
947 dprintf("(decode)");
\r
949 // allow access in any mode, like Gens does
\r
950 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
\r
952 dprintf("ret = %08x", d);
\r
956 // word RAM (1M area)
\r
957 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
958 dprintf("s68k_wram1M r32: [%06x] @%06x", a, SekPc);
\r
959 a=((a&0x1fffe)<<1);
\r
960 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
961 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;
\r
962 d |= *(u16 *)(Pico_mcd->word_ram+a+4);
\r
963 dprintf("ret = %08x", d);
\r
968 if ((a&0xff0000)==0xfe0000) {
\r
969 dprintf("s68k_bram r32: [%06x] @%06x", a, SekPc);
\r
971 d = Pico_mcd->bram[a++] << 16; // middle endian? TODO: verify against Fusion..
\r
972 d|= Pico_mcd->bram[a++] << 24;
\r
973 d|= Pico_mcd->bram[a++];
\r
974 d|= Pico_mcd->bram[a++] << 8;
\r
975 dprintf("ret = %08x", d);
\r
979 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
984 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
990 // -----------------------------------------------------------------
\r
992 void PicoWriteS68k8(u32 a,u8 d)
\r
995 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1001 if (a < 0x80000) {
\r
1002 u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));
\r
1007 if (a != 0xff0011 && (a&0xff8000) == 0xff0000) // PCM hack
\r
1011 if ((a&0xfffe00) == 0xff8000) {
\r
1013 rdprintf("s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);
\r
1014 if (a >= 0x50 && a < 0x68)
\r
1015 gfx_cd_write(a&~1, (d<<8)|d);
\r
1016 else s68k_reg_write8(a,d);
\r
1020 // word RAM (2M area)
\r
1021 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1022 dprintf("s68k_wram2M w8: [%06x] %02x @%06x", a, d, SekPc);
\r
1023 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1025 dprintf("(decode)");
\r
1027 // allow access in any mode, like Gens does
\r
1028 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;
\r
1033 // word RAM (1M area)
\r
1034 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1036 dprintf("s68k_wram1M w8: [%06x] %02x @%06x", a, d, SekPc);
\r
1037 a=((a&0x1fffe)<<1)|(a&1);
\r
1038 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1039 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;
\r
1044 if ((a&0xff0000)==0xfe0000) {
\r
1045 Pico_mcd->bram[(a>>1)&0x1fff] = d;
\r
1050 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1054 void PicoWriteS68k16(u32 a,u16 d)
\r
1056 #ifdef __debug_io2
\r
1057 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1063 if (a < 0x80000) {
\r
1064 *(u16 *)(Pico_mcd->prg_ram+a)=d;
\r
1069 if ((a&0xfffe00) == 0xff8000) {
\r
1071 rdprintf("s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);
\r
1072 if (a >= 0x50 && a < 0x68)
\r
1073 gfx_cd_write(a, d);
\r
1075 s68k_reg_write8(a, d>>8);
\r
1076 s68k_reg_write8(a+1,d&0xff);
\r
1081 // word RAM (2M area)
\r
1082 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1083 dprintf("s68k_wram2M w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1084 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1086 dprintf("(decode)");
\r
1088 // allow access in any mode, like Gens does
\r
1089 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;
\r
1094 // word RAM (1M area)
\r
1095 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1097 dprintf("s68k_wram1M w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1098 a=((a&0x1fffe)<<1);
\r
1099 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1100 *(u16 *)(Pico_mcd->word_ram+a)=d;
\r
1105 if ((a&0xff0000)==0xfe0000) {
\r
1106 dprintf("s68k_bram w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1107 a = (a>>1)&0x1fff;
\r
1108 Pico_mcd->bram[a++] = d; // Gens does little endian here, an so do we..
\r
1109 Pico_mcd->bram[a++] = d >> 8;
\r
1114 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1118 void PicoWriteS68k32(u32 a,u32 d)
\r
1120 #ifdef __debug_io2
\r
1121 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1127 if (a < 0x80000) {
\r
1128 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
1129 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1134 if ((a&0xfffe00) == 0xff8000) {
\r
1136 rdprintf("s68k_regs w32: [%02x] %08x @ %06x", a, d, SekPcS68k);
\r
1137 if (a >= 0x50 && a < 0x68) {
\r
1138 gfx_cd_write(a, d>>16);
\r
1139 gfx_cd_write(a+2, d&0xffff);
\r
1141 s68k_reg_write8(a, d>>24);
\r
1142 s68k_reg_write8(a+1,(d>>16)&0xff);
\r
1143 s68k_reg_write8(a+2,(d>>8) &0xff);
\r
1144 s68k_reg_write8(a+3, d &0xff);
\r
1149 // word RAM (2M area)
\r
1150 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1151 dprintf("s68k_wram2M w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1152 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1154 dprintf("(decode)");
\r
1156 // allow access in any mode, like Gens does
\r
1157 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
1158 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1163 // word RAM (1M area)
\r
1164 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1166 dprintf("s68k_wram1M w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1167 a=((a&0x1fffe)<<1);
\r
1168 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1169 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;
\r
1170 *(u16 *)(Pico_mcd->word_ram+a+4) = d;
\r
1175 if ((a&0xff0000)==0xfe0000) {
\r
1176 dprintf("s68k_bram w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1177 a = (a>>1)&0x1fff;
\r
1178 Pico_mcd->bram[a++] = d >> 16; // middle endian? verify?
\r
1179 Pico_mcd->bram[a++] = d >> 24;
\r
1180 Pico_mcd->bram[a++] = d;
\r
1181 Pico_mcd->bram[a++] = d >> 8;
\r
1186 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1191 // -----------------------------------------------------------------
\r
1194 #if defined(EMU_C68K)
\r
1195 static __inline int PicoMemBaseM68k(u32 pc)
\r
1201 membase=(int)Pico_mcd->bios; // Program Counter in BIOS
\r
1203 else if ((pc&0xe00000)==0xe00000)
\r
1205 membase=(int)Pico.ram-(pc&0xff0000); // Program Counter in Ram
\r
1207 else if ((pc&0xfc0000)==0x200000 && !(Pico_mcd->s68k_regs[3]&4))
\r
1209 membase=(int)Pico_mcd->word_ram-0x200000; // Program Counter in Word Ram
\r
1213 // Error - Program Counter is invalid
\r
1214 dprintf("m68k: unhandled jump to %06x", pc);
\r
1215 membase=(int)Pico.rom;
\r
1222 static u32 PicoCheckPcM68k(u32 pc)
\r
1224 pc-=PicoCpu.membase; // Get real pc
\r
1227 PicoCpu.membase=PicoMemBaseM68k(pc);
\r
1229 return PicoCpu.membase+pc;
\r
1233 static __inline int PicoMemBaseS68k(u32 pc)
\r
1237 membase=(int)Pico_mcd->prg_ram; // Program Counter in Prg RAM
\r
1238 if (pc >= 0x80000)
\r
1240 // Error - Program Counter is invalid
\r
1241 dprintf("s68k: unhandled jump to %06x", pc);
\r
1248 static u32 PicoCheckPcS68k(u32 pc)
\r
1250 pc-=PicoCpuS68k.membase; // Get real pc
\r
1253 PicoCpuS68k.membase=PicoMemBaseS68k(pc);
\r
1255 return PicoCpuS68k.membase+pc;
\r
1260 void PicoMemSetupCD()
\r
1262 dprintf("PicoMemSetupCD()");
\r
1264 // Setup m68k memory callbacks:
\r
1265 PicoCpu.checkpc=PicoCheckPcM68k;
\r
1266 PicoCpu.fetch8 =PicoCpu.read8 =PicoReadM68k8;
\r
1267 PicoCpu.fetch16=PicoCpu.read16=PicoReadM68k16;
\r
1268 PicoCpu.fetch32=PicoCpu.read32=PicoReadM68k32;
\r
1269 PicoCpu.write8 =PicoWriteM68k8;
\r
1270 PicoCpu.write16=PicoWriteM68k16;
\r
1271 PicoCpu.write32=PicoWriteM68k32;
\r
1273 PicoCpuS68k.checkpc=PicoCheckPcS68k;
\r
1274 PicoCpuS68k.fetch8 =PicoCpuS68k.read8 =PicoReadS68k8;
\r
1275 PicoCpuS68k.fetch16=PicoCpuS68k.read16=PicoReadS68k16;
\r
1276 PicoCpuS68k.fetch32=PicoCpuS68k.read32=PicoReadS68k32;
\r
1277 PicoCpuS68k.write8 =PicoWriteS68k8;
\r
1278 PicoCpuS68k.write16=PicoWriteS68k16;
\r
1279 PicoCpuS68k.write32=PicoWriteS68k32;
\r
1285 unsigned char PicoReadCD8w (unsigned int a) {
\r
1286 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k8(a) : PicoReadM68k8(a);
\r
1288 unsigned short PicoReadCD16w(unsigned int a) {
\r
1289 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k16(a) : PicoReadM68k16(a);
\r
1291 unsigned int PicoReadCD32w(unsigned int a) {
\r
1292 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k32(a) : PicoReadM68k32(a);
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1294 void PicoWriteCD8w (unsigned int a, unsigned char d) {
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1295 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k8(a, d); else PicoWriteM68k8(a, d);
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1297 void PicoWriteCD16w(unsigned int a, unsigned short d) {
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1298 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k16(a, d); else PicoWriteM68k16(a, d);
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1300 void PicoWriteCD32w(unsigned int a, unsigned int d) {
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1301 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k32(a, d); else PicoWriteM68k32(a, d);
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1304 // these are allowed to access RAM
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1305 unsigned int m68k_read_pcrelative_CD8 (unsigned int a) {
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1307 if(m68ki_cpu_p == &PicoS68kCPU) {
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1308 if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram
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1309 dprintf("s68k_read_pcrelative_CD8: can't handle %06x", a);
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1311 if(a<0x20000) return *(u8 *)(Pico.rom+(a^1)); // Bios
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1312 if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram
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1313 if(!(Pico_mcd->s68k_regs[3]&4) && (a&0xfc0000)==0x200000)
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1314 return Pico_mcd->word_ram[(a^1)&0x3fffe];
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1315 dprintf("m68k_read_pcrelative_CD8: can't handle %06x", a);
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1317 return 0;//(u8) lastread_d;
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1319 unsigned int m68k_read_pcrelative_CD16(unsigned int a) {
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1321 if(m68ki_cpu_p == &PicoS68kCPU) {
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1322 if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram
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1323 dprintf("s68k_read_pcrelative_CD16: can't handle %06x", a);
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1325 if(a<0x20000) return *(u16 *)(Pico.rom+(a&~1)); // Bios
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1326 if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram
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1327 if(!(Pico_mcd->s68k_regs[3]&4) && (a&0xfc0000)==0x200000)
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1328 return *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
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1329 dprintf("m68k_read_pcrelative_CD16: can't handle %06x", a);
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1333 unsigned int m68k_read_pcrelative_CD32(unsigned int a) {
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1335 if(m68ki_cpu_p == &PicoS68kCPU) {
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1336 if (a < 0x80000) { u16 *pm=(u16 *)(Pico_mcd->prg_ram+(a&~1)); return (pm[0]<<16)|pm[1]; } // PRG Ram
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1337 dprintf("s68k_read_pcrelative_CD32: can't handle %06x", a);
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1339 if(a<0x20000) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }
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1340 if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram
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1341 if(!(Pico_mcd->s68k_regs[3]&4) && (a&0xfc0000)==0x200000)
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1342 { u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }
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1343 dprintf("m68k_read_pcrelative_CD32: can't handle %06x", a);
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1347 #endif // EMU_M68K
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