1 // This is part of Pico Library
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3 // (c) Copyright 2004 Dave, All rights reserved.
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4 // (c) Copyright 2007 notaz, All rights reserved.
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5 // Free for non-commercial use.
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7 // For commercial use, separate licencing terms must be obtained.
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9 // A68K no longer supported here
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11 //#define __debug_io
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13 #include "../PicoInt.h"
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15 #include "../sound/sound.h"
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16 #include "../sound/ym2612.h"
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17 #include "../sound/sn76496.h"
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21 typedef unsigned char u8;
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22 typedef unsigned short u16;
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23 typedef unsigned int u32;
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25 //#define __debug_io
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26 //#define __debug_io2
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27 //#define rdprintf dprintf
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28 #define rdprintf(...)
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30 // -----------------------------------------------------------------
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32 // extern m68ki_cpu_core m68ki_cpu;
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34 extern int counter75hz;
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37 static u32 m68k_reg_read16(u32 a)
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41 // dprintf("m68k_regs r%2i: [%02x] @%06x", realsize&~1, a+(realsize&1), SekPc);
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45 d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens
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48 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);
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49 dprintf("m68k_regs r3: %02x @%06x", (u8)d, SekPc);
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52 d = Pico_mcd->s68k_regs[4]<<8;
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55 d = Pico_mcd->m.hint_vector;
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58 d = Read_CDC_Host(0);
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61 dprintf("m68k reserved read");
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64 dprintf("m68k stopwatch timer read");
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69 // comm flag/cmd/status (0xE-0x2F)
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70 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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74 dprintf("m68k_regs invalid read @ %02x", a);
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78 // dprintf("ret = %04x", d);
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82 static void m68k_reg_write8(u32 a, u32 d)
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85 // dprintf("m68k_regs w%2i: [%02x] %02x @%06x", realsize, a, d, SekPc);
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90 if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { dprintf("m68k: s68k irq 2"); SekInterruptS68k(2); }
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94 if (!(d&1)) PicoMCD |= 2; // reset pending, needed to be sure we fetch the right vectors on reset
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95 if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));
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96 if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);
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97 if ((PicoMCD&2) && (d&3)==1) {
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98 SekResetS68k(); // S68k comes out of RESET or BRQ state
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100 dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);
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102 Pico_mcd->m.busreq = d;
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105 Pico_mcd->s68k_regs[2] = d; // really use s68k side register
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108 dprintf("m68k_regs w3: %02x @%06x", (u8)d, SekPc);
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110 if ((Pico_mcd->s68k_regs[3]>>6) != ((d>>6)&3))
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111 dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));
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112 //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);
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113 //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :
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114 // ((d&2) ? "word ram to s68k" : "word ram to m68k"));
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115 d |= Pico_mcd->s68k_regs[3]&0x1d;
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116 if (!(d & 4) && (d & 2)) d &= ~1; // return word RAM to s68k in 2M mode
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117 Pico_mcd->s68k_regs[3] = d; // really use s68k side register
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120 *((char *)&Pico_mcd->m.hint_vector+1) = d;
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121 Pico_mcd->bios[0x72 + 1] = d; // simple hint vector changer
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124 *(char *)&Pico_mcd->m.hint_vector = d;
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125 Pico_mcd->bios[0x72] = d;
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128 //dprintf("m68k: comm flag: %02x", d);
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130 //dprintf("s68k @ %06x", SekPcS68k);
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132 Pico_mcd->s68k_regs[0xe] = d;
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136 if ((a&0xf0) == 0x10) {
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137 Pico_mcd->s68k_regs[a] = d;
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141 dprintf("m68k: invalid write? [%02x] %02x", a, d);
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146 static u32 s68k_reg_read16(u32 a)
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150 // dprintf("s68k_regs r%2i: [%02x] @ %06x", realsize&~1, a+(realsize&1), SekPcS68k);
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154 d = ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state
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157 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0x1f);
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158 dprintf("s68k_regs r3: %02x @%06x", (u8)d, SekPc);
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161 d = CDC_Read_Reg();
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164 d = Read_CDC_Host(1); // Gens returns 0 here on byte reads
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167 dprintf("s68k stopwatch timer read");
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170 dprintf("s68k int3 timer read");
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172 case 0x34: // fader
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173 d = 0; // no busy bit
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177 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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181 // dprintf("ret = %04x", d);
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186 static void s68k_reg_write8(u32 a, u32 d)
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188 //dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);
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190 // TODO: review against Gens
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193 return; // only m68k can change WP
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195 dprintf("s68k_regs w3: %02x @%06x", (u8)d, SekPc);
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198 d |= Pico_mcd->s68k_regs[3]&0xc2;
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199 if ((d ^ Pico_mcd->s68k_regs[3]) & 5) d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit
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201 d |= Pico_mcd->s68k_regs[3]&0xc3;
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202 if (d&1) d &= ~2; // return word RAM to m68k in 2M mode
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206 dprintf("s68k CDC dest: %x", d&7);
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207 Pico_mcd->s68k_regs[4] = (Pico_mcd->s68k_regs[4]&0xC0) | (d&7); // CDC mode
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210 //dprintf("s68k CDC reg addr: %x", d&0xf);
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216 dprintf("s68k set CDC dma addr");
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219 dprintf("s68k set stopwatch timer");
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222 dprintf("s68k set int3 timer");
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224 case 0x33: // IRQ mask
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225 dprintf("s68k irq mask: %02x", d);
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226 if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {
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227 CDD_Export_Status();
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228 // counter75hz = 0; // ???
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231 case 0x34: // fader
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232 Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;
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235 return; // d/m bit is unsetable
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237 u32 d_old = Pico_mcd->s68k_regs[0x37];
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238 Pico_mcd->s68k_regs[0x37] = d&7;
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239 if ((d&4) && !(d_old&4)) {
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240 CDD_Export_Status();
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241 // counter75hz = 0; // ???
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246 Pico_mcd->s68k_regs[a] = (u8) d;
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247 CDD_Import_Command();
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251 if ((a&0x1f0) == 0x10 || a == 0x0e || (a >= 0x38 && a < 0x42))
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253 dprintf("m68k: invalid write @ %02x?", a);
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257 Pico_mcd->s68k_regs[a] = (u8) d;
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264 static int PadRead(int i)
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266 int pad=0,value=0,TH;
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267 pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU
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268 TH=Pico.ioports[i+1]&0x40;
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270 if(PicoOpt & 0x20) { // 6 button gamepad enabled
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271 int phase = Pico.m.padTHPhase[i];
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273 if(phase == 2 && !TH) {
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274 value=(pad&0xc0)>>2; // ?0SA 0000
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276 } else if(phase == 3 && TH) {
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277 value=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ
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279 } else if(phase == 3 && !TH) {
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280 value=((pad&0xc0)>>2)|0x0f; // ?0SA 1111
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285 if(TH) value=(pad&0x3f); // ?1CB RLDU
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286 else value=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU
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290 // orr the bits, which are set as output
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291 value |= Pico.ioports[i+1]&Pico.ioports[i+4];
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293 return value; // will mirror later
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296 static u8 z80Read8(u32 a)
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298 if(Pico.m.z80Run&1) return 0;
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303 // Z80 disabled, do some faking
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304 static u8 zerosent = 0;
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305 if(a == Pico.m.z80_lastaddr) { // probably polling something
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306 u8 d = Pico.m.z80_fakeval;
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307 if((d & 0xf) == 0xf && !zerosent) {
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308 d = 0; zerosent = 1;
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310 Pico.m.z80_fakeval++;
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315 Pico.m.z80_fakeval = 0;
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319 Pico.m.z80_lastaddr = (u16) a;
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320 return Pico.zram[a];
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324 // for nonstandard reads
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325 static u32 UnusualRead16(u32 a, int realsize)
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329 dprintf("unusual r%i: %06x @%06x", realsize&~1, (a&0xfffffe)+(realsize&1), SekPc);
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332 dprintf("ret = %04x", d);
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336 static u32 OtherRead16(u32 a, int realsize)
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340 if ((a&0xff0000)==0xa00000) {
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341 if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)
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342 if ((a&0x6000)==0x4000) { if(PicoOpt&1) d=YM2612Read(); else d=Pico.m.rotate++&3; goto end; } // 0x4000-0x5fff, Fudge if disabled
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343 d=0xffff; goto end;
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345 if ((a&0xffffe0)==0xa10000) { // I/O ports
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348 case 0: d=Pico.m.hardware; break; // Hardware value (Version register)
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349 case 1: d=PadRead(0); d|=Pico.ioports[1]&0x80; break;
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350 case 2: d=PadRead(1); d|=Pico.ioports[2]&0x80; break;
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351 default: d=Pico.ioports[a]; break; // IO ports can be used as RAM
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356 // |=0x80 for Shadow of the Beast & Super Offroad; rotate fakes next fetched instruction for Time Killers
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357 if (a==0xa11100) { d=((Pico.m.z80Run&1)<<8)|0x8000|Pico.m.rotate++; goto end; }
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359 if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; }
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361 if ((a&0xffffc0)==0xa12000) {
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362 d=m68k_reg_read16(a);
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366 d = UnusualRead16(a, realsize);
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372 //extern UINT32 mz80GetRegisterValue(void *, UINT32);
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374 static void OtherWrite8(u32 a,u32 d,int realsize)
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376 if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
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377 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram
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378 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound
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379 if ((a&0xffffe0)==0xa10000) { // I/O ports
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381 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
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384 Pico.m.padDelay[0] = 0;
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385 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
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388 Pico.m.padDelay[1] = 0;
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389 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
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392 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
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396 extern int z80startCycle, z80stopCycle;
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397 //int lineCycles=(488-SekCyclesLeft)&0x1ff;
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400 // hack: detect a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)
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401 if((PicoOpt&4) && Pico.m.z80Run==1) z80_run(20);
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402 z80stopCycle = SekCyclesDone();
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403 //z80ExtraCycles += (lineCycles>>1)-(lineCycles>>5); // only meaningful in PicoFrameHints()
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405 z80startCycle = SekCyclesDone();
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406 //if(Pico.m.scanline != -1)
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407 //z80ExtraCycles -= (lineCycles>>1)-(lineCycles>>5)+16;
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409 //dprintf("set_zrun: %i [%i|%i] zPC=%04x @%06x", d, Pico.m.scanline, SekCyclesDone(), mz80GetRegisterValue(NULL, 0), SekPc);
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410 Pico.m.z80Run=(u8)d; return;
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412 if (a==0xa11200) { if(!(d&1)) z80_reset(); return; }
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414 if ((a&0xff7f00)==0xa06000) // Z80 BANK register
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416 Pico.m.z80_bank68k>>=1;
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417 Pico.m.z80_bank68k|=(d&1)<<8;
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418 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
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422 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)(d|(d<<8))); return; } // Byte access gets mirrored
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424 if ((a&0xffffc0)==0xa12000) { m68k_reg_write8(a, d); return; }
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426 dprintf("strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);
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429 static void OtherWrite16(u32 a,u32 d)
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431 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; }
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432 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)
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434 if ((a&0xffffe0)==0xa10000) { // I/O ports
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436 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
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439 Pico.m.padDelay[0] = 0;
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440 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
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443 Pico.m.padDelay[1] = 0;
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444 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
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447 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
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450 if (a==0xa11100) { OtherWrite8(a, d>>8, 16); return; }
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451 if (a==0xa11200) { if(!(d&0x100)) z80_reset(); return; }
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453 OtherWrite8(a, d>>8, 16);
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454 OtherWrite8(a+1,d&0xff, 16);
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457 // -----------------------------------------------------------------
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458 // Read Rom and read Ram
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460 u8 PicoReadM68k8(u32 a)
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464 if ((a&0xe00000)==0xe00000) { d = *(u8 *)(Pico.ram+((a^1)&0xffff)); goto end; } // Ram
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468 if (a < 0x20000) { d = *(u8 *)(Pico_mcd->bios+(a^1)); goto end; } // bios
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471 if ((a&0xfe0000)==0x020000) {
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472 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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473 d = *(prg_bank+((a^1)&0x1ffff));
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478 if (a == 0x200000 && SekPc == 0xff0b66 && Pico.m.frame_count > 1000)
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482 unsigned short *ram = (unsigned short *) Pico.ram;
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483 // unswap and dump RAM
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484 for (i = 0; i < 0x10000/2; i++)
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485 ram[i] = (ram[i]>>8) | (ram[i]<<8);
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486 ff = fopen("ram.bin", "wb");
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487 fwrite(ram, 1, 0x10000, ff);
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494 if ((a&0xfc0000)==0x200000) {
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495 dprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);
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496 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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497 if (a >= 0x220000) {
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500 a=((a&0x1fffe)<<1)|(a&1);
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501 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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502 d = Pico_mcd->word_ram[a^1];
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505 // allow access in any mode, like Gens does
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506 d = Pico_mcd->word_ram[(a^1)&0x3ffff];
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508 dprintf("ret = %02x", (u8)d);
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512 if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram
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514 if ((a&0xffffc0)==0xa12000)
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515 rdprintf("m68k_regs r8: [%02x] @%06x", a&0x3f, SekPc);
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517 d=OtherRead16(a&~1, 8|(a&1)); if ((a&1)==0) d>>=8;
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519 if ((a&0xffffc0)==0xa12000)
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520 rdprintf("ret = %02x", (u8)d);
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525 dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);
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531 u16 PicoReadM68k16(u32 a)
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535 if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram
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539 if (a < 0x20000) { d = *(u16 *)(Pico_mcd->bios+a); goto end; } // bios
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542 if ((a&0xfe0000)==0x020000) {
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543 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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544 d = *(u16 *)(prg_bank+(a&0x1fffe));
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549 if ((a&0xfc0000)==0x200000) {
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550 dprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);
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551 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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552 if (a >= 0x220000) {
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555 a=((a&0x1fffe)<<1);
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556 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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557 d = *(u16 *)(Pico_mcd->word_ram+a);
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560 // allow access in any mode, like Gens does
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561 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
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563 dprintf("ret = %04x", d);
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567 if ((a&0xffffc0)==0xa12000)
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568 rdprintf("m68k_regs r16: [%02x] @%06x", a&0x3f, SekPc);
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570 d = (u16)OtherRead16(a, 16);
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572 if ((a&0xffffc0)==0xa12000)
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573 rdprintf("ret = %04x", d);
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578 dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
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584 u32 PicoReadM68k32(u32 a)
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588 if ((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); d = (pm[0]<<16)|pm[1]; goto end; } // Ram
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592 if (a < 0x20000) { u16 *pm=(u16 *)(Pico_mcd->bios+a); d = (pm[0]<<16)|pm[1]; goto end; } // bios
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595 if ((a&0xfe0000)==0x020000) {
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596 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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597 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
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598 d = (pm[0]<<16)|pm[1];
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603 if ((a&0xfc0000)==0x200000) {
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604 dprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);
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605 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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606 if (a >= 0x220000) {
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609 a=((a&0x1fffe)<<1);
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610 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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611 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;
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612 d |= *(u16 *)(Pico_mcd->word_ram+a+4);
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615 // allow access in any mode, like Gens does
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616 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
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618 dprintf("ret = %08x", d);
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622 if ((a&0xffffc0)==0xa12000)
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623 rdprintf("m68k_regs r32: [%02x] @%06x", a&0x3f, SekPc);
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625 d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);
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627 if ((a&0xffffc0)==0xa12000)
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628 rdprintf("ret = %08x", d);
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632 dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);
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638 // -----------------------------------------------------------------
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641 void PicoWriteM68k8(u32 a,u8 d)
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644 dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
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646 //if ((a&0xe0ffff)==0xe0a9ba+0x69c)
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647 // dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
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650 if ((a&0xe00000)==0xe00000) { // Ram
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651 *(u8 *)(Pico.ram+((a^1)&0xffff)) = d;
\r
658 if ((a&0xfe0000)==0x020000) {
\r
659 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
660 *(u8 *)(prg_bank+((a^1)&0x1ffff))=d;
\r
665 if ((a&0xfc0000)==0x200000) {
\r
666 dprintf("m68k_wram w8: [%06x] %02x @%06x", a, d, SekPc);
\r
667 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
668 if (a >= 0x220000) {
\r
671 a=((a&0x1fffe)<<1)|(a&1);
\r
672 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
673 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;
\r
676 // allow access in any mode, like Gens does
\r
677 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;
\r
682 if ((a&0xffffc0)==0xa12000)
\r
683 rdprintf("m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);
\r
685 OtherWrite8(a,d,8);
\r
689 void PicoWriteM68k16(u32 a,u16 d)
\r
692 dprintf("w16: %06x, %04x", a&0xffffff, d);
\r
694 // dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
\r
696 if ((a&0xe00000)==0xe00000) { // Ram
\r
697 *(u16 *)(Pico.ram+(a&0xfffe))=d;
\r
704 if ((a&0xfe0000)==0x020000) {
\r
705 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
706 *(u16 *)(prg_bank+(a&0x1fffe))=d;
\r
711 if ((a&0xfc0000)==0x200000) {
\r
712 dprintf("m68k_wram w16: [%06x] %04x @%06x", a, d, SekPc);
\r
713 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
714 if (a >= 0x220000) {
\r
717 a=((a&0x1fffe)<<1);
\r
718 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
719 *(u16 *)(Pico_mcd->word_ram+a)=d;
\r
722 // allow access in any mode, like Gens does
\r
723 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;
\r
728 if ((a&0xffffc0)==0xa12000)
\r
729 rdprintf("m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);
\r
735 void PicoWriteM68k32(u32 a,u32 d)
\r
738 dprintf("w32: %06x, %08x", a&0xffffff, d);
\r
741 if ((a&0xe00000)==0xe00000)
\r
744 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));
\r
745 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
752 if ((a&0xfe0000)==0x020000) {
\r
753 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
754 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
\r
755 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
760 if ((a&0xfc0000)==0x200000) {
\r
761 if (d != 0) // don't log clears
\r
762 dprintf("m68k_wram w32: [%06x] %08x @%06x", a, d, SekPc);
\r
763 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
764 if (a >= 0x220000) {
\r
767 a=((a&0x1fffe)<<1);
\r
768 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
769 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;
\r
770 *(u16 *)(Pico_mcd->word_ram+a+4) = d;
\r
773 // allow access in any mode, like Gens does
\r
774 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
775 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
780 if ((a&0xffffc0)==0xa12000)
\r
781 rdprintf("m68k_regs w32: [%02x] %08x @%06x", a&0x3f, d, SekPc);
\r
783 OtherWrite16(a, (u16)(d>>16));
\r
784 OtherWrite16(a+2,(u16)d);
\r
788 // -----------------------------------------------------------------
\r
791 u8 PicoReadS68k8(u32 a)
\r
799 d = *(Pico_mcd->prg_ram+(a^1));
\r
804 if ((a&0xfffe00) == 0xff8000) {
\r
806 rdprintf("s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);
\r
807 if (a >= 0x50 && a < 0x68)
\r
808 d = gfx_cd_read(a&~1);
\r
809 else d = s68k_reg_read16(a&~1);
\r
810 if ((a&1)==0) d>>=8;
\r
811 rdprintf("ret = %02x", (u8)d);
\r
815 // word RAM (2M area)
\r
816 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
817 dprintf("s68k_wram2M r8: [%06x] @%06x", a, SekPc);
\r
818 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
820 dprintf("(decode)");
\r
822 // allow access in any mode, like Gens does
\r
823 d = Pico_mcd->word_ram[(a^1)&0x3ffff];
\r
825 dprintf("ret = %02x", (u8)d);
\r
829 // word RAM (1M area)
\r
830 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
831 dprintf("s68k_wram1M r8: [%06x] @%06x", a, SekPc);
\r
832 a=((a&0x1fffe)<<1)|(a&1);
\r
833 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
834 d = Pico_mcd->word_ram[a^1];
\r
835 dprintf("ret = %02x", (u8)d);
\r
840 if ((a&0xff0000)==0xfe0000) {
\r
841 d = Pico_mcd->bram[(a>>1)&0x1fff];
\r
845 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
850 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
856 u16 PicoReadS68k16(u32 a)
\r
864 d = *(u16 *)(Pico_mcd->prg_ram+a);
\r
869 if ((a&0xfffe00) == 0xff8000) {
\r
871 rdprintf("s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);
\r
872 if (a >= 0x50 && a < 0x68)
\r
873 d = gfx_cd_read(a);
\r
874 else d = s68k_reg_read16(a);
\r
875 rdprintf("ret = %04x", d);
\r
879 // word RAM (2M area)
\r
880 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
881 dprintf("s68k_wram2M r16: [%06x] @%06x", a, SekPc);
\r
882 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
884 dprintf("(decode)");
\r
886 // allow access in any mode, like Gens does
\r
887 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
889 dprintf("ret = %04x", d);
\r
893 // word RAM (1M area)
\r
894 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
895 dprintf("s68k_wram1M r16: [%06x] @%06x", a, SekPc);
\r
896 a=((a&0x1fffe)<<1);
\r
897 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
898 d = *(u16 *)(Pico_mcd->word_ram+a);
\r
899 dprintf("ret = %04x", d);
\r
904 if ((a&0xff0000)==0xfe0000) {
\r
905 dprintf("s68k_bram r16: [%06x] @%06x", a, SekPc);
\r
907 d = Pico_mcd->bram[a++]; // Gens does little endian here, an so do we..
\r
908 d|= Pico_mcd->bram[a++] << 8;
\r
909 dprintf("ret = %04x", d);
\r
913 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
918 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
924 u32 PicoReadS68k32(u32 a)
\r
932 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
933 d = (pm[0]<<16)|pm[1];
\r
938 if ((a&0xfffe00) == 0xff8000) {
\r
940 rdprintf("s68k_regs r32: [%02x] @ %06x", a, SekPcS68k);
\r
941 if (a >= 0x50 && a < 0x68)
\r
942 d = (gfx_cd_read(a)<<16)|gfx_cd_read(a+2);
\r
943 else d = (s68k_reg_read16(a)<<16)|s68k_reg_read16(a+2);
\r
944 rdprintf("ret = %08x", d);
\r
948 // word RAM (2M area)
\r
949 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
950 dprintf("s68k_wram2M r32: [%06x] @%06x", a, SekPc);
\r
951 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
953 dprintf("(decode)");
\r
955 // allow access in any mode, like Gens does
\r
956 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
\r
958 dprintf("ret = %08x", d);
\r
962 // word RAM (1M area)
\r
963 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
964 dprintf("s68k_wram1M r32: [%06x] @%06x", a, SekPc);
\r
965 a=((a&0x1fffe)<<1);
\r
966 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
967 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;
\r
968 d |= *(u16 *)(Pico_mcd->word_ram+a+4);
\r
969 dprintf("ret = %08x", d);
\r
974 if ((a&0xff0000)==0xfe0000) {
\r
975 dprintf("s68k_bram r32: [%06x] @%06x", a, SekPc);
\r
977 d = Pico_mcd->bram[a++] << 16; // middle endian? TODO: verify against Fusion..
\r
978 d|= Pico_mcd->bram[a++] << 24;
\r
979 d|= Pico_mcd->bram[a++];
\r
980 d|= Pico_mcd->bram[a++] << 8;
\r
981 dprintf("ret = %08x", d);
\r
985 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
990 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
996 // -----------------------------------------------------------------
\r
998 void PicoWriteS68k8(u32 a,u8 d)
\r
1000 #ifdef __debug_io2
\r
1001 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1007 if (a < 0x80000) {
\r
1008 u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));
\r
1013 if (a != 0xff0011 && (a&0xff8000) == 0xff0000) // PCM hack
\r
1017 if ((a&0xfffe00) == 0xff8000) {
\r
1019 rdprintf("s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);
\r
1020 if (a >= 0x50 && a < 0x68)
\r
1021 gfx_cd_write(a&~1, (d<<8)|d);
\r
1022 else s68k_reg_write8(a,d);
\r
1026 // word RAM (2M area)
\r
1027 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1028 dprintf("s68k_wram2M w8: [%06x] %02x @%06x", a, d, SekPc);
\r
1029 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1031 dprintf("(decode)");
\r
1033 // allow access in any mode, like Gens does
\r
1034 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;
\r
1039 // word RAM (1M area)
\r
1040 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1042 dprintf("s68k_wram1M w8: [%06x] %02x @%06x", a, d, SekPc);
\r
1043 a=((a&0x1fffe)<<1)|(a&1);
\r
1044 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1045 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;
\r
1050 if ((a&0xff0000)==0xfe0000) {
\r
1051 Pico_mcd->bram[(a>>1)&0x1fff] = d;
\r
1056 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1060 void PicoWriteS68k16(u32 a,u16 d)
\r
1062 #ifdef __debug_io2
\r
1063 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1069 if (a < 0x80000) {
\r
1070 *(u16 *)(Pico_mcd->prg_ram+a)=d;
\r
1075 if ((a&0xfffe00) == 0xff8000) {
\r
1077 rdprintf("s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);
\r
1078 if (a >= 0x50 && a < 0x68)
\r
1079 gfx_cd_write(a, d);
\r
1081 s68k_reg_write8(a, d>>8);
\r
1082 s68k_reg_write8(a+1,d&0xff);
\r
1087 // word RAM (2M area)
\r
1088 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1089 dprintf("s68k_wram2M w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1090 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1092 dprintf("(decode)");
\r
1094 // allow access in any mode, like Gens does
\r
1095 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;
\r
1100 // word RAM (1M area)
\r
1101 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1103 dprintf("s68k_wram1M w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1104 a=((a&0x1fffe)<<1);
\r
1105 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1106 *(u16 *)(Pico_mcd->word_ram+a)=d;
\r
1111 if ((a&0xff0000)==0xfe0000) {
\r
1112 dprintf("s68k_bram w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1113 a = (a>>1)&0x1fff;
\r
1114 Pico_mcd->bram[a++] = d; // Gens does little endian here, an so do we..
\r
1115 Pico_mcd->bram[a++] = d >> 8;
\r
1120 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1124 void PicoWriteS68k32(u32 a,u32 d)
\r
1126 #ifdef __debug_io2
\r
1127 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1133 if (a < 0x80000) {
\r
1134 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
1135 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1140 if ((a&0xfffe00) == 0xff8000) {
\r
1142 rdprintf("s68k_regs w32: [%02x] %08x @ %06x", a, d, SekPcS68k);
\r
1143 if (a >= 0x50 && a < 0x68) {
\r
1144 gfx_cd_write(a, d>>16);
\r
1145 gfx_cd_write(a+2, d&0xffff);
\r
1147 s68k_reg_write8(a, d>>24);
\r
1148 s68k_reg_write8(a+1,(d>>16)&0xff);
\r
1149 s68k_reg_write8(a+2,(d>>8) &0xff);
\r
1150 s68k_reg_write8(a+3, d &0xff);
\r
1155 // word RAM (2M area)
\r
1156 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1157 dprintf("s68k_wram2M w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1158 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1160 dprintf("(decode)");
\r
1162 // allow access in any mode, like Gens does
\r
1163 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
1164 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1169 // word RAM (1M area)
\r
1170 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1172 dprintf("s68k_wram1M w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1173 a=((a&0x1fffe)<<1);
\r
1174 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1175 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;
\r
1176 *(u16 *)(Pico_mcd->word_ram+a+4) = d;
\r
1181 if ((a&0xff0000)==0xfe0000) {
\r
1182 dprintf("s68k_bram w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1183 a = (a>>1)&0x1fff;
\r
1184 Pico_mcd->bram[a++] = d >> 16; // middle endian? verify?
\r
1185 Pico_mcd->bram[a++] = d >> 24;
\r
1186 Pico_mcd->bram[a++] = d;
\r
1187 Pico_mcd->bram[a++] = d >> 8;
\r
1192 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1197 // -----------------------------------------------------------------
\r
1200 #if defined(EMU_C68K)
\r
1201 static __inline int PicoMemBaseM68k(u32 pc)
\r
1207 membase=(int)Pico_mcd->bios; // Program Counter in BIOS
\r
1209 else if ((pc&0xe00000)==0xe00000)
\r
1211 membase=(int)Pico.ram-(pc&0xff0000); // Program Counter in Ram
\r
1213 else if ((pc&0xfc0000)==0x200000 && !(Pico_mcd->s68k_regs[3]&4))
\r
1215 membase=(int)Pico_mcd->word_ram-0x200000; // Program Counter in Word Ram
\r
1219 // Error - Program Counter is invalid
\r
1220 dprintf("m68k: unhandled jump to %06x", pc);
\r
1221 membase=(int)Pico.rom;
\r
1228 static u32 PicoCheckPcM68k(u32 pc)
\r
1230 pc-=PicoCpu.membase; // Get real pc
\r
1233 PicoCpu.membase=PicoMemBaseM68k(pc);
\r
1235 return PicoCpu.membase+pc;
\r
1239 static __inline int PicoMemBaseS68k(u32 pc)
\r
1243 membase=(int)Pico_mcd->prg_ram; // Program Counter in Prg RAM
\r
1244 if (pc >= 0x80000)
\r
1246 // Error - Program Counter is invalid
\r
1247 dprintf("s68k: unhandled jump to %06x", pc);
\r
1254 static u32 PicoCheckPcS68k(u32 pc)
\r
1256 pc-=PicoCpuS68k.membase; // Get real pc
\r
1259 PicoCpuS68k.membase=PicoMemBaseS68k(pc);
\r
1261 return PicoCpuS68k.membase+pc;
\r
1266 void PicoMemSetupCD()
\r
1268 dprintf("PicoMemSetupCD()");
\r
1270 // Setup m68k memory callbacks:
\r
1271 PicoCpu.checkpc=PicoCheckPcM68k;
\r
1272 PicoCpu.fetch8 =PicoCpu.read8 =PicoReadM68k8;
\r
1273 PicoCpu.fetch16=PicoCpu.read16=PicoReadM68k16;
\r
1274 PicoCpu.fetch32=PicoCpu.read32=PicoReadM68k32;
\r
1275 PicoCpu.write8 =PicoWriteM68k8;
\r
1276 PicoCpu.write16=PicoWriteM68k16;
\r
1277 PicoCpu.write32=PicoWriteM68k32;
\r
1279 PicoCpuS68k.checkpc=PicoCheckPcS68k;
\r
1280 PicoCpuS68k.fetch8 =PicoCpuS68k.read8 =PicoReadS68k8;
\r
1281 PicoCpuS68k.fetch16=PicoCpuS68k.read16=PicoReadS68k16;
\r
1282 PicoCpuS68k.fetch32=PicoCpuS68k.read32=PicoReadS68k32;
\r
1283 PicoCpuS68k.write8 =PicoWriteS68k8;
\r
1284 PicoCpuS68k.write16=PicoWriteS68k16;
\r
1285 PicoCpuS68k.write32=PicoWriteS68k32;
\r
1291 unsigned char PicoReadCD8w (unsigned int a) {
\r
1292 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k8(a) : PicoReadM68k8(a);
\r
1294 unsigned short PicoReadCD16w(unsigned int a) {
\r
1295 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k16(a) : PicoReadM68k16(a);
\r
1297 unsigned int PicoReadCD32w(unsigned int a) {
\r
1298 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k32(a) : PicoReadM68k32(a);
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1300 void PicoWriteCD8w (unsigned int a, unsigned char d) {
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1301 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k8(a, d); else PicoWriteM68k8(a, d);
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1303 void PicoWriteCD16w(unsigned int a, unsigned short d) {
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1304 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k16(a, d); else PicoWriteM68k16(a, d);
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1306 void PicoWriteCD32w(unsigned int a, unsigned int d) {
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1307 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k32(a, d); else PicoWriteM68k32(a, d);
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1310 // these are allowed to access RAM
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1311 unsigned int m68k_read_pcrelative_CD8 (unsigned int a) {
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1313 if(m68ki_cpu_p == &PicoS68kCPU) {
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1314 if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram
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1315 dprintf("s68k_read_pcrelative_CD8: can't handle %06x", a);
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1317 if(a<0x20000) return *(u8 *)(Pico.rom+(a^1)); // Bios
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1318 if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram
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1319 if(!(Pico_mcd->s68k_regs[3]&4) && (a&0xfc0000)==0x200000)
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1320 return Pico_mcd->word_ram[(a^1)&0x3fffe];
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1321 dprintf("m68k_read_pcrelative_CD8: can't handle %06x", a);
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1323 return 0;//(u8) lastread_d;
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1325 unsigned int m68k_read_pcrelative_CD16(unsigned int a) {
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1327 if(m68ki_cpu_p == &PicoS68kCPU) {
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1328 if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram
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1329 dprintf("s68k_read_pcrelative_CD16: can't handle %06x", a);
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1331 if(a<0x20000) return *(u16 *)(Pico.rom+(a&~1)); // Bios
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1332 if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram
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1333 if(!(Pico_mcd->s68k_regs[3]&4) && (a&0xfc0000)==0x200000)
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1334 return *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
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1335 dprintf("m68k_read_pcrelative_CD16: can't handle %06x", a);
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1339 unsigned int m68k_read_pcrelative_CD32(unsigned int a) {
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1341 if(m68ki_cpu_p == &PicoS68kCPU) {
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1342 if (a < 0x80000) { u16 *pm=(u16 *)(Pico_mcd->prg_ram+(a&~1)); return (pm[0]<<16)|pm[1]; } // PRG Ram
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1343 dprintf("s68k_read_pcrelative_CD32: can't handle %06x", a);
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1345 if(a<0x20000) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }
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1346 if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram
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1347 if(!(Pico_mcd->s68k_regs[3]&4) && (a&0xfc0000)==0x200000)
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1348 { u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }
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1349 dprintf("m68k_read_pcrelative_CD32: can't handle %06x", a);
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1353 #endif // EMU_M68K
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