1 // This is part of Pico Library
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3 // (c) Copyright 2004 Dave, All rights reserved.
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4 // (c) Copyright 2007 notaz, All rights reserved.
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5 // Free for non-commercial use.
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7 // For commercial use, separate licencing terms must be obtained.
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9 // A68K no longer supported here
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11 //#define __debug_io
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13 #include "../PicoInt.h"
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15 #include "../sound/sound.h"
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16 #include "../sound/ym2612.h"
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17 #include "../sound/sn76496.h"
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21 typedef unsigned char u8;
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22 typedef unsigned short u16;
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23 typedef unsigned int u32;
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25 //#define __debug_io
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26 //#define __debug_io2
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27 //#define rdprintf dprintf
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28 #define rdprintf(...)
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30 // -----------------------------------------------------------------
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32 // extern m68ki_cpu_core m68ki_cpu;
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35 static u32 m68k_reg_read16(u32 a)
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39 // dprintf("m68k_regs r%2i: [%02x] @%06x", realsize&~1, a+(realsize&1), SekPc);
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43 d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens
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46 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);
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47 dprintf("m68k_regs r3: %02x @%06x", (u8)d, SekPc);
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50 d = Pico_mcd->s68k_regs[4]<<8;
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53 d = Pico_mcd->m.hint_vector;
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56 d = Read_CDC_Host(0);
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59 dprintf("m68k reserved read");
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62 dprintf("m68k stopwatch timer read");
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67 // comm flag/cmd/status (0xE-0x2F)
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68 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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72 dprintf("m68k_regs invalid read @ %02x", a);
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76 // dprintf("ret = %04x", d);
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80 static void m68k_reg_write8(u32 a, u32 d)
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83 // dprintf("m68k_regs w%2i: [%02x] %02x @%06x", realsize, a, d, SekPc);
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88 if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { dprintf("m68k: s68k irq 2"); SekInterruptS68k(2); }
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92 if (!(d&1)) Pico_mcd->m.state_flags |= 1; // reset pending, needed to be sure we fetch the right vectors on reset
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93 if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));
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94 if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);
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95 if ((Pico_mcd->m.state_flags&1) && (d&3)==1) {
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96 SekResetS68k(); // S68k comes out of RESET or BRQ state
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97 Pico_mcd->m.state_flags&=~1;
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98 dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);
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100 Pico_mcd->m.busreq = d;
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103 Pico_mcd->s68k_regs[2] = d; // really use s68k side register
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106 dprintf("m68k_regs w3: %02x @%06x", (u8)d, SekPc);
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108 if ((Pico_mcd->s68k_regs[3]>>6) != ((d>>6)&3))
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109 dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));
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110 //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);
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111 //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :
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112 // ((d&2) ? "word ram to s68k" : "word ram to m68k"));
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113 d |= Pico_mcd->s68k_regs[3]&0x1d;
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114 if (!(d & 4) && (d & 2)) d &= ~1; // return word RAM to s68k in 2M mode
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115 Pico_mcd->s68k_regs[3] = d; // really use s68k side register
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118 *((char *)&Pico_mcd->m.hint_vector+1) = d;
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119 Pico_mcd->bios[0x72 + 1] = d; // simple hint vector changer
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122 *(char *)&Pico_mcd->m.hint_vector = d;
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123 Pico_mcd->bios[0x72] = d;
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126 //dprintf("m68k: comm flag: %02x", d);
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128 //dprintf("s68k @ %06x", SekPcS68k);
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130 Pico_mcd->s68k_regs[0xe] = d;
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134 if ((a&0xf0) == 0x10) {
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135 Pico_mcd->s68k_regs[a] = d;
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139 dprintf("m68k: invalid write? [%02x] %02x", a, d);
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144 static u32 s68k_reg_read16(u32 a)
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148 // dprintf("s68k_regs r%2i: [%02x] @ %06x", realsize&~1, a+(realsize&1), SekPcS68k);
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152 d = ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state
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155 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0x1f);
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156 dprintf("s68k_regs r3: %02x @%06x", (u8)d, SekPc);
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159 d = CDC_Read_Reg();
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162 d = Read_CDC_Host(1); // Gens returns 0 here on byte reads
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165 dprintf("s68k stopwatch timer read");
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168 dprintf("s68k int3 timer read");
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170 case 0x34: // fader
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171 d = 0; // no busy bit
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175 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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179 // dprintf("ret = %04x", d);
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184 static void s68k_reg_write8(u32 a, u32 d)
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186 //dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);
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188 // TODO: review against Gens
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191 return; // only m68k can change WP
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193 dprintf("s68k_regs w3: %02x @%06x", (u8)d, SekPc);
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196 d |= Pico_mcd->s68k_regs[3]&0xc2;
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197 if ((d ^ Pico_mcd->s68k_regs[3]) & 5) d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit
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199 d |= Pico_mcd->s68k_regs[3]&0xc3;
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200 if (d&1) d &= ~2; // return word RAM to m68k in 2M mode
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204 dprintf("s68k CDC dest: %x", d&7);
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205 Pico_mcd->s68k_regs[4] = (Pico_mcd->s68k_regs[4]&0xC0) | (d&7); // CDC mode
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208 //dprintf("s68k CDC reg addr: %x", d&0xf);
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214 dprintf("s68k set CDC dma addr");
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217 dprintf("s68k set stopwatch timer");
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220 dprintf("s68k set int3 timer");
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222 case 0x33: // IRQ mask
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223 dprintf("s68k irq mask: %02x", d);
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224 if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {
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225 CDD_Export_Status();
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228 case 0x34: // fader
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229 Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;
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232 return; // d/m bit is unsetable
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234 u32 d_old = Pico_mcd->s68k_regs[0x37];
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235 Pico_mcd->s68k_regs[0x37] = d&7;
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236 if ((d&4) && !(d_old&4)) {
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237 CDD_Export_Status();
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242 Pico_mcd->s68k_regs[a] = (u8) d;
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243 CDD_Import_Command();
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247 if ((a&0x1f0) == 0x10 || a == 0x0e || (a >= 0x38 && a < 0x42))
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249 dprintf("m68k: invalid write @ %02x?", a);
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253 Pico_mcd->s68k_regs[a] = (u8) d;
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260 static int PadRead(int i)
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262 int pad=0,value=0,TH;
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263 pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU
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264 TH=Pico.ioports[i+1]&0x40;
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266 if(PicoOpt & 0x20) { // 6 button gamepad enabled
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267 int phase = Pico.m.padTHPhase[i];
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269 if(phase == 2 && !TH) {
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270 value=(pad&0xc0)>>2; // ?0SA 0000
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272 } else if(phase == 3 && TH) {
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273 value=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ
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275 } else if(phase == 3 && !TH) {
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276 value=((pad&0xc0)>>2)|0x0f; // ?0SA 1111
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281 if(TH) value=(pad&0x3f); // ?1CB RLDU
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282 else value=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU
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286 // orr the bits, which are set as output
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287 value |= Pico.ioports[i+1]&Pico.ioports[i+4];
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289 return value; // will mirror later
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292 static u8 z80Read8(u32 a)
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294 if(Pico.m.z80Run&1) return 0;
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299 // Z80 disabled, do some faking
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300 static u8 zerosent = 0;
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301 if(a == Pico.m.z80_lastaddr) { // probably polling something
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302 u8 d = Pico.m.z80_fakeval;
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303 if((d & 0xf) == 0xf && !zerosent) {
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304 d = 0; zerosent = 1;
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306 Pico.m.z80_fakeval++;
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311 Pico.m.z80_fakeval = 0;
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315 Pico.m.z80_lastaddr = (u16) a;
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316 return Pico.zram[a];
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320 // for nonstandard reads
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321 static u32 UnusualRead16(u32 a, int realsize)
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325 dprintf("unusual r%i: %06x @%06x", realsize&~1, (a&0xfffffe)+(realsize&1), SekPc);
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328 dprintf("ret = %04x", d);
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332 static u32 OtherRead16(u32 a, int realsize)
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336 if ((a&0xff0000)==0xa00000) {
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337 if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)
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338 if ((a&0x6000)==0x4000) { if(PicoOpt&1) d=YM2612Read(); else d=Pico.m.rotate++&3; goto end; } // 0x4000-0x5fff, Fudge if disabled
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339 d=0xffff; goto end;
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341 if ((a&0xffffe0)==0xa10000) { // I/O ports
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344 case 0: d=Pico.m.hardware; break; // Hardware value (Version register)
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345 case 1: d=PadRead(0); d|=Pico.ioports[1]&0x80; break;
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346 case 2: d=PadRead(1); d|=Pico.ioports[2]&0x80; break;
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347 default: d=Pico.ioports[a]; break; // IO ports can be used as RAM
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352 // |=0x80 for Shadow of the Beast & Super Offroad; rotate fakes next fetched instruction for Time Killers
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353 if (a==0xa11100) { d=((Pico.m.z80Run&1)<<8)|0x8000|Pico.m.rotate++; goto end; }
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355 if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; }
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357 if ((a&0xffffc0)==0xa12000) {
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358 d=m68k_reg_read16(a);
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362 d = UnusualRead16(a, realsize);
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368 //extern UINT32 mz80GetRegisterValue(void *, UINT32);
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370 static void OtherWrite8(u32 a,u32 d,int realsize)
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372 if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
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373 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram
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374 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound
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375 if ((a&0xffffe0)==0xa10000) { // I/O ports
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377 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
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380 Pico.m.padDelay[0] = 0;
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381 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
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384 Pico.m.padDelay[1] = 0;
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385 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
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388 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
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392 extern int z80startCycle, z80stopCycle;
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393 //int lineCycles=(488-SekCyclesLeft)&0x1ff;
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396 // hack: detect a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)
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397 if((PicoOpt&4) && Pico.m.z80Run==1) z80_run(20);
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398 z80stopCycle = SekCyclesDone();
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399 //z80ExtraCycles += (lineCycles>>1)-(lineCycles>>5); // only meaningful in PicoFrameHints()
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401 z80startCycle = SekCyclesDone();
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402 //if(Pico.m.scanline != -1)
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403 //z80ExtraCycles -= (lineCycles>>1)-(lineCycles>>5)+16;
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405 //dprintf("set_zrun: %i [%i|%i] zPC=%04x @%06x", d, Pico.m.scanline, SekCyclesDone(), mz80GetRegisterValue(NULL, 0), SekPc);
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406 Pico.m.z80Run=(u8)d; return;
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408 if (a==0xa11200) { if(!(d&1)) z80_reset(); return; }
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410 if ((a&0xff7f00)==0xa06000) // Z80 BANK register
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412 Pico.m.z80_bank68k>>=1;
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413 Pico.m.z80_bank68k|=(d&1)<<8;
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414 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
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418 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)(d|(d<<8))); return; } // Byte access gets mirrored
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420 if ((a&0xffffc0)==0xa12000) { m68k_reg_write8(a, d); return; }
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422 dprintf("strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);
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425 static void OtherWrite16(u32 a,u32 d)
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427 if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; }
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428 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)
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430 if ((a&0xffffe0)==0xa10000) { // I/O ports
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432 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
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435 Pico.m.padDelay[0] = 0;
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436 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
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439 Pico.m.padDelay[1] = 0;
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440 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
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443 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
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446 if (a==0xa11100) { OtherWrite8(a, d>>8, 16); return; }
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447 if (a==0xa11200) { if(!(d&0x100)) z80_reset(); return; }
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449 OtherWrite8(a, d>>8, 16);
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450 OtherWrite8(a+1,d&0xff, 16);
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453 // -----------------------------------------------------------------
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454 // Read Rom and read Ram
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456 u8 PicoReadM68k8(u32 a)
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460 if ((a&0xe00000)==0xe00000) { d = *(u8 *)(Pico.ram+((a^1)&0xffff)); goto end; } // Ram
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464 if (a < 0x20000) { d = *(u8 *)(Pico_mcd->bios+(a^1)); goto end; } // bios
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467 if ((a&0xfe0000)==0x020000) {
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468 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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469 d = *(prg_bank+((a^1)&0x1ffff));
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474 if (a == 0x200000 && SekPc == 0xff0b66 && Pico.m.frame_count > 1000)
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478 unsigned short *ram = (unsigned short *) Pico.ram;
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479 // unswap and dump RAM
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480 for (i = 0; i < 0x10000/2; i++)
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481 ram[i] = (ram[i]>>8) | (ram[i]<<8);
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482 ff = fopen("ram.bin", "wb");
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483 fwrite(ram, 1, 0x10000, ff);
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490 if ((a&0xfc0000)==0x200000) {
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491 dprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);
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492 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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493 if (a >= 0x220000) {
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496 a=((a&0x1fffe)<<1)|(a&1);
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497 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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498 d = Pico_mcd->word_ram[a^1];
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501 // allow access in any mode, like Gens does
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502 d = Pico_mcd->word_ram[(a^1)&0x3ffff];
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504 dprintf("ret = %02x", (u8)d);
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508 if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram
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510 if ((a&0xffffc0)==0xa12000)
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511 rdprintf("m68k_regs r8: [%02x] @%06x", a&0x3f, SekPc);
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513 d=OtherRead16(a&~1, 8|(a&1)); if ((a&1)==0) d>>=8;
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515 if ((a&0xffffc0)==0xa12000)
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516 rdprintf("ret = %02x", (u8)d);
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521 dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);
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527 u16 PicoReadM68k16(u32 a)
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531 if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram
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535 if (a < 0x20000) { d = *(u16 *)(Pico_mcd->bios+a); goto end; } // bios
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538 if ((a&0xfe0000)==0x020000) {
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539 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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540 d = *(u16 *)(prg_bank+(a&0x1fffe));
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545 if ((a&0xfc0000)==0x200000) {
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546 dprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);
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547 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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548 if (a >= 0x220000) {
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551 a=((a&0x1fffe)<<1);
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552 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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553 d = *(u16 *)(Pico_mcd->word_ram+a);
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556 // allow access in any mode, like Gens does
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557 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
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559 dprintf("ret = %04x", d);
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563 if ((a&0xffffc0)==0xa12000)
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564 rdprintf("m68k_regs r16: [%02x] @%06x", a&0x3f, SekPc);
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566 d = (u16)OtherRead16(a, 16);
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568 if ((a&0xffffc0)==0xa12000)
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569 rdprintf("ret = %04x", d);
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574 dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
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580 u32 PicoReadM68k32(u32 a)
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584 if ((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); d = (pm[0]<<16)|pm[1]; goto end; } // Ram
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588 if (a < 0x20000) { u16 *pm=(u16 *)(Pico_mcd->bios+a); d = (pm[0]<<16)|pm[1]; goto end; } // bios
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591 if ((a&0xfe0000)==0x020000) {
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592 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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593 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
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594 d = (pm[0]<<16)|pm[1];
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599 if ((a&0xfc0000)==0x200000) {
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600 dprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);
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601 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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602 if (a >= 0x220000) {
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605 a=((a&0x1fffe)<<1);
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606 if (Pico_mcd->s68k_regs[3]&1) a+=2;
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607 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;
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608 d |= *(u16 *)(Pico_mcd->word_ram+a+4);
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611 // allow access in any mode, like Gens does
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612 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
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614 dprintf("ret = %08x", d);
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618 if ((a&0xffffc0)==0xa12000)
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619 rdprintf("m68k_regs r32: [%02x] @%06x", a&0x3f, SekPc);
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621 d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);
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623 if ((a&0xffffc0)==0xa12000)
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624 rdprintf("ret = %08x", d);
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628 dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);
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634 // -----------------------------------------------------------------
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637 void PicoWriteM68k8(u32 a,u8 d)
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640 dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
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642 //if ((a&0xe0ffff)==0xe0a9ba+0x69c)
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643 // dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
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646 if ((a&0xe00000)==0xe00000) { // Ram
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647 *(u8 *)(Pico.ram+((a^1)&0xffff)) = d;
\r
654 if ((a&0xfe0000)==0x020000) {
\r
655 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
656 *(u8 *)(prg_bank+((a^1)&0x1ffff))=d;
\r
661 if ((a&0xfc0000)==0x200000) {
\r
662 dprintf("m68k_wram w8: [%06x] %02x @%06x", a, d, SekPc);
\r
663 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
664 if (a >= 0x220000) {
\r
667 a=((a&0x1fffe)<<1)|(a&1);
\r
668 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
669 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;
\r
672 // allow access in any mode, like Gens does
\r
673 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;
\r
678 if ((a&0xffffc0)==0xa12000)
\r
679 rdprintf("m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);
\r
681 OtherWrite8(a,d,8);
\r
685 void PicoWriteM68k16(u32 a,u16 d)
\r
688 dprintf("w16: %06x, %04x", a&0xffffff, d);
\r
690 // dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
\r
692 if ((a&0xe00000)==0xe00000) { // Ram
\r
693 *(u16 *)(Pico.ram+(a&0xfffe))=d;
\r
700 if ((a&0xfe0000)==0x020000) {
\r
701 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
702 *(u16 *)(prg_bank+(a&0x1fffe))=d;
\r
707 if ((a&0xfc0000)==0x200000) {
\r
708 dprintf("m68k_wram w16: [%06x] %04x @%06x", a, d, SekPc);
\r
709 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
710 if (a >= 0x220000) {
\r
713 a=((a&0x1fffe)<<1);
\r
714 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
715 *(u16 *)(Pico_mcd->word_ram+a)=d;
\r
718 // allow access in any mode, like Gens does
\r
719 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;
\r
724 if ((a&0xffffc0)==0xa12000)
\r
725 rdprintf("m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);
\r
731 void PicoWriteM68k32(u32 a,u32 d)
\r
734 dprintf("w32: %06x, %08x", a&0xffffff, d);
\r
737 if ((a&0xe00000)==0xe00000)
\r
740 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));
\r
741 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
748 if ((a&0xfe0000)==0x020000) {
\r
749 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
750 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
\r
751 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
756 if ((a&0xfc0000)==0x200000) {
\r
757 if (d != 0) // don't log clears
\r
758 dprintf("m68k_wram w32: [%06x] %08x @%06x", a, d, SekPc);
\r
759 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
760 if (a >= 0x220000) {
\r
763 a=((a&0x1fffe)<<1);
\r
764 if (Pico_mcd->s68k_regs[3]&1) a+=2;
\r
765 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;
\r
766 *(u16 *)(Pico_mcd->word_ram+a+4) = d;
\r
769 // allow access in any mode, like Gens does
\r
770 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
771 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
776 if ((a&0xffffc0)==0xa12000)
\r
777 rdprintf("m68k_regs w32: [%02x] %08x @%06x", a&0x3f, d, SekPc);
\r
779 OtherWrite16(a, (u16)(d>>16));
\r
780 OtherWrite16(a+2,(u16)d);
\r
784 // -----------------------------------------------------------------
\r
787 u8 PicoReadS68k8(u32 a)
\r
795 d = *(Pico_mcd->prg_ram+(a^1));
\r
800 if ((a&0xfffe00) == 0xff8000) {
\r
802 rdprintf("s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);
\r
803 if (a >= 0x50 && a < 0x68)
\r
804 d = gfx_cd_read(a&~1);
\r
805 else d = s68k_reg_read16(a&~1);
\r
806 if ((a&1)==0) d>>=8;
\r
807 rdprintf("ret = %02x", (u8)d);
\r
811 // word RAM (2M area)
\r
812 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
813 dprintf("s68k_wram2M r8: [%06x] @%06x", a, SekPc);
\r
814 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
816 dprintf("(decode)");
\r
818 // allow access in any mode, like Gens does
\r
819 d = Pico_mcd->word_ram[(a^1)&0x3ffff];
\r
821 dprintf("ret = %02x", (u8)d);
\r
825 // word RAM (1M area)
\r
826 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
827 dprintf("s68k_wram1M r8: [%06x] @%06x", a, SekPc);
\r
828 a=((a&0x1fffe)<<1)|(a&1);
\r
829 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
830 d = Pico_mcd->word_ram[a^1];
\r
831 dprintf("ret = %02x", (u8)d);
\r
836 if ((a&0xff0000)==0xfe0000) {
\r
837 d = Pico_mcd->bram[(a>>1)&0x1fff];
\r
841 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
846 dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
852 u16 PicoReadS68k16(u32 a)
\r
860 d = *(u16 *)(Pico_mcd->prg_ram+a);
\r
865 if ((a&0xfffe00) == 0xff8000) {
\r
867 rdprintf("s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);
\r
868 if (a >= 0x50 && a < 0x68)
\r
869 d = gfx_cd_read(a);
\r
870 else d = s68k_reg_read16(a);
\r
871 rdprintf("ret = %04x", d);
\r
875 // word RAM (2M area)
\r
876 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
877 dprintf("s68k_wram2M r16: [%06x] @%06x", a, SekPc);
\r
878 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
880 dprintf("(decode)");
\r
882 // allow access in any mode, like Gens does
\r
883 d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
885 dprintf("ret = %04x", d);
\r
889 // word RAM (1M area)
\r
890 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
891 dprintf("s68k_wram1M r16: [%06x] @%06x", a, SekPc);
\r
892 a=((a&0x1fffe)<<1);
\r
893 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
894 d = *(u16 *)(Pico_mcd->word_ram+a);
\r
895 dprintf("ret = %04x", d);
\r
900 if ((a&0xff0000)==0xfe0000) {
\r
901 dprintf("s68k_bram r16: [%06x] @%06x", a, SekPc);
\r
903 d = Pico_mcd->bram[a++]; // Gens does little endian here, an so do we..
\r
904 d|= Pico_mcd->bram[a++] << 8;
\r
905 dprintf("ret = %04x", d);
\r
909 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
914 dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
920 u32 PicoReadS68k32(u32 a)
\r
928 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
929 d = (pm[0]<<16)|pm[1];
\r
934 if ((a&0xfffe00) == 0xff8000) {
\r
936 rdprintf("s68k_regs r32: [%02x] @ %06x", a, SekPcS68k);
\r
937 if (a >= 0x50 && a < 0x68)
\r
938 d = (gfx_cd_read(a)<<16)|gfx_cd_read(a+2);
\r
939 else d = (s68k_reg_read16(a)<<16)|s68k_reg_read16(a+2);
\r
940 rdprintf("ret = %08x", d);
\r
944 // word RAM (2M area)
\r
945 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
946 dprintf("s68k_wram2M r32: [%06x] @%06x", a, SekPc);
\r
947 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
949 dprintf("(decode)");
\r
951 // allow access in any mode, like Gens does
\r
952 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
\r
954 dprintf("ret = %08x", d);
\r
958 // word RAM (1M area)
\r
959 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
960 dprintf("s68k_wram1M r32: [%06x] @%06x", a, SekPc);
\r
961 a=((a&0x1fffe)<<1);
\r
962 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
963 d = *(u16 *)(Pico_mcd->word_ram+a) << 16;
\r
964 d |= *(u16 *)(Pico_mcd->word_ram+a+4);
\r
965 dprintf("ret = %08x", d);
\r
970 if ((a&0xff0000)==0xfe0000) {
\r
971 dprintf("s68k_bram r32: [%06x] @%06x", a, SekPc);
\r
973 d = Pico_mcd->bram[a++] << 16; // middle endian? TODO: verify against Fusion..
\r
974 d|= Pico_mcd->bram[a++] << 24;
\r
975 d|= Pico_mcd->bram[a++];
\r
976 d|= Pico_mcd->bram[a++] << 8;
\r
977 dprintf("ret = %08x", d);
\r
981 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
986 dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
992 // -----------------------------------------------------------------
\r
994 void PicoWriteS68k8(u32 a,u8 d)
\r
997 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1003 if (a < 0x80000) {
\r
1004 u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));
\r
1009 if (a != 0xff0011 && (a&0xff8000) == 0xff0000) // PCM hack
\r
1013 if ((a&0xfffe00) == 0xff8000) {
\r
1015 rdprintf("s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);
\r
1016 if (a >= 0x50 && a < 0x68)
\r
1017 gfx_cd_write(a&~1, (d<<8)|d);
\r
1018 else s68k_reg_write8(a,d);
\r
1022 // word RAM (2M area)
\r
1023 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1024 dprintf("s68k_wram2M w8: [%06x] %02x @%06x", a, d, SekPc);
\r
1025 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1027 dprintf("(decode)");
\r
1029 // allow access in any mode, like Gens does
\r
1030 *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;
\r
1035 // word RAM (1M area)
\r
1036 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1038 dprintf("s68k_wram1M w8: [%06x] %02x @%06x", a, d, SekPc);
\r
1039 a=((a&0x1fffe)<<1)|(a&1);
\r
1040 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1041 *(u8 *)(Pico_mcd->word_ram+(a^1))=d;
\r
1046 if ((a&0xff0000)==0xfe0000) {
\r
1047 Pico_mcd->bram[(a>>1)&0x1fff] = d;
\r
1052 dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1056 void PicoWriteS68k16(u32 a,u16 d)
\r
1058 #ifdef __debug_io2
\r
1059 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1065 if (a < 0x80000) {
\r
1066 *(u16 *)(Pico_mcd->prg_ram+a)=d;
\r
1071 if ((a&0xfffe00) == 0xff8000) {
\r
1073 rdprintf("s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);
\r
1074 if (a >= 0x50 && a < 0x68)
\r
1075 gfx_cd_write(a, d);
\r
1077 s68k_reg_write8(a, d>>8);
\r
1078 s68k_reg_write8(a+1,d&0xff);
\r
1083 // word RAM (2M area)
\r
1084 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1085 dprintf("s68k_wram2M w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1086 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1088 dprintf("(decode)");
\r
1090 // allow access in any mode, like Gens does
\r
1091 *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;
\r
1096 // word RAM (1M area)
\r
1097 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1099 dprintf("s68k_wram1M w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1100 a=((a&0x1fffe)<<1);
\r
1101 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1102 *(u16 *)(Pico_mcd->word_ram+a)=d;
\r
1107 if ((a&0xff0000)==0xfe0000) {
\r
1108 dprintf("s68k_bram w16: [%06x] %04x @%06x", a, d, SekPc);
\r
1109 a = (a>>1)&0x1fff;
\r
1110 Pico_mcd->bram[a++] = d; // Gens does little endian here, an so do we..
\r
1111 Pico_mcd->bram[a++] = d >> 8;
\r
1116 dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1120 void PicoWriteS68k32(u32 a,u32 d)
\r
1122 #ifdef __debug_io2
\r
1123 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1129 if (a < 0x80000) {
\r
1130 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
1131 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1136 if ((a&0xfffe00) == 0xff8000) {
\r
1138 rdprintf("s68k_regs w32: [%02x] %08x @ %06x", a, d, SekPcS68k);
\r
1139 if (a >= 0x50 && a < 0x68) {
\r
1140 gfx_cd_write(a, d>>16);
\r
1141 gfx_cd_write(a+2, d&0xffff);
\r
1143 s68k_reg_write8(a, d>>24);
\r
1144 s68k_reg_write8(a+1,(d>>16)&0xff);
\r
1145 s68k_reg_write8(a+2,(d>>8) &0xff);
\r
1146 s68k_reg_write8(a+3, d &0xff);
\r
1151 // word RAM (2M area)
\r
1152 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1153 dprintf("s68k_wram2M w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1154 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
1156 dprintf("(decode)");
\r
1158 // allow access in any mode, like Gens does
\r
1159 u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
\r
1160 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1165 // word RAM (1M area)
\r
1166 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1168 dprintf("s68k_wram1M w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1169 a=((a&0x1fffe)<<1);
\r
1170 if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;
\r
1171 *(u16 *)(Pico_mcd->word_ram+a) = d>>16;
\r
1172 *(u16 *)(Pico_mcd->word_ram+a+4) = d;
\r
1177 if ((a&0xff0000)==0xfe0000) {
\r
1178 dprintf("s68k_bram w32: [%06x] %08x @%06x", a, d, SekPc);
\r
1179 a = (a>>1)&0x1fff;
\r
1180 Pico_mcd->bram[a++] = d >> 16; // middle endian? verify?
\r
1181 Pico_mcd->bram[a++] = d >> 24;
\r
1182 Pico_mcd->bram[a++] = d;
\r
1183 Pico_mcd->bram[a++] = d >> 8;
\r
1188 dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1193 // -----------------------------------------------------------------
\r
1196 #if defined(EMU_C68K)
\r
1197 static __inline int PicoMemBaseM68k(u32 pc)
\r
1203 membase=(int)Pico_mcd->bios; // Program Counter in BIOS
\r
1205 else if ((pc&0xe00000)==0xe00000)
\r
1207 membase=(int)Pico.ram-(pc&0xff0000); // Program Counter in Ram
\r
1209 else if ((pc&0xfc0000)==0x200000 && !(Pico_mcd->s68k_regs[3]&4))
\r
1211 membase=(int)Pico_mcd->word_ram-0x200000; // Program Counter in Word Ram
\r
1215 // Error - Program Counter is invalid
\r
1216 dprintf("m68k: unhandled jump to %06x", pc);
\r
1217 membase=(int)Pico.rom;
\r
1224 static u32 PicoCheckPcM68k(u32 pc)
\r
1226 pc-=PicoCpu.membase; // Get real pc
\r
1229 PicoCpu.membase=PicoMemBaseM68k(pc);
\r
1231 return PicoCpu.membase+pc;
\r
1235 static __inline int PicoMemBaseS68k(u32 pc)
\r
1239 membase=(int)Pico_mcd->prg_ram; // Program Counter in Prg RAM
\r
1240 if (pc >= 0x80000)
\r
1242 // Error - Program Counter is invalid
\r
1243 dprintf("s68k: unhandled jump to %06x", pc);
\r
1250 static u32 PicoCheckPcS68k(u32 pc)
\r
1252 pc-=PicoCpuS68k.membase; // Get real pc
\r
1255 PicoCpuS68k.membase=PicoMemBaseS68k(pc);
\r
1257 return PicoCpuS68k.membase+pc;
\r
1262 void PicoMemSetupCD()
\r
1264 dprintf("PicoMemSetupCD()");
\r
1266 // Setup m68k memory callbacks:
\r
1267 PicoCpu.checkpc=PicoCheckPcM68k;
\r
1268 PicoCpu.fetch8 =PicoCpu.read8 =PicoReadM68k8;
\r
1269 PicoCpu.fetch16=PicoCpu.read16=PicoReadM68k16;
\r
1270 PicoCpu.fetch32=PicoCpu.read32=PicoReadM68k32;
\r
1271 PicoCpu.write8 =PicoWriteM68k8;
\r
1272 PicoCpu.write16=PicoWriteM68k16;
\r
1273 PicoCpu.write32=PicoWriteM68k32;
\r
1275 PicoCpuS68k.checkpc=PicoCheckPcS68k;
\r
1276 PicoCpuS68k.fetch8 =PicoCpuS68k.read8 =PicoReadS68k8;
\r
1277 PicoCpuS68k.fetch16=PicoCpuS68k.read16=PicoReadS68k16;
\r
1278 PicoCpuS68k.fetch32=PicoCpuS68k.read32=PicoReadS68k32;
\r
1279 PicoCpuS68k.write8 =PicoWriteS68k8;
\r
1280 PicoCpuS68k.write16=PicoWriteS68k16;
\r
1281 PicoCpuS68k.write32=PicoWriteS68k32;
\r
1287 unsigned char PicoReadCD8w (unsigned int a) {
\r
1288 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k8(a) : PicoReadM68k8(a);
\r
1290 unsigned short PicoReadCD16w(unsigned int a) {
\r
1291 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k16(a) : PicoReadM68k16(a);
\r
1293 unsigned int PicoReadCD32w(unsigned int a) {
\r
1294 return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k32(a) : PicoReadM68k32(a);
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1296 void PicoWriteCD8w (unsigned int a, unsigned char d) {
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1297 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k8(a, d); else PicoWriteM68k8(a, d);
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1299 void PicoWriteCD16w(unsigned int a, unsigned short d) {
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1300 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k16(a, d); else PicoWriteM68k16(a, d);
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1302 void PicoWriteCD32w(unsigned int a, unsigned int d) {
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1303 if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k32(a, d); else PicoWriteM68k32(a, d);
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1306 // these are allowed to access RAM
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1307 unsigned int m68k_read_pcrelative_CD8 (unsigned int a) {
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1309 if(m68ki_cpu_p == &PicoS68kCPU) {
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1310 if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram
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1311 dprintf("s68k_read_pcrelative_CD8: can't handle %06x", a);
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1313 if(a<0x20000) return *(u8 *)(Pico.rom+(a^1)); // Bios
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1314 if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram
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1315 if(!(Pico_mcd->s68k_regs[3]&4) && (a&0xfc0000)==0x200000)
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1316 return Pico_mcd->word_ram[(a^1)&0x3fffe];
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1317 dprintf("m68k_read_pcrelative_CD8: can't handle %06x", a);
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1319 return 0;//(u8) lastread_d;
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1321 unsigned int m68k_read_pcrelative_CD16(unsigned int a) {
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1323 if(m68ki_cpu_p == &PicoS68kCPU) {
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1324 if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram
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1325 dprintf("s68k_read_pcrelative_CD16: can't handle %06x", a);
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1327 if(a<0x20000) return *(u16 *)(Pico.rom+(a&~1)); // Bios
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1328 if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram
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1329 if(!(Pico_mcd->s68k_regs[3]&4) && (a&0xfc0000)==0x200000)
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1330 return *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));
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1331 dprintf("m68k_read_pcrelative_CD16: can't handle %06x", a);
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1335 unsigned int m68k_read_pcrelative_CD32(unsigned int a) {
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1337 if(m68ki_cpu_p == &PicoS68kCPU) {
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1338 if (a < 0x80000) { u16 *pm=(u16 *)(Pico_mcd->prg_ram+(a&~1)); return (pm[0]<<16)|pm[1]; } // PRG Ram
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1339 dprintf("s68k_read_pcrelative_CD32: can't handle %06x", a);
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1341 if(a<0x20000) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }
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1342 if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram
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1343 if(!(Pico_mcd->s68k_regs[3]&4) && (a&0xfc0000)==0x200000)
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1344 { u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }
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1345 dprintf("m68k_read_pcrelative_CD32: can't handle %06x", a);
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1349 #endif // EMU_M68K
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