3 @ Memory I/O handlers for Sega/Mega CD emulation
4 @ (c) Copyright 2007, Grazvydas "notaz" Ignotas
8 .equiv PCM_STEP_SHIFT, 11
16 .macro mk_m68k_jump_table on sz @ operation name, size
17 .long m_m68k_&\on&\sz&_bios @ 0x000000 - 0x01ffff
18 .long m_m68k_&\on&\sz&_prgbank @ 0x020000 - 0x03ffff
19 .long m_&\on&_null, m_&\on&_null @ 0x040000 - 0x07ffff
20 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x080000 - 0x0fffff
21 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x100000 - 0x17ffff
22 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x180000 - 0x1fffff
23 .long m_m68k_&\on&\sz&_wordram0_2M @ 0x200000 - 0x21ffff
24 .long m_m68k_&\on&\sz&_wordram1_2M @ 0x220000 - 0x23ffff
25 .long m_&\on&_null, m_&\on&_null @ 0x240000 - 0x27ffff
26 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x280000 - 0x2fffff
27 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x300000
28 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x3fffff
29 .long m_m68k_&\on&\sz&_bcram_size @ 0x400000
30 .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x420000
31 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x4fffff
32 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x500000
33 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x5fffff
34 .long m_m68k_&\on&\sz&_bcram @ 0x600000
35 .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x620000
36 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x6fffff
37 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x700000
38 .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x7dffff
39 .long m_m68k_&\on&\sz&_bcram_reg @ 0x7e0000
40 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x800000
41 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x8fffff
42 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x900000
43 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x9fffff
44 .long m_m68k_&\on&\sz&_system_io @ 0xa00000 - 0xa1ffff
45 .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xa20000 - 0xa7ffff
46 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xa80000 - 0xafffff
47 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xb00000
48 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0xbfffff
49 .long m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp @ 0xc00000
50 .long m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp @ - 0xcfffff
51 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xd00000
52 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0xdfffff
53 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ 0xe00000
54 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ - 0xefffff
55 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ 0xf00000
56 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ - 0xffffff
59 .macro mk_s68k_jump_table on sz @ operation name, size
60 .long m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg @ 0x000000 - 0x07ffff
61 .long m_s68k_&\on&\sz&_wordram_2M @ 0x080000 - 0x09ffff
62 .long m_s68k_&\on&\sz&_wordram_2M @ 0x0a0000 - 0x0bffff
63 .long m_&\on&_null @ 0x0c0000 - 0x0dffff, 1M area
64 .long m_&\on&_null @ 0x0e0000 - 0x0fffff
68 @ the jumptables themselves.
69 m_m68k_read8_table: mk_m68k_jump_table read 8
70 m_m68k_read16_table: mk_m68k_jump_table read 16
71 m_m68k_read32_table: mk_m68k_jump_table read 32
72 m_m68k_write8_table: mk_m68k_jump_table write 8
73 m_m68k_write16_table: mk_m68k_jump_table write 16
74 m_m68k_write32_table: mk_m68k_jump_table write 32
76 m_s68k_read8_table: mk_s68k_jump_table read 8
77 m_s68k_read16_table: mk_s68k_jump_table read 16
78 m_s68k_read32_table: mk_s68k_jump_table read 32
79 m_s68k_write8_table: mk_s68k_jump_table write 8
80 m_s68k_write16_table: mk_s68k_jump_table write 16
81 m_s68k_write32_table: mk_s68k_jump_table write 32
83 m_s68k_decode_write_table:
84 .long m_s68k_write8_2M_decode_b0_m0
85 .long m_s68k_write16_2M_decode_b0_m0
86 .long m_s68k_write32_2M_decode_b0_m0
87 .long m_s68k_write8_2M_decode_b0_m1
88 .long m_s68k_write16_2M_decode_b0_m1
89 .long m_s68k_write32_2M_decode_b0_m1
90 .long m_s68k_write8_2M_decode_b0_m2
91 .long m_s68k_write16_2M_decode_b0_m2
92 .long m_s68k_write32_2M_decode_b0_m2
93 .long m_s68k_write8_2M_decode_b1_m0
94 .long m_s68k_write16_2M_decode_b1_m0
95 .long m_s68k_write32_2M_decode_b1_m0
96 .long m_s68k_write8_2M_decode_b1_m1
97 .long m_s68k_write16_2M_decode_b1_m1
98 .long m_s68k_write32_2M_decode_b1_m1
99 .long m_s68k_write8_2M_decode_b1_m2
100 .long m_s68k_write16_2M_decode_b1_m2
101 .long m_s68k_write32_2M_decode_b1_m2
104 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
109 .global PicoMemResetCD
110 .global PicoMemResetCDdecode
111 .global PicoReadM68k8
112 .global PicoReadM68k16
113 .global PicoReadM68k32
114 .global PicoWriteM68k8
115 .global PicoWriteM68k16
116 .global PicoWriteM68k32
117 .global PicoReadS68k8
118 .global PicoReadS68k16
119 .global PicoReadS68k32
120 .global PicoWriteS68k8
121 .global PicoWriteS68k16
122 .global PicoWriteS68k32
124 @ externs, just for reference
128 .extern PicoVideoRead
129 .extern PicoVideoRead8
130 .extern Read_CDC_Host
131 .extern m68k_reg_write8
134 .extern s68k_reg_read16
136 .extern gfx_cd_write16
137 .extern s68k_reg_write8
138 .extern s68k_poll_adclk
140 .extern s68k_poll_detect
142 .extern m_m68k_read8_misc
143 .extern m_m68k_write8_misc
146 @ r0=reg3, r1-r3=temp
147 .macro mk_update_table on sz @ operation name, size
148 @ we only set word-ram handlers
149 ldr r1, =m_m68k_&\on&\sz&_table
150 ldr r12,=m_s68k_&\on&\sz&_table
155 ldr r2, =m_m68k_&\on&\sz&_wordram0_2M
156 ldr r3, =m_s68k_&\on&\sz&_wordram_2M
159 ldr r2, =m_&\on&_null
170 ldr r2, =m_m68k_&\on&\sz&_wordram0_1M_b0
171 ldr r3, =m_m68k_&\on&\sz&_wordram1_1M_b0
174 ldr r3, =m_s68k_&\on&\sz&_wordram_1M_b1
176 ldr r2, =m_s68k_&\on&\sz&_wordram_2M_decode_b1
184 ldr r2, =m_m68k_&\on&\sz&_wordram0_1M_b1
185 ldr r3, =m_m68k_&\on&\sz&_wordram1_1M_b1
188 ldr r3, =m_s68k_&\on&\sz&_wordram_1M_b0
190 ldr r2, =m_s68k_&\on&\sz&_wordram_2M_decode_b0
201 mk_update_table read 8
202 mk_update_table read 16
203 mk_update_table read 32
204 mk_update_table write 8
205 mk_update_table write 16
206 mk_update_table write 32
210 PicoMemResetCDdecode: @reg3
212 bxeq lr @ we should not be called in 2M mode
213 ldr r1, =m_s68k_write8_table
214 ldr r3, =m_s68k_decode_write_table
218 moveq r2, #2 @ mode3 is same as mode2?
220 addeq r2, r2, #3 @ bank1 (r2=0..5)
221 add r2, r2, r2, lsl #1 @ *= 3
222 add r2, r3, r2, lsl #2
223 ldmia r2, {r0,r3,r12}
226 str r3, [r1, #4*4+8*4]
227 str r3, [r1, #5*4+8*4]
228 str r12,[r1, #4*4+8*4*2]
229 str r12,[r1, #5*4+8*4*2]
235 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
237 .macro mk_entry_m68k table
239 bic r0, r0, #0xff000000
240 and r3, r0, #0x00fe0000
241 ldr pc, [r2, r3, lsr #15]
244 PicoReadM68k8: @ u32 a
245 mk_entry_m68k m_m68k_read8_table
247 PicoReadM68k16: @ u32 a
248 mk_entry_m68k m_m68k_read16_table
250 PicoReadM68k32: @ u32 a
251 mk_entry_m68k m_m68k_read32_table
253 PicoWriteM68k8: @ u32 a, u8 d
254 mk_entry_m68k m_m68k_write8_table
256 PicoWriteM68k16: @ u32 a, u16 d
257 mk_entry_m68k m_m68k_write16_table
259 PicoWriteM68k32: @ u32 a, u32 d
260 mk_entry_m68k m_m68k_write32_table
263 .macro mk_entry_s68k on sz
264 bic r0, r0, #0xff000000
266 blt m_s68k_&\on&\sz&_prg
268 ldrlt r2, =m_s68k_&\on&\sz&_table
269 andlt r3, r0, #0x000e0000
270 ldrlt pc, [r2, r3, lsr #15]
272 orr r3, r3, #0x00008000
274 bge m_s68k_&\on&\sz&_regs
276 bge m_s68k_&\on&\sz&_pcm
278 bge m_s68k_&\on&\sz&_backup
283 PicoReadS68k8: @ u32 a
286 PicoReadS68k16: @ u32 a
287 mk_entry_s68k read 16
289 PicoReadS68k32: @ u32 a
290 mk_entry_s68k read 32
292 PicoWriteS68k8: @ u32 a, u8 d
293 mk_entry_s68k write 8
295 PicoWriteS68k16: @ u32 a, u16 d
296 mk_entry_s68k write 16
298 PicoWriteS68k32: @ u32 a, u32 d
299 mk_entry_s68k write 32
304 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
308 @ r0=addr[in,out], r1,r2=tmp
310 ands r1, r0, #0x01c000
311 ldrne pc, [pc, r1, lsr #12]
312 beq 0f @ most common?
322 and r1, r0, #0x7e00 @ col
323 and r2, r0, #0x01fc @ row
325 orr r1, r2, r1, ror #13
328 and r1, r0, #0x3f00 @ col
329 and r2, r0, #0x00fc @ row
331 orr r1, r2, r1, ror #12
334 and r1, r0, #0x1f80 @ col
335 and r2, r0, #0x007c @ row
336 orr r1, r2, r1, ror #11
338 orr r1, r1, r2, lsr #6
341 and r1, r0, #0xfc00 @ col
342 and r2, r0, #0x03fc @ row
343 orr r1, r2, r1, ror #14
346 orr r0, r0, r1, ror #26 @ rol 4+2
350 @ r0=prt1, r1=ptr2; unaligned ptr MUST be r0
356 moveq r0, r0, ror #16
357 orrne r0, r1, r0, lsl #16
361 @ r0=prt1, r1=data, r2=ptr2; unaligned ptr MUST be r0
366 movne r1, r1, lsr #16
372 .macro bcram_reg_rw is_read addr_check
373 rsb r0, r0, #0x800000
374 ldr r2, =(Pico+0x22200)
375 cmp r0, #(0x800000-\addr_check)
381 add r2, r2, #0x110000
382 add r2, r2, #0x002200
384 ldrb r0, [r2, #0x18] @ Pico_mcd->m.bcram_reg
391 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
400 ldr r1, =(Pico+0x22200)
401 bic r0, r0, #0xfe0000
408 m_m68k_read8_prgbank:
409 ldr r1, =(Pico+0x22200)
413 orr r3, r2, #0x002200
416 and r3, r3, #0x00030000
417 cmp r3, #0x00010000 @ have bus or in reset state?
420 and r2, r2, #0xc0000000 @ r3 & 0xC0
421 add r1, r1, r2, lsr #12
426 m_m68k_read8_wordram0_2M: @ 0x200000 - 0x21ffff
427 m_m68k_read8_wordram1_2M: @ 0x220000 - 0x23ffff
428 ldr r1, =(Pico+0x22200)
429 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
436 m_m68k_read8_wordram0_1M_b0: @ 0x200000 - 0x21ffff
437 ldr r1, =(Pico+0x22200)
438 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
445 m_m68k_read8_wordram0_1M_b1: @ 0x200000 - 0x21ffff
446 ldr r1, =(Pico+0x22200)
447 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
454 m_m68k_read8_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
456 ldr r1, =(Pico+0x22200)
457 add r0, r0, #0x0c0000
464 m_m68k_read8_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
466 ldr r1, =(Pico+0x22200)
467 add r0, r0, #0x0e0000
474 m_m68k_read8_bcram_size: @ 0x400000
482 movne r0, #3 @ pretend to be a 64k cart (8<<3)
486 m_m68k_read8_bcram: @ 0x600000 - 0x61ffff
488 bic r0, r0, #0xfe0000
499 m_m68k_read8_bcram_reg: @ 0x7fffff
500 bcram_reg_rw 1, 0x7fffff
503 m_m68k_read8_system_io:
504 bic r2, r0, #0xfe0000
507 bne m_m68k_read8_misc @ now from Pico/Memory.s
509 ldr r1, =(Pico+0x22200)
511 ldr r1, [r1] @ Pico.mcd (used everywhere)
513 ldrlt pc, [pc, r0, lsl #2]
515 .long m_m68k_read8_r00
516 .long m_m68k_read8_r01
517 .long m_m68k_read8_r02
518 .long m_m68k_read8_r03
519 .long m_m68k_read8_r04
520 .long m_read_null @ unused bits
521 .long m_m68k_read8_r06
522 .long m_m68k_read8_r07
523 .long m_m68k_read8_r08
524 .long m_m68k_read8_r09
525 .long m_read_null @ reserved
527 .long m_m68k_read8_r0c
528 .long m_m68k_read8_r0d
530 add r1, r1, #0x110000
532 and r0, r0, #0x04000000 @ we need irq2 mask state
536 add r1, r1, #0x110000
537 add r1, r1, #0x002200
538 ldrb r0, [r1, #2] @ Pico_mcd->m.busreq
541 add r1, r1, #0x110000
545 add r1, r1, #0x110000
547 add r1, r1, #0x002200
550 tst r1, #2 @ DMNA pending?
556 add r1, r1, #0x110000
560 ldrb r0, [r1, #0x73] @ IRQ vector
567 bl Read_CDC_Host @ TODO: make it local
574 add r1, r1, #0x110000
575 add r1, r1, #0x002200
576 ldr r0, [r1, #0x14] @ Pico_mcd->m.timer_stopwatch
580 add r1, r1, #0x110000
581 add r1, r1, #0x002200
589 add r1, r1, #0x110000
597 cmp r2, #0xa00000 @ Z80 RAM?
599 @ ldreq r2, =z80Read8
604 bl OtherRead16 @ non-MCD version should be ok too
614 bxne lr @ invalid read
620 bic r0, r0, #0xff0000
626 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
630 ldr r1, =(Pico+0x22200)
631 bic r0, r0, #0xfe0000
638 m_m68k_read16_prgbank:
639 ldr r1, =(Pico+0x22200)
643 orr r3, r2, #0x002200
646 and r3, r3, #0x00030000
647 cmp r3, #0x00010000 @ have bus or in reset state?
650 and r2, r2, #0xc0000000 @ r3 & 0xC0
651 add r1, r1, r2, lsr #12
656 m_m68k_read16_wordram0_2M: @ 0x200000 - 0x21ffff
657 m_m68k_read16_wordram1_2M: @ 0x220000 - 0x23ffff
658 ldr r1, =(Pico+0x22200)
659 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
666 m_m68k_read16_wordram0_1M_b0: @ 0x200000 - 0x21ffff
667 ldr r1, =(Pico+0x22200)
668 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
675 m_m68k_read16_wordram0_1M_b1: @ 0x200000 - 0x21ffff
676 ldr r1, =(Pico+0x22200)
677 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
684 m_m68k_read16_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
685 @ Warning: read32 relies on NOT using r3 and r12 here
687 ldr r1, =(Pico+0x22200)
688 add r0, r0, #0x0c0000
695 m_m68k_read16_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
697 ldr r1, =(Pico+0x22200)
698 add r0, r0, #0x0e0000
705 m_m68k_read16_bcram_size: @ 0x400000
712 movne r0, #3 @ pretend to be a 64k cart
716 @ m_m68k_read16_bcram: @ 0x600000 - 0x61ffff
717 .equiv m_m68k_read16_bcram, m_m68k_read8_bcram
720 m_m68k_read16_bcram_reg: @ 0x7fffff
721 bcram_reg_rw 1, 0x7ffffe
724 m_m68k_read16_system_io:
725 bic r1, r0, #0xfe0000
728 bne m_m68k_read16_misc
730 m_m68k_read16_m68k_regs:
731 ldr r1, =(Pico+0x22200)
733 ldr r1, [r1] @ Pico.mcd (used everywhere)
735 ldrlt pc, [pc, r0, lsl #1]
737 .long m_m68k_read16_r00
738 .long m_m68k_read16_r02
739 .long m_m68k_read16_r04
740 .long m_m68k_read16_r06
741 .long m_m68k_read16_r08
742 .long m_read_null @ reserved
743 .long m_m68k_read16_r0c
745 add r1, r1, #0x110000
747 add r1, r1, #0x002200
748 ldrb r1, [r1, #2] @ Pico_mcd->m.busreq
749 and r0, r0, #0x04000000 @ we need irq2 mask state
750 orr r0, r1, r0, lsr #11
753 add r1, r1, #0x110000
756 add r1, r1, #0x002200
759 orr r0, r2, r0, lsl #8
760 tst r1, #2 @ DMNA pending?
766 add r1, r1, #0x110000
771 ldrh r0, [r1, #0x72] @ IRQ vector
777 add r1, r1, #0x110000
778 add r1, r1, #0x002200
784 addlt r1, r1, #0x110000
790 orr r0, r0, r1, lsl #8
803 bxne lr @ invalid read
810 bic r0, r0, #0xff0000
816 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
820 ldr r1, =(Pico+0x22200)
821 bic r0, r0, #0xfe0000
828 m_m68k_read32_prgbank:
829 ldr r1, =(Pico+0x22200)
833 orr r3, r2, #0x002200
836 and r3, r3, #0x00030000
837 cmp r3, #0x00010000 @ have bus or in reset state?
840 and r2, r2, #0xc0000000 @ r3 & 0xC0
841 add r1, r1, r2, lsr #12
846 m_m68k_read32_wordram0_2M: @ 0x200000 - 0x21ffff
847 m_m68k_read32_wordram1_2M: @ 0x220000 - 0x23ffff
848 ldr r1, =(Pico+0x22200)
849 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
856 m_m68k_read32_wordram0_1M_b0: @ 0x200000 - 0x21ffff
857 ldr r1, =(Pico+0x22200)
858 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
865 m_m68k_read32_wordram0_1M_b1: @ 0x200000 - 0x21ffff
866 ldr r1, =(Pico+0x22200)
867 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
874 m_m68k_read32_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
876 bne m_m68k_read32_wordram1_1M_b0_unal
878 ldr r1, =(Pico+0x22200)
879 add r0, r0, #0x0c0000
884 m_m68k_read32_wordram1_1M_b0_unal:
885 @ hopefully this doesn't happen too often
888 bl m_m68k_read16_wordram1_1M_b0 @ must not trash r12 and r3
892 bl m_m68k_read16_wordram1_1M_b0
893 orr r0, r0, r3, lsl #16
897 m_m68k_read32_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
899 bne m_m68k_read32_wordram1_1M_b1_unal
901 ldr r1, =(Pico+0x22200)
902 add r0, r0, #0x0e0000
907 m_m68k_read32_wordram1_1M_b1_unal:
910 bl m_m68k_read16_wordram1_1M_b1 @ must not trash r12 and r3
914 bl m_m68k_read16_wordram1_1M_b1
915 orr r0, r0, r3, lsl #16
919 m_m68k_read32_bcram_size: @ 0x400000
926 movne r0, #0x30000 @ pretend to be a 64k cart
930 m_m68k_read32_bcram: @ 0x600000 - 0x61ffff, not likely to be called
933 bl m_m68k_read8_bcram
937 bl m_m68k_read8_bcram
938 orr r0, r0, r3, lsl #16
942 m_m68k_read32_bcram_reg: @ 0x7fffff
943 bcram_reg_rw 1, 0x7ffffc
946 @ it is not very practical to use long access on hw registers, so I assume it is not used too much.
947 m_m68k_read32_system_io:
948 bic r1, r0, #0xfe0000
951 bne m_m68k_read32_misc
954 blt m_m68k_read32_misc
958 @ I have seen the range 0x0e-0x2f accessed quite frequently with long i/o, so here is some code for that
960 ldr r1, =(Pico+0x22200)
963 orr r2, r2, r2, lsl #16
964 add r1, r1, #0x110000
966 and r1, r2, r0 @ data is big-endian read as little, have to byteswap
967 and r0, r2, r0, lsr #8
968 orr r0, r0, r1, lsl #8
974 bl m_m68k_read16_system_io
976 bl m_m68k_read16_system_io
978 orr r0, r0, r1, lsl #16
985 bxne lr @ invalid read
993 orr r0, r0, r1, lsl #16
999 bic r0, r0, #0xff0000
1006 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1011 m_m68k_write8_bcram_size: @ 0x400000
1015 m_m68k_write8_prgbank:
1016 ldr r2, =(Pico+0x22200)
1020 orr r3, r12, #0x002200
1023 and r3, r3, #0x00030000
1024 cmp r3, #0x00010000 @ have bus or in reset state?
1026 and r12,r12,#0xc0000000 @ r3 & 0xC0
1027 add r2, r2, r12, lsr #12
1032 m_m68k_write8_wordram0_2M: @ 0x200000 - 0x21ffff
1033 m_m68k_write8_wordram1_2M: @ 0x220000 - 0x23ffff
1034 ldr r2, =(Pico+0x22200)
1035 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
1042 m_m68k_write8_wordram0_1M_b0: @ 0x200000 - 0x21ffff
1043 ldr r2, =(Pico+0x22200)
1044 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
1051 m_m68k_write8_wordram0_1M_b1: @ 0x200000 - 0x21ffff
1052 ldr r2, =(Pico+0x22200)
1053 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
1060 m_m68k_write8_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
1063 ldr r2, =(Pico+0x22200)
1064 add r0, r0, #0x0c0000
1071 m_m68k_write8_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
1074 ldr r2, =(Pico+0x22200)
1075 add r0, r0, #0x0e0000
1082 m_m68k_write8_bcram: @ 0x600000 - 0x61ffff
1083 @ can't use r3 or r12, because of write32
1085 bic r0, r0, #0xfe0000
1089 add r0, r2, r0, lsr #1
1090 ldr r2, =(Pico+0x22200)
1093 add r2, r2, #0x110000
1094 add r2, r2, #0x002200
1096 tst r2, #1 @ check bcram reg
1101 strb r0, [r2, #0x0e] @ SRam.changed = 1
1105 m_m68k_write8_bcram_reg: @ 0x7fffff
1106 bcram_reg_rw 0, 0x7fffff
1109 m_m68k_write8_system_io:
1110 bic r2, r0, #0xfe0000
1116 b m_m68k_write8_misc
1128 orr r1, r1, r1, lsl #8 @ byte access gets mirrored
1134 bic r0, r0, #0xff0000
1140 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1143 m_m68k_write16_bios:
1144 m_m68k_write16_bcram_size: @ 0x400000
1148 m_m68k_write16_prgbank:
1149 ldr r2, =(Pico+0x22200)
1153 orr r3, r12, #0x002200
1156 and r3, r3, #0x00030000
1157 cmp r3, #0x00010000 @ have bus or in reset state?
1159 and r12,r12,#0xc0000000 @ r3 & 0xC0
1160 add r2, r2, r12, lsr #12
1165 m_m68k_write16_wordram0_2M: @ 0x200000 - 0x21ffff
1166 m_m68k_write16_wordram1_2M: @ 0x220000 - 0x23ffff
1167 ldr r2, =(Pico+0x22200)
1168 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
1175 m_m68k_write16_wordram0_1M_b0: @ 0x200000 - 0x21ffff
1176 ldr r2, =(Pico+0x22200)
1177 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
1184 m_m68k_write16_wordram0_1M_b1: @ 0x200000 - 0x21ffff
1185 ldr r2, =(Pico+0x22200)
1186 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
1193 m_m68k_write16_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
1194 @ Warning: write32 relies on NOT using r12 and and keeping data in r3
1197 ldr r1, =(Pico+0x22200)
1198 add r0, r0, #0x0c0000
1205 m_m68k_write16_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
1208 ldr r1, =(Pico+0x22200)
1209 add r0, r0, #0x0e0000
1216 @ m_m68k_write16_bcram: @ 0x600000 - 0x61ffff
1217 .equiv m_m68k_write16_bcram, m_m68k_write8_bcram
1220 m_m68k_write16_bcram_reg: @ 0x7fffff
1221 bcram_reg_rw 0, 0x7ffffe
1224 m_m68k_write16_system_io:
1226 bic r2, r0, #0xfe0000
1231 m_m68k_write16_regs:
1234 beq m_m68k_write16_regs_spec
1237 stmfd sp!,{r2,r3,lr}
1240 ldmfd sp!,{r0,r1,lr}
1243 m_m68k_write16_regs_spec: @ special case
1244 ldr r2, =(Pico+0x22200)
1245 ldr r3, =s68k_poll_adclk
1248 add r0, r0, #0x00000e
1250 strb r1, [r2, r0] @ if (a == 0xe) s68k_regs[0x0e] = d >> 8;
1256 ldr r0, =PicoCpuCS68k
1257 str r1, [r0, #0x58] @ push s68k out of stopped state
1271 b SN76496Write @ lsb goes to 0x11
1276 bic r0, r0, #0xff0000
1282 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1285 m_m68k_write32_bios:
1286 m_m68k_write32_bcram_size: @ 0x400000
1290 m_m68k_write32_prgbank:
1291 ldr r2, =(Pico+0x22200)
1295 orr r3, r12, #0x002200
1298 and r3, r3, #0x00030000
1299 cmp r3, #0x00010000 @ have bus or in reset state?
1301 and r12,r12,#0xc0000000 @ r3 & 0xC0
1302 add r2, r2, r12, lsr #12
1307 m_m68k_write32_wordram0_2M: @ 0x200000 - 0x21ffff
1308 m_m68k_write32_wordram1_2M: @ 0x220000 - 0x23ffff
1309 ldr r2, =(Pico+0x22200)
1310 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
1317 m_m68k_write32_wordram0_1M_b0: @ 0x200000 - 0x21ffff
1318 ldr r2, =(Pico+0x22200)
1319 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
1326 m_m68k_write32_wordram0_1M_b1: @ 0x200000 - 0x21ffff
1327 ldr r2, =(Pico+0x22200)
1328 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
1335 m_m68k_write32_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
1337 bne m_m68k_write32_wordram1_1M_b0_unal
1340 ldr r2, =(Pico+0x22200)
1341 add r0, r0, #0x0c0000
1347 m_m68k_write32_wordram1_1M_b0_unal:
1348 @ hopefully this doesn't happen too often
1352 bl m_m68k_write16_wordram1_1M_b0 @ must not trash r12 and keep data in r3
1356 b m_m68k_write16_wordram1_1M_b0
1359 m_m68k_write32_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
1361 bne m_m68k_write32_wordram1_1M_b1_unal
1364 ldr r2, =(Pico+0x22200)
1365 add r0, r0, #0x0e0000
1371 m_m68k_write32_wordram1_1M_b1_unal:
1375 bl m_m68k_write16_wordram1_1M_b1 @ same as above
1379 b m_m68k_write16_wordram1_1M_b1
1382 m_m68k_write32_bcram: @ 0x600000 - 0x61ffff, not likely to be called
1386 bl m_m68k_write8_bcram
1389 bl m_m68k_write8_bcram
1393 m_m68k_write32_bcram_reg: @ 0x7fffff
1394 bcram_reg_rw 0, 0x7ffffc
1398 @ it is not very practical to use long access on hw registers, so I assume it is not used too much.
1399 m_m68k_write32_system_io:
1400 bic r2, r0, #0xfe0000
1403 bne m_m68k_write32_misc
1408 bge m_m68k_write32_regs_comm
1410 bge m_m68k_write32_regs_spec @ hits the nasty comm reg qiurk
1413 stmfd sp!,{r0,r1,lr}
1426 ldmfd sp!,{r0,r1,lr}
1430 m_m68k_write32_regs_comm: @ Handle the 0x10-0x1f range
1431 ldr r0, =(Pico+0x22200)
1434 orr r3, r3, r3, lsl #16
1435 add r0, r0, #0x110000
1436 and r12,r3, r1, ror #16 @ data is big-endian to be written as little, have to byteswap
1437 and r1, r3, r1, ror #24
1438 orr r1, r1, r12,lsl #8 @ end of byteswap
1441 ldr r3, =s68k_poll_adclk
1443 movne r1, r1, lsr #16
1447 ldr r0, =PicoCpuCS68k @ remove poll detected state for s68k
1453 m_m68k_write32_misc:
1455 stmfd sp!,{r0,r1,lr}
1458 ldmfd sp!,{r0,r1,lr}
1462 m_m68k_write32_regs_spec:
1464 stmfd sp!,{r0,r1,lr}
1466 bl m_m68k_write16_regs
1467 ldmfd sp!,{r0,r1,lr}
1469 b m_m68k_write16_regs
1478 moveq r0, r1, lsr #16
1479 beq SN76496Write @ which game is crazy enough to do that?
1480 stmfd sp!,{r0,r1,lr}
1483 ldmfd sp!,{r0,r1,lr}
1490 bic r0, r0, #0xff0000
1498 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1500 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1503 .macro m_s68k_read8_ram map_addr
1504 ldr r1, =(Pico+0x22200)
1508 add r0, r0, #\map_addr @ map to our address
1514 .macro m_s68k_read8_wordram_2M_decode map_addr
1515 ldr r2, =(Pico+0x22200)
1518 movs r0, r0, lsr #1 @ +4-6 <<16
1519 add r2, r2, #\map_addr @ map to our address
1521 movcc r0, r0, lsr #4
1527 m_s68k_read8_prg: @ 0x000000 - 0x07ffff
1528 m_s68k_read8_wordram_2M: @ 0x080000 - 0x0bffff
1529 m_s68k_read8_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1530 m_s68k_read8_ram 0x020000
1533 m_s68k_read8_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
1534 m_s68k_read8_wordram_2M_decode 0x080000 @ + ^ / 2
1537 m_s68k_read8_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
1538 m_s68k_read8_wordram_2M_decode 0x0a0000 @ + ^ / 2
1541 m_s68k_read8_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1545 m_s68k_read8_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1546 @ must not trash r3 and r12
1547 ldr r1, =(Pico+0x22200)
1550 bic r0, r0, #0xff0000
1551 bic r0, r0, #0x00e000
1552 add r1, r1, #0x110000
1553 add r1, r1, #0x000200
1559 @ must not trash r3 and r12
1560 ldr r1, =(Pico+0x22200)
1561 bic r0, r0, #0xff0000
1562 @ bic r0, r0, #0x008000
1565 orr r2, r2, #0x002200
1567 bge m_s68k_read8_pcm_ram
1571 orr r2, r2, #(0x48+8) @ pcm.ch + addr_offset
1574 ldr r1, [r1, r2, lsl #2]
1576 moveq r0, r1, lsr #PCM_STEP_SHIFT
1577 movne r0, r1, lsr #(PCM_STEP_SHIFT+8)
1581 m_s68k_read8_pcm_ram:
1584 add r1, r1, #0x100000 @ pcm_ram
1585 and r2, r2, #0x0f000000 @ bank
1586 add r1, r1, r2, lsr #12
1587 bic r0, r0, #0x00e000
1594 bic r0, r0, #0xff0000
1595 bic r0, r0, #0x008000
1600 cmp r2, #(0x30-0x0e)
1601 blo m_s68k_read8_comm
1604 ldrlo r2, =gfx_cd_read
1605 ldrhs r2, =s68k_reg_read16
1612 moveq r0, r0, lsr #8
1617 ldr r1, =(Pico+0x22200)
1619 add r1, r1, #0x110000
1624 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1627 .macro m_s68k_read16_ram map_addr
1628 ldr r1, =(Pico+0x22200)
1632 add r0, r0, #\map_addr @ map to our address
1638 .macro m_s68k_read16_wordram_2M_decode map_addr
1639 ldr r2, =(Pico+0x22200)
1642 mov r0, r0, lsr #1 @ +4-6 <<16
1643 add r2, r2, #\map_addr @ map to our address
1645 orr r0, r0, r0, lsl #4
1651 m_s68k_read16_prg: @ 0x000000 - 0x07ffff
1652 m_s68k_read16_wordram_2M: @ 0x080000 - 0x0bffff
1653 m_s68k_read16_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1654 m_s68k_read16_ram 0x020000
1657 m_s68k_read16_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
1658 m_s68k_read16_wordram_2M_decode 0x080000
1661 m_s68k_read16_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
1662 m_s68k_read16_wordram_2M_decode 0x0a0000
1665 m_s68k_read16_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1669 @ m_s68k_read16_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1670 @ bram is not meant to be accessed by words, does any game do this?
1671 .equiv m_s68k_read16_backup, m_s68k_read8_backup
1674 @ m_s68k_read16_pcm:
1675 @ pcm is on 8-bit bus, would this be same as byte access?
1676 .equiv m_s68k_read16_pcm, m_s68k_read8_pcm
1680 bic r0, r0, #0xff0000
1681 bic r0, r0, #0x008000
1682 bic r0, r0, #0x000001
1695 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1698 .macro m_s68k_read32_ram map_addr
1699 ldr r1, =(Pico+0x22200)
1703 add r0, r0, #\map_addr @ map to our address
1709 .macro m_s68k_read32_wordram_2M_decode map_addr
1710 ldr r2, =(Pico+0x22200)
1713 mov r0, r0, lsr #1 @ +4-6 <<16
1714 add r2, r2, #\map_addr @ map to our address
1717 ldrneb r0, [r2, #-1]
1719 orr r1, r1, r1, lsl #4
1721 orr r0, r0, r0, lsl #4
1723 orr r0, r0, r1, lsl #16
1728 m_s68k_read32_prg: @ 0x000000 - 0x07ffff
1729 m_s68k_read32_wordram_2M: @ 0x080000 - 0x0bffff
1730 m_s68k_read32_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1731 m_s68k_read32_ram 0x020000
1734 m_s68k_read32_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
1735 m_s68k_read32_wordram_2M_decode 0x080000
1738 m_s68k_read32_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
1739 m_s68k_read32_wordram_2M_decode 0x0a0000
1742 m_s68k_read32_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1746 m_s68k_read32_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1747 @ bram is not meant to be accessed by words, does any game do this?
1750 bl m_s68k_read8_backup @ must preserve r3 and r12
1754 bl m_s68k_read8_backup
1755 orr r0, r0, r3, lsl #16
1762 bl m_s68k_read8_pcm @ must preserve r3 and r12
1767 orr r0, r0, r3, lsl #16
1772 bic r0, r0, #0xff0000
1773 bic r0, r0, #0x008000
1774 bic r0, r0, #0x000001
1781 blo m_s68k_read32_regs_gfx
1787 orr r0, r0, r1, lsl #16
1791 m_s68k_read32_regs_gfx:
1797 orr r0, r0, r1, lsl #16
1802 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1805 .macro m_s68k_write8_ram map_addr
1806 ldr r2, =(Pico+0x22200)
1810 add r0, r0, #\map_addr @ map to our address
1816 .macro m_s68k_write8_2M_decode map_addr
1817 ldr r2, =(Pico+0x22200)
1820 movs r0, r0, lsr #1 @ +4-6 <<16
1821 add r2, r2, #\map_addr @ map to our address
1824 .macro m_s68k_write8_2M_decode_m0 map_addr @ mode off
1825 m_s68k_write8_2M_decode \map_addr
1828 movcc r1, r1, lsl #4
1832 cmp r0, r3 @ avoid writing if result is same
1837 .macro m_s68k_write8_2M_decode_m1 map_addr @ mode underwrite
1840 m_s68k_write8_2M_decode \map_addr
1842 movcc r1, r1, lsl #4
1853 .macro m_s68k_write8_2M_decode_m2 map_addr @ mode overwrite
1856 m_s68k_write8_2M_decode_m0 \map_addr @ same as in off mode
1861 m_s68k_write8_prg: @ 0x000000 - 0x07ffff
1862 ldr r2, =(Pico+0x22200)
1865 add r3, r0, #0x020000 @ map to our address
1866 add r12,r2, #0x110000
1868 and r12,r12,#0x00ff0000 @ wp
1874 m_s68k_write8_wordram_2M: @ 0x080000 - 0x0bffff
1875 m_s68k_write8_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1876 m_s68k_write8_ram 0x020000
1879 m_s68k_write8_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
1880 m_s68k_write8_2M_decode_m0 0x080000
1882 m_s68k_write8_2M_decode_b0_m1:
1883 m_s68k_write8_2M_decode_m1 0x080000
1885 m_s68k_write8_2M_decode_b0_m2:
1886 m_s68k_write8_2M_decode_m2 0x080000
1888 m_s68k_write8_2M_decode_b1_m0:
1889 m_s68k_write8_2M_decode_m0 0x0a0000
1891 m_s68k_write8_2M_decode_b1_m1:
1892 m_s68k_write8_2M_decode_m1 0x0a0000
1894 m_s68k_write8_2M_decode_b1_m2:
1895 m_s68k_write8_2M_decode_m2 0x0a0000
1898 m_s68k_write8_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1902 m_s68k_write8_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1903 @ must not trash r3 and r12
1904 ldr r2, =(Pico+0x22200)
1907 bic r0, r0, #0xff0000
1908 bic r0, r0, #0x00e000
1909 add r2, r2, #0x110000
1910 add r2, r2, #0x000200
1914 strb r0, [r1, #0x0e] @ SRam.changed = 1
1919 bic r0, r0, #0xff0000
1921 movlt r0, r0, lsr #1
1927 m_s68k_write8_pcm_ram:
1928 ldr r3, =(Pico+0x22200)
1929 bic r0, r0, #0x00e000
1932 add r2, r3, #0x110000
1933 add r2, r2, #0x002200
1934 add r2, r2, #0x000040
1936 add r3, r3, #0x100000 @ pcm_ram
1937 and r2, r2, #0x0f000000 @ bank
1938 add r3, r3, r2, lsr #12
1944 bic r0, r0, #0xff0000
1945 bic r0, r0, #0x008000
1953 orr r1, r1, r1, lsl #8
1957 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1960 .macro m_s68k_write16_ram map_addr
1961 ldr r2, =(Pico+0x22200)
1965 add r0, r0, #\map_addr @ map to our address
1971 .macro m_s68k_write16_2M_decode map_addr
1972 ldr r2, =(Pico+0x22200)
1975 mov r0, r0, lsr #1 @ +4-6 <<16
1976 add r2, r2, #\map_addr @ map to our address
1979 .macro m_s68k_write16_2M_decode_m0 map_addr @ mode off
1980 m_s68k_write16_2M_decode \map_addr
1982 orr r1, r1, r1, lsr #4
1987 .macro m_s68k_write16_2M_decode_m1 map_addr @ mode underwrite
1988 bics r1, r1, #0xf000
1989 bicnes r1, r1, #0x00f0
1991 orr r1, r1, r1, lsr #4
1992 m_s68k_write16_2M_decode \map_addr
2004 .macro m_s68k_write16_2M_decode_m2 map_addr @ mode overwrite
2005 bics r1, r1, #0xf000
2006 bicnes r1, r1, #0x00f0
2008 orr r1, r1, r1, lsr #4
2009 m_s68k_write16_2M_decode \map_addr
2023 m_s68k_write16_prg: @ 0x000000 - 0x07ffff
2024 ldr r2, =(Pico+0x22200)
2027 add r3, r0, #0x020000 @ map to our address
2028 add r12,r2, #0x110000
2030 and r12,r12,#0x00ff0000 @ wp
2036 m_s68k_write16_wordram_2M: @ 0x080000 - 0x0bffff
2037 m_s68k_write16_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
2038 m_s68k_write16_ram 0x020000
2041 m_s68k_write16_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
2042 m_s68k_write16_2M_decode_m0 0x080000
2044 m_s68k_write16_2M_decode_b0_m1:
2045 m_s68k_write16_2M_decode_m1 0x080000
2047 m_s68k_write16_2M_decode_b0_m2:
2048 m_s68k_write16_2M_decode_m2 0x080000
2050 m_s68k_write16_2M_decode_b1_m0:
2051 m_s68k_write16_2M_decode_m0 0x0a0000
2053 m_s68k_write16_2M_decode_b1_m1:
2054 m_s68k_write16_2M_decode_m1 0x0a0000
2056 m_s68k_write16_2M_decode_b1_m2:
2057 m_s68k_write16_2M_decode_m2 0x0a0000
2060 m_s68k_write16_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
2061 m_s68k_write16_ram 0
2064 @ m_s68k_write16_backup:
2065 .equiv m_s68k_write16_backup, m_s68k_write8_backup
2068 @ m_s68k_write16_pcm:
2069 .equiv m_s68k_write16_pcm, m_s68k_write8_pcm
2072 m_s68k_write16_regs:
2073 bic r0, r0, #0xff0000
2074 bic r0, r0, #0x008000
2080 beq m_s68k_write16_regs_spec
2086 stmfd sp!,{r2,r3,lr}
2089 ldmfd sp!,{r0,r1,lr}
2092 m_s68k_write16_regs_spec: @ special case
2093 ldr r2, =(Pico+0x22200)
2096 add r0, r0, #0x00000f
2097 strb r1, [r2, r0] @ if (a == 0xe) s68k_regs[0xf] = d;
2101 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
2104 .macro m_s68k_write32_ram map_addr
2105 ldr r2, =(Pico+0x22200)
2109 add r0, r0, #\map_addr @ map to our address
2115 .macro m_s68k_write32_2M_decode map_addr
2116 ldr r2, =(Pico+0x22200)
2119 mov r0, r0, lsr #1 @ +4-6 <<16
2120 add r2, r2, #\map_addr @ map to our address
2123 .macro m_s68k_write32_2M_decode_m0 map_addr @ mode off
2124 m_s68k_write32_2M_decode \map_addr
2125 bic r1, r1, #0x000000f0
2126 bic r1, r1, #0x00f00000
2127 orr r1, r1, r1, lsr #4
2131 strneb r1, [r2, #-1]
2136 .macro m_s68k_write32_2M_decode_m1 map_addr @ mode underwrite
2137 bics r1, r1, #0x000000f0
2138 bicnes r1, r1, #0x0000f000
2139 bicnes r1, r1, #0x00f00000
2140 bicnes r1, r1, #0xf0000000
2142 orr r1, r1, r1, lsr #4
2143 m_s68k_write32_2M_decode \map_addr
2146 ldrneb r0, [r2, #-1]
2148 and r12,r1, #0x0000000f
2149 orr r0, r0, r3, lsl #16
2150 orrne r0, r0, #0x80000000 @ remember addr lsb bit
2154 andeq r12,r1, #0x000000f0
2157 andeq r12,r1, #0x000f0000
2160 andeq r12,r1, #0x00f00000
2163 strneb r0, [r2, #-1]
2170 .macro m_s68k_write32_2M_decode_m2 map_addr @ mode overwrite
2171 bics r1, r1, #0x000000f0
2172 bicnes r1, r1, #0x0000f000
2173 bicnes r1, r1, #0x00f00000
2174 bicnes r1, r1, #0xf0000000
2176 orr r1, r1, r1, lsr #4
2177 m_s68k_write32_2M_decode \map_addr
2180 ldrneb r0, [r2, #-1]
2182 orrne r1, r1, #0x80000000 @ remember addr lsb bit
2183 orr r0, r0, r3, lsl #16
2185 andeq r12,r0, #0x0000000f
2188 andeq r12,r0, #0x000000f0
2191 andeq r12,r0, #0x000f0000
2194 andeq r12,r0, #0x00f00000
2199 strneb r1, [r2, #-1]
2208 m_s68k_write32_prg: @ 0x000000 - 0x07ffff
2209 ldr r2, =(Pico+0x22200)
2212 add r3, r0, #0x020000 @ map to our address
2213 add r12,r2, #0x110000
2215 and r12,r12,#0x00ff0000 @ wp
2224 m_s68k_write32_wordram_2M: @ 0x080000 - 0x0bffff
2225 m_s68k_write32_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
2226 m_s68k_write32_ram 0x020000
2229 m_s68k_write32_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
2230 m_s68k_write32_2M_decode_m0 0x080000
2232 m_s68k_write32_2M_decode_b0_m1:
2233 m_s68k_write32_2M_decode_m1 0x080000
2235 m_s68k_write32_2M_decode_b0_m2:
2236 m_s68k_write32_2M_decode_m2 0x080000
2238 m_s68k_write32_2M_decode_b1_m0:
2239 m_s68k_write32_2M_decode_m0 0x0a0000
2241 m_s68k_write32_2M_decode_b1_m1:
2242 m_s68k_write32_2M_decode_m1 0x0a0000
2244 m_s68k_write32_2M_decode_b1_m2:
2245 m_s68k_write32_2M_decode_m2 0x0a0000
2248 m_s68k_write32_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
2249 m_s68k_write32_ram 0
2252 m_s68k_write32_backup:
2257 bl m_s68k_write8_backup @ must preserve r3 and r12
2261 b m_s68k_write8_backup
2265 bic r0, r0, #0xff0000
2267 blt m_s68k_write32_pcm_reg
2272 m_s68k_write32_pcm_ram:
2273 ldr r3, =(Pico+0x22200)
2274 bic r0, r0, #0x00e000
2277 add r2, r3, #0x110000
2278 add r2, r2, #0x002200
2279 add r2, r2, #0x000040
2281 add r3, r3, #0x100000 @ pcm_ram
2282 and r2, r2, #0x0f000000 @ bank
2283 add r3, r3, r2, lsr #12
2290 m_s68k_write32_pcm_reg:
2292 stmfd sp!,{r0,r1,lr}
2295 ldmfd sp!,{r0,r1,lr}
2300 m_s68k_write32_regs:
2301 bic r0, r0, #0xff0000
2302 bic r0, r0, #0x008000
2308 blo m_s68k_write32_regs_gfx
2311 beq m_s68k_write32_regs_spec @ hits 0x0f
2314 beq m_s68k_write32_regs_comm
2316 stmfd sp!,{r0,r1,lr}
2329 ldmfd sp!,{r0,r1,lr}
2333 m_s68k_write32_regs_gfx:
2334 stmfd sp!,{r0,r1,lr}
2337 ldmfd sp!,{r0,r1,lr}
2341 m_s68k_write32_regs_comm: @ Handle the 0x20-0x2f range
2342 ldr r2, =(Pico+0x22200)
2345 orr r3, r3, r3, lsl #16
2346 add r2, r2, #0x110000
2347 and r12,r3, r1, ror #16 @ data is big-endian to be written as little, have to byteswap
2348 and r1, r3, r1, ror #24
2349 orr r1, r1, r12,lsl #8 @ end of byteswap
2352 movne r1, r1, lsr #16
2356 m_s68k_write32_regs_spec:
2357 stmfd sp!,{r0,r1,lr}
2359 bl m_s68k_write16_regs
2360 ldmfd sp!,{r0,r1,lr}
2362 b m_s68k_write16_regs