3 @ Memory I/O handlers for Sega/Mega CD emulation
4 @ (c) Copyright 2007, Grazvydas "notaz" Ignotas
8 .equiv PCM_STEP_SHIFT, 11
16 .macro mk_m68k_jump_table on sz @ operation name, size
17 .long m_m68k_&\on&\sz&_bios @ 0x000000 - 0x01ffff
18 .long m_m68k_&\on&\sz&_prgbank @ 0x020000 - 0x03ffff
19 .long m_&\on&_null, m_&\on&_null @ 0x040000 - 0x07ffff
20 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x080000 - 0x0fffff
21 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x100000 - 0x17ffff
22 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x180000 - 0x1fffff
23 .long m_m68k_&\on&\sz&_wordram0_2M @ 0x200000 - 0x21ffff
24 .long m_m68k_&\on&\sz&_wordram1_2M @ 0x220000 - 0x23ffff
25 .long m_&\on&_null, m_&\on&_null @ 0x240000 - 0x27ffff
26 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x280000 - 0x2fffff
27 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x300000
28 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x3fffff
29 .long m_m68k_&\on&\sz&_bcram_size @ 0x400000
30 .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x420000
31 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x4fffff
32 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x500000
33 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x5fffff
34 .long m_m68k_&\on&\sz&_bcram @ 0x600000
35 .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x620000
36 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x6fffff
37 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x700000
38 .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x7dffff
39 .long m_m68k_&\on&\sz&_bcram_reg @ 0x7e0000
40 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x800000
41 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x8fffff
42 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x900000
43 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x9fffff
44 .long m_m68k_&\on&\sz&_system_io @ 0xa00000 - 0xa1ffff
45 .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xa20000 - 0xa7ffff
46 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xa80000 - 0xafffff
47 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xb00000
48 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0xbfffff
49 .long m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp @ 0xc00000
50 .long m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp @ - 0xcfffff
51 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xd00000
52 .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0xdfffff
53 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ 0xe00000
54 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ - 0xefffff
55 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ 0xf00000
56 .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ - 0xffffff
59 .macro mk_s68k_jump_table on sz @ operation name, size
60 .long m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg @ 0x000000 - 0x07ffff
61 .long m_s68k_&\on&\sz&_wordram_2M @ 0x080000 - 0x09ffff
62 .long m_s68k_&\on&\sz&_wordram_2M @ 0x0a0000 - 0x0bffff
63 .long m_&\on&_null @ 0x0c0000 - 0x0dffff, 1M area
64 .long m_&\on&_null @ 0x0e0000 - 0x0fffff
68 @ the jumptables themselves.
69 m_m68k_read8_table: mk_m68k_jump_table read 8
70 m_m68k_read16_table: mk_m68k_jump_table read 16
71 m_m68k_read32_table: mk_m68k_jump_table read 32
72 m_m68k_write8_table: mk_m68k_jump_table write 8
73 m_m68k_write16_table: mk_m68k_jump_table write 16
74 m_m68k_write32_table: mk_m68k_jump_table write 32
76 m_s68k_read8_table: mk_s68k_jump_table read 8
77 m_s68k_read16_table: mk_s68k_jump_table read 16
78 m_s68k_read32_table: mk_s68k_jump_table read 32
79 m_s68k_write8_table: mk_s68k_jump_table write 8
80 m_s68k_write16_table: mk_s68k_jump_table write 16
81 m_s68k_write32_table: mk_s68k_jump_table write 32
83 m_s68k_decode_write_table:
84 .long m_s68k_write8_2M_decode_b0_m0
85 .long m_s68k_write16_2M_decode_b0_m0
86 .long m_s68k_write32_2M_decode_b0_m0
87 .long m_s68k_write8_2M_decode_b0_m1
88 .long m_s68k_write16_2M_decode_b0_m1
89 .long m_s68k_write32_2M_decode_b0_m1
90 .long m_s68k_write8_2M_decode_b0_m2
91 .long m_s68k_write16_2M_decode_b0_m2
92 .long m_s68k_write32_2M_decode_b0_m2
93 .long m_s68k_write8_2M_decode_b1_m0
94 .long m_s68k_write16_2M_decode_b1_m0
95 .long m_s68k_write32_2M_decode_b1_m0
96 .long m_s68k_write8_2M_decode_b1_m1
97 .long m_s68k_write16_2M_decode_b1_m1
98 .long m_s68k_write32_2M_decode_b1_m1
99 .long m_s68k_write8_2M_decode_b1_m2
100 .long m_s68k_write16_2M_decode_b1_m2
101 .long m_s68k_write32_2M_decode_b1_m2
104 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
109 .global PicoMemResetCD
110 .global PicoMemResetCDdecode
111 .global PicoReadM68k8
112 .global PicoReadM68k16
113 .global PicoReadM68k32
114 .global PicoWriteM68k8
115 .global PicoWriteM68k16
116 .global PicoWriteM68k32
117 .global PicoReadS68k8
118 .global PicoReadS68k16
119 .global PicoReadS68k32
120 .global PicoWriteS68k8
121 .global PicoWriteS68k16
122 .global PicoWriteS68k32
124 @ externs, just for reference
128 .extern PicoVideoRead
129 .extern Read_CDC_Host
130 .extern m68k_reg_write8
134 .extern s68k_reg_read16
136 .extern gfx_cd_write16
137 .extern s68k_reg_write8
138 .extern s68k_poll_adclk
140 .extern s68k_poll_detect
144 @ r0=reg3, r1-r3=temp
145 .macro mk_update_table on sz @ operation name, size
146 @ we only set word-ram handlers
147 ldr r1, =m_m68k_&\on&\sz&_table
148 ldr r12,=m_s68k_&\on&\sz&_table
153 ldr r2, =m_m68k_&\on&\sz&_wordram0_2M
154 ldr r3, =m_s68k_&\on&\sz&_wordram_2M
157 ldr r2, =m_&\on&_null
168 ldr r2, =m_m68k_&\on&\sz&_wordram0_1M_b0
169 ldr r3, =m_m68k_&\on&\sz&_wordram1_1M_b0
172 ldr r3, =m_s68k_&\on&\sz&_wordram_1M_b1
174 ldr r2, =m_s68k_&\on&\sz&_wordram_2M_decode_b1
182 ldr r2, =m_m68k_&\on&\sz&_wordram0_1M_b1
183 ldr r3, =m_m68k_&\on&\sz&_wordram1_1M_b1
186 ldr r3, =m_s68k_&\on&\sz&_wordram_1M_b0
188 ldr r2, =m_s68k_&\on&\sz&_wordram_2M_decode_b0
199 mk_update_table read 8
200 mk_update_table read 16
201 mk_update_table read 32
202 mk_update_table write 8
203 mk_update_table write 16
204 mk_update_table write 32
208 PicoMemResetCDdecode: @reg3
210 bxeq lr @ we should not be called in 2M mode
211 ldr r1, =m_s68k_write8_table
212 ldr r3, =m_s68k_decode_write_table
216 moveq r2, #2 @ mode3 is same as mode2?
218 addeq r2, r2, #3 @ bank1 (r2=0..5)
219 add r2, r2, r2, lsl #1 @ *= 3
220 add r2, r3, r2, lsl #2
221 ldmia r2, {r0,r3,r12}
224 str r3, [r1, #4*4+8*4]
225 str r3, [r1, #5*4+8*4]
226 str r12,[r1, #4*4+8*4*2]
227 str r12,[r1, #5*4+8*4*2]
233 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
235 .macro mk_entry_m68k table
237 bic r0, r0, #0xff000000
238 and r3, r0, #0x00fe0000
239 ldr pc, [r2, r3, lsr #15]
242 PicoReadM68k8: @ u32 a
243 mk_entry_m68k m_m68k_read8_table
245 PicoReadM68k16: @ u32 a
246 mk_entry_m68k m_m68k_read16_table
248 PicoReadM68k32: @ u32 a
249 mk_entry_m68k m_m68k_read32_table
251 PicoWriteM68k8: @ u32 a, u8 d
252 mk_entry_m68k m_m68k_write8_table
254 PicoWriteM68k16: @ u32 a, u16 d
255 mk_entry_m68k m_m68k_write16_table
257 PicoWriteM68k32: @ u32 a, u32 d
258 mk_entry_m68k m_m68k_write32_table
261 .macro mk_entry_s68k on sz
262 bic r0, r0, #0xff000000
264 blt m_s68k_&\on&\sz&_prg
266 ldrlt r2, =m_s68k_&\on&\sz&_table
267 andlt r3, r0, #0x000e0000
268 ldrlt pc, [r2, r3, lsr #15]
270 orr r3, r3, #0x00008000
272 bge m_s68k_&\on&\sz&_regs
274 bge m_s68k_&\on&\sz&_pcm
276 bge m_s68k_&\on&\sz&_backup
281 PicoReadS68k8: @ u32 a
284 PicoReadS68k16: @ u32 a
285 mk_entry_s68k read 16
287 PicoReadS68k32: @ u32 a
288 mk_entry_s68k read 32
290 PicoWriteS68k8: @ u32 a, u8 d
291 mk_entry_s68k write 8
293 PicoWriteS68k16: @ u32 a, u16 d
294 mk_entry_s68k write 16
296 PicoWriteS68k32: @ u32 a, u32 d
297 mk_entry_s68k write 32
302 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
306 @ r0=addr[in,out], r1,r2=tmp
308 ands r1, r0, #0x01c000
309 ldrne pc, [pc, r1, lsr #12]
310 beq 0f @ most common?
320 and r1, r0, #0x7e00 @ col
321 and r2, r0, #0x01fc @ row
323 orr r1, r2, r1, ror #13
326 and r1, r0, #0x3f00 @ col
327 and r2, r0, #0x00fc @ row
329 orr r1, r2, r1, ror #12
332 and r1, r0, #0x1f80 @ col
333 and r2, r0, #0x007c @ row
334 orr r1, r2, r1, ror #11
336 orr r1, r1, r2, lsr #6
339 and r1, r0, #0xfc00 @ col
340 and r2, r0, #0x03fc @ row
341 orr r1, r2, r1, ror #14
344 orr r0, r0, r1, ror #26 @ rol 4+2
348 @ r0=prt1, r1=ptr2; unaligned ptr MUST be r0
354 moveq r0, r0, ror #16
355 orrne r0, r1, r0, lsl #16
359 @ r0=prt1, r1=data, r2=ptr2; unaligned ptr MUST be r0
364 movne r1, r1, lsr #16
370 .macro bcram_reg_rw is_read addr_check
371 rsb r0, r0, #0x800000
372 ldr r2, =(Pico+0x22200)
373 cmp r0, #(0x800000-\addr_check)
379 add r2, r2, #0x110000
380 add r2, r2, #0x002200
389 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
398 ldr r1, =(Pico+0x22200)
399 bic r0, r0, #0xfe0000
406 m_m68k_read8_prgbank:
407 ldr r1, =(Pico+0x22200)
411 orr r3, r2, #0x002200
414 and r3, r3, #0x00030000
415 cmp r3, #0x00010000 @ have bus or in reset state?
418 and r2, r2, #0xc0000000 @ r3 & 0xC0
419 add r1, r1, r2, lsr #12
424 m_m68k_read8_wordram0_2M: @ 0x200000 - 0x21ffff
425 m_m68k_read8_wordram1_2M: @ 0x220000 - 0x23ffff
426 ldr r1, =(Pico+0x22200)
427 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
434 m_m68k_read8_wordram0_1M_b0: @ 0x200000 - 0x21ffff
435 ldr r1, =(Pico+0x22200)
436 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
443 m_m68k_read8_wordram0_1M_b1: @ 0x200000 - 0x21ffff
444 ldr r1, =(Pico+0x22200)
445 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
452 m_m68k_read8_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
454 ldr r1, =(Pico+0x22200)
455 add r0, r0, #0x0c0000
462 m_m68k_read8_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
464 ldr r1, =(Pico+0x22200)
465 add r0, r0, #0x0e0000
472 m_m68k_read8_bcram_size: @ 0x400000
480 movne r0, #3 @ pretend to be a 64k cart (8<<3)
484 m_m68k_read8_bcram: @ 0x600000 - 0x61ffff
486 bic r0, r0, #0xfe0000
497 m_m68k_read8_bcram_reg: @ 0x7fffff
498 bcram_reg_rw 1, 0x7fffff
501 m_m68k_read8_system_io:
502 bic r2, r0, #0xfe0000
505 bne m_m68k_read8_misc
507 ldr r1, =(Pico+0x22200)
509 ldr r1, [r1] @ Pico.mcd (used everywhere)
511 ldrlt pc, [pc, r0, lsl #2]
513 .long m_m68k_read8_r00
514 .long m_m68k_read8_r01
515 .long m_m68k_read8_r02
516 .long m_m68k_read8_r03
517 .long m_m68k_read8_r04
518 .long m_read_null @ unused bits
519 .long m_m68k_read8_r06
520 .long m_m68k_read8_r07
521 .long m_m68k_read8_r08
522 .long m_m68k_read8_r09
523 .long m_read_null @ reserved
525 .long m_m68k_read8_r0c
526 .long m_m68k_read8_r0d
528 add r1, r1, #0x110000
530 and r0, r0, #0x04000000 @ we need irq2 mask state
534 add r1, r1, #0x110000
535 add r1, r1, #0x002200
536 ldrb r0, [r1, #2] @ Pico_mcd->m.busreq
539 add r1, r1, #0x110000
543 add r1, r1, #0x110000
545 add r1, r1, #0x002200
548 tst r1, #2 @ DMNA pending?
554 add r1, r1, #0x110000
558 ldrb r0, [r1, #0x73] @ IRQ vector
565 bl Read_CDC_Host @ TODO: make it local
572 add r1, r1, #0x110000
573 add r1, r1, #0x002200
574 ldr r0, [r1, #0x14] @ Pico_mcd->m.timer_stopwatch
578 add r1, r1, #0x110000
579 add r1, r1, #0x002200
587 add r1, r1, #0x110000
595 cmp r2, #0xa00000 @ Z80 RAM?
597 @ ldreq r2, =z80Read8
602 bl OtherRead16 @ non-MCD version should be ok too
612 bxne lr @ invalid read
615 bl PicoVideoRead @ TODO: implement it in asm
624 bic r0, r0, #0xff0000
630 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
634 ldr r1, =(Pico+0x22200)
635 bic r0, r0, #0xfe0000
642 m_m68k_read16_prgbank:
643 ldr r1, =(Pico+0x22200)
647 orr r3, r2, #0x002200
650 and r3, r3, #0x00030000
651 cmp r3, #0x00010000 @ have bus or in reset state?
654 and r2, r2, #0xc0000000 @ r3 & 0xC0
655 add r1, r1, r2, lsr #12
660 m_m68k_read16_wordram0_2M: @ 0x200000 - 0x21ffff
661 m_m68k_read16_wordram1_2M: @ 0x220000 - 0x23ffff
662 ldr r1, =(Pico+0x22200)
663 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
670 m_m68k_read16_wordram0_1M_b0: @ 0x200000 - 0x21ffff
671 ldr r1, =(Pico+0x22200)
672 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
679 m_m68k_read16_wordram0_1M_b1: @ 0x200000 - 0x21ffff
680 ldr r1, =(Pico+0x22200)
681 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
688 m_m68k_read16_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
689 @ Warning: read32 relies on NOT using r3 and r12 here
691 ldr r1, =(Pico+0x22200)
692 add r0, r0, #0x0c0000
699 m_m68k_read16_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
701 ldr r1, =(Pico+0x22200)
702 add r0, r0, #0x0e0000
709 m_m68k_read16_bcram_size: @ 0x400000
716 movne r0, #3 @ pretend to be a 64k cart
720 @ m_m68k_read16_bcram: @ 0x600000 - 0x61ffff
721 .equiv m_m68k_read16_bcram, m_m68k_read8_bcram
724 m_m68k_read16_bcram_reg: @ 0x7fffff
725 bcram_reg_rw 1, 0x7ffffe
728 m_m68k_read16_system_io:
729 bic r1, r0, #0xfe0000
732 bne m_m68k_read16_misc
734 m_m68k_read16_m68k_regs:
735 ldr r1, =(Pico+0x22200)
737 ldr r1, [r1] @ Pico.mcd (used everywhere)
739 ldrlt pc, [pc, r0, lsl #1]
741 .long m_m68k_read16_r00
742 .long m_m68k_read16_r02
743 .long m_m68k_read16_r04
744 .long m_m68k_read16_r06
745 .long m_m68k_read16_r08
746 .long m_read_null @ reserved
747 .long m_m68k_read16_r0c
749 add r1, r1, #0x110000
751 add r1, r1, #0x002200
752 ldrb r1, [r1, #2] @ Pico_mcd->m.busreq
753 and r0, r0, #0x04000000 @ we need irq2 mask state
754 orr r0, r1, r0, lsr #11
757 add r1, r1, #0x110000
760 add r1, r1, #0x002200
763 orr r0, r2, r0, lsl #8
764 tst r1, #2 @ DMNA pending?
770 add r1, r1, #0x110000
775 ldrh r0, [r1, #0x72] @ IRQ vector
781 add r1, r1, #0x110000
782 add r1, r1, #0x002200
788 addlt r1, r1, #0x110000
794 orr r0, r0, r1, lsl #8
807 bxne lr @ invalid read
814 bic r0, r0, #0xff0000
820 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
824 ldr r1, =(Pico+0x22200)
825 bic r0, r0, #0xfe0000
832 m_m68k_read32_prgbank:
833 ldr r1, =(Pico+0x22200)
837 orr r3, r2, #0x002200
840 and r3, r3, #0x00030000
841 cmp r3, #0x00010000 @ have bus or in reset state?
844 and r2, r2, #0xc0000000 @ r3 & 0xC0
845 add r1, r1, r2, lsr #12
850 m_m68k_read32_wordram0_2M: @ 0x200000 - 0x21ffff
851 m_m68k_read32_wordram1_2M: @ 0x220000 - 0x23ffff
852 ldr r1, =(Pico+0x22200)
853 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
860 m_m68k_read32_wordram0_1M_b0: @ 0x200000 - 0x21ffff
861 ldr r1, =(Pico+0x22200)
862 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
869 m_m68k_read32_wordram0_1M_b1: @ 0x200000 - 0x21ffff
870 ldr r1, =(Pico+0x22200)
871 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
878 m_m68k_read32_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
880 bne m_m68k_read32_wordram1_1M_b0_unal
882 ldr r1, =(Pico+0x22200)
883 add r0, r0, #0x0c0000
888 m_m68k_read32_wordram1_1M_b0_unal:
889 @ hopefully this doesn't happen too often
892 bl m_m68k_read16_wordram1_1M_b0 @ must not trash r12 and r3
896 bl m_m68k_read16_wordram1_1M_b0
897 orr r0, r0, r3, lsl #16
901 m_m68k_read32_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
903 bne m_m68k_read32_wordram1_1M_b1_unal
905 ldr r1, =(Pico+0x22200)
906 add r0, r0, #0x0e0000
911 m_m68k_read32_wordram1_1M_b1_unal:
914 bl m_m68k_read16_wordram1_1M_b1 @ must not trash r12 and r3
918 bl m_m68k_read16_wordram1_1M_b1
919 orr r0, r0, r3, lsl #16
923 m_m68k_read32_bcram_size: @ 0x400000
930 movne r0, #0x30000 @ pretend to be a 64k cart
934 m_m68k_read32_bcram: @ 0x600000 - 0x61ffff, not likely to be called
937 bl m_m68k_read8_bcram
941 bl m_m68k_read8_bcram
942 orr r0, r0, r3, lsl #16
946 m_m68k_read32_bcram_reg: @ 0x7fffff
947 bcram_reg_rw 1, 0x7ffffc
950 @ it is not very practical to use long access on hw registers, so I assume it is not used too much.
951 m_m68k_read32_system_io:
952 bic r1, r0, #0xfe0000
955 bne m_m68k_read32_misc
958 blt m_m68k_read32_misc
962 @ I have seen the range 0x0e-0x2f accessed quite frequently with long i/o, so here is some code for that
964 ldr r1, =(Pico+0x22200)
967 orr r2, r2, r2, lsl #16
968 add r1, r1, #0x110000
970 and r1, r2, r0 @ data is big-endian read as little, have to byteswap
971 and r0, r2, r0, lsr #8
972 orr r0, r0, r1, lsl #8
978 bl m_m68k_read16_system_io
980 bl m_m68k_read16_system_io
982 orr r0, r0, r1, lsl #16
989 bxne lr @ invalid read
997 orr r0, r0, r1, lsl #16
1003 bic r0, r0, #0xff0000
1010 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1015 m_m68k_write8_bcram_size: @ 0x400000
1019 m_m68k_write8_prgbank:
1020 ldr r2, =(Pico+0x22200)
1024 orr r3, r12, #0x002200
1027 and r3, r3, #0x00030000
1028 cmp r3, #0x00010000 @ have bus or in reset state?
1030 and r12,r12,#0xc0000000 @ r3 & 0xC0
1031 add r2, r2, r12, lsr #12
1036 m_m68k_write8_wordram0_2M: @ 0x200000 - 0x21ffff
1037 m_m68k_write8_wordram1_2M: @ 0x220000 - 0x23ffff
1038 ldr r2, =(Pico+0x22200)
1039 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
1046 m_m68k_write8_wordram0_1M_b0: @ 0x200000 - 0x21ffff
1047 ldr r2, =(Pico+0x22200)
1048 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
1055 m_m68k_write8_wordram0_1M_b1: @ 0x200000 - 0x21ffff
1056 ldr r2, =(Pico+0x22200)
1057 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
1064 m_m68k_write8_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
1067 ldr r2, =(Pico+0x22200)
1068 add r0, r0, #0x0c0000
1075 m_m68k_write8_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
1078 ldr r2, =(Pico+0x22200)
1079 add r0, r0, #0x0e0000
1086 m_m68k_write8_bcram: @ 0x600000 - 0x61ffff
1087 @ can't use r3 or r12, because of write32
1089 bic r0, r0, #0xfe0000
1093 add r0, r2, r0, lsr #1
1094 ldr r2, =(Pico+0x22200)
1097 add r2, r2, #0x110000
1098 add r2, r2, #0x002200
1100 tst r2, #1 @ check bcram reg
1105 strb r0, [r2, #0x0e] @ SRam.changed = 1
1109 m_m68k_write8_bcram_reg: @ 0x7fffff
1110 bcram_reg_rw 0, 0x7fffff
1113 m_m68k_write8_system_io:
1114 bic r2, r0, #0xfe0000
1131 orr r1, r1, r1, lsl #8 @ byte access gets mirrored
1137 bic r0, r0, #0xff0000
1143 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1146 m_m68k_write16_bios:
1147 m_m68k_write16_bcram_size: @ 0x400000
1151 m_m68k_write16_prgbank:
1152 ldr r2, =(Pico+0x22200)
1156 orr r3, r12, #0x002200
1159 and r3, r3, #0x00030000
1160 cmp r3, #0x00010000 @ have bus or in reset state?
1162 and r12,r12,#0xc0000000 @ r3 & 0xC0
1163 add r2, r2, r12, lsr #12
1168 m_m68k_write16_wordram0_2M: @ 0x200000 - 0x21ffff
1169 m_m68k_write16_wordram1_2M: @ 0x220000 - 0x23ffff
1170 ldr r2, =(Pico+0x22200)
1171 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
1178 m_m68k_write16_wordram0_1M_b0: @ 0x200000 - 0x21ffff
1179 ldr r2, =(Pico+0x22200)
1180 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
1187 m_m68k_write16_wordram0_1M_b1: @ 0x200000 - 0x21ffff
1188 ldr r2, =(Pico+0x22200)
1189 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
1196 m_m68k_write16_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
1197 @ Warning: write32 relies on NOT using r12 and and keeping data in r3
1200 ldr r1, =(Pico+0x22200)
1201 add r0, r0, #0x0c0000
1208 m_m68k_write16_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
1211 ldr r1, =(Pico+0x22200)
1212 add r0, r0, #0x0e0000
1219 @ m_m68k_write16_bcram: @ 0x600000 - 0x61ffff
1220 .equiv m_m68k_write16_bcram, m_m68k_write8_bcram
1223 m_m68k_write16_bcram_reg: @ 0x7fffff
1224 bcram_reg_rw 0, 0x7ffffe
1227 m_m68k_write16_system_io:
1229 bic r2, r0, #0xfe0000
1234 m_m68k_write16_regs:
1237 beq m_m68k_write16_regs_spec
1240 stmfd sp!,{r2,r3,lr}
1243 ldmfd sp!,{r0,r1,lr}
1246 m_m68k_write16_regs_spec: @ special case
1247 ldr r2, =(Pico+0x22200)
1248 ldr r3, =s68k_poll_adclk
1251 add r0, r0, #0x00000e
1253 strb r1, [r2, r0] @ if (a == 0xe) s68k_regs[0x0e] = d >> 8;
1259 ldr r0, =PicoCpuS68k
1260 str r1, [r0, #0x58] @ push s68k out of stopped state
1274 b SN76496Write @ lsb goes to 0x11
1279 bic r0, r0, #0xff0000
1285 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1288 m_m68k_write32_bios:
1289 m_m68k_write32_bcram_size: @ 0x400000
1293 m_m68k_write32_prgbank:
1294 ldr r2, =(Pico+0x22200)
1298 orr r3, r12, #0x002200
1301 and r3, r3, #0x00030000
1302 cmp r3, #0x00010000 @ have bus or in reset state?
1304 and r12,r12,#0xc0000000 @ r3 & 0xC0
1305 add r2, r2, r12, lsr #12
1310 m_m68k_write32_wordram0_2M: @ 0x200000 - 0x21ffff
1311 m_m68k_write32_wordram1_2M: @ 0x220000 - 0x23ffff
1312 ldr r2, =(Pico+0x22200)
1313 sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
1320 m_m68k_write32_wordram0_1M_b0: @ 0x200000 - 0x21ffff
1321 ldr r2, =(Pico+0x22200)
1322 sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
1329 m_m68k_write32_wordram0_1M_b1: @ 0x200000 - 0x21ffff
1330 ldr r2, =(Pico+0x22200)
1331 sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
1338 m_m68k_write32_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
1340 bne m_m68k_write32_wordram1_1M_b0_unal
1343 ldr r2, =(Pico+0x22200)
1344 add r0, r0, #0x0c0000
1350 m_m68k_write32_wordram1_1M_b0_unal:
1351 @ hopefully this doesn't happen too often
1355 bl m_m68k_write16_wordram1_1M_b0 @ must not trash r12 and keep data in r3
1359 b m_m68k_write16_wordram1_1M_b0
1362 m_m68k_write32_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
1364 bne m_m68k_write32_wordram1_1M_b1_unal
1367 ldr r2, =(Pico+0x22200)
1368 add r0, r0, #0x0e0000
1374 m_m68k_write32_wordram1_1M_b1_unal:
1378 bl m_m68k_write16_wordram1_1M_b1 @ same as above
1382 b m_m68k_write16_wordram1_1M_b1
1385 m_m68k_write32_bcram: @ 0x600000 - 0x61ffff, not likely to be called
1389 bl m_m68k_write8_bcram
1392 bl m_m68k_write8_bcram
1396 m_m68k_write32_bcram_reg: @ 0x7fffff
1397 bcram_reg_rw 0, 0x7ffffc
1401 @ it is not very practical to use long access on hw registers, so I assume it is not used too much.
1402 m_m68k_write32_system_io:
1403 bic r2, r0, #0xfe0000
1406 bne m_m68k_write32_misc
1411 bge m_m68k_write32_regs_comm
1413 bge m_m68k_write32_regs_spec @ hits the nasty comm reg qiurk
1416 stmfd sp!,{r0,r1,lr}
1429 ldmfd sp!,{r0,r1,lr}
1433 m_m68k_write32_regs_comm: @ Handle the 0x10-0x1f range
1434 ldr r0, =(Pico+0x22200)
1437 orr r3, r3, r3, lsl #16
1438 add r0, r0, #0x110000
1439 and r12,r3, r1, ror #16 @ data is big-endian to be written as little, have to byteswap
1440 and r1, r3, r1, ror #24
1441 orr r1, r1, r12,lsl #8 @ end of byteswap
1444 ldr r3, =s68k_poll_adclk
1446 movne r1, r1, lsr #16
1450 ldr r0, =PicoCpuS68k @ remove poll detected state for s68k
1456 m_m68k_write32_misc:
1458 stmfd sp!,{r0,r1,lr}
1461 ldmfd sp!,{r0,r1,lr}
1465 m_m68k_write32_regs_spec:
1467 stmfd sp!,{r0,r1,lr}
1469 bl m_m68k_write16_regs
1470 ldmfd sp!,{r0,r1,lr}
1472 b m_m68k_write16_regs
1481 moveq r0, r1, lsr #16
1482 beq SN76496Write @ which game is crazy enough to do that?
1483 stmfd sp!,{r0,r1,lr}
1486 ldmfd sp!,{r0,r1,lr}
1493 bic r0, r0, #0xff0000
1501 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1503 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1506 .macro m_s68k_read8_ram map_addr
1507 ldr r1, =(Pico+0x22200)
1511 add r0, r0, #\map_addr @ map to our address
1517 .macro m_s68k_read8_wordram_2M_decode map_addr
1518 ldr r2, =(Pico+0x22200)
1521 movs r0, r0, lsr #1 @ +4-6 <<16
1522 add r2, r2, #\map_addr @ map to our address
1524 movcc r0, r0, lsr #4
1530 m_s68k_read8_prg: @ 0x000000 - 0x07ffff
1531 m_s68k_read8_wordram_2M: @ 0x080000 - 0x0bffff
1532 m_s68k_read8_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1533 m_s68k_read8_ram 0x020000
1536 m_s68k_read8_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
1537 m_s68k_read8_wordram_2M_decode 0x080000 @ + ^ / 2
1540 m_s68k_read8_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
1541 m_s68k_read8_wordram_2M_decode 0x0a0000 @ + ^ / 2
1544 m_s68k_read8_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1548 m_s68k_read8_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1549 @ must not trash r3 and r12
1550 ldr r1, =(Pico+0x22200)
1553 bic r0, r0, #0xff0000
1554 bic r0, r0, #0x00e000
1555 add r1, r1, #0x110000
1556 add r1, r1, #0x000200
1562 @ must not trash r3 and r12
1563 ldr r1, =(Pico+0x22200)
1564 bic r0, r0, #0xff0000
1565 @ bic r0, r0, #0x008000
1568 orr r2, r2, #0x002200
1570 bge m_s68k_read8_pcm_ram
1574 orr r2, r2, #(0x48+8) @ pcm.ch + addr_offset
1577 ldr r1, [r1, r2, lsl #2]
1579 moveq r0, r1, lsr #PCM_STEP_SHIFT
1580 movne r0, r1, lsr #(PCM_STEP_SHIFT+8)
1584 m_s68k_read8_pcm_ram:
1587 add r1, r1, #0x100000 @ pcm_ram
1588 and r2, r2, #0x0f000000 @ bank
1589 add r1, r1, r2, lsr #12
1590 bic r0, r0, #0x00e000
1597 bic r0, r0, #0xff0000
1598 bic r0, r0, #0x008000
1603 cmp r2, #(0x30-0x0e)
1604 blo m_s68k_read8_comm
1607 ldrlo r2, =gfx_cd_read
1608 ldrhs r2, =s68k_reg_read16
1615 moveq r0, r0, lsr #8
1620 ldr r1, =(Pico+0x22200)
1622 add r1, r1, #0x110000
1627 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1630 .macro m_s68k_read16_ram map_addr
1631 ldr r1, =(Pico+0x22200)
1635 add r0, r0, #\map_addr @ map to our address
1641 .macro m_s68k_read16_wordram_2M_decode map_addr
1642 ldr r2, =(Pico+0x22200)
1645 mov r0, r0, lsr #1 @ +4-6 <<16
1646 add r2, r2, #\map_addr @ map to our address
1648 orr r0, r0, r0, lsl #4
1654 m_s68k_read16_prg: @ 0x000000 - 0x07ffff
1655 m_s68k_read16_wordram_2M: @ 0x080000 - 0x0bffff
1656 m_s68k_read16_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1657 m_s68k_read16_ram 0x020000
1660 m_s68k_read16_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
1661 m_s68k_read16_wordram_2M_decode 0x080000
1664 m_s68k_read16_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
1665 m_s68k_read16_wordram_2M_decode 0x0a0000
1668 m_s68k_read16_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1672 @ m_s68k_read16_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1673 @ bram is not meant to be accessed by words, does any game do this?
1674 .equiv m_s68k_read16_backup, m_s68k_read8_backup
1677 @ m_s68k_read16_pcm:
1678 @ pcm is on 8-bit bus, would this be same as byte access?
1679 .equiv m_s68k_read16_pcm, m_s68k_read8_pcm
1683 bic r0, r0, #0xff0000
1684 bic r0, r0, #0x008000
1685 bic r0, r0, #0x000001
1698 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1701 .macro m_s68k_read32_ram map_addr
1702 ldr r1, =(Pico+0x22200)
1706 add r0, r0, #\map_addr @ map to our address
1712 .macro m_s68k_read32_wordram_2M_decode map_addr
1713 ldr r2, =(Pico+0x22200)
1716 mov r0, r0, lsr #1 @ +4-6 <<16
1717 add r2, r2, #\map_addr @ map to our address
1720 ldrneb r0, [r2, #-1]
1722 orr r1, r1, r1, lsl #4
1724 orr r0, r0, r0, lsl #4
1726 orr r0, r0, r1, lsl #16
1731 m_s68k_read32_prg: @ 0x000000 - 0x07ffff
1732 m_s68k_read32_wordram_2M: @ 0x080000 - 0x0bffff
1733 m_s68k_read32_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1734 m_s68k_read32_ram 0x020000
1737 m_s68k_read32_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
1738 m_s68k_read32_wordram_2M_decode 0x080000
1741 m_s68k_read32_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
1742 m_s68k_read32_wordram_2M_decode 0x0a0000
1745 m_s68k_read32_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1749 m_s68k_read32_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1750 @ bram is not meant to be accessed by words, does any game do this?
1753 bl m_s68k_read8_backup @ must preserve r3 and r12
1757 bl m_s68k_read8_backup
1758 orr r0, r0, r3, lsl #16
1765 bl m_s68k_read8_pcm @ must preserve r3 and r12
1770 orr r0, r0, r3, lsl #16
1775 bic r0, r0, #0xff0000
1776 bic r0, r0, #0x008000
1777 bic r0, r0, #0x000001
1784 blo m_s68k_read32_regs_gfx
1790 orr r0, r0, r1, lsl #16
1794 m_s68k_read32_regs_gfx:
1800 orr r0, r0, r1, lsl #16
1805 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1808 .macro m_s68k_write8_ram map_addr
1809 ldr r2, =(Pico+0x22200)
1813 add r0, r0, #\map_addr @ map to our address
1819 .macro m_s68k_write8_2M_decode map_addr
1820 ldr r2, =(Pico+0x22200)
1823 movs r0, r0, lsr #1 @ +4-6 <<16
1824 add r2, r2, #\map_addr @ map to our address
1827 .macro m_s68k_write8_2M_decode_m0 map_addr @ mode off
1828 m_s68k_write8_2M_decode \map_addr
1831 movcc r1, r1, lsl #4
1835 cmp r0, r3 @ avoid writing if result is same
1840 .macro m_s68k_write8_2M_decode_m1 map_addr @ mode underwrite
1843 m_s68k_write8_2M_decode \map_addr
1845 movcc r1, r1, lsl #4
1856 .macro m_s68k_write8_2M_decode_m2 map_addr @ mode overwrite
1859 m_s68k_write8_2M_decode_m0 \map_addr @ same as in off mode
1864 m_s68k_write8_prg: @ 0x000000 - 0x07ffff
1865 ldr r2, =(Pico+0x22200)
1868 add r3, r0, #0x020000 @ map to our address
1869 add r12,r2, #0x110000
1871 and r12,r12,#0x00ff0000 @ wp
1877 m_s68k_write8_wordram_2M: @ 0x080000 - 0x0bffff
1878 m_s68k_write8_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
1879 m_s68k_write8_ram 0x020000
1882 m_s68k_write8_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
1883 m_s68k_write8_2M_decode_m0 0x080000
1885 m_s68k_write8_2M_decode_b0_m1:
1886 m_s68k_write8_2M_decode_m1 0x080000
1888 m_s68k_write8_2M_decode_b0_m2:
1889 m_s68k_write8_2M_decode_m2 0x080000
1891 m_s68k_write8_2M_decode_b1_m0:
1892 m_s68k_write8_2M_decode_m0 0x0a0000
1894 m_s68k_write8_2M_decode_b1_m1:
1895 m_s68k_write8_2M_decode_m1 0x0a0000
1897 m_s68k_write8_2M_decode_b1_m2:
1898 m_s68k_write8_2M_decode_m2 0x0a0000
1901 m_s68k_write8_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
1905 m_s68k_write8_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
1906 @ must not trash r3 and r12
1907 ldr r2, =(Pico+0x22200)
1910 bic r0, r0, #0xff0000
1911 bic r0, r0, #0x00e000
1912 add r2, r2, #0x110000
1913 add r2, r2, #0x000200
1917 strb r0, [r1, #0x0e] @ SRam.changed = 1
1922 bic r0, r0, #0xff0000
1924 movlt r0, r0, lsr #1
1930 m_s68k_write8_pcm_ram:
1931 ldr r3, =(Pico+0x22200)
1932 bic r0, r0, #0x00e000
1935 add r2, r3, #0x110000
1936 add r2, r2, #0x002200
1937 add r2, r2, #0x000040
1939 add r3, r3, #0x100000 @ pcm_ram
1940 and r2, r2, #0x0f000000 @ bank
1941 add r3, r3, r2, lsr #12
1947 bic r0, r0, #0xff0000
1948 bic r0, r0, #0x008000
1956 orr r1, r1, r1, lsl #8
1960 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1963 .macro m_s68k_write16_ram map_addr
1964 ldr r2, =(Pico+0x22200)
1968 add r0, r0, #\map_addr @ map to our address
1974 .macro m_s68k_write16_2M_decode map_addr
1975 ldr r2, =(Pico+0x22200)
1978 mov r0, r0, lsr #1 @ +4-6 <<16
1979 add r2, r2, #\map_addr @ map to our address
1982 .macro m_s68k_write16_2M_decode_m0 map_addr @ mode off
1983 m_s68k_write16_2M_decode \map_addr
1985 orr r1, r1, r1, lsr #4
1990 .macro m_s68k_write16_2M_decode_m1 map_addr @ mode underwrite
1991 bics r1, r1, #0xf000
1992 bicnes r1, r1, #0x00f0
1994 orr r1, r1, r1, lsr #4
1995 m_s68k_write16_2M_decode \map_addr
2007 .macro m_s68k_write16_2M_decode_m2 map_addr @ mode overwrite
2008 bics r1, r1, #0xf000
2009 bicnes r1, r1, #0x00f0
2011 orr r1, r1, r1, lsr #4
2012 m_s68k_write16_2M_decode \map_addr
2026 m_s68k_write16_prg: @ 0x000000 - 0x07ffff
2027 ldr r2, =(Pico+0x22200)
2030 add r3, r0, #0x020000 @ map to our address
2031 add r12,r2, #0x110000
2033 and r12,r12,#0x00ff0000 @ wp
2039 m_s68k_write16_wordram_2M: @ 0x080000 - 0x0bffff
2040 m_s68k_write16_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
2041 m_s68k_write16_ram 0x020000
2044 m_s68k_write16_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
2045 m_s68k_write16_2M_decode_m0 0x080000
2047 m_s68k_write16_2M_decode_b0_m1:
2048 m_s68k_write16_2M_decode_m1 0x080000
2050 m_s68k_write16_2M_decode_b0_m2:
2051 m_s68k_write16_2M_decode_m2 0x080000
2053 m_s68k_write16_2M_decode_b1_m0:
2054 m_s68k_write16_2M_decode_m0 0x0a0000
2056 m_s68k_write16_2M_decode_b1_m1:
2057 m_s68k_write16_2M_decode_m1 0x0a0000
2059 m_s68k_write16_2M_decode_b1_m2:
2060 m_s68k_write16_2M_decode_m2 0x0a0000
2063 m_s68k_write16_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
2064 m_s68k_write16_ram 0
2067 @ m_s68k_write16_backup:
2068 .equiv m_s68k_write16_backup, m_s68k_write8_backup
2071 @ m_s68k_write16_pcm:
2072 .equiv m_s68k_write16_pcm, m_s68k_write8_pcm
2075 m_s68k_write16_regs:
2076 bic r0, r0, #0xff0000
2077 bic r0, r0, #0x008000
2083 beq m_s68k_write16_regs_spec
2089 stmfd sp!,{r2,r3,lr}
2092 ldmfd sp!,{r0,r1,lr}
2095 m_s68k_write16_regs_spec: @ special case
2096 ldr r2, =(Pico+0x22200)
2099 add r0, r0, #0x00000f
2100 strb r1, [r2, r0] @ if (a == 0xe) s68k_regs[0xf] = d;
2104 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
2107 .macro m_s68k_write32_ram map_addr
2108 ldr r2, =(Pico+0x22200)
2112 add r0, r0, #\map_addr @ map to our address
2118 .macro m_s68k_write32_2M_decode map_addr
2119 ldr r2, =(Pico+0x22200)
2122 mov r0, r0, lsr #1 @ +4-6 <<16
2123 add r2, r2, #\map_addr @ map to our address
2126 .macro m_s68k_write32_2M_decode_m0 map_addr @ mode off
2127 m_s68k_write32_2M_decode \map_addr
2128 bic r1, r1, #0x000000f0
2129 bic r1, r1, #0x00f00000
2130 orr r1, r1, r1, lsr #4
2134 strneb r1, [r2, #-1]
2139 .macro m_s68k_write32_2M_decode_m1 map_addr @ mode underwrite
2140 bics r1, r1, #0x000000f0
2141 bicnes r1, r1, #0x0000f000
2142 bicnes r1, r1, #0x00f00000
2143 bicnes r1, r1, #0xf0000000
2145 orr r1, r1, r1, lsr #4
2146 m_s68k_write32_2M_decode \map_addr
2149 ldrneb r0, [r2, #-1]
2151 and r12,r1, #0x0000000f
2152 orr r0, r0, r3, lsl #16
2153 orrne r0, r0, #0x80000000 @ remember addr lsb bit
2157 andeq r12,r1, #0x000000f0
2160 andeq r12,r1, #0x000f0000
2163 andeq r12,r1, #0x00f00000
2166 strneb r0, [r2, #-1]
2173 .macro m_s68k_write32_2M_decode_m2 map_addr @ mode overwrite
2174 bics r1, r1, #0x000000f0
2175 bicnes r1, r1, #0x0000f000
2176 bicnes r1, r1, #0x00f00000
2177 bicnes r1, r1, #0xf0000000
2179 orr r1, r1, r1, lsr #4
2180 m_s68k_write32_2M_decode \map_addr
2183 ldrneb r0, [r2, #-1]
2185 orrne r1, r1, #0x80000000 @ remember addr lsb bit
2186 orr r0, r0, r3, lsl #16
2188 andeq r12,r0, #0x0000000f
2191 andeq r12,r0, #0x000000f0
2194 andeq r12,r0, #0x000f0000
2197 andeq r12,r0, #0x00f00000
2202 strneb r1, [r2, #-1]
2211 m_s68k_write32_prg: @ 0x000000 - 0x07ffff
2212 ldr r2, =(Pico+0x22200)
2215 add r3, r0, #0x020000 @ map to our address
2216 add r12,r2, #0x110000
2218 and r12,r12,#0x00ff0000 @ wp
2227 m_s68k_write32_wordram_2M: @ 0x080000 - 0x0bffff
2228 m_s68k_write32_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
2229 m_s68k_write32_ram 0x020000
2232 m_s68k_write32_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
2233 m_s68k_write32_2M_decode_m0 0x080000
2235 m_s68k_write32_2M_decode_b0_m1:
2236 m_s68k_write32_2M_decode_m1 0x080000
2238 m_s68k_write32_2M_decode_b0_m2:
2239 m_s68k_write32_2M_decode_m2 0x080000
2241 m_s68k_write32_2M_decode_b1_m0:
2242 m_s68k_write32_2M_decode_m0 0x0a0000
2244 m_s68k_write32_2M_decode_b1_m1:
2245 m_s68k_write32_2M_decode_m1 0x0a0000
2247 m_s68k_write32_2M_decode_b1_m2:
2248 m_s68k_write32_2M_decode_m2 0x0a0000
2251 m_s68k_write32_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
2252 m_s68k_write32_ram 0
2255 m_s68k_write32_backup:
2260 bl m_s68k_write8_backup @ must preserve r3 and r12
2264 b m_s68k_write8_backup
2268 bic r0, r0, #0xff0000
2270 blt m_s68k_write32_pcm_reg
2275 m_s68k_write32_pcm_ram:
2276 ldr r3, =(Pico+0x22200)
2277 bic r0, r0, #0x00e000
2280 add r2, r3, #0x110000
2281 add r2, r2, #0x002200
2282 add r2, r2, #0x000040
2284 add r3, r3, #0x100000 @ pcm_ram
2285 and r2, r2, #0x0f000000 @ bank
2286 add r3, r3, r2, lsr #12
2293 m_s68k_write32_pcm_reg:
2295 stmfd sp!,{r0,r1,lr}
2298 ldmfd sp!,{r0,r1,lr}
2303 m_s68k_write32_regs:
2304 bic r0, r0, #0xff0000
2305 bic r0, r0, #0x008000
2311 blo m_s68k_write32_regs_gfx
2314 beq m_s68k_write32_regs_spec @ hits 0x0f
2317 beq m_s68k_write32_regs_comm
2319 stmfd sp!,{r0,r1,lr}
2332 ldmfd sp!,{r0,r1,lr}
2336 m_s68k_write32_regs_gfx:
2337 stmfd sp!,{r0,r1,lr}
2340 ldmfd sp!,{r0,r1,lr}
2344 m_s68k_write32_regs_comm: @ Handle the 0x20-0x2f range
2345 ldr r2, =(Pico+0x22200)
2348 orr r3, r3, r3, lsl #16
2349 add r2, r2, #0x110000
2350 and r12,r3, r1, ror #16 @ data is big-endian to be written as little, have to byteswap
2351 and r1, r3, r1, ror #24
2352 orr r1, r1, r12,lsl #8 @ end of byteswap
2355 movne r1, r1, lsr #16
2359 m_s68k_write32_regs_spec:
2360 stmfd sp!,{r0,r1,lr}
2362 bl m_s68k_write16_regs
2363 ldmfd sp!,{r0,r1,lr}
2365 b m_s68k_write16_regs