4 static FILE *AsmFile=NULL;
\r
6 static int CycloneVer=0x0099; // Version number of library
\r
7 int *CyJump=NULL; // Jump table
\r
8 int ms=USE_MS_SYNTAX; // If non-zero, output in Microsoft ARMASM format
\r
9 const char * const Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2
\r
10 const char * const Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2
\r
11 int Cycles; // Current cycles for opcode
\r
12 int pc_dirty; // something changed PC during processing
\r
15 // opcodes often used by games
\r
16 static const unsigned short hot_opcodes[] = {
\r
19 0x51c8, // dbra Dn, $2
\r
20 0x4a38, // tst.b $0.w
\r
21 0xd040, // add.w Dn, Dn
\r
22 0x4a79, // tst.w $0.l
\r
23 0x0240, // andi.w #$0, D0
\r
24 0x2038, // move.l $0.w, D0
\r
25 0xb0b8, // cmp.l $0.w, D0
\r
27 0x30c0, // move.w D0, (A0)+
\r
28 0x3028, // move.w ($0,A0), D0
\r
29 0x0c40, // cmpi.w #$0, D0
\r
30 0x0c79, // cmpi.w #$0, $0.l
\r
33 0x3000, // move.w D0, D0
\r
34 0x0839, // btst #$0, $0.l
\r
35 0x7000, // moveq #$0, D0
\r
36 0x3040, // movea.w D0, A0
\r
37 0x0838, // btst #$0, $0.w
\r
38 0x4a39, // tst.b $0.l
\r
39 0x33d8, // move.w (A0)+, $0.l
\r
41 0xb038, // cmp.b $0.w, D0
\r
42 0x3039, // move.w $0.l, D0
\r
46 0x5e40, // addq.w #7, D0
\r
47 0x1039, // move.b $0.l, D0
\r
48 0x20c0, // move.l D0, (A0)+
\r
49 0x1018, // move.b (A0)+, D0
\r
50 0x30d0, // move.w (A0), (A0)+
\r
51 0x3080, // move.w D0, (A0)
\r
52 0x3018, // move.w (A0)+, D0
\r
53 0xc040, // and.w D0, D0
\r
54 0x3180, // move.w D0, (A0,D0.w)
\r
55 0x1198, // move.b (A0)+, (A0,D0.w)
\r
60 0x41f0, // lea (A0,D0.w), A0
\r
61 0x4a28, // tst.b ($0,A0)
\r
62 0x0828, // btst #$0, ($0,A0)
\r
63 0x0640, // addi.w #$0, D0
\r
64 0x10c0, // move.b D0, (A0)+
\r
65 0x10d8, // move.b (A0)+, (A0)+
\r
67 #define hot_opcode_count (int)(sizeof(hot_opcodes) / sizeof(hot_opcodes[0]))
\r
69 static int is_op_hot(int op)
\r
72 for (i = 0; i < hot_opcode_count; i++)
\r
73 if (op == hot_opcodes[i])
\r
78 void ot(const char *format, ...)
\r
83 // notaz: stop me from leaving newlines in the middle of format string
\r
84 // and generating bad code
\r
85 for(i=0, len=strlen(format); i < len && format[i] != '\n'; i++);
\r
86 if(i < len-1 && format[len-1] != '\n') printf("\nWARNING: possible improper newline placement:\n%s\n", format);
\r
88 if (format[0] == ' ' && format[1] == ' ' && format[2] != ' ' && format[2] != '.')
\r
91 va_start(valist,format);
\r
92 if (AsmFile) vfprintf(AsmFile,format,valist);
\r
98 if (ms) ot(" LTORG\n");
\r
99 else ot(" .ltorg\n");
\r
102 #if (CYCLONE_FOR_GENESIS == 2)
\r
103 // r12=ptr to tas in table, trashes r0,r1
\r
104 static void ChangeTAS(int norm)
\r
106 ot(" ldr r0,=Op4ad0%s\n",norm?"_":"");
\r
107 ot(" mov r1,#8\n");
\r
108 ot("setrtas_loop%i0%s ;@ 4ad0-4ad7\n",norm,ms?"":":");
\r
109 ot(" subs r1,r1,#1\n");
\r
110 ot(" str r0,[r12],#4\n");
\r
111 ot(" bne setrtas_loop%i0\n",norm);
\r
112 ot(" ldr r0,=Op4ad8%s\n",norm?"_":"");
\r
113 ot(" mov r1,#7\n");
\r
114 ot("setrtas_loop%i1%s ;@ 4ad8-4ade\n",norm,ms?"":":");
\r
115 ot(" subs r1,r1,#1\n");
\r
116 ot(" str r0,[r12],#4\n");
\r
117 ot(" bne setrtas_loop%i1\n",norm);
\r
118 ot(" ldr r0,=Op4adf%s\n",norm?"_":"");
\r
119 ot(" str r0,[r12],#4\n");
\r
120 ot(" ldr r0,=Op4ae0%s\n",norm?"_":"");
\r
121 ot(" mov r1,#7\n");
\r
122 ot("setrtas_loop%i2%s ;@ 4ae0-4ae6\n",norm,ms?"":":");
\r
123 ot(" subs r1,r1,#1\n");
\r
124 ot(" str r0,[r12],#4\n");
\r
125 ot(" bne setrtas_loop%i2\n",norm);
\r
126 ot(" ldr r0,=Op4ae7%s\n",norm?"_":"");
\r
127 ot(" str r0,[r12],#4\n");
\r
128 ot(" ldr r0,=Op4ae8%s\n",norm?"_":"");
\r
129 ot(" mov r1,#8\n");
\r
130 ot("setrtas_loop%i3%s ;@ 4ae8-4aef\n",norm,ms?"":":");
\r
131 ot(" subs r1,r1,#1\n");
\r
132 ot(" str r0,[r12],#4\n");
\r
133 ot(" bne setrtas_loop%i3\n",norm);
\r
134 ot(" ldr r0,=Op4af0%s\n",norm?"_":"");
\r
135 ot(" mov r1,#8\n");
\r
136 ot("setrtas_loop%i4%s ;@ 4af0-4af7\n",norm,ms?"":":");
\r
137 ot(" subs r1,r1,#1\n");
\r
138 ot(" str r0,[r12],#4\n");
\r
139 ot(" bne setrtas_loop%i4\n",norm);
\r
140 ot(" ldr r0,=Op4af8%s\n",norm?"_":"");
\r
141 ot(" str r0,[r12],#4\n");
\r
142 ot(" ldr r0,=Op4af9%s\n",norm?"_":"");
\r
143 ot(" str r0,[r12],#4\n");
\r
147 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
148 static void AddressErrorWrapper(char rw, const char *dataprg, int iw)
\r
150 ot("ExceptionAddressError_%c_%s%s\n", rw, dataprg, ms?"":":");
\r
151 ot(" ldr r1,[r7,#0x44]\n");
\r
152 ot(" mov r6,#0x%02x\n", iw);
\r
153 ot(" mov r11,r0\n");
\r
154 ot(" tst r1,#0x20\n");
\r
155 ot(" orrne r6,r6,#4\n");
\r
156 ot(" b ExceptionAddressError\n");
\r
163 #if MEMHANDLERS_NEED_PC
\r
165 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
170 static void PrintFramework()
\r
172 int state_flags_to_check = 1; // stopped
\r
174 state_flags_to_check |= 2; // tracing
\r
177 state_flags_to_check |= 0x10; // halted
\r
180 ot(";@ --------------------------- Framework --------------------------\n");
\r
181 if (ms) ot("CycloneRun\n");
\r
182 else ot("CycloneRun:\n");
\r
184 ot(" stmdb sp!,{r4-r8,r10,r11,lr}\n");
\r
186 ot(" mov r7,r0 ;@ r7 = Pointer to Cpu Context\n");
\r
187 ot(" ;@ r0-3 = Temporary registers\n");
\r
188 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");
\r
189 ot(" ldr r6,=CycloneJumpTab ;@ r6 = Opcode Jump table\n");
\r
190 ot(" ldr r5,[r7,#0x5c] ;@ r5 = Cycles\n");
\r
191 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");
\r
192 ot(" ;@ r8 = Current Opcode\n");
\r
193 ot(" ldr r1,[r7,#0x44] ;@ Get SR high T_S__III and irq level\n");
\r
194 ot(" mov r10,r10,lsl #28;@ r10 = Flags 0xf0000000, cpsr format\n");
\r
195 ot(" ;@ r11 = Source value / Memory Base\n");
\r
196 ot(" str r6,[r7,#0x54] ;@ make a copy to avoid literal pools\n");
\r
198 #if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE
\r
199 ot(" mov r2,#0\n");
\r
200 ot(" str r2,[r7,#0x98] ;@ clear custom CycloneEnd\n");
\r
202 ot(";@ CheckInterrupt:\n");
\r
203 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]
\r
204 ot(" beq NoInts0\n");
\r
205 ot(" cmp r0,#6 ;@ irq>6 ?\n");
\r
206 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");
\r
207 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");
\r
208 ot(" bgt CycloneDoInterrupt\n");
\r
209 ot("NoInts0%s\n", ms?"":":");
\r
211 ot(";@ Check if our processor is in special state\n");
\r
212 ot(";@ and jump to opcode handler if not\n");
\r
213 ot(" ldr r0,[r7,#0x58] ;@ state_flags\n");
\r
214 ot(" ldrh r8,[r4],#2 ;@ Fetch first opcode\n");
\r
215 ot(" tst r0,#0x%02x ;@ special state?\n", state_flags_to_check);
\r
216 ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
218 ot("CycloneSpecial%s\n", ms?"":":");
\r
220 ot(" tst r0,#2 ;@ tracing?\n");
\r
221 ot(" bne CycloneDoTrace\n");
\r
223 ot(";@ stopped or halted\n");
\r
224 ot(" mov r5,#0\n");
\r
225 ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");
\r
226 ot(" ldmia sp!,{r4-r8,r10,r11,pc} ;@ we are stopped, do nothing!\n");
\r
230 ot(";@ We come back here after execution\n");
\r
231 ot("CycloneEnd%s\n", ms?"":":");
\r
232 ot(" sub r4,r4,#2\n");
\r
233 ot("CycloneEndNoBack%s\n", ms?"":":");
\r
234 #if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE
\r
235 ot(" ldr r1,[r7,#0x98]\n");
\r
236 ot(" mov r10,r10,lsr #28\n");
\r
237 ot(" tst r1,r1\n");
\r
238 ot(" bxne r1 ;@ jump to alternative CycloneEnd\n");
\r
240 ot(" mov r10,r10,lsr #28\n");
\r
242 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");
\r
243 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
244 ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
245 ot(" ldmia sp!,{r4-r8,r10,r11,pc}\n");
\r
250 ot("CycloneInit%s\n", ms?"":":");
\r
251 #if COMPRESS_JUMPTABLE
\r
252 ot(";@ decompress jump table\n");
\r
253 ot(" ldr r12,=CycloneJumpTab\n");
\r
254 ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");
\r
255 ot(" ldr r1,[r0,#-4]\n");
\r
256 ot(" tst r1,r1\n");
\r
257 ot(" movne pc,lr ;@ already uncompressed\n");
\r
258 ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");
\r
259 ot("unc_loop%s\n", ms?"":":");
\r
260 ot(" ldrh r1,[r0],#2\n");
\r
261 ot(" and r2,r1,#0xf\n");
\r
262 ot(" bic r1,r1,#0xf\n");
\r
263 ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");
\r
264 ot(" cmp r2,#0xf\n");
\r
265 ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");
\r
266 ot(" tst r2,r2\n");
\r
267 ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");
\r
268 ot(" tst r2,r2\n");
\r
269 ot(" beq unc_finish ;@ done decompressing\n");
\r
270 ot(" tst r1,r1\n");
\r
271 ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");
\r
272 ot(" beq unc_loop\n");
\r
273 ot("unc_loop_in%s\n", ms?"":":");
\r
274 ot(" subs r2,r2,#1\n");
\r
275 ot(" str r1,[r12],#4\n");
\r
276 ot(" bgt unc_loop_in\n");
\r
277 ot(" b unc_loop\n");
\r
278 ot("unc_finish%s\n", ms?"":":");
\r
279 ot(" ldr r12,=CycloneJumpTab\n");
\r
280 ot(" ;@ set a-line and f-line handlers\n");
\r
281 ot(" add r0,r12,#0xa000*4\n");
\r
282 ot(" ldr r1,[r0,#4] ;@ a-line handler\n");
\r
283 ot(" ldr r3,[r0,#8] ;@ f-line handler\n");
\r
284 ot(" mov r2,#0x1000\n");
\r
285 ot("unc_fill3%s\n", ms?"":":");
\r
286 ot(" subs r2,r2,#1\n");
\r
287 ot(" str r1,[r0],#4\n");
\r
288 ot(" bgt unc_fill3\n");
\r
289 ot(" add r0,r12,#0xf000*4\n");
\r
290 ot(" mov r2,#0x1000\n");
\r
291 ot("unc_fill4%s\n", ms?"":":");
\r
292 ot(" subs r2,r2,#1\n");
\r
293 ot(" str r3,[r0],#4\n");
\r
294 ot(" bgt unc_fill4\n");
\r
298 ot(";@ do nothing\n");
\r
304 ot("CycloneReset%s\n", ms?"":":");
\r
305 ot(" stmfd sp!,{r7,lr}\n");
\r
306 ot(" mov r7,r0\n");
\r
307 ot(" mov r0,#0\n");
\r
308 ot(" str r0,[r7,#0x58] ;@ state_flags\n");
\r
309 ot(" str r0,[r7,#0x48] ;@ OSP\n");
\r
310 ot(" mov r1,#0x27 ;@ Supervisor mode\n");
\r
311 ot(" strb r1,[r7,#0x44] ;@ set SR high\n");
\r
312 ot(" strb r0,[r7,#0x47] ;@ IRQ\n");
\r
314 ot(" str r0,[r7,#0x3c] ;@ Stack pointer\n");
\r
315 ot(" mov r0,#0\n");
\r
316 ot(" str r0,[r7,#0x60] ;@ Membase\n");
\r
317 ot(" mov r0,#4\n");
\r
319 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
320 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
322 ot(" mov lr,pc\n");
\r
323 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
325 ot(" str r0,[r7,#0x40] ;@ PC + base\n");
\r
326 ot(" ldmfd sp!,{r7,pc}\n");
\r
330 // 68k: XNZVC, ARM: NZCV
\r
331 ot("CycloneSetSr%s\n", ms?"":":");
\r
332 ot(" mov r2,r1,lsr #8\n");
\r
333 // ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");
\r
334 // ot(" eor r3,r3,r2\n");
\r
335 // ot(" tst r3,#0x20\n");
\r
337 ot(" and r2,r2,#0xa7 ;@ only defined bits\n");
\r
339 ot(" and r2,r2,#0x27 ;@ only defined bits\n");
\r
341 ot(" strb r2,[r0,#0x44] ;@ set SR high\n");
\r
342 ot(" mov r2,r1,lsl #25\n");
\r
343 ot(" str r2,[r0,#0x4c] ;@ the X flag\n");
\r
344 ot(" bic r2,r1,#0xf3\n");
\r
345 ot(" tst r1,#1\n");
\r
346 ot(" orrne r2,r2,#2\n");
\r
347 ot(" tst r1,#2\n");
\r
348 ot(" orrne r2,r2,#1\n");
\r
349 ot(" strb r2,[r0,#0x46] ;@ flags\n");
\r
354 ot("CycloneGetSr%s\n", ms?"":":");
\r
355 ot(" ldrb r1,[r0,#0x46] ;@ flags\n");
\r
356 ot(" bic r2,r1,#0xf3\n");
\r
357 ot(" tst r1,#1\n");
\r
358 ot(" orrne r2,r2,#2\n");
\r
359 ot(" tst r1,#2\n");
\r
360 ot(" orrne r2,r2,#1\n");
\r
361 ot(" ldr r1,[r0,#0x4c] ;@ the X flag\n");
\r
362 ot(" tst r1,#0x20000000\n");
\r
363 ot(" orrne r2,r2,#0x10\n");
\r
364 ot(" ldrb r1,[r0,#0x44] ;@ the SR high\n");
\r
365 ot(" orr r0,r2,r1,lsl #8\n");
\r
370 ot("CyclonePack%s\n", ms?"":":");
\r
371 ot(" stmfd sp!,{r4,r5,lr}\n");
\r
372 ot(" mov r4,r0\n");
\r
373 ot(" mov r5,r1\n");
\r
374 ot(" mov r3,#16\n");
\r
375 ot(";@ 0x00-0x3f: DA registers\n");
\r
376 ot("c_pack_loop%s\n",ms?"":":");
\r
377 ot(" ldr r1,[r0],#4\n");
\r
378 ot(" subs r3,r3,#1\n");
\r
379 ot(" str r1,[r5],#4\n");
\r
380 ot(" bne c_pack_loop\n");
\r
381 ot(";@ 0x40: PC\n");
\r
382 ot(" ldr r0,[r4,#0x40] ;@ PC + Memory Base\n");
\r
383 ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");
\r
384 ot(" sub r0,r0,r1\n");
\r
385 ot(" str r0,[r5],#4\n");
\r
386 ot(";@ 0x44: SR\n");
\r
387 ot(" mov r0,r4\n");
\r
388 ot(" bl CycloneGetSr\n");
\r
389 ot(" strh r0,[r5],#2\n");
\r
390 ot(";@ 0x46: IRQ level\n");
\r
391 ot(" ldrb r0,[r4,#0x47]\n");
\r
392 ot(" strb r0,[r5],#2\n");
\r
393 ot(";@ 0x48: other SP\n");
\r
394 ot(" ldr r0,[r4,#0x48]\n");
\r
395 ot(" str r0,[r5],#4\n");
\r
396 ot(";@ 0x4c: CPU state flags\n");
\r
397 ot(" ldr r0,[r4,#0x58]\n");
\r
398 ot(" str r0,[r5],#4\n");
\r
399 ot(" ldmfd sp!,{r4,r5,pc}\n");
\r
403 ot("CycloneUnpack%s\n", ms?"":":");
\r
404 ot(" stmfd sp!,{r5,r7,lr}\n");
\r
405 ot(" mov r7,r0\n");
\r
406 ot(" movs r5,r1\n");
\r
407 ot(" beq c_unpack_do_pc\n");
\r
408 ot(" mov r3,#16\n");
\r
409 ot(";@ 0x00-0x3f: DA registers\n");
\r
410 ot("c_unpack_loop%s\n",ms?"":":");
\r
411 ot(" ldr r1,[r5],#4\n");
\r
412 ot(" subs r3,r3,#1\n");
\r
413 ot(" str r1,[r0],#4\n");
\r
414 ot(" bne c_unpack_loop\n");
\r
415 ot(";@ 0x40: PC\n");
\r
416 ot(" ldr r0,[r5],#4 ;@ PC\n");
\r
417 ot(" str r0,[r7,#0x40] ;@ handle later\n");
\r
418 ot(";@ 0x44: SR\n");
\r
419 ot(" ldrh r1,[r5],#2\n");
\r
420 ot(" mov r0,r7\n");
\r
421 ot(" bl CycloneSetSr\n");
\r
422 ot(";@ 0x46: IRQ level\n");
\r
423 ot(" ldrb r0,[r5],#2\n");
\r
424 ot(" strb r0,[r7,#0x47]\n");
\r
425 ot(";@ 0x48: other SP\n");
\r
426 ot(" ldr r0,[r5],#4\n");
\r
427 ot(" str r0,[r7,#0x48]\n");
\r
428 ot(";@ 0x4c: CPU state flags\n");
\r
429 ot(" ldr r0,[r5],#4\n");
\r
430 ot(" str r0,[r7,#0x58]\n");
\r
431 ot("c_unpack_do_pc%s\n",ms?"":":");
\r
432 ot(" ldr r0,[r7,#0x40] ;@ unbased PC\n");
\r
433 #if USE_CHECKPC_CALLBACK
\r
434 ot(" mov r1,#0\n");
\r
435 ot(" str r1,[r7,#0x60] ;@ Memory base\n");
\r
436 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
437 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
439 ot(" mov lr,pc\n");
\r
440 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
443 ot(" ldr r1,[r7,#0x60] ;@ Memory base\n");
\r
444 ot(" add r0,r0,r1 ;@ r0 = Memory Base + New PC\n");
\r
446 ot(" str r0,[r7,#0x40] ;@ PC + Memory Base\n");
\r
447 ot(" ldmfd sp!,{r5,r7,pc}\n");
\r
451 ot("CycloneFlushIrq%s\n", ms?"":":");
\r
452 ot(" ldr r1,[r0,#0x44] ;@ Get SR high T_S__III and irq level\n");
\r
453 ot(" mov r2,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]
\r
454 ot(" cmp r2,#6 ;@ irq>6 ?\n");
\r
455 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");
\r
456 ot(" cmple r2,r1 ;@ irq<=6: Is irq<=mask ?\n");
\r
457 ot(" movle r0,#0\n");
\r
458 ot(" bxle lr ;@ no ints\n");
\r
460 ot(" stmdb sp!,{r4,r5,r7,r8,r10,r11,lr}\n");
\r
461 ot(" mov r7,r0\n");
\r
462 ot(" mov r0,r2\n");
\r
463 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");
\r
464 ot(" mov r5,#0\n");
\r
465 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");
\r
466 ot(" mov r10,r10,lsl #28 ;@ r10 = Flags 0xf0000000, cpsr format\n");
\r
467 ot(" adr r2,CycloneFlushIrqEnd\n");
\r
468 ot(" str r2,[r7,#0x98] ;@ set custom CycloneEnd\n");
\r
469 ot(" b CycloneDoInterrupt\n");
\r
471 ot("CycloneFlushIrqEnd%s\n", ms?"":":");
\r
472 ot(" rsb r0,r5,#0\n");
\r
473 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");
\r
474 ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
475 ot(" ldmia sp!,{r4,r5,r7,r8,r10,r11,lr}\n");
\r
481 ot("CycloneSetRealTAS%s\n", ms?"":":");
\r
482 #if (CYCLONE_FOR_GENESIS == 2)
\r
483 ot(" ldr r12,=CycloneJumpTab\n");
\r
484 ot(" tst r0,r0\n");
\r
485 ot(" add r12,r12,#0x4a00*4\n");
\r
486 ot(" add r12,r12,#0x00d0*4\n");
\r
487 ot(" beq setrtas_off\n");
\r
490 ot("setrtas_off%s\n",ms?"":":");
\r
500 ot(";@ DoInterrupt - r0=IRQ level\n");
\r
501 ot("CycloneDoInterruptGoBack%s\n", ms?"":":");
\r
502 ot(" sub r4,r4,#2\n");
\r
503 ot("CycloneDoInterrupt%s\n", ms?"":":");
\r
504 ot(" bic r8,r8,#0xff000000\n");
\r
505 ot(" orr r8,r8,r0,lsl #29 ;@ abuse r8\n");
\r
507 // Steps are from "M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL", p. 6-4
\r
508 // but their order is based on http://pasti.fxatari.com/68kdocs/68kPrefetch.html
\r
509 // 1. Make a temporary copy of the status register and set the status register for exception processing.
\r
510 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");
\r
511 ot(" and r0,r0,#7\n");
\r
512 ot(" orr r3,r0,#0x20 ;@ Supervisor mode + IRQ level\n");
\r
513 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");
\r
514 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
515 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");
\r
517 ot(" str r2,[r7,#0x58]\n");
\r
518 ot(" ldrb r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");
\r
519 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");
\r
522 // 3. Save the current processor context.
\r
523 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");
\r
524 ot(" ldr r11,[r7,#0x3c] ;@ Get A7\n");
\r
525 ot(" tst r6,#0x20\n");
\r
526 ot(";@ get our SP:\n");
\r
527 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");
\r
528 ot(" streq r11,[r7,#0x48]\n");
\r
529 ot(" moveq r11,r2\n");
\r
530 ot(";@ Push old PC onto stack\n");
\r
531 ot(" sub r0,r11,#4 ;@ Predecremented A7\n");
\r
532 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");
\r
534 ot(";@ Push old SR:\n");
\r
535 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");
\r
536 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");
\r
537 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");
\r
538 ot(" tst r2,#1 ;@ 1 if C!=V\n");
\r
539 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");
\r
540 ot(" and r0,r0,#0x20000000\n");
\r
541 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");
\r
542 ot(" orr r1,r1,r6,lsl #8 ;@ Include old SR high\n");
\r
543 ot(" sub r0,r11,#6 ;@ Predecrement A7\n");
\r
544 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
545 MemHandler(1,1,0,0); // already checked for address error by prev MemHandler
\r
548 // 2. Obtain the exception vector.
\r
549 ot(" mov r11,r8,lsr #29\n");
\r
550 ot(" mov r0,r11\n");
\r
551 #if USE_INT_ACK_CALLBACK
\r
552 ot(";@ call IrqCallback if it is defined\n");
\r
553 #if INT_ACK_NEEDS_STUFF
\r
554 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
555 ot(" mov r1,r10,lsr #28\n");
\r
556 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
557 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
559 ot(" ldr r3,[r7,#0x8c] ;@ IrqCallback\n");
\r
560 ot(" add lr,pc,#4*3\n");
\r
561 ot(" tst r3,r3\n");
\r
562 ot(" streqb r3,[r7,#0x47] ;@ just clear IRQ if there is no callback\n");
\r
563 ot(" mvneq r0,#0 ;@ and simulate -1 return\n");
\r
565 #if INT_ACK_CHANGES_CYCLES
\r
566 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
568 ot(";@ get IRQ vector address:\n");
\r
569 ot(" cmn r0,#1 ;@ returned -1?\n");
\r
570 ot(" addeq r0,r11,#0x18 ;@ use autovector then\n");
\r
571 ot(" cmn r0,#2 ;@ returned -2?\n"); // should be safe as above add should never result in -2
\r
572 ot(" moveq r0,#0x18 ;@ use spurious interrupt then\n");
\r
573 #else // !USE_INT_ACK_CALLBACK
\r
574 ot(";@ Clear irq:\n");
\r
575 ot(" mov r2,#0\n");
\r
576 ot(" strb r2,[r7,#0x47]\n");
\r
577 ot(" add r0,r0,#0x18 ;@ use autovector\n");
\r
579 ot(" mov r0,r0,lsl #2 ;@ get vector address\n");
\r
581 ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");
\r
582 ot(";@ Read IRQ Vector:\n");
\r
583 MemHandler(0,2,0,0);
\r
584 ot(" tst r0,r0 ;@ uninitialized int vector?\n");
\r
585 ot(" moveq r0,#0x3c\n");
\r
586 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
587 ot(" bleq %sread32 ;@ Call read32(r0) handler\n", MEMHANDLERS_DIRECT_PREFIX);
\r
589 ot(" moveq lr,pc\n");
\r
590 ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");
\r
592 #if USE_CHECKPC_CALLBACK
\r
593 ot(" add lr,pc,#4\n");
\r
594 ot(" add r0,r0,r11 ;@ r0 = Memory Base + New PC\n");
\r
595 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
596 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
598 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
600 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
601 ot(" mov r4,r0\n");
\r
603 ot(" bic r4,r0,#1\n");
\r
606 ot(" add r4,r0,r11 ;@ r4 = Memory Base + New PC\n");
\r
607 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
608 ot(" bic r4,r4,#1\n");
\r
613 // 4. Obtain a new context and resume instruction processing.
\r
614 // note: the obtain part was already done in previous steps
\r
615 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
616 ot(" tst r4,#1\n");
\r
617 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
619 ot(" ldr r6,[r7,#0x54]\n");
\r
620 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");
\r
621 ot(" subs r5,r5,#44 ;@ Subtract cycles\n");
\r
622 ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
623 ot(" b CycloneEnd\n");
\r
627 // trashes all temp regs
\r
628 ot("Exception%s\n", ms?"":":");
\r
629 ot(" ;@ Cause an Exception - Vector number in r0\n");
\r
630 ot(" mov r11,lr ;@ Preserve ARM return address\n");
\r
631 ot(" bic r8,r8,#0xff000000\n");
\r
632 ot(" orr r8,r8,r0,lsl #24 ;@ abuse r8\n");
\r
634 // 1. Make a temporary copy of the status register and set the status register for exception processing.
\r
635 ot(" ldr r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");
\r
636 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");
\r
637 ot(" and r3,r6,#0x27 ;@ clear trace and unused flags\n");
\r
638 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");
\r
639 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");
\r
640 ot(" str r2,[r7,#0x58]\n");
\r
641 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");
\r
644 // 3. Save the current processor context.
\r
645 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");
\r
646 ot(" tst r6,#0x20\n");
\r
647 ot(";@ get our SP:\n");
\r
648 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");
\r
649 ot(" streq r0,[r7,#0x48]\n");
\r
650 ot(" moveq r0,r2\n");
\r
651 ot(";@ Push old PC onto stack\n");
\r
652 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");
\r
653 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");
\r
654 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
655 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");
\r
657 ot(";@ Push old SR:\n");
\r
658 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");
\r
659 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");
\r
660 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");
\r
661 ot(" tst r2,#1 ;@ 1 if C!=V\n");
\r
662 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");
\r
663 ot(" and r0,r0,#0x20000000\n");
\r
664 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");
\r
665 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
666 ot(" orr r1,r1,r6,lsl #8 ;@ Include SR high\n");
\r
667 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
668 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
669 MemHandler(1,1,0,0);
\r
672 // 2. Obtain the exception vector
\r
673 ot(";@ Read Exception Vector:\n");
\r
674 ot(" mov r0,r8,lsr #24\n");
\r
675 ot(" mov r0,r0,lsl #2\n");
\r
676 MemHandler(0,2,0,0);
\r
677 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");
\r
678 #if USE_CHECKPC_CALLBACK
\r
679 ot(" add lr,pc,#4\n");
\r
680 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");
\r
681 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
682 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
684 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
686 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
687 ot(" mov r4,r0\n");
\r
689 ot(" bic r4,r0,#1\n");
\r
692 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");
\r
693 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
694 ot(" bic r4,r4,#1\n");
\r
699 // 4. Resume execution.
\r
700 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
701 ot(" tst r4,#1\n");
\r
702 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
704 ot(" ldr r6,[r7,#0x54]\n");
\r
705 ot(" bx r11 ;@ Return\n");
\r
709 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
710 // first some wrappers: I see no point inlining this code,
\r
711 // as it will be executed in really rare cases.
\r
712 AddressErrorWrapper('r', "data", 0x11);
\r
713 AddressErrorWrapper('r', "prg", 0x12);
\r
714 AddressErrorWrapper('w', "data", 0x01);
\r
715 // there are no program writes
\r
716 // cpu space is only for bus errors?
\r
717 ot("ExceptionAddressError_r_prg_r4%s\n", ms?"":":");
\r
718 ot(" ldr r1,[r7,#0x44]\n");
\r
719 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");
\r
720 ot(" mov r6,#0x12\n");
\r
721 ot(" sub r11,r4,r3\n");
\r
722 ot(" tst r1,#0x20\n");
\r
723 ot(" orrne r6,r6,#4\n");
\r
726 ot("ExceptionAddressError%s\n", ms?"":":");
\r
727 ot(";@ r6 - info word (without instruction/not bit), r11 - faulting address\n");
\r
729 // 1. Make a temporary copy of the status register and set the status register for exception processing.
\r
730 ot(" ldrb r0,[r7,#0x44] ;@ Get old SR high\n");
\r
731 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");
\r
732 ot(" and r3,r0,#0x27 ;@ clear trace and unused flags\n");
\r
733 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");
\r
734 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");
\r
735 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");
\r
736 ot(" tst r2,#4\n");
\r
737 ot(" orrne r6,r6,#8 ;@ complete info word\n");
\r
738 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");
\r
740 ot(" tst r2,#8\n");
\r
741 ot(" orrne r2,r2,#0x10 ;@ HALT\n");
\r
742 ot(" orr r2,r2,#8 ;@ processing address error\n");
\r
743 ot(" str r2,[r7,#0x58]\n");
\r
744 ot(" movne r5,#0\n");
\r
745 ot(" bne CycloneEndNoBack ;@ bye bye\n");
\r
747 ot(" str r2,[r7,#0x58]\n");
\r
749 ot(" and r10,r10,#0xf0000000\n");
\r
750 ot(" orr r10,r10,r0,lsl #4 ;@ some preparations for SR push\n");
\r
753 // 3. Save the current processor context + additional information.
\r
754 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");
\r
755 ot(" tst r10,#0x200\n");
\r
756 ot(";@ get our SP:\n");
\r
757 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");
\r
758 ot(" streq r0,[r7,#0x48]\n");
\r
759 ot(" moveq r0,r2\n");
\r
761 ot(";@ Push old PC onto stack\n");
\r
762 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");
\r
763 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");
\r
764 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");
\r
765 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
766 MemHandler(1,2,0,EMULATE_HALT);
\r
768 ot(";@ Push old SR:\n");
\r
769 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");
\r
770 ot(" mov r1,r10,ror #28 ;@ ____NZCV\n");
\r
771 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");
\r
772 ot(" tst r2,#1 ;@ 1 if C!=V\n");
\r
773 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");
\r
774 ot(" and r0,r0,#0x20000000\n");
\r
775 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");
\r
776 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
777 ot(" and r10,r10,#0xf0000000\n");
\r
778 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
779 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
780 MemHandler(1,1,0,0);
\r
781 // IR (instruction register)
\r
782 ot(";@ Push IR:\n");
\r
783 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
784 ot(" mov r1,r8\n");
\r
785 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
786 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
787 MemHandler(1,1,0,0);
\r
789 ot(";@ Push address:\n");
\r
790 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
791 ot(" mov r1,r11\n");
\r
792 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");
\r
793 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
794 MemHandler(1,2,0,0);
\r
795 // information word
\r
796 ot(";@ Push info word:\n");
\r
797 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
798 ot(" mov r1,r6\n");
\r
799 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
800 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
801 MemHandler(1,1,0,0);
\r
804 // 2. Obtain the exception vector
\r
805 ot(";@ Read Exception Vector:\n");
\r
806 ot(" mov r0,#0x0c\n");
\r
807 MemHandler(0,2,0,0);
\r
808 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");
\r
809 #if USE_CHECKPC_CALLBACK
\r
810 ot(" add lr,pc,#4\n");
\r
811 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");
\r
812 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
813 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
815 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
817 ot(" mov r4,r0\n");
\r
819 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");
\r
823 #if EMULATE_ADDRESS_ERRORS_JUMP && EMULATE_HALT
\r
824 ot(" tst r4,#1\n");
\r
825 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
827 ot(" bic r4,r4,#1\n");
\r
830 // 4. Resume execution.
\r
831 ot(" ldr r6,[r7,#0x54]\n");
\r
832 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");
\r
833 ot(" subs r5,r5,#50 ;@ Subtract cycles\n");
\r
834 ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
835 ot(" b CycloneEnd\n");
\r
841 // expects srh and irq level in r1, next opcode already fetched to r8
\r
842 ot("CycloneDoTraceWithChecks%s\n", ms?"":":");
\r
843 ot(" ldr r0,[r7,#0x58]\n");
\r
844 ot(" cmp r5,#0\n");
\r
845 ot(" orr r0,r0,#2 ;@ go to trace mode\n");
\r
846 ot(" str r0,[r7,#0x58]\n");
\r
847 ot(" blt CycloneEnd\n"); // should take care of situation where we come here when already tracing
\r
848 ot(";@ CheckInterrupt:\n");
\r
849 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n");
\r
850 ot(" beq CycloneDoTrace\n");
\r
851 ot(" cmp r0,#6 ;@ irq>6 ?\n");
\r
852 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");
\r
853 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");
\r
854 ot(" bgt CycloneDoInterruptGoBack\n");
\r
857 // expects next opcode to be already fetched to r8
\r
858 ot("CycloneDoTrace%s\n", ms?"":":");
\r
859 ot(" str r5,[r7,#0x9c] ;@ save cycles\n");
\r
860 ot(" ldr r1,[r7,#0x98]\n");
\r
861 ot(" mov r5,#0\n");
\r
862 ot(" str r1,[r7,#0xa0]\n");
\r
863 ot(" adr r0,TraceEnd\n");
\r
864 ot(" str r0,[r7,#0x98] ;@ store TraceEnd as CycloneEnd hadler\n");
\r
865 ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
868 ot("TraceEnd%s\n", ms?"":":");
\r
869 ot(" ldr r2,[r7,#0x58]\n");
\r
870 ot(" ldr r0,[r7,#0x9c] ;@ restore cycles\n");
\r
871 ot(" ldr r1,[r7,#0xa0] ;@ old CycloneEnd handler\n");
\r
872 ot(" mov r10,r10,lsl #28\n");
\r
873 ot(" add r5,r0,r5\n");
\r
874 ot(" str r1,[r7,#0x98]\n");
\r
875 ot(";@ still tracing?\n"); // exception might have happend
\r
876 ot(" tst r2,#2\n");
\r
877 ot(" beq TraceDisabled\n");
\r
878 ot(";@ trace exception\n");
\r
879 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
880 ot(" ldr r1,[r7,#0x58]\n");
\r
881 ot(" mov r0,#9\n");
\r
882 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");
\r
883 ot(" str r1,[r7,#0x58]\n");
\r
885 ot(" mov r0,#9\n");
\r
887 ot(" bl Exception\n");
\r
888 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");
\r
889 ot(" subs r5,r5,#34 ;@ Subtract cycles\n");
\r
890 ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
891 ot(" b CycloneEnd\n");
\r
893 ot("TraceDisabled%s\n", ms?"":":");
\r
894 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");
\r
895 ot(" cmp r5,#0\n");
\r
896 ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
897 ot(" b CycloneEnd\n");
\r
902 // ---------------------------------------------------------------------------
\r
903 // Call Read(r0), Write(r0,r1) or Fetch(r0)
\r
904 // Trashes r0-r3,r12,lr
\r
905 int MemHandler(int type,int size,int addrreg,int need_addrerr_check)
\r
907 int func=0x68+type*0xc+(size<<2); // Find correct offset
\r
910 #if MEMHANDLERS_NEED_FLAGS
\r
911 ot(" mov r3,r10,lsr #28\n");
\r
912 ot(" strb r3,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
916 #if (MEMHANDLERS_ADDR_MASK & 0xff000000)
\r
917 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0xff000000);
\r
920 #if (MEMHANDLERS_ADDR_MASK & 0x00ff0000)
\r
921 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x00ff0000);
\r
924 #if (MEMHANDLERS_ADDR_MASK & 0x0000ff00)
\r
925 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x0000ff00);
\r
928 #if (MEMHANDLERS_ADDR_MASK & 0x000000ff)
\r
929 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x000000ff);
\r
933 #if EMULATE_ADDRESS_ERRORS_IO
\r
934 if (size > 0 && need_addrerr_check)
\r
936 ot(" add lr,pc,#4*%i\n", addrreg==0?2:3); // helps to prevent interlocks
\r
937 if (addrreg != 0) ot(" mov r0,r%i\n", addrreg);
\r
938 ot(" tst r0,#1 ;@ address error?\n");
\r
940 case 0: ot(" bne ExceptionAddressError_r_data\n"); break;
\r
941 case 1: ot(" bne ExceptionAddressError_w_data\n"); break;
\r
942 case 2: ot(" bne ExceptionAddressError_r_prg\n"); break;
\r
948 sprintf(what, "%s%d", type==0 ? "read" : (type==1 ? "write" : "fetch"), 8<<size);
\r
949 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
951 ot(" mov r0,r%i\n", addrreg);
\r
952 ot(" bl %s%s ;@ Call ", MEMHANDLERS_DIRECT_PREFIX, what);
\r
953 (void)func; // avoid warning
\r
957 ot(" add lr,pc,#4\n");
\r
958 ot(" mov r0,r%i\n", addrreg);
\r
961 ot(" mov lr,pc\n");
\r
962 ot(" ldr pc,[r7,#0x%x] ;@ Call ",func);
\r
965 // Document what we are calling:
\r
966 if (type==1) ot("%s(r0,r1)",what);
\r
967 else ot("%s(r0)", what);
\r
970 #if MEMHANDLERS_CHANGE_FLAGS
\r
971 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");
\r
972 ot(" mov r10,r10,lsl #28\n");
\r
974 #if MEMHANDLERS_CHANGE_PC
\r
975 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
981 static void PrintOpcodes()
\r
985 printf("Creating Opcodes: [");
\r
987 ot(";@ ---------------------------- Opcodes ---------------------------\n");
\r
989 // Emit null opcode:
\r
990 ot("Op____%s ;@ Called if an opcode is not recognised\n", ms?"":":");
\r
991 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
992 ot(" ldr r1,[r7,#0x58]\n");
\r
993 ot(" sub r4,r4,#2\n");
\r
994 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");
\r
995 ot(" str r1,[r7,#0x58]\n");
\r
997 ot(" sub r4,r4,#2\n");
\r
999 #if USE_UNRECOGNIZED_CALLBACK
\r
1000 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
1001 ot(" mov r1,r10,lsr #28\n");
\r
1002 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
1003 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
1004 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");
\r
1005 ot(" tst r11,r11\n");
\r
1006 ot(" movne lr,pc\n");
\r
1007 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");
\r
1008 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");
\r
1009 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
1010 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
1011 ot(" mov r10,r10,lsl #28\n");
\r
1012 ot(" tst r0,r0\n");
\r
1013 ot(" moveq r0,#4\n");
\r
1014 ot(" bleq Exception\n");
\r
1016 ot(" mov r0,#4\n");
\r
1017 ot(" bl Exception\n");
\r
1023 // Unrecognised a-line and f-line opcodes throw an exception:
\r
1024 ot("Op__al%s ;@ Unrecognised a-line opcode\n", ms?"":":");
\r
1025 ot(" sub r4,r4,#2\n");
\r
1026 #if USE_AFLINE_CALLBACK
\r
1027 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
1028 ot(" mov r1,r10,lsr #28\n");
\r
1029 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
1030 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
1031 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");
\r
1032 ot(" tst r11,r11\n");
\r
1033 ot(" movne lr,pc\n");
\r
1034 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");
\r
1035 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");
\r
1036 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
1037 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
1038 ot(" mov r10,r10,lsl #28\n");
\r
1039 ot(" tst r0,r0\n");
\r
1040 ot(" moveq r0,#0x0a\n");
\r
1041 ot(" bleq Exception\n");
\r
1043 ot(" mov r0,#0x0a\n");
\r
1044 ot(" bl Exception\n");
\r
1050 ot("Op__fl%s ;@ Unrecognised f-line opcode\n", ms?"":":");
\r
1051 ot(" sub r4,r4,#2\n");
\r
1052 #if USE_AFLINE_CALLBACK
\r
1053 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
1054 ot(" mov r1,r10,lsr #28\n");
\r
1055 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
1056 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
1057 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");
\r
1058 ot(" tst r11,r11\n");
\r
1059 ot(" movne lr,pc\n");
\r
1060 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");
\r
1061 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");
\r
1062 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
1063 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
1064 ot(" mov r10,r10,lsl #28\n");
\r
1065 ot(" tst r0,r0\n");
\r
1066 ot(" moveq r0,#0x0b\n");
\r
1067 ot(" bleq Exception\n");
\r
1069 ot(" mov r0,#0x0b\n");
\r
1070 ot(" bl Exception\n");
\r
1077 for (op=0;op<hot_opcode_count;op++)
\r
1078 OpAny(hot_opcodes[op]);
\r
1080 for (op=0;op<0x10000;op++)
\r
1082 if ((op&0xfff)==0) { printf("%x",op>>12); fflush(stdout); } // Update progress
\r
1084 if (!is_op_hot(op))
\r
1094 static void ott(const char *str, int par, const char *nl, int nlp, int counter, int size)
\r
1097 case 0: if((counter&7)==0) ot(ms?" dcb ":" .byte "); break;
\r
1098 case 1: if((counter&7)==0) ot(ms?" dcw ":" .hword "); break;
\r
1099 case 2: if((counter&7)==0) ot(ms?" dcd ":" .long "); break;
\r
1102 if((counter&7)==7) ot(nl,nlp); else ot(",");
\r
1105 static void PrintJumpTable()
\r
1107 int i=0,op=0,len=0;
\r
1109 ot(";@ -------------------------- Jump Table --------------------------\n");
\r
1111 // space for decompressed table
\r
1112 ot(ms?" area |.data|, data\n":" .data\n .align 4\n\n");
\r
1114 #if COMPRESS_JUMPTABLE
\r
1115 int handlers=0,reps=0,*indexes,ip,u,out;
\r
1116 // use some weird compression on the jump table
\r
1117 indexes=(int *)malloc(0x10000*4);
\r
1118 if(!indexes) { printf("ERROR: out of memory\n"); exit(1); }
\r
1121 ot("CycloneJumpTab%s\n", ms?"":":");
\r
1123 for(i = 0; i < 0xa000/8; i++)
\r
1124 ot(" dcd 0,0,0,0,0,0,0,0\n");
\r
1126 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", 0xa000/8);
\r
1128 // hanlers live in "a-line" part of the table
\r
1129 // first output nop,a-line,f-line handlers
\r
1130 ot(ms?" dcd Op____,Op__al,Op__fl,":" .long Op____,Op__al,Op__fl,");
\r
1133 for(i=0;i<len;i++)
\r
1137 for(u=i-1; u>=0; u--) if(op == CyJump[u]) break; // already done with this op?
\r
1138 if(u==-1 && op >= 0) {
\r
1139 ott("Op%.4x",op," ;@ %.4x\n",i,handlers,2);
\r
1140 indexes[op] = handlers;
\r
1145 fseek(AsmFile, -1, SEEK_CUR); // remove last comma
\r
1146 for(i = 8-(handlers&7); i > 0; i--)
\r
1151 for(i = (0x4000-handlers)/8; i > 0; i--)
\r
1152 ot(" dcd 0,0,0,0,0,0,0,0\n");
\r
1154 ot(ms?"":" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x4000-handlers)/8);
\r
1156 printf("total distinct hanlers: %i\n",handlers);
\r
1158 for(i=0,ip=0; i < 0xf000; i++, ip++) {
\r
1161 // it must skip a-line area, because we keep our data there
\r
1162 ott("0x%.4x", handlers<<4, "\n",0,ip++,1);
\r
1163 ott("0x%.4x", 0x1000, "\n",0,ip,1);
\r
1167 for(reps=1; i < 0xf000; i++, reps++) if(op != CyJump[i+1]) break;
\r
1168 if(op>=0) out=indexes[op]<<4; else out=0; // unrecognised
\r
1169 if(reps <= 0xe || reps==0x10) {
\r
1170 if(reps!=0x10) out|=reps; else out|=0xf; // 0xf means 0x10 (0xf appeared to be unused anyway)
\r
1171 ott("0x%.4x", out, "\n",0,ip,1);
\r
1173 ott("0x%.4x", out, "\n",0,ip++,1);
\r
1174 ott("0x%.4x", reps,"\n",0,ip,1);
\r
1177 if(ip&1) ott("0x%.4x", 0, "\n",0,ip++,1);
\r
1178 if(ip&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma
\r
1180 for(i = 8-(ip&7); i > 0; i--)
\r
1185 for(i = (0x2000-ip/2)/8+1; i > 0; i--)
\r
1186 ot(" dcd 0,0,0,0,0,0,0,0\n");
\r
1188 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x2000-ip/2)/8+1);
\r
1193 ot("CycloneJumpTab%s\n", ms?"":":");
\r
1194 len=0xfffe; // Hmmm, armasm 2.50.8684 messes up with a 0x10000 long jump table
\r
1195 // notaz: same thing with GNU as 2.9-psion-98r2 (reloc overflow)
\r
1196 // this is due to COFF objects using only 2 bytes for reloc count
\r
1198 for (i=0;i<len;i++)
\r
1202 if(op>=0) ott("Op%.4x",op," ;@ %.4x\n",i-7,i,2);
\r
1203 else if(op==-2) ott("Op__al",0, " ;@ %.4x\n",i-7,i,2);
\r
1204 else if(op==-3) ott("Op__fl",0, " ;@ %.4x\n",i-7,i,2);
\r
1205 else ott("Op____",0, " ;@ %.4x\n",i-7,i,2);
\r
1207 if(i&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma
\r
1210 ot(";@ notaz: we don't want to crash if we run into those 2 missing opcodes\n");
\r
1211 ot(";@ so we leave this pattern to patch it later\n");
\r
1212 ot("%s 0x78563412\n", ms?" dcd":" .long");
\r
1213 ot("%s 0x56341290\n", ms?" dcd":" .long");
\r
1217 static int CycloneMake()
\r
1220 const char *name="Cyclone.s";
\r
1221 const char *globl=ms?"export":".global";
\r
1223 // Open the assembly file
\r
1224 if (ms) name="Cyclone.asm";
\r
1225 AsmFile=fopen(name,"wt"); if (AsmFile==NULL) return 1;
\r
1227 printf("Making %s...\n",name);
\r
1229 ot("\n;@ Dave's Cyclone 68000 Emulator v%x.%.3x - Assembler Output\n\n",CycloneVer>>12,CycloneVer&0xfff);
\r
1231 ot(";@ (c) Copyright 2003 Dave, All rights reserved.\n");
\r
1232 ot(";@ some code (c) Copyright 2005-2007 notaz, All rights reserved.\n");
\r
1233 ot(";@ Cyclone 68000 is free for non-commercial use.\n\n");
\r
1234 ot(";@ For commercial use, separate licencing terms must be obtained.\n\n");
\r
1236 CyJump=(int *)malloc(0x40000); if (CyJump==NULL) return 1;
\r
1237 memset(CyJump,0xff,0x40000); // Init to -1
\r
1238 for(i=0xa000; i<0xb000; i++) CyJump[i] = -2; // a-line emulation
\r
1239 for(i=0xf000; i<0x10000; i++) CyJump[i] = -3; // f-line emulation
\r
1241 ot(ms?" area |.text|, code\n":" .text\n .align 4\n\n");
\r
1242 ot(" %s CycloneInit\n",globl);
\r
1243 ot(" %s CycloneReset\n",globl);
\r
1244 ot(" %s CycloneRun\n",globl);
\r
1245 ot(" %s CycloneSetSr\n",globl);
\r
1246 ot(" %s CycloneGetSr\n",globl);
\r
1247 ot(" %s CycloneFlushIrq\n",globl);
\r
1248 ot(" %s CyclonePack\n",globl);
\r
1249 ot(" %s CycloneUnpack\n",globl);
\r
1250 ot(" %s CycloneVer\n",globl);
\r
1251 #if (CYCLONE_FOR_GENESIS == 2)
\r
1252 ot(" %s CycloneSetRealTAS\n",globl);
\r
1253 ot(" %s CycloneDoInterrupt\n",globl);
\r
1254 ot(" %s CycloneDoTrace\n",globl);
\r
1255 ot(" %s CycloneJumpTab\n",globl);
\r
1256 ot(" %s Op____\n",globl);
\r
1257 ot(" %s Op6001\n",globl);
\r
1258 ot(" %s Op6601\n",globl);
\r
1259 ot(" %s Op6701\n",globl);
\r
1262 ot(ms?"CycloneVer dcd 0x":"CycloneVer: .long 0x");
\r
1263 ot("%.4x\n",CycloneVer);
\r
1269 printf("~%i ARM instructions used for opcode handlers\n", arm_op_count);
\r
1272 if (ms) ot(" END\n");
\r
1274 ot("\n\n;@ vim:filetype=armasm\n");
\r
1276 fclose(AsmFile); AsmFile=NULL;
\r
1279 printf("Assembling...\n");
\r
1280 // Assemble the file
\r
1281 if (ms) system("armasm Cyclone.asm");
\r
1282 else system("as -o Cyclone.o Cyclone.s");
\r
1283 printf("Done!\n\n");
\r
1292 printf("\n Dave's Cyclone 68000 Emulator v%x.%.3x - Core Creator\n\n",CycloneVer>>12,CycloneVer&0xfff);
\r
1294 // Make GAS or ARMASM version
\r