4 #if USE_CHECKPC_CALLBACK
\r
5 static void CheckPc()
\r
7 ot(";@ Check Memory Base+pc (r4)\n");
\r
8 ot(" add lr,pc,#4\n");
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10 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
16 // Push 32-bit value in r1 - trashes r0-r3,r12,lr
\r
19 ot(";@ Push r1 onto stack\n");
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20 ot(" ldr r0,[r7,#0x3c]\n");
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21 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");
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22 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
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27 // Push SR - trashes r0-r3,r12,lr
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28 void OpPushSr(int high)
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30 ot(";@ Push SR:\n");
\r
32 ot(" ldr r0,[r7,#0x3c]\n");
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33 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
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34 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
39 // Pop SR - trashes r0-r3
\r
40 static void PopSr(int high)
\r
43 ot(" ldr r0,[r7,#0x3c]\n");
\r
44 ot(" add r1,r0,#2 ;@ Postincrement A7\n");
\r
45 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");
\r
51 // Pop PC - assumes r10=Memory Base - trashes r0-r3
\r
55 ot(" ldr r0,[r7,#0x3c]\n");
\r
56 ot(" add r1,r0,#4 ;@ Postincrement A7\n");
\r
57 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");
\r
59 ot(" add r4,r0,r10 ;@ r4=Memory Base+PC\n");
\r
69 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
72 ot(" and r0,r8,#0xf ;@ Get trap number\n");
\r
73 ot(" orr r0,r0,#0x20\n");
\r
74 ot(" mov r0,r0,asl #2\n");
\r
75 ot(" bl Exception\n");
\r
83 // --------------------- Opcodes 0x4e50+ ---------------------
\r
91 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
97 EaCalc(10, 7, 8, 2, 1);
\r
98 EaRead(10, 1, 8, 2, 7, 1);
\r
101 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");
\r
102 ot(" sub r0,r0,#4 ;@ A7-=4\n");
\r
103 ot(" mov r11,r0\n");
\r
104 if(reg==7) ot(" mov r1,r0\n");
\r
107 ot(";@ Write An to Stack\n");
\r
110 ot(";@ Save to An\n");
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112 EaWrite(10,11, 8, 2, 7, 1);
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114 ot(";@ Get offset:\n");
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115 EaCalc(0,0,0x3c,1);
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116 EaRead(0,0,0x3c,1,0);
\r
118 ot(" add r11,r11,r0 ;@ Add offset to A7\n");
\r
119 ot(" str r11,[r7,#0x3c]\n");
\r
127 // --------------------- Opcodes 0x4e58+ ---------------------
\r
133 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
138 EaCalc(10, 7, 8, 2, 1);
\r
139 EaRead(10, 0, 8, 2, 7, 1);
\r
141 ot(" add r11,r0,#4 ;@ A7+=4\n");
\r
143 ot(";@ Pop An from stack:\n");
\r
146 ot(" str r11,[r7,#0x3c] ;@ Save A7\n");
\r
148 ot(";@ An = value from stack:\n");
\r
149 EaWrite(10, 0, 8, 2, 7, 1);
\r
156 // --------------------- Opcodes 0x4e70+ ---------------------
\r
161 type=op&7; // 01001110 01110ttt, reset/nop/stop/rte/rtd/rts/trapv/rtr
\r
172 OpStart(op); Cycles=20;
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175 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
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178 CheckInterrupt(op);
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184 OpStart(op); Cycles=16;
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185 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
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191 OpStart(op); Cycles=4;
\r
192 ot(" tst r9,#0x10000000\n");
\r
193 ot(" subne r5,r5,#%i\n",30);
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194 ot(" movne r0,#0x1c ;@ TRAPV exception\n");
\r
195 ot(" blne Exception\n");
\r
200 OpStart(op); Cycles=20;
\r
202 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
\r
212 // --------------------- Opcodes 0x4e80+ ---------------------
\r
213 // Emit a Jsr/Jmp opcode, 01001110 1meeeeee
\r
221 // See if we can do this opcode:
\r
222 if (EaCanRead(sea,-1)==0) return 1;
\r
225 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
229 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
\r
231 EaCalc(0,0x003f,sea,0);
\r
233 ot(";@ Jump - Get new PC from r0\n");
\r
236 // Jmp - Get new PC from r0
\r
237 ot(" add r4,r0,r10 ;@ r4 = Memory Base + New PC\n");
\r
242 ot(";@ Jsr - Push old PC first\n");
\r
243 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");
\r
244 ot(" add r4,r0,r10 ;@ r4 = Memory Base + New PC\n");
\r
245 ot(" mov r1,r1,lsl #8\n");
\r
246 ot(" ldr r0,[r7,#0x3c]\n");
\r
247 ot(" mov r1,r1,asr #8\n");
\r
248 ot(";@ Push r1 onto stack\n");
\r
249 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");
\r
250 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
255 #if USE_CHECKPC_CALLBACK
\r
259 Cycles=(op&0x40) ? 4 : 12;
\r
260 Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);
\r
267 // --------------------- Opcodes 0x50c8+ ---------------------
\r
269 // ARM version of 68000 condition codes:
\r
270 static char *Cond[16]=
\r
272 "", "", "hi","ls","cc","cs","ne","eq",
\r
273 "vc","vs","pl","mi","ge","lt","gt","le"
\r
276 // Emit a Dbra opcode, 0101cccc 11001nnn vv
\r
282 use=op&~7; // Use same handler
\r
285 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
290 ot(";@ Is the condition true?\n");
\r
291 if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");
\r
292 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
\r
293 if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000\n");
\r
294 ot(";@ If so, don't dbra\n");
\r
295 ot(" b%s DbraTrue%.4x\n",Cond[cc],op);
\r
299 ot(";@ Decrement Dn.w\n");
\r
300 ot(" and r1,r8,#0x0007\n");
\r
301 ot(" mov r1,r1,lsl #2\n");
\r
302 ot(" ldrsh r0,[r7,r1]\n");
\r
303 ot(" sub r0,r0,#1\n");
\r
304 ot(" strh r0,[r7,r1]\n");
\r
307 ot(";@ Check if Dn.w is -1\n");
\r
308 ot(" cmps r0,#-1\n");
\r
309 ot(" beq DbraMin1%.4x\n",op);
\r
312 ot(";@ Get Branch offset:\n");
\r
313 ot(" ldrsh r0,[r4]\n");
\r
314 ot(" add r4,r4,r0 ;@ r4 = New PC\n");
\r
319 ot(";@ Dn.w is -1:\n");
\r
320 ot("DbraMin1%.4x%s\n", op, ms?"":":");
\r
321 ot(" add r4,r4,#2 ;@ Skip branch offset\n");
\r
326 ot(";@ condition true:\n");
\r
327 ot("DbraTrue%.4x%s\n", op, ms?"":":");
\r
328 ot(" add r4,r4,#2 ;@ Skip branch offset\n");
\r
336 // --------------------- Opcodes 0x6000+ ---------------------
\r
337 // Emit a Branch opcode 0110cccc nn (cccc=condition)
\r
338 int OpBranch(int op)
\r
344 offset=(char)(op&0xff);
\r
347 // Special offsets:
\r
348 if (offset==0) size=1;
\r
349 if (offset==-1) size=2;
\r
351 if (size) use=op; // 16-bit or 32-bit
\r
352 else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches
\r
354 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
357 ot(";@ Get Branch offset:\n");
\r
360 EaCalc(0,0,0x3c,size);
\r
361 EaRead(0,0,0x3c,size,0);
\r
364 // above code messes cycles
\r
365 Cycles=10; // Assume branch taken
\r
367 if (size==0) ot(" mov r0,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");
\r
369 if (cc==1) ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
\r
373 ot(";@ Is the condition true?\n");
\r
374 if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");
\r
375 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
\r
376 if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000\n");
\r
378 if (size==0) ot(" mov r0,r0,asr #24 ;@ ...shift down\n\n");
\r
380 ot(" b%s DontBranch%.4x\n",Cond[cc^1],op);
\r
386 if (size==0) ot(" mov r0,r0,asr #24 ;@ ...shift down\n\n");
\r
389 ot(";@ Branch taken - Add on r0 to PC\n");
\r
393 ot(";@ Bsr - remember old PC\n");
\r
394 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");
\r
395 ot(" mov r1,r1, lsl #8\n");
\r
396 ot(" mov r1,r1, asr #8\n");
\r
398 if (size) ot(" sub r4,r4,#%d ;@ (Branch is relative to Opcode+2)\n",1<<size);
\r
399 ot(" ldr r2,[r7,#0x3c]\n");
\r
400 ot(" add r4,r4,r0 ;@ r4 = New PC\n");
\r
401 ot(";@ Push r1 onto stack\n");
\r
402 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");
\r
403 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
406 Cycles=18; // always 18
\r
410 if (size) ot(" sub r4,r4,#%d ;@ (Branch is relative to Opcode+2)\n",1<<size);
\r
411 ot(" add r4,r4,r0 ;@ r4 = New PC\n");
\r
415 #if USE_CHECKPC_CALLBACK
\r
416 if (offset==0 || offset==-1)
\r
418 ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");
\r
427 ot("DontBranch%.4x%s\n", op, ms?"":":");
\r
428 Cycles+=(size==1)? 2 : -2; // Branch not taken
\r