4 // in/out address in r0, trashes all temp regs
\r
5 static void CheckPc(void)
\r
7 #if USE_CHECKPC_CALLBACK
\r
8 ot(";@ Check Memory Base+pc\n");
\r
10 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
15 // Push 32-bit value in r1 - trashes r0-r3,r12,lr
\r
18 ot(";@ Push r1 onto stack\n");
\r
19 ot(" ldr r0,[r7,#0x3c]\n");
\r
20 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");
\r
21 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
26 // Push SR - trashes r0-r3,r12,lr
\r
27 void OpPushSr(int high)
\r
29 ot(";@ Push SR:\n");
\r
31 ot(" ldr r0,[r7,#0x3c]\n");
\r
32 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
33 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
38 // Pop SR - trashes r0-r3
\r
39 static void PopSr(int high)
\r
42 ot(" ldr r0,[r7,#0x3c]\n");
\r
43 ot(" add r1,r0,#2 ;@ Postincrement A7\n");
\r
44 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");
\r
50 // Pop PC - assumes r10=Memory Base - trashes r0-r3
\r
54 ot(" ldr r0,[r7,#0x3c]\n");
\r
55 ot(" add r1,r0,#4 ;@ Postincrement A7\n");
\r
56 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");
\r
58 ot(" add r0,r0,r10 ;@ Memory Base+PC\n");
\r
61 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
64 ot(" bic r4,r0,#1\n");
\r
73 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
76 ot(" and r0,r8,#0xf ;@ Get trap number\n");
\r
77 ot(" orr r0,r0,#0x20 ;@ 32+n\n");
\r
78 ot(" bl Exception\n");
\r
81 Cycles=38; OpEnd(0x10);
\r
86 // --------------------- Opcodes 0x4e50+ ---------------------
\r
94 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
100 EaCalc(10, 7, 8, 2, 1);
\r
101 EaRead(10, 1, 8, 2, 7, 1);
\r
104 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");
\r
105 ot(" sub r0,r0,#4 ;@ A7-=4\n");
\r
106 ot(" mov r11,r0\n");
\r
107 if(reg==7) ot(" mov r1,r0\n");
\r
110 ot(";@ Write An to Stack\n");
\r
113 ot(";@ Save to An\n");
\r
115 EaWrite(10,11, 8, 2, 7, 1);
\r
117 ot(";@ Get offset:\n");
\r
118 EaCalc(0,0,0x3c,1);
\r
119 EaRead(0,0,0x3c,1,0);
\r
121 ot(" add r11,r11,r0 ;@ Add offset to A7\n");
\r
122 ot(" str r11,[r7,#0x3c]\n");
\r
130 // --------------------- Opcodes 0x4e58+ ---------------------
\r
136 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
141 EaCalc(10, 0xf, 8, 2, 1);
\r
142 EaRead(10, 0, 8, 2, 0xf, 1);
\r
144 ot(" add r11,r0,#4 ;@ A7+=4\n");
\r
146 ot(";@ Pop An from stack:\n");
\r
149 ot(" str r11,[r7,#0x3c] ;@ Save A7\n");
\r
151 ot(";@ An = value from stack:\n");
\r
152 EaWrite(10, 0, 8, 2, 7, 1);
\r
159 // --------------------- Opcodes 0x4e70+ ---------------------
\r
160 // 01001110 01110ttt
\r
165 type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr
\r
176 OpStart(op,0x10,0,0,1); Cycles=20;
\r
178 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
\r
180 ot(" ldr r1,[r7,#0x44] ;@ reload SR high\n");
\r
182 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO || EMULATE_HALT
\r
183 ot(" ldr r1,[r7,#0x58]\n");
\r
184 ot(" bic r1,r1,#0x0c ;@ clear 'not processing instruction' and 'doing addr error' bits\n");
\r
185 ot(" str r1,[r7,#0x58]\n");
\r
187 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
188 ot(" tst r4,#1 ;@ address error?\n");
\r
189 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
191 opend_check_interrupt = 1;
\r
192 opend_check_trace = 1;
\r
197 OpStart(op,0x10); Cycles=16;
\r
198 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
\r
200 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
201 ot(" tst r4,#1 ;@ address error?\n");
\r
202 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
208 OpStart(op,0x10,0,1); Cycles=4;
\r
209 ot(" tst r9,#0x10000000\n");
\r
210 ot(" subne r5,r5,#%i\n",34);
\r
211 ot(" movne r0,#7 ;@ TRAPV exception\n");
\r
212 ot(" blne Exception\n");
\r
213 opend_op_changes_cycles = 1;
\r
218 OpStart(op,0x10); Cycles=20;
\r
220 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
\r
222 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
223 ot(" tst r4,#1 ;@ address error?\n");
\r
224 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
234 // --------------------- Opcodes 0x4e80+ ---------------------
\r
235 // Emit a Jsr/Jmp opcode, 01001110 1meeeeee
\r
243 // See if we can do this opcode:
\r
244 if (EaCanRead(sea,-1)==0) return 1;
\r
247 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
249 OpStart(op,(op&0x40)?0:0x10);
\r
251 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
\r
253 EaCalc(11,0x003f,sea,0);
\r
255 ot(";@ Jump - Get new PC from r11\n");
\r
256 ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");
\r
261 ot(" ldr r2,[r7,#0x3c]\n");
\r
262 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");
\r
264 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
265 // jsr prefetches next instruction before pushing old PC,
\r
266 // according to http://pasti.fxatari.com/68kdocs/68kPrefetch.html
\r
267 ot(" mov r4,r0\n");
\r
268 ot(" tst r4,#1 ;@ address error?\n");
\r
269 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
271 ot(" bic r4,r0,#1\n");
\r
276 ot(";@ Push old PC onto stack\n");
\r
277 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");
\r
278 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
282 Cycles=(op&0x40) ? 4 : 12;
\r
283 Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);
\r
285 OpEnd((op&0x40)?0:0x10);
\r
290 // --------------------- Opcodes 0x50c8+ ---------------------
\r
292 // ARM version of 68000 condition codes:
\r
293 static char *Cond[16]=
\r
295 "", "", "hi","ls","cc","cs","ne","eq",
\r
296 "vc","vs","pl","mi","ge","lt","gt","le"
\r
299 // Emit a Dbra opcode, 0101cccc 11001nnn vv
\r
305 use=op&~7; // Use same handler
\r
308 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
317 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");
\r
318 ot(" beq DbraTrue\n\n");
\r
321 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");
\r
322 ot(" bne DbraTrue\n\n");
\r
325 ot(";@ Is the condition true?\n");
\r
326 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
\r
327 ot(";@ If so, don't dbra\n");
\r
328 ot(" b%s DbraTrue\n\n",Cond[cc]);
\r
334 ot(";@ Decrement Dn.w\n");
\r
335 ot(" and r1,r8,#0x0007\n");
\r
336 ot(" mov r1,r1,lsl #2\n");
\r
337 ot(" ldrsh r0,[r7,r1]\n");
\r
338 ot(" sub r0,r0,#1\n");
\r
339 ot(" strh r0,[r7,r1]\n");
\r
342 ot(";@ Check if Dn.w is -1\n");
\r
343 ot(" cmn r0,#1\n");
\r
345 #if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP
\r
346 ot(" beq DbraMin1\n");
\r
349 ot(";@ Get Branch offset:\n");
\r
350 ot(" ldrsh r0,[r4]\n");
\r
351 ot(" add r0,r4,r0 ;@ r0 = New PC\n");
\r
353 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
354 ot(" mov r4,r0\n");
\r
355 ot(" tst r4,#1 ;@ address error?\n");
\r
356 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
358 ot(" bic r4,r0,#1\n");
\r
362 ot(";@ Get Branch offset:\n");
\r
363 ot(" ldrnesh r0,[r4]\n");
\r
364 ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");
\r
365 ot(" subeq r5,r5,#4 ;@ additional cycles\n");
\r
366 ot(" addne r4,r4,r0 ;@ r4 = New PC\n");
\r
367 ot(" bic r4,r4,#1\n"); // we do not emulate address errors
\r
374 //if (cc==0||cc>=2)
\r
377 ot(";@ condition true:\n");
\r
378 ot("DbraTrue%s\n", ms?"":":");
\r
379 ot(" add r4,r4,#2 ;@ Skip branch offset\n");
\r
385 #if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP
\r
388 ot(";@ Dn.w is -1:\n");
\r
389 ot("DbraMin1%s\n", ms?"":":");
\r
390 ot(" add r4,r4,#2 ;@ Skip branch offset\n");
\r
400 // --------------------- Opcodes 0x6000+ ---------------------
\r
401 // Emit a Branch opcode 0110cccc nn (cccc=condition)
\r
402 int OpBranch(int op)
\r
404 int size=0,use=0,checkpc=0;
\r
409 offset=(char)(op&0xff);
\r
412 // Special offsets:
\r
413 if (offset==0) size=1;
\r
414 if (offset==-1) size=2;
\r
416 if (size==2) size=0; // 000 model does not support long displacement
\r
417 if (size) use=op; // 16-bit or 32-bit
\r
418 else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches
\r
420 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
421 OpStart(op,size?0x10:0);
\r
422 Cycles=10; // Assume branch taken
\r
424 if (cc==1) ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
\r
432 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");
\r
433 ot(" bne BccDontBranch%i\n\n",8<<size);
\r
436 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");
\r
437 ot(" beq BccDontBranch%i\n\n",8<<size);
\r
440 ot(";@ Is the condition true?\n");
\r
441 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
\r
442 ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);
\r
450 ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");
\r
454 ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");
\r
455 ot(" ldrh r11,[r4,#2]\n");
\r
456 ot(" orr r11,r11,r2,lsl #16\n");
\r
461 ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");
\r
462 asr_r11=",asr #24";
\r
465 ot(";@ Branch taken - Add on r0 to PC\n");
\r
469 ot(";@ Bsr - remember old PC\n");
\r
470 ot(" ldr r2,[r7,#0x3c]\n");
\r
471 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");
\r
472 if (size) ot(" add r1,r1,#%d\n",1<<size);
\r
474 ot(";@ Push r1 onto stack\n");
\r
475 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");
\r
476 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
479 Cycles=18; // always 18
\r
482 ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);
\r
484 #if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8
\r
485 if (offset!=0 && offset!=-1) checkpc=1;
\r
487 #if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16
\r
488 if (offset==0) checkpc=1;
\r
490 #if USE_CHECKPC_CALLBACK
\r
491 if (offset==-1) checkpc=1;
\r
493 if (checkpc) CheckPc();
\r
494 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
495 ot(" mov r4,r0\n");
\r
496 ot(" tst r4,#1 ;@ address error?\n");
\r
497 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
499 ot(" bic r4,r0,#1\n");
\r
503 OpEnd(size?0x10:0);
\r
505 // since all "DontBranch" code is same for every size, output only once
\r
506 if (cc>=2&&(op&0xff00)==0x6200)
\r
508 ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");
\r
509 if (size) ot(" add r4,r4,#%d\n",1<<size);
\r
510 Cycles+=(size==1) ? 2 : -2; // Branch not taken
\r