4 static void CheckPc(int reg)
\r
6 #if USE_CHECKPC_CALLBACK
\r
7 ot(";@ Check Memory Base+pc (r4)\n");
\r
9 ot(" mov r0,r%i\n", reg);
\r
11 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
14 ot(" bic r4,r%d,#1\n",reg); // we do not emulate address errors
\r
19 // Push 32-bit value in r1 - trashes r0-r3,r12,lr
\r
22 ot(";@ Push r1 onto stack\n");
\r
23 ot(" ldr r0,[r7,#0x3c]\n");
\r
24 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");
\r
25 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
30 // Push SR - trashes r0-r3,r12,lr
\r
31 void OpPushSr(int high)
\r
33 ot(";@ Push SR:\n");
\r
35 ot(" ldr r0,[r7,#0x3c]\n");
\r
36 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
37 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
42 // Pop SR - trashes r0-r3
\r
43 static void PopSr(int high)
\r
46 ot(" ldr r0,[r7,#0x3c]\n");
\r
47 ot(" add r1,r0,#2 ;@ Postincrement A7\n");
\r
48 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");
\r
54 // Pop PC - assumes r10=Memory Base - trashes r0-r3
\r
58 ot(" ldr r0,[r7,#0x3c]\n");
\r
59 ot(" add r1,r0,#4 ;@ Postincrement A7\n");
\r
60 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");
\r
62 ot(" add r0,r0,r10 ;@ Memory Base+PC\n");
\r
72 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
75 ot(" and r0,r8,#0xf ;@ Get trap number\n");
\r
76 ot(" orr r0,r0,#0x20\n");
\r
77 ot(" mov r0,r0,asl #2\n");
\r
78 ot(" bl Exception\n");
\r
81 Cycles=38; OpEnd(0x10);
\r
86 // --------------------- Opcodes 0x4e50+ ---------------------
\r
94 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
100 EaCalc(10, 7, 8, 2, 1);
\r
101 EaRead(10, 1, 8, 2, 7, 1);
\r
104 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");
\r
105 ot(" sub r0,r0,#4 ;@ A7-=4\n");
\r
106 ot(" mov r11,r0\n");
\r
107 if(reg==7) ot(" mov r1,r0\n");
\r
110 ot(";@ Write An to Stack\n");
\r
113 ot(";@ Save to An\n");
\r
115 EaWrite(10,11, 8, 2, 7, 1);
\r
117 ot(";@ Get offset:\n");
\r
118 EaCalc(0,0,0x3c,1);
\r
119 EaRead(0,0,0x3c,1,0);
\r
121 ot(" add r11,r11,r0 ;@ Add offset to A7\n");
\r
122 ot(" str r11,[r7,#0x3c]\n");
\r
130 // --------------------- Opcodes 0x4e58+ ---------------------
\r
136 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
141 EaCalc(10, 0xf, 8, 2, 1);
\r
142 EaRead(10, 0, 8, 2, 0xf, 1);
\r
144 ot(" add r11,r0,#4 ;@ A7+=4\n");
\r
146 ot(";@ Pop An from stack:\n");
\r
149 ot(" str r11,[r7,#0x3c] ;@ Save A7\n");
\r
151 ot(";@ An = value from stack:\n");
\r
152 EaWrite(10, 0, 8, 2, 7, 1);
\r
159 // --------------------- Opcodes 0x4e70+ ---------------------
\r
160 // 01001110 01110ttt
\r
165 type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr
\r
176 OpStart(op,0x10); Cycles=20;
\r
179 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
\r
182 CheckInterrupt(op);
\r
187 OpStart(op,0x10); Cycles=16;
\r
188 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
\r
194 OpStart(op,0x10); Cycles=4;
\r
195 ot(" tst r9,#0x10000000\n");
\r
196 ot(" subne r5,r5,#%i\n",34);
\r
197 ot(" movne r0,#0x1c ;@ TRAPV exception\n");
\r
198 ot(" blne Exception\n");
\r
203 OpStart(op,0x10); Cycles=20;
\r
205 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
\r
215 // --------------------- Opcodes 0x4e80+ ---------------------
\r
216 // Emit a Jsr/Jmp opcode, 01001110 1meeeeee
\r
224 // See if we can do this opcode:
\r
225 if (EaCanRead(sea,-1)==0) return 1;
\r
228 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
230 OpStart(op,(op&0x40)?0:0x10);
\r
232 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
\r
234 EaCalc(11,0x003f,sea,0);
\r
236 ot(";@ Jump - Get new PC from r0\n");
\r
239 // Jmp - Get new PC from r11
\r
240 ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");
\r
245 ot(";@ Jsr - Push old PC first\n");
\r
246 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");
\r
247 ot(" mov r1,r1,lsl #8\n");
\r
248 ot(" ldr r0,[r7,#0x3c]\n");
\r
249 ot(" mov r1,r1,asr #8\n");
\r
250 ot(";@ Push r1 onto stack\n");
\r
251 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");
\r
252 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
254 ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");
\r
260 Cycles=(op&0x40) ? 4 : 12;
\r
261 Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);
\r
263 OpEnd((op&0x40)?0:0x10);
\r
268 // --------------------- Opcodes 0x50c8+ ---------------------
\r
270 // ARM version of 68000 condition codes:
\r
271 static char *Cond[16]=
\r
273 "", "", "hi","ls","cc","cs","ne","eq",
\r
274 "vc","vs","pl","mi","ge","lt","gt","le"
\r
277 // Emit a Dbra opcode, 0101cccc 11001nnn vv
\r
283 use=op&~7; // Use same handler
\r
286 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
295 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");
\r
296 ot(" beq DbraTrue\n\n");
\r
299 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");
\r
300 ot(" bne DbraTrue\n\n");
\r
303 ot(";@ Is the condition true?\n");
\r
304 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
\r
305 ot(";@ If so, don't dbra\n");
\r
306 ot(" b%s DbraTrue\n\n",Cond[cc]);
\r
312 ot(";@ Decrement Dn.w\n");
\r
313 ot(" and r1,r8,#0x0007\n");
\r
314 ot(" mov r1,r1,lsl #2\n");
\r
315 ot(" ldrsh r0,[r7,r1]\n");
\r
316 ot(" sub r0,r0,#1\n");
\r
317 ot(" strh r0,[r7,r1]\n");
\r
320 ot(";@ Check if Dn.w is -1\n");
\r
321 ot(" cmn r0,#1\n");
\r
323 #if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA
\r
324 ot(" beq DbraMin1\n");
\r
327 ot(";@ Get Branch offset:\n");
\r
328 ot(" ldrsh r0,[r4]\n");
\r
329 ot(" add r0,r4,r0 ;@ r4 = New PC\n");
\r
333 ot(";@ Get Branch offset:\n");
\r
334 ot(" ldrnesh r0,[r4]\n");
\r
335 ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");
\r
336 ot(" subeq r5,r5,#4 ;@ additional cycles\n");
\r
337 ot(" addne r4,r4,r0 ;@ r4 = New PC\n");
\r
338 ot(" bic r4,r4,#1\n"); // we do not emulate address errors
\r
345 //if (cc==0||cc>=2)
\r
348 ot(";@ condition true:\n");
\r
349 ot("DbraTrue%s\n", ms?"":":");
\r
350 ot(" add r4,r4,#2 ;@ Skip branch offset\n");
\r
356 #if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA
\r
359 ot(";@ Dn.w is -1:\n");
\r
360 ot("DbraMin1%s\n", ms?"":":");
\r
361 ot(" add r4,r4,#2 ;@ Skip branch offset\n");
\r
371 // --------------------- Opcodes 0x6000+ ---------------------
\r
372 // Emit a Branch opcode 0110cccc nn (cccc=condition)
\r
373 int OpBranch(int op)
\r
375 int size=0,use=0,checkpc=0;
\r
380 offset=(char)(op&0xff);
\r
383 // Special offsets:
\r
384 if (offset==0) size=1;
\r
385 if (offset==-1) size=2;
\r
387 if (size==2) size=0; // 000 model does not support long displacement
\r
388 if (size) use=op; // 16-bit or 32-bit
\r
389 else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches
\r
391 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
392 OpStart(op,size?0x10:0);
\r
393 Cycles=10; // Assume branch taken
\r
395 if (cc==1) ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");
\r
403 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");
\r
404 ot(" bne BccDontBranch%i\n\n",8<<size);
\r
407 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");
\r
408 ot(" beq BccDontBranch%i\n\n",8<<size);
\r
411 ot(";@ Is the condition true?\n");
\r
412 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
\r
413 ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);
\r
421 ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");
\r
425 ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");
\r
426 ot(" ldrh r11,[r4,#2]\n");
\r
427 ot(" orr r11,r11,r2,lsl #16\n");
\r
432 ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");
\r
433 asr_r11=",asr #24";
\r
436 ot(";@ Branch taken - Add on r0 to PC\n");
\r
440 ot(";@ Bsr - remember old PC\n");
\r
441 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");
\r
442 if (size) ot(" add r1,r1,#%d\n",1<<size);
\r
443 ot(" mov r1,r1, lsl #8\n");
\r
444 ot(" ldr r2,[r7,#0x3c]\n");
\r
445 ot(" mov r1,r1, asr #8\n");
\r
447 ot(";@ Push r1 onto stack\n");
\r
448 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");
\r
449 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
452 Cycles=18; // always 18
\r
455 ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);
\r
457 #if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8
\r
458 if (offset!=0 && offset!=-1) checkpc=1;
\r
460 #if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16
\r
461 if (offset==0) checkpc=1;
\r
463 #if USE_CHECKPC_CALLBACK
\r
464 if (offset==-1) checkpc=1;
\r
472 ot(" bic r4,r0,#1\n"); // we do not emulate address errors
\r
476 OpEnd(size?0x10:0);
\r
478 // since all "DontBranch" code is same for every size, output only once
\r
479 if (cc>=2&&(op&0xff00)==0x6200)
\r
481 ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");
\r
482 if (size) ot(" add r4,r4,#%d\n",1<<size);
\r
483 Cycles+=(size==1) ? 2 : -2; // Branch not taken
\r