3 // --------------------- Opcodes 0x0100+ ---------------------
\r
4 // Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa
\r
5 int OpBtstReg(int op)
\r
8 int type=0,sea=0,tea=0;
\r
11 type=(op>>6)&3; // Btst/Bchg/Bclr/Bset
\r
12 // Get source and target EA
\r
15 if (tea<0x10) size=2; // For registers, 32-bits
\r
17 if ((tea&0x38)==0x08) return 1; // movep
\r
19 // See if we can do this opcode:
\r
20 if (EaCanRead(tea,0)==0) return 1;
\r
23 if (EaCanWrite(tea)==0) return 1;
\r
27 use&=~0x0e00; // Use same handler for all registers
\r
28 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
32 if(type==1||type==3) {
\r
36 if(size>=2) Cycles+=2;
\r
39 EaCalc (0,0x0e00,sea,0);
\r
40 EaRead (0, 0,sea,0,0x0e00);
\r
42 ot(" and r10,r0,#7 ;@ mem - do mod 8\n");
\r
43 else ot(" and r10,r0,#31 ;@ reg - do mod 32\n");
\r
46 EaCalc(11,0x003f,tea,size);
\r
47 EaRead(11, 0,tea,size,0x003f);
\r
49 ot(" tst r0,r1,lsl r10 ;@ Do arithmetic\n");
\r
50 ot(" bicne r9,r9,#0x40000000\n");
\r
51 ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");
\r
56 if (type==1) ot(" eor r1,r0,r1,lsl r10 ;@ Toggle bit\n");
\r
57 if (type==2) ot(" bic r1,r0,r1,lsl r10 ;@ Clear bit\n");
\r
58 if (type==3) ot(" orr r1,r0,r1,lsl r10 ;@ Set bit\n");
\r
60 EaWrite(11, 1,tea,size,0x003f);
\r
67 // --------------------- Opcodes 0x0800+ ---------------------
\r
68 // Emit a Btst/Bchg/Bclr/Bset (Immediate) opcode 00001000 ttaaaaaa nn
\r
69 int OpBtstImm(int op)
\r
71 int type=0,sea=0,tea=0;
\r
76 // Get source and target EA
\r
79 if (tea<0x10) size=2; // For registers, 32-bits
\r
81 // See if we can do this opcode:
\r
82 if (EaCanRead(tea,0)==0||EaAn(tea)||tea==0x3c) return 1;
\r
85 if (EaCanWrite(tea)==0) return 1;
\r
89 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
93 ot(" mov r10,#1\n");
\r
95 EaCalc ( 0,0x0000,sea,0);
\r
96 EaRead ( 0, 0,sea,0,0);
\r
97 ot(" bic r9,r9,#0x40000000 ;@ Blank Z flag\n");
\r
99 ot(" and r0,r0,#7 ;@ mem - do mod 8\n");
\r
100 else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n");
\r
101 ot(" mov r10,r10,lsl r0 ;@ Make bit mask\n");
\r
104 if(type==1||type==3) {
\r
108 if(size>=2) Cycles+=2;
\r
111 EaCalc (11,0x003f,tea,size);
\r
112 EaRead (11, 0,tea,size,0x003f);
\r
113 ot(" tst r0,r10 ;@ Do arithmetic\n");
\r
114 ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");
\r
119 if (type==1) ot(" eor r1,r0,r10 ;@ Toggle bit\n");
\r
120 if (type==2) ot(" bic r1,r0,r10 ;@ Clear bit\n");
\r
121 if (type==3) ot(" orr r1,r0,r10 ;@ Set bit\n");
\r
123 EaWrite(11, 1,tea,size,0x003f);
\r
131 // --------------------- Opcodes 0x4000+ ---------------------
\r
134 // 01000tt0 xxeeeeee (tt=negx/clr/neg/not, xx=size, eeeeee=EA)
\r
135 int type=0,size=0,ea=0,use=0;
\r
139 size=(op>>6)&3; if (size>=3) return 1;
\r
141 // See if we can do this opcode:
\r
142 if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;
\r
143 if (EaCanWrite(ea )==0) return 1;
\r
146 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
148 OpStart(op); Cycles=size<2?4:6;
\r
151 #ifdef CYCLONE_FOR_GENESIS
\r
152 // This is same as in Starscream core, CLR uses only 6 cycles for memory EAs.
\r
153 // May be this is similar case as with TAS opcode, but this time the dummy
\r
154 // read is ignored somehow? Without this hack Fatal Rewind hangs even in Gens.
\r
155 if(type==1&&size<2) Cycles-=2;
\r
159 EaCalc (10,0x003f,ea,size);
\r
161 if (type!=1) EaRead (10,0,ea,size,0x003f); // Don't need to read for 'clr'
\r
162 if (type==1) ot("\n");
\r
168 if(size!=2) ot(" mov r0,r0,lsl #%i\n",size?16:24);
\r
169 ot(" rscs r1,r0,#0 ;@ do arithmetic\n");
\r
170 ot(" orr r3,r9,#0xb0000000 ;@ for old Z\n");
\r
173 ot(" movs r1,r1,asr #%i\n",size?16:24);
\r
174 ot(" orreq r9,r9,#0x40000000 ;@ possily missed Z\n");
\r
176 ot(" andeq r9,r9,r3 ;@ fix Z\n");
\r
183 ot(" mov r1,#0\n");
\r
184 ot(" mov r9,#0x40000000 ;@ NZCV=0100\n");
\r
191 if(size!=2) ot(" mov r0,r0,lsl #%i\n",size?16:24);
\r
192 ot(" rsbs r1,r0,#0\n");
\r
194 if(size!=2) ot(" mov r1,r1,asr #%i\n",size?16:24);
\r
201 ot(" mvn r1,r0\n");
\r
202 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
\r
207 EaWrite(10, 1,ea,size,0x003f);
\r
214 // --------------------- Opcodes 0x4840+ ---------------------
\r
215 // Swap, 01001000 01000nnn swap Dn
\r
221 use=op&~0x0007; // Use same opcode for all An
\r
223 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
225 OpStart(op); Cycles=4;
\r
227 EaCalc (10,0x0007,ea,2,1);
\r
228 EaRead (10, 0,ea,2,0x0007,1);
\r
230 ot(" mov r1,r0,ror #16\n");
\r
231 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
\r
234 EaWrite(10, 1,8,2,0x0007,1);
\r
241 // --------------------- Opcodes 0x4a00+ ---------------------
\r
242 // Emit a Tst opcode, 01001010 xxeeeeee
\r
249 size=(op>>6)&3; if (size>=3) return 1;
\r
251 // See if we can do this opcode:
\r
252 if (EaCanWrite(sea)==0||EaAn(sea)) return 1;
\r
255 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
257 OpStart(op); Cycles=4;
\r
259 EaCalc ( 0,0x003f,sea,size,1);
\r
260 EaRead ( 0, 0,sea,size,0x003f,1);
\r
262 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
\r
263 ot(" mrs r9,cpsr ;@ r9=flags\n");
\r
270 // --------------------- Opcodes 0x4880+ ---------------------
\r
271 // Emit an Ext opcode, 01001000 1x000nnn
\r
280 shift=32-(8<<size);
\r
283 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
285 OpStart(op); Cycles=4;
\r
287 EaCalc (10,0x0007,ea,size+1);
\r
288 EaRead (10, 0,ea,size+1,0x0007);
\r
290 ot(" mov r0,r0,asl #%d\n",shift);
\r
291 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
\r
292 ot(" mrs r9,cpsr ;@ r9=flags\n");
\r
293 ot(" mov r1,r0,asr #%d\n",shift);
\r
296 EaWrite(10, 1,ea,size+1,0x0007);
\r
302 // --------------------- Opcodes 0x50c0+ ---------------------
\r
303 // Emit a Set cc opcode, 0101cccc 11eeeeee
\r
310 "al","", "hi","ls","cc","cs","ne","eq",
\r
311 "vc","vs","pl","mi","ge","lt","gt","le"
\r
317 if ((ea&0x38)==0x08) return 1; // dbra, not scc
\r
319 // See if we can do this opcode:
\r
320 if (EaCanWrite(ea)==0) return 1;
\r
323 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
325 OpStart(op); Cycles=8;
\r
326 if (ea<8) Cycles=4;
\r
328 ot(" mov r1,#0\n");
\r
332 ot(";@ Is the condition true?\n");
\r
333 if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");
\r
334 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
\r
335 if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");
\r
336 ot(" mvn%s r1,r1\n",cond[cc]);
\r
339 if (cc!=1 && ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);
\r
342 EaCalc (0,0x003f, ea,size);
\r
343 EaWrite(0, 1, ea,size,0x003f);
\r
349 // Emit a Asr/Lsr/Roxr/Ror opcode
\r
350 static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
\r
352 char pct[8]=""; // count
\r
353 int shift=32-(8<<size);
\r
355 if (count>=1) sprintf(pct,"#%d",count); // Fixed count
\r
359 ot(";@ Use Dn for count:\n");
\r
360 ot(" and r2,r8,#7<<9\n");
\r
361 ot(" ldr r2,[r7,r2,lsr #7]\n");
\r
362 ot(" and r2,r2,#63\n");
\r
368 ot(" mov r2,r8,lsr #9 ;@ Get 'n'\n");
\r
369 ot(" and r2,r2,#7\n\n"); strcpy(pct,"r2");
\r
372 // Take 2*n cycles:
\r
373 if (count<0) ot(" sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");
\r
374 else Cycles+=count<<1;
\r
379 if (dir==0 && size<2)
\r
381 ot(";@ For shift right, use loworder bits for the operation:\n");
\r
382 ot(" mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));
\r
386 if (type==0 && dir) ot(" mov r3,r0 ;@ save old value for V flag calculation\n");
\r
388 ot(";@ Shift register:\n");
\r
389 if (type==0) ot(" movs r0,r0,%s %s\n",dir?"asl":"asr",pct);
\r
390 if (type==1) ot(" movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);
\r
392 if (dir==0 && size<2)
\r
394 ot(";@ restore after right shift:\n");
\r
395 ot(" mov r0,r0,lsl #%d\n",32-(8<<size));
\r
400 if (usereg) { // store X only if count is not 0
\r
401 ot(" cmp %s,#0 ;@ shifting by 0?\n",pct);
\r
402 ot(" biceq r9,r9,#0x20000000 ;@ if so, clear carry\n");
\r
403 ot(" movne r1,r9,lsr #28\n");
\r
404 ot(" strneb r1,[r7,#0x45] ;@ else Save X bit\n");
\r
406 // count will never be 0 if we use immediate
\r
407 ot(" mov r1,r9,lsr #28\n");
\r
408 ot(" strb r1,[r7,#0x45] ;@ Save X bit\n");
\r
411 if (type==0 && dir) {
\r
412 ot(";@ calculate V flag (set if sign bit changes at anytime):\n");
\r
413 ot(" mov r1,#0x80000000\n");
\r
414 ot(" ands r3,r3,r1,asr %s\n", pct);
\r
415 ot(" cmpne r3,r1,asr %s\n", pct);
\r
416 ot(" biceq r9,r9,#0x10000000\n");
\r
417 ot(" orrne r9,r9,#0x10000000\n");
\r
423 // --------------------------------------
\r
432 ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);
\r
433 ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));
\r
436 ot(" movs r0,r0,rrx\n");
\r
439 ot(" ldrb r3,[r7,#0x45]\n");
\r
440 ot(" movs r0,r0,lsl #1\n");
\r
442 ot(" tst r3,#2\n");
\r
443 ot(" orrne r0,r0,#0x%x\n", 1<<(32-wide));
\r
444 ot(" bicne r9,r9,#0x40000000 ;@ clear Z in case it got there\n");
\r
446 ot(" bic r9,r9,#0x10000000 ;@ make suve V is clear\n");
\r
452 ot(";@ Reduce r2 until <0:\n");
\r
453 ot("Reduce_%.4x%s\n",op,ms?"":":");
\r
454 ot(" subs r2,r2,#%d\n",wide+1);
\r
455 ot(" bpl Reduce_%.4x\n",op);
\r
456 ot(" adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);
\r
457 ot(" beq norotx%.4x\n",op);
\r
461 if (usereg||count < 0)
\r
463 if (dir) ot(" rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);
\r
467 if (dir) ot(" mov r2,#%d ;@ Reversed\n",wide+1-count);
\r
468 else ot(" mov r2,#%d\n",count);
\r
471 if (shift) ot(" mov r0,r0,lsr #%d ;@ Shift down\n",shift);
\r
473 ot(";@ Rotate bits:\n");
\r
474 ot(" mov r3,r0,lsr r2 ;@ Get right part\n");
\r
475 ot(" rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);
\r
476 ot(" movs r0,r0,lsl r2 ;@ Get left part\n");
\r
477 ot(" orr r0,r3,r0 ;@ r0=Rotated value\n");
\r
479 ot(";@ Insert X bit into r2-1:\n");
\r
480 ot(" ldrb r3,[r7,#0x45]\n");
\r
481 ot(" sub r2,r2,#1\n");
\r
482 ot(" and r3,r3,#2\n");
\r
483 ot(" mov r3,r3,lsr #1\n");
\r
484 ot(" orr r0,r0,r3,lsl r2\n");
\r
487 if (shift) ot(" movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);
\r
488 OpGetFlags(0,!usereg);
\r
490 ot(" tst r0,r0\n");
\r
491 ot(" bicne r9,r9,#0x40000000 ;@ make sure we didn't mess Z\n");
\r
493 if (usereg) { // store X only if count is not 0
\r
494 ot(" mov r2,r9,lsr #28\n");
\r
495 ot(" strb r2,[r7,#0x45] ;@ if not 0, Save X bit\n");
\r
496 ot(" b nozerox%.4x\n",op);
\r
497 ot("norotx%.4x%s\n",op,ms?"":":");
\r
498 ot(" ldrb r2,[r7,#0x45]\n");
\r
499 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
\r
501 ot(" and r2,r2,#2\n");
\r
502 ot(" orr r9,r9,r2,lsl #28 ;@ C = old_X\n");
\r
503 ot("nozerox%.4x%s\n",op,ms?"":":");
\r
509 // --------------------------------------
\r
515 ot(";@ Mirror value in whole 32 bits:\n");
\r
516 if (size<=0) ot(" orr r0,r0,r0,lsr #8\n");
\r
517 if (size<=1) ot(" orr r0,r0,r0,lsr #16\n");
\r
521 ot(";@ Rotate register:\n");
\r
524 if (dir) ot(" rsbs %s,%s,#32\n",pct,pct);
\r
525 ot(" movs r0,r0,ror %s\n",pct);
\r
530 if (dir) ror=32-ror;
\r
531 if (ror&31) ot(" movs r0,r0,ror #%d\n",ror);
\r
535 if (!dir) ot(" bic r9,r9,#0x10000000 ;@ make suve V is clear\n");
\r
538 ot(";@ Get carry bit from bit 0:\n");
\r
541 ot(" cmp %s,#32 ;@ rotating by 0?\n",pct);
\r
542 ot(" tstne r0,#1 ;@ no, check bit 0\n");
\r
545 ot(" tst r0,#1\n");
\r
546 ot(" orrne r9,r9,#0x20000000\n");
\r
547 ot(" biceq r9,r9,#0x20000000\n");
\r
551 // if we rotate something by 0, ARM doesn't clear C
\r
552 // so we need to detect that
\r
553 ot(" cmp %s,#0\n",pct);
\r
554 ot(" biceq r9,r9,#0x20000000\n");
\r
559 // --------------------------------------
\r
564 // Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn
\r
565 // (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)
\r
570 int size=0,usereg=0,type=0;
\r
576 if (size>=3) return 1; // use OpAsrEa()
\r
580 if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8
\r
582 // Use the same opcode for target registers:
\r
585 // As long as count is not 8, use the same opcode for all shift counts::
\r
586 if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }
\r
587 if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn
\r
589 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
591 OpStart(op); Cycles=size<2?6:8;
\r
593 EaCalc(10,0x0007, ea,size,1);
\r
594 EaRead(10, 0, ea,size,0x0007,1);
\r
596 EmitAsr(op,type,dir,count, size,usereg);
\r
598 EaWrite(10, 0, ea,size,0x0007,1);
\r
605 // Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee
\r
606 int OpAsrEa(int op)
\r
608 int use=0,type=0,dir=0,ea=0,size=1;
\r
614 if (ea<0x10) return 1;
\r
615 // See if we can do this opcode:
\r
616 if (EaCanRead(ea,0)==0) return 1;
\r
617 if (EaCanWrite(ea)==0) return 1;
\r
620 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
622 OpStart(op); Cycles=6; // EmitAsr() will add 2
\r
624 EaCalc (10,0x003f,ea,size,1);
\r
625 EaRead (10, 0,ea,size,0x003f,1);
\r
627 EmitAsr(op,type,dir,1,size,0);
\r
629 EaWrite(10, 0,ea,size,0x003f,1);
\r
642 // See if we can do this opcode:
\r
643 if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;
\r
646 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
648 OpStart(op); Cycles=4;
\r
649 if(ea>=8) Cycles+=10;
\r
651 EaCalc (10,0x003f,ea,0,1);
\r
652 EaRead (10, 1,ea,0,0x003f,1);
\r
654 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
\r
658 #if CYCLONE_FOR_GENESIS
\r
659 // the original Sega hardware ignores write-back phase (to memory only)
\r
662 ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");
\r
664 EaWrite(10, 1,ea,0,0x003f,1);
\r
665 #if CYCLONE_FOR_GENESIS
\r