3 // --------------------- Opcodes 0x0100+ ---------------------
\r
4 // Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa
\r
5 int OpBtstReg(int op)
\r
8 int type=0,sea=0,tea=0;
\r
11 type=(op>>6)&3; // Btst/Bchg/Bclr/Bset
\r
12 // Get source and target EA
\r
15 if (tea<0x10) size=2; // For registers, 32-bits
\r
17 if ((tea&0x38)==0x08) return 1; // movep
\r
19 // See if we can do this opcode:
\r
20 if (EaCanRead(tea,0)==0) return 1;
\r
23 if (EaCanWrite(tea)==0) return 1;
\r
26 use=OpBase(op,size);
\r
27 use&=~0x0e00; // Use same handler for all registers
\r
28 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
32 if(type==1||type==3) {
\r
36 if(size>=2) Cycles+=2;
\r
39 EaCalcReadNoSE(-1,10,sea,0,0x0e00);
\r
41 EaCalcReadNoSE((type>0)?11:-1,0,tea,size,0x003f);
\r
44 ot(" and r10,r10,#7 ;@ mem - do mod 8\n"); // size always 0
\r
45 else ot(" and r10,r10,#31 ;@ reg - do mod 32\n"); // size always 2
\r
49 ot(" tst r0,r1,lsl r10 ;@ Do arithmetic\n");
\r
50 ot(" bicne r9,r9,#0x40000000\n");
\r
51 ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");
\r
56 if (type==1) ot(" eor r1,r0,r1,lsl r10 ;@ Toggle bit\n");
\r
57 if (type==2) ot(" bic r1,r0,r1,lsl r10 ;@ Clear bit\n");
\r
58 if (type==3) ot(" orr r1,r0,r1,lsl r10 ;@ Set bit\n");
\r
60 EaWrite(11, 1,tea,size,0x003f,0,0);
\r
67 // --------------------- Opcodes 0x0800+ ---------------------
\r
68 // Emit a Btst/Bchg/Bclr/Bset (Immediate) opcode 00001000 ttaaaaaa nn
\r
69 int OpBtstImm(int op)
\r
71 int type=0,sea=0,tea=0;
\r
76 // Get source and target EA
\r
79 if (tea<0x10) size=2; // For registers, 32-bits
\r
81 // See if we can do this opcode:
\r
82 if (EaCanRead(tea,0)==0||EaAn(tea)||tea==0x3c) return 1;
\r
85 if (EaCanWrite(tea)==0) return 1;
\r
88 use=OpBase(op,size);
\r
89 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
91 OpStart(op,sea,tea);
\r
94 EaCalcReadNoSE(-1,0,sea,0,0);
\r
95 ot(" mov r10,#1\n");
\r
96 ot(" bic r9,r9,#0x40000000 ;@ Blank Z flag\n");
\r
98 ot(" and r0,r0,#7 ;@ mem - do mod 8\n"); // size always 0
\r
99 else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2
\r
100 ot(" mov r10,r10,lsl r0 ;@ Make bit mask\n");
\r
103 if(type==1||type==3) {
\r
107 if(size>=2) Cycles+=2;
\r
110 EaCalcReadNoSE((type>0)?11:-1,0,tea,size,0x003f);
\r
111 ot(" tst r0,r10 ;@ Do arithmetic\n");
\r
112 ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");
\r
117 if (type==1) ot(" eor r1,r0,r10 ;@ Toggle bit\n");
\r
118 if (type==2) ot(" bic r1,r0,r10 ;@ Clear bit\n");
\r
119 if (type==3) ot(" orr r1,r0,r10 ;@ Set bit\n");
\r
121 EaWrite(11, 1,tea,size,0x003f,0,0);
\r
129 // --------------------- Opcodes 0x4000+ ---------------------
\r
132 // 01000tt0 xxeeeeee (tt=negx/clr/neg/not, xx=size, eeeeee=EA)
\r
133 int type=0,size=0,ea=0,use=0;
\r
137 size=(op>>6)&3; if (size>=3) return 1;
\r
139 // See if we can do this opcode:
\r
140 if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;
\r
141 if (EaCanWrite(ea )==0) return 1;
\r
143 use=OpBase(op,size);
\r
144 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
146 OpStart(op,ea); Cycles=size<2?4:6;
\r
149 #if CYCLONE_FOR_GENESIS
\r
150 // This is same as in Starscream core, CLR uses only 6 cycles for memory EAs.
\r
151 // May be this is similar case as with TAS opcode, but this time the dummy
\r
152 // read is ignored somehow? Without this hack Fatal Rewind hangs even in Gens.
\r
153 if(type==1&&size<2) Cycles-=2;
\r
157 EaCalc (10,0x003f,ea,size,0,0);
\r
159 if (type!=1) EaRead (10,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)
\r
160 if (type==1) ot("\n");
\r
166 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);
\r
167 ot(" rscs r1,r0,#0 ;@ do arithmetic\n");
\r
168 ot(" orr r3,r9,#0xb0000000 ;@ for old Z\n");
\r
171 ot(" movs r1,r1,asr #%i\n",size?16:24);
\r
172 ot(" orreq r9,r9,#0x40000000 ;@ possily missed Z\n");
\r
174 ot(" andeq r9,r9,r3 ;@ fix Z\n");
\r
181 ot(" mov r1,#0\n");
\r
182 ot(" mov r9,#0x40000000 ;@ NZCV=0100\n");
\r
189 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);
\r
190 ot(" rsbs r1,r0,#0\n");
\r
192 if(size!=2) ot(" mov r1,r1,asr #%i\n",size?16:24);
\r
200 ot(" mov r0,r0,asl #%i\n",size?16:24);
\r
201 ot(" mvn r1,r0,asr #%i\n",size?16:24);
\r
204 ot(" mvn r1,r0\n");
\r
205 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
\r
210 if (type==1) eawrite_check_addrerr=1;
\r
211 EaWrite(10, 1,ea,size,0x003f,0,0);
\r
218 // --------------------- Opcodes 0x4840+ ---------------------
\r
219 // Swap, 01001000 01000nnn swap Dn
\r
225 use=op&~0x0007; // Use same opcode for all An
\r
227 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
229 OpStart(op); Cycles=4;
\r
231 EaCalc (10,0x0007,ea,2,1);
\r
232 EaRead (10, 0,ea,2,0x0007,1);
\r
234 ot(" mov r1,r0,ror #16\n");
\r
235 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
\r
238 EaWrite(10, 1,8,2,0x0007,1);
\r
245 // --------------------- Opcodes 0x4a00+ ---------------------
\r
246 // Emit a Tst opcode, 01001010 xxeeeeee
\r
253 size=(op>>6)&3; if (size>=3) return 1;
\r
255 // See if we can do this opcode:
\r
256 if (EaCanWrite(sea)==0||EaAn(sea)) return 1;
\r
258 use=OpBase(op,size);
\r
259 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
261 OpStart(op,sea); Cycles=4;
\r
263 EaCalc ( 0,0x003f,sea,size,1);
\r
264 EaRead ( 0, 0,sea,size,0x003f,1);
\r
266 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
\r
267 ot(" mrs r9,cpsr ;@ r9=flags\n");
\r
274 // --------------------- Opcodes 0x4880+ ---------------------
\r
275 // Emit an Ext opcode, 01001000 1x000nnn
\r
284 shift=32-(8<<size);
\r
286 use=OpBase(op,size);
\r
287 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
289 OpStart(op); Cycles=4;
\r
291 EaCalc (10,0x0007,ea,size+1,0,0);
\r
292 EaRead (10, 0,ea,size+1,0x0007,0,0);
\r
294 ot(" mov r0,r0,asl #%d\n",shift);
\r
295 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
\r
296 ot(" mrs r9,cpsr ;@ r9=flags\n");
\r
297 ot(" mov r1,r0,asr #%d\n",shift);
\r
300 EaWrite(10, 1,ea,size+1,0x0007,0,0);
\r
306 // --------------------- Opcodes 0x50c0+ ---------------------
\r
307 // Emit a Set cc opcode, 0101cccc 11eeeeee
\r
311 int size=0,use=0,changed_cycles=0;
\r
314 "al","", "hi","ls","cc","cs","ne","eq",
\r
315 "vc","vs","pl","mi","ge","lt","gt","le"
\r
321 if ((ea&0x38)==0x08) return 1; // dbra, not scc
\r
323 // See if we can do this opcode:
\r
324 if (EaCanWrite(ea)==0) return 1;
\r
326 use=OpBase(op,size);
\r
327 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
329 changed_cycles=ea<8 && cc>=2;
\r
330 OpStart(op,ea,0,changed_cycles); Cycles=8;
\r
331 if (ea<8) Cycles=4;
\r
334 ot(" mov r1,#0\n");
\r
339 ot(" mvn r1,#0\n");
\r
340 if (ea<8) Cycles+=2;
\r
345 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");
\r
346 ot(" mvneq r1,r1\n");
\r
347 if (ea<8) ot(" subeq r5,r5,#2 ;@ Extra cycles\n");
\r
350 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");
\r
351 ot(" mvnne r1,r1\n");
\r
352 if (ea<8) ot(" subne r5,r5,#2 ;@ Extra cycles\n");
\r
355 ot(";@ Is the condition true?\n");
\r
356 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");
\r
357 ot(" mvn%s r1,r1\n",cond[cc]);
\r
358 if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);
\r
364 eawrite_check_addrerr=1;
\r
365 EaCalc (0,0x003f, ea,size,0,0);
\r
366 EaWrite(0, 1, ea,size,0x003f,0,0);
\r
368 opend_op_changes_cycles=changed_cycles;
\r
373 // Emit a Asr/Lsr/Roxr/Ror opcode
\r
374 static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
\r
376 char pct[8]=""; // count
\r
377 int shift=32-(8<<size);
\r
379 if (count>=1) sprintf(pct,"#%d",count); // Fixed count
\r
383 ot(";@ Use Dn for count:\n");
\r
384 ot(" and r2,r8,#0x0e00\n");
\r
385 ot(" ldr r2,[r7,r2,lsr #7]\n");
\r
386 ot(" and r2,r2,#63\n");
\r
392 ot(" mov r2,r8,lsr #9 ;@ Get 'n'\n");
\r
393 ot(" and r2,r2,#7\n\n"); strcpy(pct,"r2");
\r
396 // Take 2*n cycles:
\r
397 if (count<0) ot(" sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");
\r
398 else Cycles+=count<<1;
\r
403 if (dir==0 && size<2)
\r
405 ot(";@ For shift right, use loworder bits for the operation:\n");
\r
406 ot(" mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));
\r
410 if (type==0 && dir) ot(" adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");
\r
412 ot(";@ Shift register:\n");
\r
413 if (type==0) ot(" movs r0,r0,%s %s\n",dir?"asl":"asr",pct);
\r
414 if (type==1) ot(" movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);
\r
417 if (usereg) { // store X only if count is not 0
\r
418 ot(" cmp %s,#0 ;@ shifting by 0?\n",pct);
\r
419 ot(" biceq r9,r9,#0x20000000 ;@ if so, clear carry\n");
\r
420 ot(" strne r9,[r7,#0x4c] ;@ else Save X bit\n");
\r
422 // count will never be 0 if we use immediate
\r
423 ot(" str r9,[r7,#0x4c] ;@ Save X bit\n");
\r
427 if (dir==0 && size<2)
\r
429 ot(";@ restore after right shift:\n");
\r
430 ot(" movs r0,r0,lsl #%d\n",32-(8<<size));
\r
432 ot(" orrmi r9,r9,#0x80000000 ;@ Potentially missed N flag\n");
\r
436 if (type==0 && dir) {
\r
437 ot(";@ calculate V flag (set if sign bit changes at anytime):\n");
\r
438 ot(" mov r1,#0x80000000\n");
\r
439 ot(" ands r3,r3,r1,asr %s\n", pct);
\r
440 ot(" cmpne r3,r1,asr %s\n", pct);
\r
441 ot(" eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this
\r
442 ot(" tsteq r1,#0x80000000\n");
\r
443 ot(" orrne r9,r9,#0x10000000\n");
\r
448 // --------------------------------------
\r
457 ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);
\r
458 ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));
\r
461 ot(" movs r0,r0,rrx\n");
\r
464 ot(" ldr r3,[r7,#0x4c]\n");
\r
465 ot(" movs r0,r0,lsl #1\n");
\r
467 ot(" tst r3,#0x20000000\n");
\r
468 ot(" orrne r0,r0,#0x%x\n", 1<<(32-wide));
\r
469 ot(" bicne r9,r9,#0x40000000 ;@ clear Z in case it got there\n");
\r
471 ot(" bic r9,r9,#0x10000000 ;@ make suve V is clear\n");
\r
479 ot(" subs r2,r2,#33\n");
\r
480 ot(" addmis r2,r2,#33 ;@ Now r2=0-%d\n",wide);
\r
484 ot(";@ Reduce r2 until <0:\n");
\r
485 ot("Reduce_%.4x%s\n",op,ms?"":":");
\r
486 ot(" subs r2,r2,#%d\n",wide+1);
\r
487 ot(" bpl Reduce_%.4x\n",op);
\r
488 ot(" adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);
\r
490 ot(" beq norotx_%.4x\n",op);
\r
494 if (usereg||count < 0)
\r
496 if (dir) ot(" rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);
\r
500 if (dir) ot(" mov r2,#%d ;@ Reversed\n",wide+1-count);
\r
501 else ot(" mov r2,#%d\n",count);
\r
504 if (shift) ot(" mov r0,r0,lsr #%d ;@ Shift down\n",shift);
\r
507 ot(";@ First get X bit (middle):\n");
\r
508 ot(" ldr r3,[r7,#0x4c]\n");
\r
509 ot(" rsb r1,r2,#%d\n",wide);
\r
510 ot(" and r3,r3,#0x20000000\n");
\r
511 ot(" mov r3,r3,lsr #29\n");
\r
512 ot(" mov r3,r3,lsl r1\n");
\r
514 ot(";@ Rotate bits:\n");
\r
515 ot(" orr r3,r3,r0,lsr r2 ;@ Orr right part\n");
\r
516 ot(" rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);
\r
517 ot(" orrs r0,r3,r0,lsl r2 ;@ Orr left part, set flags\n");
\r
520 if (shift) ot(" movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);
\r
521 OpGetFlags(0,!usereg);
\r
522 if (usereg) { // store X only if count is not 0
\r
523 ot(" str r9,[r7,#0x4c] ;@ if not 0, Save X bit\n");
\r
524 ot(" b nozerox%.4x\n",op);
\r
525 ot("norotx_%.4x%s\n",op,ms?"":":");
\r
526 ot(" ldr r2,[r7,#0x4c]\n");
\r
527 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
\r
529 ot(" and r2,r2,#0x20000000\n");
\r
530 ot(" orr r9,r9,r2 ;@ C = old_X\n");
\r
531 ot("nozerox%.4x%s\n",op,ms?"":":");
\r
537 // --------------------------------------
\r
543 ot(";@ Mirror value in whole 32 bits:\n");
\r
544 if (size<=0) ot(" orr r0,r0,r0,lsr #8\n");
\r
545 if (size<=1) ot(" orr r0,r0,r0,lsr #16\n");
\r
549 ot(";@ Rotate register:\n");
\r
550 if (!dir) ot(" adds r0,r0,#0 ;@ first clear V and C\n"); // ARM does not clear C if rot count is 0
\r
553 if (dir) ot(" rsb %s,%s,#32\n",pct,pct);
\r
554 ot(" movs r0,r0,ror %s\n",pct);
\r
559 if (dir) ror=32-ror;
\r
560 if (ror&31) ot(" movs r0,r0,ror #%d\n",ror);
\r
566 ot(" bic r9,r9,#0x30000000 ;@ clear CV\n");
\r
567 ot(";@ Get carry bit from bit 0:\n");
\r
570 ot(" cmp %s,#32 ;@ rotating by 0?\n",pct);
\r
571 ot(" tstne r0,#1 ;@ no, check bit 0\n");
\r
574 ot(" tst r0,#1\n");
\r
575 ot(" orrne r9,r9,#0x20000000\n");
\r
580 // --------------------------------------
\r
585 // Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn
\r
586 // (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)
\r
591 int size=0,usereg=0,type=0;
\r
596 if (size>=3) return 1; // use OpAsrEa()
\r
600 if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8
\r
602 // Use the same opcode for target registers:
\r
605 // As long as count is not 8, use the same opcode for all shift counts:
\r
606 if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }
\r
607 if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn
\r
609 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
611 OpStart(op,ea,0,count<0); Cycles=size<2?6:8;
\r
613 EaCalc(10,0x0007, ea,size,1);
\r
614 EaRead(10, 0, ea,size,0x0007,1);
\r
616 EmitAsr(op,type,dir,count, size,usereg);
\r
618 EaWrite(10, 0, ea,size,0x0007,1);
\r
620 opend_op_changes_cycles = (count<0);
\r
626 // Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee
\r
627 int OpAsrEa(int op)
\r
629 int use=0,type=0,dir=0,ea=0,size=1;
\r
635 if (ea<0x10) return 1;
\r
636 // See if we can do this opcode:
\r
637 if (EaCanRead(ea,0)==0) return 1;
\r
638 if (EaCanWrite(ea)==0) return 1;
\r
640 use=OpBase(op,size);
\r
641 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
643 OpStart(op,ea); Cycles=6; // EmitAsr() will add 2
\r
645 EaCalc (10,0x003f,ea,size,1);
\r
646 EaRead (10, 0,ea,size,0x003f,1);
\r
648 EmitAsr(op,type,dir,1,size,0);
\r
650 EaWrite(10, 0,ea,size,0x003f,1);
\r
656 int OpTas(int op, int gen_special)
\r
663 // See if we can do this opcode:
\r
664 if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;
\r
667 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
669 if (!gen_special) OpStart(op,ea);
\r
671 ot("Op%.4x_%s\n", op, ms?"":":");
\r
674 if(ea>=8) Cycles+=10;
\r
676 EaCalc (10,0x003f,ea,0,1);
\r
677 EaRead (10, 1,ea,0,0x003f,1);
\r
679 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
\r
683 #if CYCLONE_FOR_GENESIS
\r
684 // the original Sega hardware ignores write-back phase (to memory only)
\r
685 if (ea < 0x10 || gen_special) {
\r
687 ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");
\r
689 EaWrite(10, 1,ea,0,0x003f,1);
\r
690 #if CYCLONE_FOR_GENESIS
\r
696 #if (CYCLONE_FOR_GENESIS == 2)
\r
697 if (!gen_special && ea >= 0x10) {
\r