5 // Pack our flags into r1, in SR/CCR register format
\r
7 void OpFlagsToReg(int high)
\r
9 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");
\r
10 ot(" mov r1,r9,lsr #28 ;@ ____NZCV\n");
\r
11 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");
\r
12 ot(" tst r2,#1 ;@ 1 if C!=V\n");
\r
13 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");
\r
15 if (high) ot(" ldrb r2,[r7,#0x44] ;@ Include SR high\n");
\r
16 ot(" and r0,r0,#0x20000000\n");
\r
17 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");
\r
18 if (high) ot(" orr r1,r1,r2,lsl #8\n");
\r
22 // Convert SR/CRR register in r0 to our flags
\r
24 void OpRegToFlags(int high, int srh_reg)
\r
26 ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");
\r
27 ot(" mov r2,r0,lsl #25\n");
\r
28 ot(" tst r1,#1 ;@ 1 if C!=V\n");
\r
29 ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");
\r
30 ot(" str r2,[r7,#0x4c] ;@ Store X bit\n");
\r
31 ot(" mov r9,r0,lsl #28 ;@ r9=NZCV...\n");
\r
35 int mask=EMULATE_TRACE?0xa7:0x27;
\r
36 ot(" mov r%i,r0,ror #8\n",srh_reg);
\r
37 ot(" and r%i,r%i,#0x%02x ;@ only take defined bits\n",srh_reg,srh_reg,mask);
\r
38 ot(" strb r%i,[r7,#0x44] ;@ Store SR high\n",srh_reg);
\r
45 ot(";@ ----------\n");
\r
46 ot(";@ tried execute privileged instruction in user mode\n");
\r
47 ot("WrongPrivilegeMode%s\n",ms?"":":");
\r
48 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
49 ot(" ldr r1,[r7,#0x58]\n");
\r
50 ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");
\r
51 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");
\r
52 ot(" str r1,[r7,#0x58]\n");
\r
54 ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");
\r
56 ot(" mov r0,#8 ;@ privilege violation\n");
\r
57 ot(" bl Exception\n");
\r
62 // does OSP and A7 swapping if needed
\r
63 // new or old SR (not the one already in [r7,#0x44]) should be passed in r11
\r
64 // uses srh from srh_reg (loads if < 0), trashes r0,r11
\r
65 void SuperChange(int op,int srh_reg)
\r
67 ot(";@ A7 <-> OSP?\n");
\r
69 ot(" ldr r0,[r7,#0x44] ;@ Get other SR high\n");
\r
72 ot(" eor r0,r%i,r11\n",srh_reg);
\r
73 ot(" tst r0,#0x20\n");
\r
74 ot(" beq no_sp_swap%.4x\n",op);
\r
75 ot(" ;@ swap OSP and A7:\n");
\r
76 ot(" ldr r11,[r7,#0x3C] ;@ Get A7\n");
\r
77 ot(" ldr r0, [r7,#0x48] ;@ Get OSP\n");
\r
78 ot(" str r11,[r7,#0x48]\n");
\r
79 ot(" str r0, [r7,#0x3C]\n");
\r
80 ot("no_sp_swap%.4x%s\n", op, ms?"":":");
\r
85 // --------------------- Opcodes 0x1000+ ---------------------
\r
86 // Emit a Move opcode, 00xxdddd ddssssss
\r
93 // Get source and target EA
\r
95 tea =(op&0x01c0)>>3;
\r
96 tea|=(op&0x0e00)>>9;
\r
98 if (tea>=8 && tea<0x10) movea=1;
\r
100 // Find size extension
\r
104 case 0x1000: size=0; break;
\r
105 case 0x3000: size=1; break;
\r
106 case 0x2000: size=2; break;
\r
109 if (size<1 && (movea || EaAn(sea))) return 1; // move.b An,* and movea.b * are invalid
\r
111 // See if we can do this opcode:
\r
112 if (EaCanRead (sea,size)==0) return 1;
\r
113 if (EaCanWrite(tea )==0) return 1;
\r
115 use=OpBase(op,size);
\r
116 if (tea<0x38) use&=~0x0e00; // Use same handler for register ?0-7
\r
118 if (tea==0x1f || tea==0x27) use|=0x0e00; // Specific handler for (a7)+ and -(a7)
\r
120 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
122 OpStart(op,sea,tea); Cycles=4;
\r
124 EaCalcRead(-1,1,sea,size,0x003f);
\r
128 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
\r
129 ot(" mrs r9,cpsr ;@ r9=NZCV flags\n");
\r
133 if (movea) size=2; // movea always expands to 32-bits
\r
135 eawrite_check_addrerr=1;
\r
137 if ((tea&0x38)==0x20 && size==2) { // -(An)
\r
138 EaCalc (10,0x0e00,tea,size,0,0);
\r
139 ot(" mov r11,r1\n");
\r
140 ot(" add r0,r10,#2\n");
\r
141 EaWrite(0, 1,tea,1,0x0e00,0,0);
\r
142 EaWrite(10, 11,tea,1,0x0e00,1);
\r
147 EaCalc (0,0x0e00,tea,size,0,0);
\r
148 EaWrite(0, 1,tea,size,0x0e00,0,0);
\r
151 #if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES
\r
152 // this is a bit hacky
\r
153 if ((tea==0x39||(tea&0x38)==0x10)&&size>=1)
\r
154 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
157 if((tea&0x38)==0x20) Cycles-=2; // less cycles when dest is -(An)
\r
163 // --------------------- Opcodes 0x41c0+ ---------------------
\r
164 // Emit an Lea opcode, 0100nnn1 11aaaaaa
\r
171 tea=(op&0x0e00)>>9; tea|=8;
\r
173 if (EaCanRead(sea,-1)==0) return 1; // See if we can do this opcode
\r
176 use&=~0x0e00; // Also use 1 handler for target ?0-7
\r
177 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
179 OpStart(op,sea,tea);
\r
181 eawrite_check_addrerr=1;
\r
182 EaCalc (1,0x003f,sea,0); // Lea
\r
183 EaCalc (0,0x0e00,tea,2);
\r
184 EaWrite(0, 1,tea,2,0x0e00);
\r
186 Cycles=Ea_add_ns(g_lea_cycle_table,sea);
\r
193 // --------------------- Opcodes 0x40c0+ ---------------------
\r
194 // Move SR opcode, 01000tt0 11aaaaaa move SR
\r
195 int OpMoveSr(int op)
\r
200 type=(op>>9)&3; // from SR, from CCR, to CCR, to SR
\r
203 if(EaAn(ea)) return 1; // can't use An regs
\r
208 if (EaCanWrite(ea)==0) return 1; // See if we can do this opcode:
\r
212 return 1; // no such op in 68000
\r
215 if (EaCanRead(ea,size)==0) return 1; // See if we can do this opcode:
\r
219 use=OpBase(op,size);
\r
220 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
222 // 68000 model allows reading whole SR in user mode (but newer models don't)
\r
223 OpStart(op,ea,0,0,type==3);
\r
225 if (type==0) Cycles=(ea>=8)?8:6;
\r
227 if (type==0 || type==1)
\r
229 eawrite_check_addrerr=1;
\r
230 OpFlagsToReg(type==0);
\r
231 EaCalc (0,0x003f,ea,size,0,0);
\r
232 EaWrite(0, 1,ea,size,0x003f,0,0);
\r
235 if (type==2 || type==3)
\r
237 EaCalcReadNoSE(-1,0,ea,size,0x003f);
\r
238 OpRegToFlags(type==3,1);
\r
241 opend_check_interrupt = 1;
\r
242 opend_check_trace = 1;
\r
254 // Ori/Andi/Eori $nnnn,sr 0000t0t0 01111100
\r
255 int OpArithSr(int op)
\r
259 int sr_mask=EMULATE_TRACE?0xa7:0x27;
\r
261 type=(op>>9)&5; if (type==4) return 1;
\r
262 size=(op>>6)&1; // ccr or sr?
\r
265 use=OpBase(op,size);
\r
266 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
268 OpStart(op,ea,0,0,size!=0); Cycles=16;
\r
270 EaCalcRead(-1,0,ea,size,0x003f);
\r
272 ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");
\r
273 ot(" tst r1,#1 ;@ 1 if C!=V\n");
\r
274 ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");
\r
275 ot(" ldr r2,[r7,#0x4c] ;@ Load old X bit\n");
\r
277 // note: old srh is already in r11 (done by OpStart)
\r
279 ot(" orr r9,r9,r0,lsl #28\n");
\r
280 ot(" orr r2,r2,r0,lsl #25 ;@ X bit\n");
\r
282 ot(" orr r1,r11,r0,lsr #8\n");
\r
283 ot(" and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);
\r
287 ot(" and r9,r9,r0,lsl #28\n");
\r
288 ot(" and r2,r2,r0,lsl #25 ;@ X bit\n");
\r
290 ot(" and r1,r11,r0,lsr #8\n");
\r
293 ot(" eor r9,r9,r0,lsl #28\n");
\r
294 ot(" eor r2,r2,r0,lsl #25 ;@ X bit\n");
\r
296 ot(" eor r1,r11,r0,lsr #8\n");
\r
297 ot(" and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);
\r
301 ot(" str r2,[r7,#0x4c] ;@ Save X bit\n");
\r
303 ot(" strb r1,[r7,#0x44]\n");
\r
306 // we can't enter supervisor mode, nor unmask irqs just by using OR
\r
307 if (size!=0 && type!=0) {
\r
310 opend_check_interrupt = 1;
\r
312 // also can't set trace bit with AND
\r
313 if (size!=0 && type!=1)
\r
314 opend_check_trace = 1;
\r
321 // --------------------- Opcodes 0x4850+ ---------------------
\r
322 // Emit an Pea opcode, 01001000 01aaaaaa
\r
328 ea=op&0x003f; if (ea<0x10) return 1; // Swap opcode
\r
329 if (EaCanRead(ea,-1)==0) return 1; // See if we can do this opcode:
\r
332 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
336 ot(" ldr r10,[r7,#0x3c]\n");
\r
337 EaCalc (1,0x003f, ea,0);
\r
339 ot(" sub r0,r10,#4 ;@ Predecrement A7\n");
\r
340 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
342 MemHandler(1,2); // Write 32-bit
\r
345 Cycles=6+Ea_add_ns(g_pea_cycle_table,ea);
\r
352 // --------------------- Opcodes 0x4880+ ---------------------
\r
353 // Emit a Movem opcode, 01001d00 1xeeeeee regmask
\r
354 int OpMovem(int op)
\r
356 int size=0,ea=0,cea=0,dir=0;
\r
357 int use=0,decr=0,change=0;
\r
359 size=((op>>6)&1)+1; // word, long
\r
361 dir=(op>>10)&1; // Direction (1==ea2reg)
\r
364 if (ea<0x10 || ea>0x3b || (ea&0x38)==0x20) return 1; // Invalid EA
\r
366 if (ea<0x10 || ea>0x39 || (ea&0x38)==0x18) return 1;
\r
369 if ((ea&0x38)==0x18 || (ea&0x38)==0x20) change=1;
\r
370 if ((ea&0x38)==0x20) decr=1; // -(An), bitfield is decr
\r
372 cea=ea; if (change) cea=0x10;
\r
374 use=OpBase(op,size);
\r
375 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
377 OpStart(op,ea,0,1);
\r
379 ot(" ldrh r11,[r4],#2 ;@ r11=register mask\n");
\r
381 ot(";@ r10=Register Index*4:\n");
\r
382 if (decr) ot(" mov r10,#0x40 ;@ order reversed for -(An)\n");
\r
383 else ot(" mov r10,#-4\n");
\r
386 ot(";@ Get the address into r6:\n");
\r
387 EaCalc(6,0x003f,cea,size);
\r
390 ot(" tst r11,r11\n"); // sanity check
\r
391 ot(" beq NoRegs%.4x\n",op);
\r
393 #if EMULATE_ADDRESS_ERRORS_IO
\r
395 ot(" tst r6,#1 ;@ address error?\n");
\r
396 ot(" movne r0,r6\n");
\r
397 ot(" bne ExceptionAddressError_%c_data\n",dir?'r':'w');
\r
401 ot("Movemloop%.4x%s\n",op, ms?"":":");
\r
402 ot(" add r10,r10,#%d ;@ r10=Next Register\n",decr?-4:4);
\r
403 ot(" movs r11,r11,lsr #1\n");
\r
404 ot(" bcc Movemloop%.4x\n",op);
\r
407 if (decr) ot(" sub r6,r6,#%d ;@ Pre-decrement address\n",1<<size);
\r
411 ot(" ;@ Copy memory to register:\n",1<<size);
\r
412 earead_check_addrerr=0; // already checked
\r
413 EaRead (6,0,ea,size,0x003f);
\r
414 ot(" str r0,[r7,r10] ;@ Save value into Dn/An\n");
\r
418 // if (size == 2 && decr && SPLIT_MOVEL_PD) we should do 2xWrite16 here
\r
419 // (same as in movel.l ?, -(An)), but as this is not likely to be needed and
\r
420 // we do not want the performance hit, we do single Write32 instead.
\r
421 ot(" ;@ Copy register to memory:\n",1<<size);
\r
422 ot(" ldr r1,[r7,r10] ;@ Load value from Dn/An\n");
\r
423 EaWrite(6,1,ea,size,0x003f);
\r
426 if (decr==0) ot(" add r6,r6,#%d ;@ Post-increment address\n",1<<size);
\r
428 ot(" sub r5,r5,#%d ;@ Take some cycles\n",2<<size);
\r
429 ot(" tst r11,r11\n");
\r
430 ot(" bne Movemloop%.4x\n",op);
\r
435 ot(";@ Write back address:\n");
\r
436 EaCalc (0,0x0007,8|(ea&7),2);
\r
437 EaWrite(0, 6,8|(ea&7),2,0x0007);
\r
440 ot("NoRegs%.4x%s\n",op, ms?"":":");
\r
441 ot(" ldr r6,=CycloneJumpTab ;@ restore Opcode Jump table\n");
\r
445 if (ea==0x3a) Cycles=16; // ($nn,PC)
\r
446 else if (ea==0x3b) Cycles=18; // ($nn,pc,Rn)
\r
452 Cycles+=Ea_add_ns(g_movem_cycle_table,ea);
\r
454 opend_op_changes_cycles = 1;
\r
462 // --------------------- Opcodes 0x4e60+ ---------------------
\r
463 // Emit a Move USP opcode, 01001110 0110dnnn move An to/from USP
\r
464 int OpMoveUsp(int op)
\r
468 dir=(op>>3)&1; // Direction
\r
469 use=op&~0x0007; // Use same opcode for all An
\r
471 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
473 OpStart(op,0,0,0,1); Cycles=4;
\r
477 eawrite_check_addrerr=1;
\r
478 ot(" ldr r1,[r7,#0x48] ;@ Get from USP\n\n");
\r
479 EaCalc (0,0x000f,8,2,1);
\r
480 EaWrite(0, 1,8,2,0x000f,1);
\r
484 EaCalc (0,0x000f,8,2,1);
\r
485 EaRead (0, 0,8,2,0x000f,1);
\r
486 ot(" str r0,[r7,#0x48] ;@ Put in USP\n\n");
\r
494 // --------------------- Opcodes 0x7000+ ---------------------
\r
495 // Emit a Move Quick opcode, 0111nnn0 dddddddd moveq #dd,Dn
\r
496 int OpMoveq(int op)
\r
500 use=op&0xf100; // Use same opcode for all values
\r
501 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
503 OpStart(op); Cycles=4;
\r
505 ot(" movs r0,r8,asl #24\n");
\r
506 ot(" and r1,r8,#0x0e00\n");
\r
507 ot(" mov r0,r0,asr #24 ;@ Sign extended Quick value\n");
\r
508 ot(" mrs r9,cpsr ;@ r9=NZ flags\n");
\r
509 ot(" str r0,[r7,r1,lsr #7] ;@ Store into Dn\n");
\r
517 // --------------------- Opcodes 0xc140+ ---------------------
\r
518 // Emit a Exchange opcode:
\r
519 // 1100ttt1 01000sss exg ds,dt
\r
520 // 1100ttt1 01001sss exg as,at
\r
521 // 1100ttt1 10001sss exg as,dt
\r
528 if (type!=0x40 && type!=0x48 && type!=0x88) return 1; // Not an exg opcode
\r
530 use=op&0xf1f8; // Use same opcode for all values
\r
531 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
533 OpStart(op); Cycles=6;
\r
535 ot(" and r10,r8,#0x0e00 ;@ Find T register\n");
\r
536 ot(" and r11,r8,#0x000f ;@ Find S register\n");
\r
537 if (type==0x48) ot(" orr r10,r10,#0x1000 ;@ T is an address register\n");
\r
539 ot(" ldr r0,[r7,r10,lsr #7] ;@ Get T\n");
\r
540 ot(" ldr r1,[r7,r11,lsl #2] ;@ Get S\n");
\r
542 ot(" str r0,[r7,r11,lsl #2] ;@ T->S\n");
\r
543 ot(" str r1,[r7,r10,lsr #7] ;@ S->T\n");
\r
551 // ------------------------- movep -------------------------------
\r
552 // 0000ddd1 0z001sss
\r
553 // 0000sss1 1z001ddd (to mem)
\r
554 int OpMovep(int op)
\r
557 int size=1,use=0,dir,aadd=0;
\r
560 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler (for all dests, srcs)
\r
563 ea = (op&0x0007)|0x28;
\r
564 rea= (op&0x0e00)>>9;
\r
567 // Find size extension
\r
568 if(op&0x0040) size=2;
\r
572 if(dir) { // reg to mem
\r
573 EaCalcReadNoSE(-1,11,rea,size,0x0e00);
\r
575 EaCalc(10,0x000f,ea,size);
\r
576 if(size==2) { // if operand is long
\r
577 ot(" mov r1,r11,lsr #24 ;@ first byte\n");
\r
578 EaWrite(10,1,ea,0,0x000f); // store first byte
\r
579 ot(" add r0,r10,#%i\n",(aadd+=2));
\r
580 ot(" mov r1,r11,lsr #16 ;@ second byte\n");
\r
581 EaWrite(0,1,ea,0,0x000f); // store second byte
\r
582 ot(" add r0,r10,#%i\n",(aadd+=2));
\r
584 ot(" mov r0,r10\n");
\r
586 ot(" mov r1,r11,lsr #8 ;@ first or third byte\n");
\r
587 EaWrite(0,1,ea,0,0x000f);
\r
588 ot(" add r0,r10,#%i\n",(aadd+=2));
\r
589 ot(" and r1,r11,#0xff\n");
\r
590 EaWrite(0,1,ea,0,0x000f);
\r
591 } else { // mem to reg
\r
592 EaCalc(10,0x000f,ea,size,1);
\r
593 EaRead(10,11,ea,0,0x000f,1); // read first byte
\r
594 ot(" add r0,r10,#2\n");
\r
595 EaRead(0,1,ea,0,0x000f,1); // read second byte
\r
596 if(size==2) { // if operand is long
\r
597 ot(" orr r11,r11,r1,lsr #8 ;@ second byte\n");
\r
598 ot(" add r0,r10,#4\n");
\r
599 EaRead(0,1,ea,0,0x000f,1);
\r
600 ot(" orr r11,r11,r1,lsr #16 ;@ third byte\n");
\r
601 ot(" add r0,r10,#6\n");
\r
602 EaRead(0,1,ea,0,0x000f,1);
\r
603 ot(" orr r1,r11,r1,lsr #24 ;@ fourth byte\n");
\r
605 ot(" orr r1,r11,r1,lsr #8 ;@ second byte\n");
\r
607 // store the result
\r
608 EaCalc(11,0x0e00,rea,size,1); // reg number -> r11
\r
609 EaWrite(11,1,rea,size,0x0e00,1);
\r
612 Cycles=(size==2)?24:16;
\r
618 // Emit a Stop/Reset opcodes, 01001110 011100t0 imm
\r
619 int OpStopReset(int op)
\r
621 int type=(op>>1)&1; // stop/reset
\r
623 OpStart(op,0,0,0,1);
\r
626 // copy immediate to SR, stop the CPU and eat all remaining cycles.
\r
627 ot(" ldrh r0,[r4],#2 ;@ Fetch the immediate\n");
\r
633 ot(" ldr r0,[r7,#0x58]\n");
\r
634 ot(" mov r5,#0 ;@ eat cycles\n");
\r
635 ot(" orr r0,r0,#1 ;@ stopped\n");
\r
636 ot(" str r0,[r7,#0x58]\n");
\r
645 #if USE_RESET_CALLBACK
\r
646 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
647 ot(" mov r1,r9,lsr #28\n");
\r
648 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
649 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
650 ot(" ldr r11,[r7,#0x90] ;@ ResetCallback\n");
\r
651 ot(" tst r11,r11\n");
\r
652 ot(" movne lr,pc\n");
\r
653 ot(" bxne r11 ;@ call ResetCallback if it is defined\n");
\r
654 ot(" ldrb r9,[r7,#0x46] ;@ r9 = Load Flags (NZCV)\n");
\r
655 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
656 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
657 ot(" mov r9,r9,lsl #28\n");
\r