4 * Cyclone 68000 configuration file
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9 * If this option is enabled, Microsoft ARMASM compatible output is generated.
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10 * Otherwise GNU as syntax is used.
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12 #define USE_MS_SYNTAX 0
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15 * Enable this option if you are going to use Cyclone to emulate Genesis /
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16 * Mega Drive system. As VDP chip in these systems had control of the bus,
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17 * several instructions were acting differently, for example TAS did'n have
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18 * the write-back phase. That will be emulated, if this option is enebled.
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19 * This option also alters timing slightly.
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21 #define CYCLONE_FOR_GENESIS 1
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24 * This option compresses Cyclone's jumptable. Because of this the executable
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25 * will be smaller and load slightly faster and less relocations will be needed.
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26 * This also fixes the crash problem with 0xfffe and 0xffff opcodes.
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27 * Warning: if you enable this, you MUST call CycloneInit() before calling
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28 * CycloneRun(), or else it will crash.
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30 #define COMPRESS_JUMPTABLE 1
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33 * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle
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34 * count in ARM registers instead of the context for performance reasons. If you for
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35 * any reason need to access them in your memory handlers, enable the options below,
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36 * otherwise disable them to improve performance.
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37 * Warning: the PC value will not point to start of instruction (it will be middle or
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38 * end), also updating PC is dangerous, as Cyclone may internally increment the PC
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39 * before fetching the next instruction and continue executing at wrong location.
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41 #define MEMHANDLERS_NEED_PC 0
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42 #define MEMHANDLERS_NEED_FLAGS 0
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43 #define MEMHANDLERS_NEED_CYCLES 1
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44 #define MEMHANDLERS_CHANGE_PC 0
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45 #define MEMHANDLERS_CHANGE_FLAGS 0
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46 #define MEMHANDLERS_CHANGE_CYCLES 0
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49 * If enabled, Cyclone will call IrqCallback routine from it's context whenever it
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50 * acknowledges an IRQ. IRQ level is not cleared automatically, do this in your
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51 * hadler if needed. PC, flags and cycles are valid in the context and can be read.
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52 * If disabled, it simply clears the IRQ level and continues execution.
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54 #define USE_INT_ACK_CALLBACK 1
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57 * Enable this if you need/change PC, flags or cycles in your IrqCallback function.
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59 #define INT_ACK_NEEDS_STUFF 0
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60 #define INT_ACK_CHANGES_STUFF 0
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63 * If enabled, ResetCallback is called from the context, whenever RESET opcode is
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64 * encountered. All context members are valid and can be changed.
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65 * If disabled, RESET opcode acts as an NOP.
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67 #define USE_RESET_CALLBACK 1
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70 * If enabled, UnrecognizedCallback is called if an invalid opcode is
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71 * encountered. All context members are valid and can be changed. The handler
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72 * should return zero if you want Cyclone to gererate "Illegal Instruction"
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73 * exception after this, or nonzero if not. In the later case you shuold change
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74 * the PC by yourself, or else Cyclone will keep executing that opcode all over
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76 * If disabled, "Illegal Instruction" exception is generated and execution is
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79 #define USE_UNRECOGNIZED_CALLBACK 1
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82 * This option will also call UnrecognizedCallback for a-line and f-line
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83 * (0xa*** and 0xf***) opcodes the same way as described above, only appropriate
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84 * exceptions will be generated.
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86 #define USE_AFLINE_CALLBACK 1
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89 * This makes Cyclone to call checkpc from it's context whenever it changes the PC
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90 * by a large value. It takes and should return the PC value in PC+membase form.
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91 * The flags and cycle counter are not valid in this function.
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93 #define USE_CHECKPC_CALLBACK 1
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96 * When this option is enabled Cyclone will do two word writes instead of one
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97 * long write when handling MOVE.L with pre-decrementing destination, as described in
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98 * Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).
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99 * Enable this if you are emulating a 16 bit system.
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101 #define SPLIT_MOVEL_PD 1
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