1 /******************************************************************************
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3 * CZ80 (Z80 CPU emulator) version 0.9
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4 * Compiled with Dev-C++
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5 * Copyright 2004-2005 Stéphane Dallongeville
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9 *****************************************************************************/
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24 /******************************/
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25 /* Compiler dependant defines */
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26 /******************************/
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29 #define UINT8 unsigned char
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33 #define INT8 signed char
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37 #define UINT16 unsigned short
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41 #define INT16 signed short
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45 #define UINT32 unsigned int
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49 #define INT32 signed int
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53 #define FPTR uintptr_t
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56 /*************************************/
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57 /* Z80 core Structures & definitions */
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58 /*************************************/
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60 #define CZ80_FETCH_BITS 4 // [4-12] default = 8
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62 #define CZ80_FETCH_SFT (16 - CZ80_FETCH_BITS)
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63 #define CZ80_FETCH_BANK (1 << CZ80_FETCH_BITS)
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65 #define PICODRIVE_HACKS 1
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66 #define CZ80_LITTLE_ENDIAN 1
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67 #define CZ80_USE_JUMPTABLE 1
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68 #define CZ80_BIG_FLAGS_ARRAY 1
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69 //#ifdef BUILD_CPS1PSP
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70 //#define CZ80_ENCRYPTED_ROM 1
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72 #define CZ80_ENCRYPTED_ROM 0
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74 #define CZ80_EMULATE_R_EXACTLY 1
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76 #define zR8(A) (*CPU->pzR8[A])
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77 #define zR16(A) (CPU->pzR16[A]->W)
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79 #define pzAF &(CPU->AF)
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80 #define zAF CPU->AF.W
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81 #define zlAF CPU->AF.B.L
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82 #define zhAF CPU->AF.B.H
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86 #define pzBC &(CPU->BC)
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87 #define zBC CPU->BC.W
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88 #define zlBC CPU->BC.B.L
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89 #define zhBC CPU->BC.B.H
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93 #define pzDE &(CPU->DE)
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94 #define zDE CPU->DE.W
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95 #define zlDE CPU->DE.B.L
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96 #define zhDE CPU->DE.B.H
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100 #define pzHL &(CPU->HL)
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101 #define zHL CPU->HL.W
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102 #define zlHL CPU->HL.B.L
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103 #define zhHL CPU->HL.B.H
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107 #define zAF2 CPU->AF2.W
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108 #define zlAF2 CPU->AF2.B.L
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109 #define zhAF2 CPU->AF2.B.H
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113 #define zBC2 CPU->BC2.W
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114 #define zDE2 CPU->DE2.W
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115 #define zHL2 CPU->HL2.W
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117 #define pzIX &(CPU->IX)
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118 #define zIX CPU->IX.W
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119 #define zlIX CPU->IX.B.L
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120 #define zhIX CPU->IX.B.H
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122 #define pzIY &(CPU->IY)
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123 #define zIY CPU->IY.W
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124 #define zlIY CPU->IY.B.L
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125 #define zhIY CPU->IY.B.H
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127 #define pzSP &(CPU->SP)
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128 #define zSP CPU->SP.W
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129 #define zlSP CPU->SP.B.L
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130 #define zhSP CPU->SP.B.H
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132 #define zRealPC (PC - CPU->BasePC)
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136 #define zIM CPU->IM
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138 #define zwR CPU->R.W
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139 #define zR1 CPU->R.B.L
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140 #define zR2 CPU->R.B.H
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143 #define zIFF CPU->IFF.W
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144 #define zIFF1 CPU->IFF.B.L
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145 #define zIFF2 CPU->IFF.B.H
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147 #define CZ80_SF_SFT 7
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148 #define CZ80_ZF_SFT 6
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149 #define CZ80_YF_SFT 5
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150 #define CZ80_HF_SFT 4
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151 #define CZ80_XF_SFT 3
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152 #define CZ80_PF_SFT 2
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153 #define CZ80_VF_SFT 2
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154 #define CZ80_NF_SFT 1
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155 #define CZ80_CF_SFT 0
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157 #define CZ80_SF (1 << CZ80_SF_SFT)
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158 #define CZ80_ZF (1 << CZ80_ZF_SFT)
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159 #define CZ80_YF (1 << CZ80_YF_SFT)
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160 #define CZ80_HF (1 << CZ80_HF_SFT)
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161 #define CZ80_XF (1 << CZ80_XF_SFT)
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162 #define CZ80_PF (1 << CZ80_PF_SFT)
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163 #define CZ80_VF (1 << CZ80_VF_SFT)
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164 #define CZ80_NF (1 << CZ80_NF_SFT)
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165 #define CZ80_CF (1 << CZ80_CF_SFT)
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167 #define CZ80_IFF_SFT CZ80_PF_SFT
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168 #define CZ80_IFF CZ80_PF
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170 #ifndef IRQ_LINE_STATE
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171 #define IRQ_LINE_STATE
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172 #define CLEAR_LINE 0 /* clear (a fired, held or pulsed) line */
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173 #define ASSERT_LINE 1 /* assert an interrupt immediately */
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174 #define HOLD_LINE 2 /* hold interrupt line until acknowledged */
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175 #define PULSE_LINE 3 /* pulse interrupt line for one instruction */
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176 #define IRQ_LINE_NMI 127 /* IRQ line for NMIs */
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206 #if CZ80_LITTLE_ENDIAN
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217 typedef struct cz80_t
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235 UINT32 unusedPC; /* left for binary compat */
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257 FPTR Fetch[CZ80_FETCH_BANK];
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258 #if CZ80_ENCRYPTED_ROM
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260 FPTR OPFetch[CZ80_FETCH_BANK];
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266 UINT8 (*Read_Byte)(UINT32 address);
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267 void (*Write_Byte)(UINT32 address, UINT8 data);
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269 UINT8 (*IN_Port)(UINT16 port);
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270 void (*OUT_Port)(UINT16 port, UINT8 value);
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272 INT32 (*Interrupt_Callback)(INT32 irqline);
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277 /*************************/
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278 /* Publics Z80 variables */
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279 /*************************/
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281 extern cz80_struc CZ80;
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283 /*************************/
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284 /* Publics Z80 functions */
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285 /*************************/
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287 void Cz80_Init(cz80_struc *CPU);
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289 void Cz80_Reset(cz80_struc *CPU);
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291 INT32 Cz80_Exec(cz80_struc *CPU, INT32 cycles);
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293 void Cz80_Set_IRQ(cz80_struc *CPU, INT32 line, INT32 state);
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295 UINT32 Cz80_Get_Reg(cz80_struc *CPU, INT32 regnum);
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296 void Cz80_Set_Reg(cz80_struc *CPU, INT32 regnum, UINT32 value);
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298 void Cz80_Set_Fetch(cz80_struc *CPU, UINT32 low_adr, UINT32 high_adr, FPTR fetch_adr);
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299 #if CZ80_ENCRYPTED_ROM
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300 void Cz80_Set_Encrypt_Range(cz80_struc *CPU, UINT32 low_adr, UINT32 high_adr, UINT32 decrypted_rom);
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303 void Cz80_Set_ReadB(cz80_struc *CPU, UINT8 (*Func)(UINT32 address));
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304 void Cz80_Set_WriteB(cz80_struc *CPU, void (*Func)(UINT32 address, UINT8 data));
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306 void Cz80_Set_INPort(cz80_struc *CPU, UINT8 (*Func)(UINT16 port));
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307 void Cz80_Set_OUTPort(cz80_struc *CPU, void (*Func)(UINT16 port, UINT8 value));
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309 void Cz80_Set_IRQ_Callback(cz80_struc *CPU, INT32 (*Func)(INT32 irqline));
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315 #endif /* CZ80_H */
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