1 // Basic macros to emit ARM instructions and some utils
3 // (c) Copyright 2008-2009, Grazvydas "notaz" Ignotas
4 // Free for non-commercial use.
8 // XXX: tcache_ptr type for SVP and SH2 compilers differs..
9 #define EMIT_PTR(ptr, x) \
12 ptr = (void *)((u8 *)ptr + sizeof(u32)); \
16 #define EMIT(x) EMIT_PTR(tcache_ptr, x)
18 #define A_R4M (1 << 4)
19 #define A_R5M (1 << 5)
20 #define A_R6M (1 << 6)
21 #define A_R7M (1 << 7)
22 #define A_R8M (1 << 8)
23 #define A_R9M (1 << 9)
24 #define A_R10M (1 << 10)
25 #define A_R11M (1 << 11)
26 #define A_R14M (1 << 14)
43 #define A_COND_CS A_COND_HS
44 #define A_COND_CC A_COND_LO
46 /* unified conditions */
47 #define DCOND_EQ A_COND_EQ
48 #define DCOND_NE A_COND_NE
49 #define DCOND_MI A_COND_MI
50 #define DCOND_PL A_COND_PL
51 #define DCOND_HI A_COND_HI
52 #define DCOND_HS A_COND_HS
53 #define DCOND_LO A_COND_LO
54 #define DCOND_GE A_COND_GE
55 #define DCOND_GT A_COND_GT
56 #define DCOND_LT A_COND_LT
57 #define DCOND_LS A_COND_LS
58 #define DCOND_LE A_COND_LE
59 #define DCOND_VS A_COND_VS
60 #define DCOND_VC A_COND_VC
62 /* addressing mode 1 */
68 #define A_AM1_IMM(ror2,imm8) (((ror2)<<8) | (imm8) | 0x02000000)
69 #define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
70 #define A_AM1_REG_XREG(rs,shift_op,rm) (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm))
72 /* data processing op */
88 #define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
89 EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
91 #define EOP_C_DOP_IMM( cond,op,s,rn,rd,ror2,imm8) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
92 #define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
93 #define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs, shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs, shift_op,rm))
95 #define EOP_MOV_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
96 #define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
97 #define EOP_EOR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_EOR,0,rn,rd,ror2,imm8)
98 #define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
99 #define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
100 #define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
101 #define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
102 #define EOP_TST_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
103 #define EOP_CMP_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
104 #define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
106 #define EOP_MOV_IMM_C(cond,rd, ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_MOV,0, 0,rd,ror2,imm8)
107 #define EOP_ORR_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_ORR,0,rn,rd,ror2,imm8)
108 #define EOP_RSB_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_RSB,0,rn,rd,ror2,imm8)
110 #define EOP_MOV_REG(cond,s,rd, rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
111 #define EOP_ORR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
112 #define EOP_ADD_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
113 #define EOP_ADC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADC,s,rn,rd,shift_imm,shift_op,rm)
114 #define EOP_SUB_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SUB,s,rn,rd,shift_imm,shift_op,rm)
115 #define EOP_SBC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SBC,s,rn,rd,shift_imm,shift_op,rm)
116 #define EOP_AND_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_AND,s,rn,rd,shift_imm,shift_op,rm)
117 #define EOP_EOR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_EOR,s,rn,rd,shift_imm,shift_op,rm)
118 #define EOP_CMP_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_CMP,1,rn, 0,shift_imm,shift_op,rm)
119 #define EOP_TST_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
120 #define EOP_TEQ_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TEQ,1,rn, 0,shift_imm,shift_op,rm)
122 #define EOP_MOV_REG2(s,rd, rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
123 #define EOP_ADD_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
124 #define EOP_SUB_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
126 #define EOP_MOV_REG_SIMPLE(rd,rm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,0)
127 #define EOP_MOV_REG_LSL(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,shift_imm)
128 #define EOP_MOV_REG_LSR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSR,shift_imm)
129 #define EOP_MOV_REG_ASR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ASR,shift_imm)
130 #define EOP_MOV_REG_ROR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ROR,shift_imm)
132 #define EOP_ORR_REG_SIMPLE(rd,rm) EOP_ORR_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
133 #define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
134 #define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
135 #define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ASR,shift_imm)
136 #define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ROR,shift_imm)
138 #define EOP_ADD_REG_SIMPLE(rd,rm) EOP_ADD_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
139 #define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
140 #define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
142 #define EOP_TST_REG_SIMPLE(rn,rm) EOP_TST_REG(A_COND_AL, rn, 0,A_AM1_LSL,rm)
144 #define EOP_MOV_REG2_LSL(rd, rm,rs) EOP_MOV_REG2(0,rd, rm,A_AM1_LSL,rs)
145 #define EOP_MOV_REG2_ROR(rd, rm,rs) EOP_MOV_REG2(0,rd, rm,A_AM1_ROR,rs)
146 #define EOP_ADD_REG2_LSL(rd,rn,rm,rs) EOP_ADD_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
147 #define EOP_SUB_REG2_LSL(rd,rn,rm,rs) EOP_SUB_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
149 /* addressing mode 2 */
150 #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
151 EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
153 /* addressing mode 3 */
154 #define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
155 EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
156 ((s)<<6) | ((h)<<5) | (immed_reg))
158 #define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf))
160 #define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
163 #define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
164 #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
165 #define EOP_LDR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
166 #define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
167 #define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
169 #define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
170 #define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
171 #define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
172 #define EOP_STRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
173 #define EOP_STRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
174 #define EOP_STRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)
177 #define EOP_XXM(cond,p,u,s,w,l,rn,list) \
178 EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
180 #define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
181 #define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
184 #define EOP_C_BX(cond,rm) \
185 EMIT(((cond)<<28) | 0x012fff10 | (rm))
187 #define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
189 #define EOP_C_B(cond,l,signed_immed_24) \
190 EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
192 #define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
193 #define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
196 #define EOP_C_MUL(cond,s,rd,rs,rm) \
197 EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm))
199 #define EOP_C_UMULL(cond,s,rdhi,rdlo,rs,rm) \
200 EMIT(((cond)<<28) | 0x00800000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
202 #define EOP_C_SMULL(cond,s,rdhi,rdlo,rs,rm) \
203 EMIT(((cond)<<28) | 0x00c00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
205 #define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
207 #define EOP_C_MRS(cond,rd) \
208 EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12))
210 #define EOP_C_MSR_IMM(cond,ror2,imm) \
211 EMIT(((cond)<<28) | 0x0328f000 | ((ror2)<<8) | (imm)) // cpsr_f
213 #define EOP_C_MSR_REG(cond,rm) \
214 EMIT(((cond)<<28) | 0x0128f000 | (rm)) // cpsr_f
216 #define EOP_MRS(rd) EOP_C_MRS(A_COND_AL,rd)
217 #define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
218 #define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm)
221 static void emith_op_imm(int cond, int s, int op, int r, unsigned int imm)
223 int ror2, rd = r, rn = r;
231 for (v = imm, ror2 = 0; v != 0 || op == A_OP_MOV; v >>= 8, ror2 -= 8/2) {
232 /* shift down to get 'best' rot2 */
233 for (; v && !(v & 3); v >>= 2)
236 EOP_C_DOP_IMM(cond, op, s, rn, rd, ror2 & 0x0f, v & 0xff);
238 if (op == A_OP_MOV) {
246 #define emith_top_imm(cond, op, r, imm) { \
248 for (ror2 = 0, v = imm; v && !(v & 3); v >>= 2) \
250 EOP_C_DOP_IMM(cond, op, 1, r, 0, ror2 & 0x0f, v & 0xff); \
253 #define is_offset_24(val) \
254 ((val) >= (int)0xff000000 && (val) <= 0x00ffffff)
256 static int emith_xbranch(int cond, void *target, int is_call)
258 int val = (u32 *)target - (u32 *)tcache_ptr - 2;
259 int direct = is_offset_24(val);
260 u32 *start_ptr = (u32 *)tcache_ptr;
264 EOP_C_B(cond,is_call,val & 0xffffff); // b, bl target
269 // elprintf(EL_SVP, "emitting indirect jmp %08x->%08x", tcache_ptr, target);
271 EOP_ADD_IMM(14,15,0,8); // add lr,pc,#8
272 EOP_C_AM2_IMM(cond,1,0,1,15,15,0); // ldrcc pc,[pc]
273 EOP_MOV_REG_SIMPLE(15,15); // mov pc, pc
276 // should never happen
277 elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
282 return (u32 *)tcache_ptr - start_ptr;
286 // fake "simple" or "short" jump - using cond insns instead
287 #define EMITH_SJMP_START(cond) \
290 #define EMITH_SJMP_END(cond) \
293 #define emith_move_r_r(d, s) \
294 EOP_MOV_REG_SIMPLE(d, s)
296 #define emith_or_r_r_r_lsl(d, s1, s2, lslimm) \
297 EOP_ORR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
299 #define emith_eor_r_r_r_lsl(d, s1, s2, lslimm) \
300 EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
302 #define emith_or_r_r_r(d, s1, s2) \
303 emith_or_r_r_r_lsl(d, s1, s2, 0)
305 #define emith_eor_r_r_r(d, s1, s2) \
306 emith_eor_r_r_r_lsl(d, s1, s2, 0)
308 #define emith_add_r_r(d, s) \
309 EOP_ADD_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
311 #define emith_sub_r_r(d, s) \
312 EOP_SUB_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
314 #define emith_and_r_r(d, s) \
315 EOP_AND_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
317 #define emith_or_r_r(d, s) \
318 emith_or_r_r_r(d, d, s)
320 #define emith_eor_r_r(d, s) \
321 emith_eor_r_r_r(d, d, s)
323 #define emith_tst_r_r(d, s) \
324 EOP_TST_REG(A_COND_AL,d,s,A_AM1_LSL,0)
326 #define emith_teq_r_r(d, s) \
327 EOP_TEQ_REG(A_COND_AL,d,s,A_AM1_LSL,0)
329 #define emith_cmp_r_r(d, s) \
330 EOP_CMP_REG(A_COND_AL,d,s,A_AM1_LSL,0)
332 #define emith_addf_r_r(d, s) \
333 EOP_ADD_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
335 #define emith_subf_r_r(d, s) \
336 EOP_SUB_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
338 #define emith_adcf_r_r(d, s) \
339 EOP_ADC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
341 #define emith_sbcf_r_r(d, s) \
342 EOP_SBC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
344 #define emith_move_r_imm(r, imm) \
345 emith_op_imm(A_COND_AL, 0, A_OP_MOV, r, imm)
347 #define emith_add_r_imm(r, imm) \
348 emith_op_imm(A_COND_AL, 0, A_OP_ADD, r, imm)
350 #define emith_sub_r_imm(r, imm) \
351 emith_op_imm(A_COND_AL, 0, A_OP_SUB, r, imm)
353 #define emith_bic_r_imm(r, imm) \
354 emith_op_imm(A_COND_AL, 0, A_OP_BIC, r, imm)
356 #define emith_or_r_imm(r, imm) \
357 emith_op_imm(A_COND_AL, 0, A_OP_ORR, r, imm)
359 // note: only use 8bit imm for these
360 #define emith_tst_r_imm(r, imm) \
361 emith_top_imm(A_COND_AL, A_OP_TST, r, imm)
363 #define emith_cmp_r_imm(r, imm) \
364 emith_top_imm(A_COND_AL, A_OP_CMP, r, imm)
366 #define emith_subf_r_imm(r, imm) \
367 emith_op_imm(A_COND_AL, 1, A_OP_SUB, r, imm)
369 #define emith_add_r_imm_c(cond, r, imm) \
370 emith_op_imm(cond, 0, A_OP_ADD, r, imm)
372 #define emith_sub_r_imm_c(cond, r, imm) \
373 emith_op_imm(cond, 0, A_OP_SUB, r, imm)
375 #define emith_or_r_imm_c(cond, r, imm) \
376 emith_op_imm(cond, 0, A_OP_ORR, r, imm)
378 #define emith_bic_r_imm_c(cond, r, imm) \
379 emith_op_imm(cond, 0, A_OP_BIC, r, imm)
381 #define emith_lsl(d, s, cnt) \
382 EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSL,cnt)
384 #define emith_lsr(d, s, cnt) \
385 EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSR,cnt)
387 #define emith_ror(d, s, cnt) \
388 EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,cnt)
390 #define emith_lslf(d, s, cnt) \
391 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSL,cnt)
393 #define emith_lsrf(d, s, cnt) \
394 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSR,cnt)
396 #define emith_asrf(d, s, cnt) \
397 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ASR,cnt)
399 // note: only C flag updated correctly
400 #define emith_rolf(d, s, cnt) { \
401 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,32-(cnt)); \
402 /* we don't have ROL so we shift to get the right carry */ \
403 EOP_TST_REG(A_COND_AL,d,d,A_AM1_LSR,1); \
406 #define emith_rorf(d, s, cnt) \
407 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,cnt)
409 #define emith_rolcf(d) \
412 #define emith_rorcf(d) \
413 EOP_MOV_REG(A_COND_AL,1,d,d,A_AM1_ROR,0) /* ROR #0 -> RRX */
415 #define emith_mul(d, s1, s2) { \
416 if ((d) != (s1)) /* rd != rm limitation */ \
417 EOP_MUL(d, s1, s2); \
419 EOP_MUL(d, s2, s1); \
422 #define emith_mul_u64(dlo, dhi, s1, s2) \
423 EOP_C_UMULL(A_COND_AL,0,dhi,dlo,s1,s2)
425 #define emith_mul_s64(dlo, dhi, s1, s2) \
426 EOP_C_SMULL(A_COND_AL,0,dhi,dlo,s1,s2)
429 #define emith_ctx_read(r, offs) \
430 EOP_LDR_IMM(r, CONTEXT_REG, offs)
432 #define emith_ctx_write(r, offs) \
433 EOP_STR_IMM(r, CONTEXT_REG, offs)
435 #define emith_clear_msb(d, s, count) { \
437 if ((count) <= 8) { \
439 t = (0xff << t) & 0xff; \
440 EOP_BIC_IMM(d,s,8/2,t); \
441 } else if ((count) >= 24) { \
444 EOP_AND_IMM(d,s,0,t); \
446 EOP_MOV_REG_LSL(d,s,count); \
447 EOP_MOV_REG_LSR(d,d,count); \
451 #define emith_sext(d, s, bits) { \
452 EOP_MOV_REG_LSL(d,s,32 - (bits)); \
453 EOP_MOV_REG_ASR(d,d,32 - (bits)); \
456 // put bit0 of r0 to carry
457 #define emith_set_carry(r0) \
458 EOP_TST_REG(A_COND_AL,r0,r0,A_AM1_LSR,1) /* shift out to carry */ \
460 // put bit0 of r0 to carry (for subtraction, inverted on ARM)
461 #define emith_set_carry_sub(r0) { \
462 int t = rcache_get_tmp(); \
463 EOP_EOR_IMM(t,r0,0,1); /* invert */ \
464 EOP_MOV_REG(A_COND_AL,1,t,t,A_AM1_LSR,1); /* shift out to carry */ \
465 rcache_free_tmp(t); \
468 #define host_arg2reg(rd, arg) \
472 #define emith_pass_arg_r(arg, reg) \
473 EOP_MOV_REG_SIMPLE(arg, reg)
475 #define emith_pass_arg_imm(arg, imm) \
476 emith_move_r_imm(arg, imm)
478 #define emith_call_cond(cond, target) \
479 emith_xbranch(cond, target, 1)
481 #define emith_jump_cond(cond, target) \
482 emith_xbranch(cond, target, 0)
484 #define emith_call(target) \
485 emith_call_cond(A_COND_AL, target)
487 #define emith_jump(target) \
488 emith_jump_cond(A_COND_AL, target)
490 /* SH2 drc specific */
491 #define emith_sh2_test_t() { \
492 int r = rcache_get_reg(SHR_SR, RC_GR_READ); \
493 EOP_TST_IMM(r, 0, 1); \
496 #define emith_sh2_dtbf_loop() { \
498 tmp = rcache_get_tmp(); \
499 cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
500 rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW); \
501 emith_sub_r_imm(rn, 1); /* sub rn, #1 */ \
502 emith_bic_r_imm(cr, 1); /* bic cr, #1 */ \
503 emith_sub_r_imm(cr, (cycles+1) << 12); /* sub cr, #(cycles+1)<<12 */ \
505 emith_asrf(tmp, cr, 2+12); /* movs tmp, cr, asr #2+12 */ \
506 EOP_MOV_IMM_C(A_COND_MI,tmp,0,0); /* movmi tmp, #0 */ \
507 emith_lsl(cr, cr, 20); /* mov cr, cr, lsl #20 */ \
508 emith_lsr(cr, cr, 20); /* mov cr, cr, lsr #20 */ \
509 emith_subf_r_r(rn, tmp); /* subs rn, tmp */ \
510 EOP_RSB_IMM_C(A_COND_LS,tmp,rn,0,0); /* rsbls tmp, rn, #0 */ \
511 EOP_ORR_REG(A_COND_LS,0,cr,cr,tmp,A_AM1_LSL,12+2); /* orrls cr,tmp,lsl #12+2 */\
512 EOP_ORR_IMM_C(A_COND_LS,cr,cr,0,1); /* orrls cr, #1 */ \
513 EOP_MOV_IMM_C(A_COND_LS,rn,0,0); /* movls rn, #0 */ \
514 rcache_free_tmp(tmp); \
517 #define emith_write_sr(srcr) { \
518 int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
519 emith_lsr(srr, srr, 12); \
520 emith_or_r_r_r_lsl(srr, srr, srcr, 20); \
521 emith_ror(srr, srr, 20); \
524 #define emith_carry_to_t(srr, is_sub) { \
525 if (is_sub) { /* has inverted C on ARM */ \
526 emith_or_r_imm_c(A_COND_CC, srr, 1); \
527 emith_bic_r_imm_c(A_COND_CS, srr, 1); \
529 emith_or_r_imm_c(A_COND_CS, srr, 1); \
530 emith_bic_r_imm_c(A_COND_CC, srr, 1); \