3 * temp registers must be eax-edx due to use of SETcc and r/w 8/16.
4 * note about silly things like emith_eor_r_r_r:
5 * these are here because the compiler was designed
6 * for ARM as it's primary target.
10 enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
12 #define CONTEXT_REG xBP
15 #define ICOND_JNO 0x01
17 #define ICOND_JAE 0x03
19 #define ICOND_JNE 0x05
20 #define ICOND_JBE 0x06
23 #define ICOND_JNS 0x09
25 #define ICOND_JGE 0x0d
26 #define ICOND_JLE 0x0e
31 // unified conditions (we just use rel8 jump instructions for x86)
32 #define DCOND_EQ ICOND_JE
33 #define DCOND_NE ICOND_JNE
34 #define DCOND_MI ICOND_JS // MInus
35 #define DCOND_PL ICOND_JNS // PLus or zero
36 #define DCOND_HI ICOND_JA // higher (unsigned)
37 #define DCOND_HS ICOND_JAE // higher || same (unsigned)
38 #define DCOND_LO ICOND_JB // lower (unsigned)
39 #define DCOND_LS ICOND_JBE // lower || same (unsigned)
40 #define DCOND_GE ICOND_JGE // greater || equal (signed)
41 #define DCOND_GT ICOND_JG // greater (signed)
42 #define DCOND_LE ICOND_JLE // less || equal (signed)
43 #define DCOND_LT ICOND_JL // less (signed)
44 #define DCOND_VS ICOND_JO // oVerflow Set
45 #define DCOND_VC ICOND_JNO // oVerflow Clear
47 #define EMIT_PTR(ptr, val, type) \
50 #define EMIT(val, type) { \
51 EMIT_PTR(tcache_ptr, val, type); \
52 tcache_ptr += sizeof(type); \
55 #define EMIT_OP(op) { \
60 #define EMIT_MODRM(mod,r,rm) \
61 EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)
63 #define EMIT_SIB(scale,index,base) \
64 EMIT(((scale)<<6) | ((index)<<3) | (base), u8)
66 #define EMIT_OP_MODRM(op,mod,r,rm) do { \
68 EMIT_MODRM(mod, r, rm); \
71 #define JMP8_POS(ptr) \
75 #define JMP8_EMIT(op, ptr) \
76 EMIT_PTR(ptr, 0x70|(op), u8); \
77 EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
79 #define JMP8_EMIT_NC(ptr) \
80 EMIT_PTR(ptr, IOP_JMP, u8); \
81 EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
84 #define emith_move_r_r(dst, src) \
85 EMIT_OP_MODRM(0x8b, 3, dst, src)
87 #define emith_add_r_r(d, s) \
88 EMIT_OP_MODRM(0x01, 3, s, d)
90 #define emith_sub_r_r(d, s) \
91 EMIT_OP_MODRM(0x29, 3, s, d)
93 #define emith_adc_r_r(d, s) \
94 EMIT_OP_MODRM(0x11, 3, s, d)
96 #define emith_sbc_r_r(d, s) \
97 EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */
99 #define emith_or_r_r(d, s) \
100 EMIT_OP_MODRM(0x09, 3, s, d)
102 #define emith_and_r_r(d, s) \
103 EMIT_OP_MODRM(0x21, 3, s, d)
105 #define emith_eor_r_r(d, s) \
106 EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */
108 #define emith_tst_r_r(d, s) \
109 EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */
111 #define emith_cmp_r_r(d, s) \
112 EMIT_OP_MODRM(0x39, 3, s, d)
114 // fake teq - test equivalence - get_flags(d ^ s)
115 #define emith_teq_r_r(d, s) { \
117 emith_eor_r_r(d, s); \
121 #define emith_mvn_r_r(d, s) { \
123 emith_move_r_r(d, s); \
124 EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
127 #define emith_negc_r_r(d, s) { \
128 int tmp_ = rcache_get_tmp(); \
129 emith_move_r_imm(tmp_, 0); \
130 emith_sbc_r_r(tmp_, s); \
131 emith_move_r_r(d, tmp_); \
132 rcache_free_tmp(tmp_); \
135 #define emith_neg_r_r(d, s) { \
137 emith_move_r_r(d, s); \
138 EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
142 #define emith_eor_r_r_r(d, s1, s2) { \
144 emith_eor_r_r(d, s2); \
145 } else if (d == s2) { \
146 emith_eor_r_r(d, s1); \
148 emith_move_r_r(d, s1); \
149 emith_eor_r_r(d, s2); \
154 #define emith_or_r_r_lsl(d, s, lslimm) { \
155 int tmp_ = rcache_get_tmp(); \
156 emith_lsl(tmp_, s, lslimm); \
157 emith_or_r_r(d, tmp_); \
158 rcache_free_tmp(tmp_); \
162 #define emith_eor_r_r_lsr(d, s, lsrimm) { \
164 emith_lsr(s, s, lsrimm); \
165 emith_eor_r_r(d, s); \
170 #define emith_move_r_imm(r, imm) { \
171 EMIT_OP(0xb8 + (r)); \
175 #define emith_move_r_imm_s8(r, imm) \
176 emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
178 #define emith_arith_r_imm(op, r, imm) do { \
179 EMIT_OP_MODRM(0x81, 3, op, r); \
183 #define emith_add_r_imm(r, imm) \
184 emith_arith_r_imm(0, r, imm)
186 #define emith_or_r_imm(r, imm) \
187 emith_arith_r_imm(1, r, imm)
189 #define emith_adc_r_imm(r, imm) \
190 emith_arith_r_imm(2, r, imm)
192 #define emith_sbc_r_imm(r, imm) \
193 emith_arith_r_imm(3, r, imm) // sbb
195 #define emith_and_r_imm(r, imm) \
196 emith_arith_r_imm(4, r, imm)
198 #define emith_sub_r_imm(r, imm) \
199 emith_arith_r_imm(5, r, imm)
201 #define emith_eor_r_imm(r, imm) \
202 emith_arith_r_imm(6, r, imm)
204 #define emith_cmp_r_imm(r, imm) \
205 emith_arith_r_imm(7, r, imm)
207 #define emith_tst_r_imm(r, imm) do { \
208 EMIT_OP_MODRM(0xf7, 3, 0, r); \
213 #define emith_bic_r_imm(r, imm) \
214 emith_arith_r_imm(4, r, ~(imm))
216 // fake conditionals (using SJMP instead)
217 #define emith_move_r_imm_c(cond, r, imm) { \
219 emith_move_r_imm(r, imm); \
222 #define emith_add_r_imm_c(cond, r, imm) { \
224 emith_add_r_imm(r, imm); \
227 #define emith_sub_r_imm_c(cond, r, imm) { \
229 emith_sub_r_imm(r, imm); \
232 #define emith_or_r_imm_c(cond, r, imm) \
233 emith_or_r_imm(r, imm)
234 #define emith_eor_r_imm_c(cond, r, imm) \
235 emith_eor_r_imm(r, imm)
236 #define emith_bic_r_imm_c(cond, r, imm) \
237 emith_bic_r_imm(r, imm)
238 #define emith_ror_c(cond, d, s, cnt) \
241 #define emith_read_r_r_offs_c(cond, r, rs, offs) \
242 emith_read_r_r_offs(r, rs, offs)
243 #define emith_write_r_r_offs_c(cond, r, rs, offs) \
244 emith_write_r_r_offs(r, rs, offs)
245 #define emith_read8_r_r_offs_c(cond, r, rs, offs) \
246 emith_read8_r_r_offs(r, rs, offs)
247 #define emith_write8_r_r_offs_c(cond, r, rs, offs) \
248 emith_write8_r_r_offs(r, rs, offs)
249 #define emith_read16_r_r_offs_c(cond, r, rs, offs) \
250 emith_read16_r_r_offs(r, rs, offs)
251 #define emith_write16_r_r_offs_c(cond, r, rs, offs) \
252 emith_write16_r_r_offs(r, rs, offs)
253 #define emith_jump_reg_c(cond, r) \
255 #define emith_jump_ctx_c(cond, offs) \
257 #define emith_ret_c(cond) \
261 #define emith_add_r_r_imm(d, s, imm) { \
263 emith_move_r_r(d, s); \
264 emith_add_r_imm(d, imm); \
267 #define emith_and_r_r_imm(d, s, imm) { \
269 emith_move_r_r(d, s); \
270 emith_and_r_imm(d, imm); \
274 #define emith_shift(op, d, s, cnt) { \
276 emith_move_r_r(d, s); \
277 EMIT_OP_MODRM(0xc1, 3, op, d); \
281 #define emith_lsl(d, s, cnt) \
282 emith_shift(4, d, s, cnt)
284 #define emith_lsr(d, s, cnt) \
285 emith_shift(5, d, s, cnt)
287 #define emith_asr(d, s, cnt) \
288 emith_shift(7, d, s, cnt)
290 #define emith_rol(d, s, cnt) \
291 emith_shift(0, d, s, cnt)
293 #define emith_ror(d, s, cnt) \
294 emith_shift(1, d, s, cnt)
296 #define emith_rolc(r) \
297 EMIT_OP_MODRM(0xd1, 3, 2, r)
299 #define emith_rorc(r) \
300 EMIT_OP_MODRM(0xd1, 3, 3, r)
303 #define emith_push(r) \
306 #define emith_push_imm(imm) { \
311 #define emith_pop(r) \
314 #define emith_neg_r(r) \
315 EMIT_OP_MODRM(0xf7, 3, 3, r)
317 #define emith_clear_msb(d, s, count) { \
321 emith_move_r_r(d, s); \
322 emith_and_r_imm(d, t); \
325 #define emith_clear_msb_c(cond, d, s, count) { \
327 emith_clear_msb(d, s, count); \
330 #define emith_sext(d, s, bits) { \
331 emith_lsl(d, s, 32 - (bits)); \
332 emith_asr(d, d, 32 - (bits)); \
335 #define emith_setc(r) { \
337 EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
341 #define emith_mul_(op, dlo, dhi, s1, s2) { \
343 if (dlo != xAX && dhi != xAX) \
345 if (dlo != xDX && dhi != xDX) \
349 else if ((s2) == xAX) \
352 emith_move_r_r(xAX, s1); \
355 EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
356 /* XXX: using push/pop for the case of edx->eax; eax->edx */ \
357 if (dhi != xDX && dhi != -1) \
360 emith_move_r_r(dlo, xAX); \
361 if (dhi != xDX && dhi != -1) \
363 if (dlo != xDX && dhi != xDX) \
365 if (dlo != xAX && dhi != xAX) \
369 #define emith_mul_u64(dlo, dhi, s1, s2) \
370 emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
372 #define emith_mul_s64(dlo, dhi, s1, s2) \
373 emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
375 #define emith_mul(d, s1, s2) \
376 emith_mul_(4, d, -1, s1, s2)
378 // (dlo,dhi) += signed(s1) * signed(s2)
379 #define emith_mula_s64(dlo, dhi, s1, s2) { \
382 emith_mul_(5, dlo, dhi, s1, s2); \
383 EMIT_OP_MODRM(0x03, 0, dlo, 4); \
384 EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
385 EMIT_OP_MODRM(0x13, 1, dhi, 4); \
387 EMIT(4, u8); /* adc dhi, [esp+4] */ \
388 emith_add_r_imm(xSP, 4*2); \
391 // "flag" instructions are the same
392 #define emith_subf_r_imm emith_sub_r_imm
393 #define emith_addf_r_r emith_add_r_r
394 #define emith_subf_r_r emith_sub_r_r
395 #define emith_adcf_r_r emith_adc_r_r
396 #define emith_sbcf_r_r emith_sbc_r_r
397 #define emith_eorf_r_r emith_eor_r_r
398 #define emith_negcf_r_r emith_negc_r_r
400 #define emith_lslf emith_lsl
401 #define emith_lsrf emith_lsr
402 #define emith_asrf emith_asr
403 #define emith_rolf emith_rol
404 #define emith_rorf emith_ror
405 #define emith_rolcf emith_rolc
406 #define emith_rorcf emith_rorc
408 #define emith_deref_op(op, r, rs, offs) do { \
409 /* mov r <-> [ebp+#offs] */ \
410 if ((offs) >= 0x80) { \
411 EMIT_OP_MODRM(op, 2, r, rs); \
414 EMIT_OP_MODRM(op, 1, r, rs); \
419 #define is_abcdx(r) (xAX <= (r) && (r) <= xDX)
421 #define emith_read_r_r_offs(r, rs, offs) \
422 emith_deref_op(0x8b, r, rs, offs)
424 #define emith_write_r_r_offs(r, rs, offs) \
425 emith_deref_op(0x89, r, rs, offs)
427 // note: don't use prefixes on this
428 #define emith_read8_r_r_offs(r, rs, offs) do { \
431 r_ = rcache_get_tmp(); \
432 emith_deref_op(0x8a, r_, rs, offs); \
434 emith_move_r_r(r, r_); \
435 rcache_free_tmp(r_); \
439 #define emith_write8_r_r_offs(r, rs, offs) do {\
441 if (!is_abcdx(r)) { \
442 r_ = rcache_get_tmp(); \
443 emith_move_r_r(r_, r); \
445 emith_deref_op(0x88, r_, rs, offs); \
447 rcache_free_tmp(r_); \
450 #define emith_read16_r_r_offs(r, rs, offs) { \
451 EMIT(0x66, u8); /* operand override */ \
452 emith_read_r_r_offs(r, rs, offs); \
455 #define emith_write16_r_r_offs(r, rs, offs) { \
457 emith_write_r_r_offs(r, rs, offs); \
460 #define emith_ctx_read(r, offs) \
461 emith_read_r_r_offs(r, CONTEXT_REG, offs)
463 #define emith_ctx_write(r, offs) \
464 emith_write_r_r_offs(r, CONTEXT_REG, offs)
466 #define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
467 int r_ = r, offs_ = offs, cnt_ = cnt; \
468 for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
469 emith_ctx_read(r_, offs_); \
472 #define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
473 int r_ = r, offs_ = offs, cnt_ = cnt; \
474 for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
475 emith_ctx_write(r_, offs_); \
478 // assumes EBX is free
479 #define emith_ret_to_ctx(offs) { \
481 emith_ctx_write(xBX, offs); \
484 #define emith_jump(ptr) { \
485 u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
490 #define emith_jump_patchable(target) \
493 #define emith_jump_cond(cond, ptr) { \
494 u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \
496 EMIT_OP(0x80 | (cond)); \
500 #define emith_jump_cond_patchable(cond, target) \
501 emith_jump_cond(cond, target)
503 #define emith_jump_patch(ptr, target) do { \
504 u32 disp_ = (u32)(target) - ((u32)(ptr) + 4); \
505 u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \
506 EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
509 #define emith_jump_at(ptr, target) { \
510 u32 disp_ = (u32)(target) - ((u32)(ptr) + 5); \
511 EMIT_PTR(ptr, 0xe9, u8); \
512 EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
515 #define emith_call(ptr) { \
516 u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
521 #define emith_call_cond(cond, ptr) \
524 #define emith_call_reg(r) \
525 EMIT_OP_MODRM(0xff, 3, 2, r)
527 #define emith_call_ctx(offs) { \
528 EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
532 #define emith_ret() \
535 #define emith_jump_reg(r) \
536 EMIT_OP_MODRM(0xff, 3, 4, r)
538 #define emith_jump_ctx(offs) { \
539 EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
543 #define emith_push_ret()
545 #define emith_pop_and_ret() \
548 #define EMITH_JMP_START(cond) { \
552 #define EMITH_JMP_END(cond) \
553 JMP8_EMIT(cond, cond_ptr); \
556 #define EMITH_JMP3_START(cond) { \
557 u8 *cond_ptr, *else_ptr; \
560 #define EMITH_JMP3_MID(cond) \
561 JMP8_POS(else_ptr); \
562 JMP8_EMIT(cond, cond_ptr);
564 #define EMITH_JMP3_END() \
565 JMP8_EMIT_NC(else_ptr); \
568 // "simple" jump (no more then a few insns)
569 // ARM will use conditional instructions here
570 #define EMITH_SJMP_START EMITH_JMP_START
571 #define EMITH_SJMP_END EMITH_JMP_END
573 #define EMITH_SJMP3_START EMITH_JMP3_START
574 #define EMITH_SJMP3_MID EMITH_JMP3_MID
575 #define EMITH_SJMP3_END EMITH_JMP3_END
577 #define emith_pass_arg_r(arg, reg) { \
579 host_arg2reg(rd, arg); \
580 emith_move_r_r(rd, reg); \
583 #define emith_pass_arg_imm(arg, imm) { \
585 host_arg2reg(rd, arg); \
586 emith_move_r_imm(rd, imm); \
589 #define host_instructions_updated(base, end)
591 #define host_arg2reg(rd, arg) \
593 case 0: rd = xAX; break; \
594 case 1: rd = xDX; break; \
595 case 2: rd = xCX; break; \
598 /* SH2 drc specific */
599 #define emith_sh2_drc_entry() { \
606 #define emith_sh2_drc_exit() { \
614 // assumes EBX is free temporary
615 #define emith_sh2_wcall(a, tab, ret_ptr) { \
617 host_arg2reg(arg2_, 2); \
618 emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
619 EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
620 EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
621 emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \
622 emith_push_imm((long)(ret_ptr)); \
623 emith_jump_reg(xBX); \
626 #define emith_sh2_dtbf_loop() { \
627 u8 *jmp0; /* negative cycles check */ \
628 u8 *jmp1; /* unsinged overflow check */ \
630 int tmp_ = rcache_get_tmp(); \
631 cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
632 rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
633 emith_sub_r_imm(rn, 1); \
634 emith_sub_r_imm(cr, (cycles+1) << 12); \
636 emith_asr(tmp_, cr, 2+12); \
637 JMP8_POS(jmp0); /* no negative cycles */ \
638 emith_move_r_imm(tmp_, 0); \
639 JMP8_EMIT(ICOND_JNS, jmp0); \
640 emith_and_r_imm(cr, 0xffe); \
641 emith_subf_r_r(rn, tmp_); \
642 JMP8_POS(jmp1); /* no overflow */ \
643 emith_neg_r(rn); /* count left */ \
644 emith_lsl(rn, rn, 2+12); \
645 emith_or_r_r(cr, rn); \
646 emith_or_r_imm(cr, 1); \
647 emith_move_r_imm(rn, 0); \
648 JMP8_EMIT(ICOND_JA, jmp1); \
649 rcache_free_tmp(tmp_); \
652 #define emith_write_sr(sr, srcr) { \
653 int tmp_ = rcache_get_tmp(); \
654 emith_clear_msb(tmp_, srcr, 22); \
655 emith_bic_r_imm(sr, 0x3ff); \
656 emith_or_r_r(sr, tmp_); \
657 rcache_free_tmp(tmp_); \
660 #define emith_tpop_carry(sr, is_sub) \
663 #define emith_tpush_carry(sr, is_sub) \
664 emith_adc_r_r(sr, sr)
668 * t = carry(Rn += Rm)
670 * t = carry(Rn -= Rm)
673 #define emith_sh2_div1_step(rn, rm, sr) { \
675 int tmp_ = rcache_get_tmp(); \
676 emith_eor_r_r(tmp_, tmp_); \
677 emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
678 JMP8_POS(jmp0); /* je do_sub */ \
679 emith_add_r_r(rn, rm); \
680 JMP8_POS(jmp1); /* jmp done */ \
681 JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */ \
682 emith_sub_r_r(rn, rm); \
683 JMP8_EMIT_NC(jmp1); /* done: */ \
685 EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
686 rcache_free_tmp(tmp_); \