11 static int reg_map_g2h[] = {
20 enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
22 #define EMIT_PTR(ptr, val, type) \
25 #define EMIT(val, type) { \
26 EMIT_PTR(tcache_ptr, val, type); \
27 tcache_ptr = (char *)tcache_ptr + sizeof(type); \
30 #define EMIT_OP(op) { \
35 #define EMIT_MODRM(mod,r,rm) \
36 EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)
38 #define EMIT_OP_MODRM(op,mod,r,rm) { \
40 EMIT_MODRM(mod, r, rm); \
43 #define emith_move_r_r(dst, src) \
44 EMIT_OP_MODRM(0x8b, 3, dst, src)
46 #define emith_move_r_imm(r, imm) { \
47 EMIT_OP(0xb8 + (r)); \
51 #define emith_add_r_imm(r, imm) { \
52 EMIT_OP_MODRM(0x81, 3, 0, r); \
56 #define emith_sub_r_imm(r, imm) { \
57 EMIT_OP_MODRM(0x81, 3, 5, r); \
61 // XXX: offs is 8bit only
62 #define emith_ctx_read(r, offs) { \
63 EMIT_OP_MODRM(0x8b, 1, r, 5); \
64 EMIT(offs, u8); /* mov tmp, [ebp+#offs] */ \
67 #define emith_ctx_write(r, offs) { \
68 EMIT_OP_MODRM(0x89, 1, r, 5); \
69 EMIT(offs, u8); /* mov [ebp+#offs], tmp */ \
72 #define emith_ctx_sub(val, offs) { \
73 EMIT_OP_MODRM(0x81, 1, 5, 5); \
75 EMIT(val, u32); /* sub [ebp+#offs], dword val */ \
78 #define emith_test_t() { \
79 if (reg_map_g2h[SHR_SR] == -1) { \
80 EMIT_OP_MODRM(0xf6, 1, 0, 5); \
81 EMIT(SHR_SR * 4, u8); \
82 EMIT(0x01, u8); /* test [ebp+SHR_SR], byte 1 */ \
84 EMIT_OP_MODRM(0xf7, 3, 0, reg_map_g2h[SHR_SR]); \
85 EMIT(0x01, u16); /* test <reg>, word 1 */ \
89 #define emith_jump(ptr) { \
90 u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
95 #define emith_call(ptr) { \
96 u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
101 #define EMIT_CONDITIONAL(code, is_nonzero) { \
102 char *ptr = tcache_ptr; \
103 tcache_ptr = (char *)tcache_ptr + 2; \
105 EMIT_PTR(ptr, ((is_nonzero) ? 0x75 : 0x74), u8); \
106 EMIT_PTR(ptr + 1, ((char *)tcache_ptr - (ptr + 2)), u8); \
109 static void emith_pass_arg(int count, ...)
116 for (i = 0; i < count; i++) {
117 long av = va_arg(vl, long);
121 case 0: r = xAX; break;
122 case 1: r = xDX; break;
123 case 2: r = xCX; break;
125 emith_move_r_imm(r, av);