6 /* ======================================================================== */
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7 /* ========================= LICENSING & COPYRIGHT ======================== */
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8 /* ======================================================================== */
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13 * A portable Motorola M680x0 processor emulation engine.
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14 * Copyright 1998-2001 Karl Stenerud. All rights reserved.
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16 * This code may be freely used for non-commercial purposes as long as this
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17 * copyright notice remains unaltered in the source code and any binary files
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18 * containing this code in compiled form.
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20 * All other lisencing terms must be negotiated with the author
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23 * The latest version of this code can be obtained at:
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24 * http://kstenerud.cjb.net
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27 /* Special thanks to Bart Trzynadlowski for his insight into the
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28 * undocumented features of this chip:
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30 * http://dynarec.com/~bart/files/68knotes.txt
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34 /* Input file for m68kmake
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35 * -----------------------
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37 * All sections begin with 80 X's in a row followed by an end-of-line
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39 * After this, m68kmake will expect to find one of the following section
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41 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
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42 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
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43 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
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44 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
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45 * M68KMAKE_TABLE_BODY - the table itself
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46 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
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47 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
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48 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
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50 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
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51 * M68KMAKE_TABLE_BODY must be second last in the file.
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53 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
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54 * primitives themselves. Each opcode handler begins with:
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55 * M68KMAKE_OP(A, B, C, D)
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57 * where A is the opcode handler name, B is the size of the operation,
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58 * C denotes any special processing mode, and D denotes a specific
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60 * For C and D where nothing is specified, use "."
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63 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
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64 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
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65 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
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67 * All opcode handler primitives end with a closing curly brace "}" at column 1
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69 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
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70 * and do not put a closing curly brace at column 1 unless it is
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71 * marking the end of the handler!
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73 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
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74 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
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75 * opcode handlers to handle variations in the opcode handler.
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76 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
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77 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
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78 * be interpreted on instructions where the corresponding table entry
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79 * specifies multiple effective addressing modes.
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81 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
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83 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
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84 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
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85 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
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88 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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89 M68KMAKE_PROTOTYPE_HEADER
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91 #ifndef M68KOPS__HEADER
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92 #define M68KOPS__HEADER
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94 /* ======================================================================== */
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95 /* ============================ OPCODE HANDLERS =========================== */
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96 /* ======================================================================== */
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100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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101 M68KMAKE_PROTOTYPE_FOOTER
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104 /* Build the opcode handler table */
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105 void m68ki_build_opcode_table(void);
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107 extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
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108 extern unsigned char m68ki_cycles[][0x10000];
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111 /* ======================================================================== */
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112 /* ============================== END OF FILE ============================= */
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113 /* ======================================================================== */
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115 #endif /* M68KOPS__HEADER */
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119 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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120 M68KMAKE_TABLE_HEADER
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122 /* ======================================================================== */
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123 /* ========================= OPCODE TABLE BUILDER ========================= */
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124 /* ======================================================================== */
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126 #include "m68kops.h"
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128 #define NUM_CPU_TYPES 4
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130 void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
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131 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
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133 /* This is used to generate the opcode handler jump table */
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136 void (*opcode_handler)(void); /* handler function */
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137 unsigned int mask; /* mask on opcode */
\r
138 unsigned int match; /* what to match after masking */
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139 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
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140 } opcode_handler_struct;
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143 /* Opcode handler table */
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144 static opcode_handler_struct m68k_opcode_handler_table[] =
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146 /* function mask match 000 010 020 040 */
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150 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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151 M68KMAKE_TABLE_FOOTER
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153 {0, 0, 0, {0, 0, 0, 0}}
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157 /* Build the opcode handler jump table */
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158 void m68ki_build_opcode_table(void)
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160 opcode_handler_struct *ostruct;
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166 for(i = 0; i < 0x10000; i++)
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168 /* default to illegal */
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169 m68ki_instruction_jump_table[i] = m68k_op_illegal;
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170 for(k=0;k<NUM_CPU_TYPES;k++)
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171 m68ki_cycles[k][i] = 0;
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174 ostruct = m68k_opcode_handler_table;
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175 while(ostruct->mask != 0xff00)
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177 for(i = 0;i < 0x10000;i++)
\r
179 if((i & ostruct->mask) == ostruct->match)
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181 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
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182 for(k=0;k<NUM_CPU_TYPES;k++)
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183 m68ki_cycles[k][i] = ostruct->cycles[k];
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188 while(ostruct->mask == 0xff00)
\r
190 for(i = 0;i <= 0xff;i++)
\r
192 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
\r
193 for(k=0;k<NUM_CPU_TYPES;k++)
\r
194 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
\r
198 while(ostruct->mask == 0xf1f8)
\r
200 for(i = 0;i < 8;i++)
\r
202 for(j = 0;j < 8;j++)
\r
204 instr = ostruct->match | (i << 9) | j;
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205 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
\r
206 for(k=0;k<NUM_CPU_TYPES;k++)
\r
207 m68ki_cycles[k][instr] = ostruct->cycles[k];
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212 while(ostruct->mask == 0xfff0)
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214 for(i = 0;i <= 0x0f;i++)
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216 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
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217 for(k=0;k<NUM_CPU_TYPES;k++)
\r
218 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
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222 while(ostruct->mask == 0xf1ff)
\r
224 for(i = 0;i <= 0x07;i++)
\r
226 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
\r
227 for(k=0;k<NUM_CPU_TYPES;k++)
\r
228 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
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232 while(ostruct->mask == 0xfff8)
\r
234 for(i = 0;i <= 0x07;i++)
\r
236 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
\r
237 for(k=0;k<NUM_CPU_TYPES;k++)
\r
238 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
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242 while(ostruct->mask == 0xffff)
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244 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
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245 for(k=0;k<NUM_CPU_TYPES;k++)
\r
246 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
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252 /* ======================================================================== */
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253 /* ============================== END OF FILE ============================= */
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254 /* ======================================================================== */
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258 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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259 M68KMAKE_OPCODE_HANDLER_HEADER
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261 #include "m68kcpu.h"
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263 /* ======================================================================== */
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264 /* ========================= INSTRUCTION HANDLERS ========================= */
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265 /* ======================================================================== */
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269 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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270 M68KMAKE_OPCODE_HANDLER_FOOTER
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272 /* ======================================================================== */
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273 /* ============================== END OF FILE ============================= */
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274 /* ======================================================================== */
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278 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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279 M68KMAKE_TABLE_BODY
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281 The following table is arranged as follows:
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283 name: Opcode mnemonic
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285 size: Operation size
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287 spec proc: Special processing mode:
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290 r: register operand
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291 rr: register to register
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292 mm: memory to memory
\r
293 er: effective address to register
\r
294 re: register to effective address
\r
295 dd: data register to data register
\r
296 da: data register to address register
\r
297 aa: address register to address register
\r
298 cr: control register to register
\r
299 rc: register to control register
\r
300 toc: to condition code register
\r
301 tos: to status register
\r
302 tou: to user stack pointer
\r
303 frc: from condition code register
\r
304 frs: from status register
\r
305 fru: from user stack pointer
\r
306 * for move.x, the special processing mode is a specific
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307 destination effective addressing mode.
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309 spec ea: Specific effective addressing mode:
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313 a: address register
\r
314 ai: address register indirect
\r
315 pi: address register indirect with postincrement
\r
316 pd: address register indirect with predecrement
\r
317 di: address register indirect with displacement
\r
318 ix: address register indirect with index
\r
319 aw: absolute word address
\r
320 al: absolute long address
\r
321 pcdi: program counter relative with displacement
\r
322 pcix: program counter relative with index
\r
323 a7: register specified in instruction is A7
\r
324 ax7: register field X of instruction is A7
\r
325 ay7: register field Y of instruction is A7
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326 axy7: register fields X and Y of instruction are A7
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328 bit pattern: Pattern to recognize this opcode. "." means don't care.
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330 allowed ea: List of allowed addressing modes:
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332 A: address register indirect
\r
333 +: ARI (address register indirect) with postincrement
\r
334 -: ARI with predecrement
\r
335 D: ARI with displacement
\r
337 W: absolute word address
\r
338 L: absolute long address
\r
339 d: program counter indirect with displacement
\r
340 x: program counter indirect with index
\r
342 mode: CPU operating mode for each cpu type. U = user or supervisor,
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343 S = supervisor only, "." = opcode not present.
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345 cpu cycles: Base number of cycles required to execute this opcode on the
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346 specified CPU type.
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347 Use "." if CPU does not have this opcode.
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351 spec spec allowed ea mode cpu cycles
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352 name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments
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353 ====== ==== ==== ==== ================ ========== = = = = === === === === =============
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354 M68KMAKE_TABLE_START
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355 1010 0 . . 1010............ .......... U U U U 4 4 4 4
\r
356 1111 0 . . 1111............ .......... U U U U 4 4 4 4
\r
357 abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4
\r
358 abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16
\r
359 abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16
\r
360 abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16
\r
361 abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16
\r
362 add 8 er d 1101...000000... .......... U U U U 4 4 2 2
\r
363 add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
364 add 16 er d 1101...001000... .......... U U U U 4 4 2 2
\r
365 add 16 er a 1101...001001... .......... U U U U 4 4 2 2
\r
366 add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
367 add 32 er d 1101...010000... .......... U U U U 6 6 2 2
\r
368 add 32 er a 1101...010001... .......... U U U U 6 6 2 2
\r
369 add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
370 add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4
\r
371 add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4
\r
372 add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4
\r
373 adda 16 . d 1101...011000... .......... U U U U 8 8 2 2
\r
374 adda 16 . a 1101...011001... .......... U U U U 8 8 2 2
\r
375 adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2
\r
376 adda 32 . d 1101...111000... .......... U U U U 6 6 2 2
\r
377 adda 32 . a 1101...111001... .......... U U U U 6 6 2 2
\r
378 adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2
\r
379 addi 8 . d 0000011000000... .......... U U U U 8 8 2 2
\r
380 addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4
\r
381 addi 16 . d 0000011001000... .......... U U U U 8 8 2 2
\r
382 addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4
\r
383 addi 32 . d 0000011010000... .......... U U U U 16 14 2 2
\r
384 addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4
\r
385 addq 8 . d 0101...000000... .......... U U U U 4 4 2 2
\r
386 addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4
\r
387 addq 16 . d 0101...001000... .......... U U U U 4 4 2 2
\r
388 addq 16 . a 0101...001001... .......... U U U U 4 4 2 2
\r
389 addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4
\r
390 addq 32 . d 0101...010000... .......... U U U U 8 8 2 2
\r
391 addq 32 . a 0101...010001... .......... U U U U 8 8 2 2
\r
392 addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4
\r
393 addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2
\r
394 addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2
\r
395 addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2
\r
396 addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12
\r
397 addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12
\r
398 addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12
\r
399 addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12
\r
400 addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12
\r
401 addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12
\r
402 and 8 er d 1100...000000... .......... U U U U 4 4 2 2
\r
403 and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
404 and 16 er d 1100...001000... .......... U U U U 4 4 2 2
\r
405 and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
406 and 32 er d 1100...010000... .......... U U U U 6 6 2 2
\r
407 and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
408 and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4
\r
409 and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4
\r
410 and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4
\r
411 andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12
\r
412 andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12
\r
413 andi 8 . d 0000001000000... .......... U U U U 8 8 2 2
\r
414 andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4
\r
415 andi 16 . d 0000001001000... .......... U U U U 8 8 2 2
\r
416 andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4
\r
417 andi 32 . d 0000001010000... .......... U U U U 14 14 2 2
\r
418 andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4
\r
419 asr 8 s . 1110...000000... .......... U U U U 6 6 6 6
\r
420 asr 16 s . 1110...001000... .......... U U U U 6 6 6 6
\r
421 asr 32 s . 1110...010000... .......... U U U U 8 8 6 6
\r
422 asr 8 r . 1110...000100... .......... U U U U 6 6 6 6
\r
423 asr 16 r . 1110...001100... .......... U U U U 6 6 6 6
\r
424 asr 32 r . 1110...010100... .......... U U U U 8 8 6 6
\r
425 asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5
\r
426 asl 8 s . 1110...100000... .......... U U U U 6 6 8 8
\r
427 asl 16 s . 1110...101000... .......... U U U U 6 6 8 8
\r
428 asl 32 s . 1110...110000... .......... U U U U 8 8 8 8
\r
429 asl 8 r . 1110...100100... .......... U U U U 6 6 8 8
\r
430 asl 16 r . 1110...101100... .......... U U U U 6 6 8 8
\r
431 asl 32 r . 1110...110100... .......... U U U U 8 8 8 8
\r
432 asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6
\r
433 bcc 8 . . 0110............ .......... U U U U 10 10 6 6
\r
434 bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6
\r
435 bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6
\r
436 bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4
\r
437 bchg 32 r d 0000...101000... .......... U U U U 8 8 4 4
\r
438 bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4
\r
439 bchg 32 s d 0000100001000... .......... U U U U 12 12 4 4
\r
440 bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 10 4 4
\r
441 bclr 32 r d 0000...110000... .......... U U U U 10 10 4 4
\r
442 bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4
\r
443 bclr 32 s d 0000100010000... .......... U U U U 14 14 4 4
\r
444 bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct
\r
445 bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20
\r
446 bfclr 32 . d 1110110011000... .......... . . U U . . 12 12
\r
447 bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20
\r
448 bfexts 32 . d 1110101111000... .......... . . U U . . 8 8
\r
449 bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15
\r
450 bfextu 32 . d 1110100111000... .......... . . U U . . 8 8
\r
451 bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15
\r
452 bfffo 32 . d 1110110111000... .......... . . U U . . 18 18
\r
453 bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28
\r
454 bfins 32 . d 1110111111000... .......... . . U U . . 10 10
\r
455 bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17
\r
456 bfset 32 . d 1110111011000... .......... . . U U . . 12 12
\r
457 bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20
\r
458 bftst 32 . d 1110100011000... .......... . . U U . . 6 6
\r
459 bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13
\r
460 bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10
\r
461 bra 8 . . 01100000........ .......... U U U U 10 10 10 10
\r
462 bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10
\r
463 bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10
\r
464 bset 32 r d 0000...111000... .......... U U U U 8 8 4 4
\r
465 bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4
\r
466 bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4
\r
467 bset 32 s d 0000100011000... .......... U U U U 12 12 4 4
\r
468 bsr 8 . . 01100001........ .......... U U U U 18 18 7 7
\r
469 bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7
\r
470 bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7
\r
471 btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4
\r
472 btst 32 r d 0000...100000... .......... U U U U 6 6 4 4
\r
473 btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4
\r
474 btst 32 s d 0000100000000... .......... U U U U 10 10 4 4
\r
475 callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated
\r
476 cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12
\r
477 cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12
\r
478 cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12
\r
479 cas2 16 . . 0000110011111100 .......... . . U U . . 12 12
\r
480 cas2 32 . . 0000111011111100 .......... . . U U . . 12 12
\r
481 chk 16 . d 0100...110000... .......... U U U U 10 8 8 8
\r
482 chk 16 . . 0100...110...... A+-DXWLdxI U U U U 10 8 8 8
\r
483 chk 32 . d 0100...100000... .......... . . U U . . 8 8
\r
484 chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8
\r
485 chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23
\r
486 chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23
\r
487 chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18
\r
488 chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23
\r
489 chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23
\r
490 chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18
\r
491 chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23
\r
492 chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23
\r
493 chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18
\r
494 clr 8 . d 0100001000000... .......... U U U U 4 4 2 2
\r
495 clr 8 . . 0100001000...... A+-DXWL... U U U U 6 4 4 4 notaz hack: changed 000 cycles 8 -> 6 like in starscream for Fatal Rewind
\r
496 clr 16 . d 0100001001000... .......... U U U U 4 4 2 2
\r
497 clr 16 . . 0100001001...... A+-DXWL... U U U U 6 4 4 4 ditto
\r
498 clr 32 . d 0100001010000... .......... U U U U 6 6 2 2
\r
499 clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4
\r
500 cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2
\r
501 cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
502 cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2
\r
503 cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2
\r
504 cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
505 cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2
\r
506 cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2
\r
507 cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
508 cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4
\r
509 cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4
\r
510 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4
\r
511 cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4
\r
512 cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4
\r
513 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4
\r
514 cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2
\r
515 cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2
\r
516 cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7
\r
517 cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9
\r
518 cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2
\r
519 cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2
\r
520 cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7
\r
521 cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9
\r
522 cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2
\r
523 cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2
\r
524 cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7
\r
525 cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9
\r
526 cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9
\r
527 cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9
\r
528 cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9
\r
529 cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9
\r
530 cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9
\r
531 cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9
\r
532 cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated
\r
533 cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated
\r
534 cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated
\r
535 cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated
\r
536 cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated
\r
537 dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6
\r
538 dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6
\r
539 dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6
\r
540 divs 16 . d 1000...111000... .......... U U U U 158 122 56 56
\r
541 divs 16 . . 1000...111...... A+-DXWLdxI U U U U 158 122 56 56
\r
542 divu 16 . d 1000...011000... .......... U U U U 140 108 44 44
\r
543 divu 16 . . 1000...011...... A+-DXWLdxI U U U U 140 108 44 44
\r
544 divl 32 . d 0100110001000... .......... . . U U . . 84 84
\r
545 divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84
\r
546 eor 8 . d 1011...100000... .......... U U U U 4 4 2 2
\r
547 eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4
\r
548 eor 16 . d 1011...101000... .......... U U U U 4 4 2 2
\r
549 eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4
\r
550 eor 32 . d 1011...110000... .......... U U U U 8 6 2 2
\r
551 eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4
\r
552 eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12
\r
553 eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12
\r
554 eori 8 . d 0000101000000... .......... U U U U 8 8 2 2
\r
555 eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4
\r
556 eori 16 . d 0000101001000... .......... U U U U 8 8 2 2
\r
557 eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4
\r
558 eori 32 . d 0000101010000... .......... U U U U 16 14 2 2
\r
559 eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4
\r
560 exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2
\r
561 exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2
\r
562 exg 32 da . 1100...110001... .......... U U U U 6 6 2 2
\r
563 ext 16 . . 0100100010000... .......... U U U U 4 4 4 4
\r
564 ext 32 . . 0100100011000... .......... U U U U 4 4 4 4
\r
565 extb 32 . . 0100100111000... .......... . . U U . . 4 4
\r
566 illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4
\r
567 jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0
\r
568 jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0
\r
569 lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2
\r
570 link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5
\r
571 link 16 . . 0100111001010... .......... U U U U 16 16 5 5
\r
572 link 32 . a7 0100100000001111 .......... . . U U . . 6 6
\r
573 link 32 . . 0100100000001... .......... . . U U . . 6 6
\r
574 lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4
\r
575 lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4
\r
576 lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4
\r
577 lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6
\r
578 lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6
\r
579 lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6
\r
580 lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5
\r
581 lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4
\r
582 lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4
\r
583 lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4
\r
584 lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6
\r
585 lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6
\r
586 lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6
\r
587 lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5
\r
588 move 8 d d 0001...000000... .......... U U U U 4 4 2 2
\r
589 move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
590 move 8 ai d 0001...010000... .......... U U U U 8 8 4 4
\r
591 move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4
\r
592 move 8 pi d 0001...011000... .......... U U U U 8 8 4 4
\r
593 move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4
\r
594 move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4
\r
595 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4
\r
596 move 8 pd d 0001...100000... .......... U U U U 8 8 5 5
\r
597 move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5
\r
598 move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5
\r
599 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5
\r
600 move 8 di d 0001...101000... .......... U U U U 12 12 5 5
\r
601 move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5
\r
602 move 8 ix d 0001...110000... .......... U U U U 14 14 7 7
\r
603 move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7
\r
604 move 8 aw d 0001000111000... .......... U U U U 12 12 4 4
\r
605 move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4
\r
606 move 8 al d 0001001111000... .......... U U U U 16 16 6 6
\r
607 move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6
\r
608 move 16 d d 0011...000000... .......... U U U U 4 4 2 2
\r
609 move 16 d a 0011...000001... .......... U U U U 4 4 2 2
\r
610 move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
611 move 16 ai d 0011...010000... .......... U U U U 8 8 4 4
\r
612 move 16 ai a 0011...010001... .......... U U U U 8 8 4 4
\r
613 move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4
\r
614 move 16 pi d 0011...011000... .......... U U U U 8 8 4 4
\r
615 move 16 pi a 0011...011001... .......... U U U U 8 8 4 4
\r
616 move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4
\r
617 move 16 pd d 0011...100000... .......... U U U U 8 8 5 5
\r
618 move 16 pd a 0011...100001... .......... U U U U 8 8 5 5
\r
619 move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5
\r
620 move 16 di d 0011...101000... .......... U U U U 12 12 5 5
\r
621 move 16 di a 0011...101001... .......... U U U U 12 12 5 5
\r
622 move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5
\r
623 move 16 ix d 0011...110000... .......... U U U U 14 14 7 7
\r
624 move 16 ix a 0011...110001... .......... U U U U 14 14 7 7
\r
625 move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7
\r
626 move 16 aw d 0011000111000... .......... U U U U 12 12 4 4
\r
627 move 16 aw a 0011000111001... .......... U U U U 12 12 4 4
\r
628 move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4
\r
629 move 16 al d 0011001111000... .......... U U U U 16 16 6 6
\r
630 move 16 al a 0011001111001... .......... U U U U 16 16 6 6
\r
631 move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6
\r
632 move 32 d d 0010...000000... .......... U U U U 4 4 2 2
\r
633 move 32 d a 0010...000001... .......... U U U U 4 4 2 2
\r
634 move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
635 move 32 ai d 0010...010000... .......... U U U U 12 12 4 4
\r
636 move 32 ai a 0010...010001... .......... U U U U 12 12 4 4
\r
637 move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4
\r
638 move 32 pi d 0010...011000... .......... U U U U 12 12 4 4
\r
639 move 32 pi a 0010...011001... .......... U U U U 12 12 4 4
\r
640 move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4
\r
641 move 32 pd d 0010...100000... .......... U U U U 12 14 5 5
\r
642 move 32 pd a 0010...100001... .......... U U U U 12 14 5 5
\r
643 move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5
\r
644 move 32 di d 0010...101000... .......... U U U U 16 16 5 5
\r
645 move 32 di a 0010...101001... .......... U U U U 16 16 5 5
\r
646 move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5
\r
647 move 32 ix d 0010...110000... .......... U U U U 18 18 7 7
\r
648 move 32 ix a 0010...110001... .......... U U U U 18 18 7 7
\r
649 move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7
\r
650 move 32 aw d 0010000111000... .......... U U U U 16 16 4 4
\r
651 move 32 aw a 0010000111001... .......... U U U U 16 16 4 4
\r
652 move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4
\r
653 move 32 al d 0010001111000... .......... U U U U 20 20 6 6
\r
654 move 32 al a 0010001111001... .......... U U U U 20 20 6 6
\r
655 move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6
\r
656 movea 16 . d 0011...001000... .......... U U U U 4 4 2 2
\r
657 movea 16 . a 0011...001001... .......... U U U U 4 4 2 2
\r
658 movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
659 movea 32 . d 0010...001000... .......... U U U U 4 4 2 2
\r
660 movea 32 . a 0010...001001... .......... U U U U 4 4 2 2
\r
661 movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
662 move 16 frc d 0100001011000... .......... . U U U . 4 4 4
\r
663 move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4
\r
664 move 16 toc d 0100010011000... .......... U U U U 12 12 4 4
\r
665 move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4
\r
666 move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000
\r
667 move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000
\r
668 move 16 tos d 0100011011000... .......... S S S S 12 12 8 8
\r
669 move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8
\r
670 move 32 fru . 0100111001101... .......... S S S S 4 6 2 2
\r
671 move 32 tou . 0100111001100... .......... S S S S 4 6 2 2
\r
672 movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6
\r
673 movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12
\r
674 movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4
\r
675 movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4
\r
676 movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4
\r
677 movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4
\r
678 movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8
\r
679 movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9
\r
680 movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11
\r
681 movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8
\r
682 movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8
\r
683 movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9
\r
684 movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11
\r
685 movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8
\r
686 movep 16 er . 0000...100001... .......... U U U U 16 16 12 12
\r
687 movep 32 er . 0000...101001... .......... U U U U 24 24 18 18
\r
688 movep 16 re . 0000...110001... .......... U U U U 16 16 11 11
\r
689 movep 32 re . 0000...111001... .......... U U U U 24 24 17 17
\r
690 moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2
\r
691 moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5
\r
692 moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5
\r
693 moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5
\r
694 move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing
\r
695 muls 16 . d 1100...111000... .......... U U U U 54 32 27 27
\r
696 muls 16 . . 1100...111...... A+-DXWLdxI U U U U 54 32 27 27
\r
697 mulu 16 . d 1100...011000... .......... U U U U 54 30 27 27
\r
698 mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 54 30 27 27
\r
699 mull 32 . d 0100110000000... .......... . . U U . . 43 43
\r
700 mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43
\r
701 nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6
\r
702 nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6
\r
703 neg 8 . d 0100010000000... .......... U U U U 4 4 2 2
\r
704 neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4
\r
705 neg 16 . d 0100010001000... .......... U U U U 4 4 2 2
\r
706 neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4
\r
707 neg 32 . d 0100010010000... .......... U U U U 6 6 2 2
\r
708 neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4
\r
709 negx 8 . d 0100000000000... .......... U U U U 4 4 2 2
\r
710 negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4
\r
711 negx 16 . d 0100000001000... .......... U U U U 4 4 2 2
\r
712 negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4
\r
713 negx 32 . d 0100000010000... .......... U U U U 6 6 2 2
\r
714 negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4
\r
715 nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2
\r
716 not 8 . d 0100011000000... .......... U U U U 4 4 2 2
\r
717 not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4
\r
718 not 16 . d 0100011001000... .......... U U U U 4 4 2 2
\r
719 not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4
\r
720 not 32 . d 0100011010000... .......... U U U U 6 6 2 2
\r
721 not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4
\r
722 or 8 er d 1000...000000... .......... U U U U 4 4 2 2
\r
723 or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
724 or 16 er d 1000...001000... .......... U U U U 4 4 2 2
\r
725 or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
726 or 32 er d 1000...010000... .......... U U U U 6 6 2 2
\r
727 or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
728 or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4
\r
729 or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4
\r
730 or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4
\r
731 ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12
\r
732 ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12
\r
733 ori 8 . d 0000000000000... .......... U U U U 8 8 2 2
\r
734 ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4
\r
735 ori 16 . d 0000000001000... .......... U U U U 8 8 2 2
\r
736 ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4
\r
737 ori 32 . d 0000000010000... .......... U U U U 16 14 2 2
\r
738 ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4
\r
739 pack 16 rr . 1000...101000... .......... . . U U . . 6 6
\r
740 pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13
\r
741 pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13
\r
742 pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13
\r
743 pack 16 mm . 1000...101001... .......... . . U U . . 13 13
\r
744 pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5
\r
745 pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing
\r
746 reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0
\r
747 ror 8 s . 1110...000011... .......... U U U U 6 6 8 8
\r
748 ror 16 s . 1110...001011... .......... U U U U 6 6 8 8
\r
749 ror 32 s . 1110...010011... .......... U U U U 8 8 8 8
\r
750 ror 8 r . 1110...000111... .......... U U U U 6 6 8 8
\r
751 ror 16 r . 1110...001111... .......... U U U U 6 6 8 8
\r
752 ror 32 r . 1110...010111... .......... U U U U 8 8 8 8
\r
753 ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7
\r
754 rol 8 s . 1110...100011... .......... U U U U 6 6 8 8
\r
755 rol 16 s . 1110...101011... .......... U U U U 6 6 8 8
\r
756 rol 32 s . 1110...110011... .......... U U U U 8 8 8 8
\r
757 rol 8 r . 1110...100111... .......... U U U U 6 6 8 8
\r
758 rol 16 r . 1110...101111... .......... U U U U 6 6 8 8
\r
759 rol 32 r . 1110...110111... .......... U U U U 8 8 8 8
\r
760 rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7
\r
761 roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12
\r
762 roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12
\r
763 roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12
\r
764 roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12
\r
765 roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12
\r
766 roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12
\r
767 roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5
\r
768 roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12
\r
769 roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12
\r
770 roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12
\r
771 roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12
\r
772 roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12
\r
773 roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12
\r
774 roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5
\r
775 rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10
\r
776 rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated
\r
777 rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated
\r
778 rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14
\r
779 rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10
\r
780 sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4
\r
781 sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16
\r
782 sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16
\r
783 sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16
\r
784 sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16
\r
785 st 8 . d 0101000011000... .......... U U U U 6 4 4 4
\r
786 st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6
\r
787 sf 8 . d 0101000111000... .......... U U U U 4 4 4 4
\r
788 sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6
\r
789 scc 8 . d 0101....11000... .......... U U U U 4 4 4 4
\r
790 scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6
\r
791 stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8
\r
792 sub 8 er d 1001...000000... .......... U U U U 4 4 2 2
\r
793 sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
794 sub 16 er d 1001...001000... .......... U U U U 4 4 2 2
\r
795 sub 16 er a 1001...001001... .......... U U U U 4 4 2 2
\r
796 sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
797 sub 32 er d 1001...010000... .......... U U U U 6 6 2 2
\r
798 sub 32 er a 1001...010001... .......... U U U U 6 6 2 2
\r
799 sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
800 sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4
\r
801 sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4
\r
802 sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4
\r
803 suba 16 . d 1001...011000... .......... U U U U 8 8 2 2
\r
804 suba 16 . a 1001...011001... .......... U U U U 8 8 2 2
\r
805 suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2
\r
806 suba 32 . d 1001...111000... .......... U U U U 6 6 2 2
\r
807 suba 32 . a 1001...111001... .......... U U U U 6 6 2 2
\r
808 suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2
\r
809 subi 8 . d 0000010000000... .......... U U U U 8 8 2 2
\r
810 subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4
\r
811 subi 16 . d 0000010001000... .......... U U U U 8 8 2 2
\r
812 subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4
\r
813 subi 32 . d 0000010010000... .......... U U U U 16 14 2 2
\r
814 subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4
\r
815 subq 8 . d 0101...100000... .......... U U U U 4 4 2 2
\r
816 subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4
\r
817 subq 16 . d 0101...101000... .......... U U U U 4 4 2 2
\r
818 subq 16 . a 0101...101001... .......... U U U U 8 4 2 2
\r
819 subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4
\r
820 subq 32 . d 0101...110000... .......... U U U U 8 8 2 2
\r
821 subq 32 . a 0101...110001... .......... U U U U 8 8 2 2
\r
822 subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4
\r
823 subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2
\r
824 subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2
\r
825 subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2
\r
826 subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12
\r
827 subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12
\r
828 subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12
\r
829 subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12
\r
830 subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12
\r
831 subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12
\r
832 swap 32 . . 0100100001000... .......... U U U U 4 4 4 4
\r
833 tas 8 . d 0100101011000... .......... U U U U 4 4 4 4
\r
834 tas 8 . . 0100101011...... A+-DXWL... U U U U 14 14 12 12
\r
835 trap 0 . . 010011100100.... .......... U U U U 4 4 4 4
\r
836 trapt 0 . . 0101000011111100 .......... . . U U . . 4 4
\r
837 trapt 16 . . 0101000011111010 .......... . . U U . . 6 6
\r
838 trapt 32 . . 0101000011111011 .......... . . U U . . 8 8
\r
839 trapf 0 . . 0101000111111100 .......... . . U U . . 4 4
\r
840 trapf 16 . . 0101000111111010 .......... . . U U . . 6 6
\r
841 trapf 32 . . 0101000111111011 .......... . . U U . . 8 8
\r
842 trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4
\r
843 trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6
\r
844 trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8
\r
845 trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4
\r
846 tst 8 . d 0100101000000... .......... U U U U 4 4 2 2
\r
847 tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2
\r
848 tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7
\r
849 tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9
\r
850 tst 8 . i 0100101000111100 .......... . . U U . . 6 6
\r
851 tst 16 . d 0100101001000... .......... U U U U 4 4 2 2
\r
852 tst 16 . a 0100101001001... .......... . . U U . . 2 2
\r
853 tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2
\r
854 tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7
\r
855 tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9
\r
856 tst 16 . i 0100101001111100 .......... . . U U . . 6 6
\r
857 tst 32 . d 0100101010000... .......... U U U U 4 4 2 2
\r
858 tst 32 . a 0100101010001... .......... . . U U . . 2 2
\r
859 tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2
\r
860 tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7
\r
861 tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9
\r
862 tst 32 . i 0100101010111100 .......... . . U U . . 6 6
\r
863 unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6
\r
864 unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6
\r
865 unpk 16 rr . 1000...110000... .......... . . U U . . 8 8
\r
866 unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13
\r
867 unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13
\r
868 unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13
\r
869 unpk 16 mm . 1000...110001... .......... . . U U . . 13 13
\r
873 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
\r
874 M68KMAKE_OPCODE_HANDLER_BODY
\r
876 M68KMAKE_OP(1010, 0, ., .)
\r
878 m68ki_exception_1010();
\r
882 M68KMAKE_OP(1111, 0, ., .)
\r
884 m68ki_exception_1111();
\r
888 M68KMAKE_OP(abcd, 8, rr, .)
\r
893 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
895 FLAG_V = ~res; /* Undefined V behavior */
\r
899 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
900 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
904 FLAG_V &= res; /* Undefined V behavior part II */
\r
905 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
907 res = MASK_OUT_ABOVE_8(res);
\r
910 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
914 M68KMAKE_OP(abcd, 8, mm, ax7)
\r
916 uint src = OPER_AY_PD_8();
\r
917 uint ea = EA_A7_PD_8();
\r
918 uint dst = m68ki_read_8(ea);
\r
919 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
921 FLAG_V = ~res; /* Undefined V behavior */
\r
925 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
926 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
930 FLAG_V &= res; /* Undefined V behavior part II */
\r
931 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
933 res = MASK_OUT_ABOVE_8(res);
\r
936 m68ki_write_8(ea, res);
\r
940 M68KMAKE_OP(abcd, 8, mm, ay7)
\r
942 uint src = OPER_A7_PD_8();
\r
943 uint ea = EA_AX_PD_8();
\r
944 uint dst = m68ki_read_8(ea);
\r
945 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
947 FLAG_V = ~res; /* Undefined V behavior */
\r
951 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
952 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
956 FLAG_V &= res; /* Undefined V behavior part II */
\r
957 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
959 res = MASK_OUT_ABOVE_8(res);
\r
962 m68ki_write_8(ea, res);
\r
966 M68KMAKE_OP(abcd, 8, mm, axy7)
\r
968 uint src = OPER_A7_PD_8();
\r
969 uint ea = EA_A7_PD_8();
\r
970 uint dst = m68ki_read_8(ea);
\r
971 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
973 FLAG_V = ~res; /* Undefined V behavior */
\r
977 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
978 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
982 FLAG_V &= res; /* Undefined V behavior part II */
\r
983 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
985 res = MASK_OUT_ABOVE_8(res);
\r
988 m68ki_write_8(ea, res);
\r
992 M68KMAKE_OP(abcd, 8, mm, .)
\r
994 uint src = OPER_AY_PD_8();
\r
995 uint ea = EA_AX_PD_8();
\r
996 uint dst = m68ki_read_8(ea);
\r
997 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
999 FLAG_V = ~res; /* Undefined V behavior */
\r
1003 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
1004 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
1008 FLAG_V &= res; /* Undefined V behavior part II */
\r
1009 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
1011 res = MASK_OUT_ABOVE_8(res);
\r
1014 m68ki_write_8(ea, res);
\r
1018 M68KMAKE_OP(add, 8, er, d)
\r
1020 uint* r_dst = &DX;
\r
1021 uint src = MASK_OUT_ABOVE_8(DY);
\r
1022 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1023 uint res = src + dst;
\r
1025 FLAG_N = NFLAG_8(res);
\r
1026 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1027 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1028 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1030 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1034 M68KMAKE_OP(add, 8, er, .)
\r
1036 uint* r_dst = &DX;
\r
1037 uint src = M68KMAKE_GET_OPER_AY_8;
\r
1038 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1039 uint res = src + dst;
\r
1041 FLAG_N = NFLAG_8(res);
\r
1042 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1043 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1044 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1046 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1050 M68KMAKE_OP(add, 16, er, d)
\r
1052 uint* r_dst = &DX;
\r
1053 uint src = MASK_OUT_ABOVE_16(DY);
\r
1054 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1055 uint res = src + dst;
\r
1057 FLAG_N = NFLAG_16(res);
\r
1058 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1059 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1060 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1062 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1066 M68KMAKE_OP(add, 16, er, a)
\r
1068 uint* r_dst = &DX;
\r
1069 uint src = MASK_OUT_ABOVE_16(AY);
\r
1070 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1071 uint res = src + dst;
\r
1073 FLAG_N = NFLAG_16(res);
\r
1074 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1075 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1076 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1078 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1082 M68KMAKE_OP(add, 16, er, .)
\r
1084 uint* r_dst = &DX;
\r
1085 uint src = M68KMAKE_GET_OPER_AY_16;
\r
1086 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1087 uint res = src + dst;
\r
1089 FLAG_N = NFLAG_16(res);
\r
1090 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1091 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1092 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1094 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1098 M68KMAKE_OP(add, 32, er, d)
\r
1100 uint* r_dst = &DX;
\r
1102 uint dst = *r_dst;
\r
1103 uint res = src + dst;
\r
1105 FLAG_N = NFLAG_32(res);
\r
1106 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1107 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1108 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1114 M68KMAKE_OP(add, 32, er, a)
\r
1116 uint* r_dst = &DX;
\r
1118 uint dst = *r_dst;
\r
1119 uint res = src + dst;
\r
1121 FLAG_N = NFLAG_32(res);
\r
1122 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1123 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1124 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1130 M68KMAKE_OP(add, 32, er, .)
\r
1132 uint* r_dst = &DX;
\r
1133 uint src = M68KMAKE_GET_OPER_AY_32;
\r
1134 uint dst = *r_dst;
\r
1135 uint res = src + dst;
\r
1137 FLAG_N = NFLAG_32(res);
\r
1138 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1139 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1140 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1146 M68KMAKE_OP(add, 8, re, .)
\r
1148 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1149 uint src = MASK_OUT_ABOVE_8(DX);
\r
1150 uint dst = m68ki_read_8(ea);
\r
1151 uint res = src + dst;
\r
1153 FLAG_N = NFLAG_8(res);
\r
1154 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1155 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1156 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1158 m68ki_write_8(ea, FLAG_Z);
\r
1162 M68KMAKE_OP(add, 16, re, .)
\r
1164 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1165 uint src = MASK_OUT_ABOVE_16(DX);
\r
1166 uint dst = m68ki_read_16(ea);
\r
1167 uint res = src + dst;
\r
1169 FLAG_N = NFLAG_16(res);
\r
1170 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1171 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1172 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1174 m68ki_write_16(ea, FLAG_Z);
\r
1178 M68KMAKE_OP(add, 32, re, .)
\r
1180 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1182 uint dst = m68ki_read_32(ea);
\r
1183 uint res = src + dst;
\r
1185 FLAG_N = NFLAG_32(res);
\r
1186 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1187 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1188 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1190 m68ki_write_32(ea, FLAG_Z);
\r
1194 M68KMAKE_OP(adda, 16, ., d)
\r
1196 uint* r_dst = &AX;
\r
1198 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
\r
1202 M68KMAKE_OP(adda, 16, ., a)
\r
1204 uint* r_dst = &AX;
\r
1206 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
\r
1210 M68KMAKE_OP(adda, 16, ., .)
\r
1212 uint* r_dst = &AX;
\r
1214 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(M68KMAKE_GET_OPER_AY_16));
\r
1218 M68KMAKE_OP(adda, 32, ., d)
\r
1220 uint* r_dst = &AX;
\r
1222 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
\r
1226 M68KMAKE_OP(adda, 32, ., a)
\r
1228 uint* r_dst = &AX;
\r
1230 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
\r
1234 M68KMAKE_OP(adda, 32, ., .)
\r
1236 uint* r_dst = &AX;
\r
1238 *r_dst = MASK_OUT_ABOVE_32(*r_dst + M68KMAKE_GET_OPER_AY_32);
\r
1242 M68KMAKE_OP(addi, 8, ., d)
\r
1244 uint* r_dst = &DY;
\r
1245 uint src = OPER_I_8();
\r
1246 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1247 uint res = src + dst;
\r
1249 FLAG_N = NFLAG_8(res);
\r
1250 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1251 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1252 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1254 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1258 M68KMAKE_OP(addi, 8, ., .)
\r
1260 uint src = OPER_I_8();
\r
1261 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1262 uint dst = m68ki_read_8(ea);
\r
1263 uint res = src + dst;
\r
1265 FLAG_N = NFLAG_8(res);
\r
1266 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1267 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1268 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1270 m68ki_write_8(ea, FLAG_Z);
\r
1274 M68KMAKE_OP(addi, 16, ., d)
\r
1276 uint* r_dst = &DY;
\r
1277 uint src = OPER_I_16();
\r
1278 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1279 uint res = src + dst;
\r
1281 FLAG_N = NFLAG_16(res);
\r
1282 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1283 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1284 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1286 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1290 M68KMAKE_OP(addi, 16, ., .)
\r
1292 uint src = OPER_I_16();
\r
1293 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1294 uint dst = m68ki_read_16(ea);
\r
1295 uint res = src + dst;
\r
1297 FLAG_N = NFLAG_16(res);
\r
1298 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1299 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1300 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1302 m68ki_write_16(ea, FLAG_Z);
\r
1306 M68KMAKE_OP(addi, 32, ., d)
\r
1308 uint* r_dst = &DY;
\r
1309 uint src = OPER_I_32();
\r
1310 uint dst = *r_dst;
\r
1311 uint res = src + dst;
\r
1313 FLAG_N = NFLAG_32(res);
\r
1314 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1315 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1316 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1322 M68KMAKE_OP(addi, 32, ., .)
\r
1324 uint src = OPER_I_32();
\r
1325 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1326 uint dst = m68ki_read_32(ea);
\r
1327 uint res = src + dst;
\r
1329 FLAG_N = NFLAG_32(res);
\r
1330 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1331 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1332 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1334 m68ki_write_32(ea, FLAG_Z);
\r
1338 M68KMAKE_OP(addq, 8, ., d)
\r
1340 uint* r_dst = &DY;
\r
1341 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1342 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1343 uint res = src + dst;
\r
1345 FLAG_N = NFLAG_8(res);
\r
1346 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1347 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1348 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1350 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1354 M68KMAKE_OP(addq, 8, ., .)
\r
1356 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1357 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1358 uint dst = m68ki_read_8(ea);
\r
1359 uint res = src + dst;
\r
1361 FLAG_N = NFLAG_8(res);
\r
1362 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1363 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1364 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1366 m68ki_write_8(ea, FLAG_Z);
\r
1370 M68KMAKE_OP(addq, 16, ., d)
\r
1372 uint* r_dst = &DY;
\r
1373 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1374 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1375 uint res = src + dst;
\r
1377 FLAG_N = NFLAG_16(res);
\r
1378 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1379 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1380 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1382 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1386 M68KMAKE_OP(addq, 16, ., a)
\r
1388 uint* r_dst = &AY;
\r
1390 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
\r
1394 M68KMAKE_OP(addq, 16, ., .)
\r
1396 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1397 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1398 uint dst = m68ki_read_16(ea);
\r
1399 uint res = src + dst;
\r
1401 FLAG_N = NFLAG_16(res);
\r
1402 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1403 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1404 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1406 m68ki_write_16(ea, FLAG_Z);
\r
1410 M68KMAKE_OP(addq, 32, ., d)
\r
1412 uint* r_dst = &DY;
\r
1413 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1414 uint dst = *r_dst;
\r
1415 uint res = src + dst;
\r
1417 FLAG_N = NFLAG_32(res);
\r
1418 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1419 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1420 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1426 M68KMAKE_OP(addq, 32, ., a)
\r
1428 uint* r_dst = &AY;
\r
1430 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
\r
1434 M68KMAKE_OP(addq, 32, ., .)
\r
1436 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1437 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1438 uint dst = m68ki_read_32(ea);
\r
1439 uint res = src + dst;
\r
1442 FLAG_N = NFLAG_32(res);
\r
1443 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1444 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1445 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1447 m68ki_write_32(ea, FLAG_Z);
\r
1451 M68KMAKE_OP(addx, 8, rr, .)
\r
1453 uint* r_dst = &DX;
\r
1454 uint src = MASK_OUT_ABOVE_8(DY);
\r
1455 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1456 uint res = src + dst + XFLAG_AS_1();
\r
1458 FLAG_N = NFLAG_8(res);
\r
1459 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1460 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1462 res = MASK_OUT_ABOVE_8(res);
\r
1465 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1469 M68KMAKE_OP(addx, 16, rr, .)
\r
1471 uint* r_dst = &DX;
\r
1472 uint src = MASK_OUT_ABOVE_16(DY);
\r
1473 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1474 uint res = src + dst + XFLAG_AS_1();
\r
1476 FLAG_N = NFLAG_16(res);
\r
1477 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1478 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1480 res = MASK_OUT_ABOVE_16(res);
\r
1483 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1487 M68KMAKE_OP(addx, 32, rr, .)
\r
1489 uint* r_dst = &DX;
\r
1491 uint dst = *r_dst;
\r
1492 uint res = src + dst + XFLAG_AS_1();
\r
1494 FLAG_N = NFLAG_32(res);
\r
1495 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1496 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1498 res = MASK_OUT_ABOVE_32(res);
\r
1505 M68KMAKE_OP(addx, 8, mm, ax7)
\r
1507 uint src = OPER_AY_PD_8();
\r
1508 uint ea = EA_A7_PD_8();
\r
1509 uint dst = m68ki_read_8(ea);
\r
1510 uint res = src + dst + XFLAG_AS_1();
\r
1512 FLAG_N = NFLAG_8(res);
\r
1513 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1514 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1516 res = MASK_OUT_ABOVE_8(res);
\r
1519 m68ki_write_8(ea, res);
\r
1523 M68KMAKE_OP(addx, 8, mm, ay7)
\r
1525 uint src = OPER_A7_PD_8();
\r
1526 uint ea = EA_AX_PD_8();
\r
1527 uint dst = m68ki_read_8(ea);
\r
1528 uint res = src + dst + XFLAG_AS_1();
\r
1530 FLAG_N = NFLAG_8(res);
\r
1531 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1532 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1534 res = MASK_OUT_ABOVE_8(res);
\r
1537 m68ki_write_8(ea, res);
\r
1541 M68KMAKE_OP(addx, 8, mm, axy7)
\r
1543 uint src = OPER_A7_PD_8();
\r
1544 uint ea = EA_A7_PD_8();
\r
1545 uint dst = m68ki_read_8(ea);
\r
1546 uint res = src + dst + XFLAG_AS_1();
\r
1548 FLAG_N = NFLAG_8(res);
\r
1549 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1550 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1552 res = MASK_OUT_ABOVE_8(res);
\r
1555 m68ki_write_8(ea, res);
\r
1559 M68KMAKE_OP(addx, 8, mm, .)
\r
1561 uint src = OPER_AY_PD_8();
\r
1562 uint ea = EA_AX_PD_8();
\r
1563 uint dst = m68ki_read_8(ea);
\r
1564 uint res = src + dst + XFLAG_AS_1();
\r
1566 FLAG_N = NFLAG_8(res);
\r
1567 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1568 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1570 res = MASK_OUT_ABOVE_8(res);
\r
1573 m68ki_write_8(ea, res);
\r
1577 M68KMAKE_OP(addx, 16, mm, .)
\r
1579 uint src = OPER_AY_PD_16();
\r
1580 uint ea = EA_AX_PD_16();
\r
1581 uint dst = m68ki_read_16(ea);
\r
1582 uint res = src + dst + XFLAG_AS_1();
\r
1584 FLAG_N = NFLAG_16(res);
\r
1585 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1586 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1588 res = MASK_OUT_ABOVE_16(res);
\r
1591 m68ki_write_16(ea, res);
\r
1595 M68KMAKE_OP(addx, 32, mm, .)
\r
1597 uint src = OPER_AY_PD_32();
\r
1598 uint ea = EA_AX_PD_32();
\r
1599 uint dst = m68ki_read_32(ea);
\r
1600 uint res = src + dst + XFLAG_AS_1();
\r
1602 FLAG_N = NFLAG_32(res);
\r
1603 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1604 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1606 res = MASK_OUT_ABOVE_32(res);
\r
1609 m68ki_write_32(ea, res);
\r
1613 M68KMAKE_OP(and, 8, er, d)
\r
1615 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
\r
1617 FLAG_N = NFLAG_8(FLAG_Z);
\r
1618 FLAG_C = CFLAG_CLEAR;
\r
1619 FLAG_V = VFLAG_CLEAR;
\r
1623 M68KMAKE_OP(and, 8, er, .)
\r
1625 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
\r
1627 FLAG_N = NFLAG_8(FLAG_Z);
\r
1628 FLAG_C = CFLAG_CLEAR;
\r
1629 FLAG_V = VFLAG_CLEAR;
\r
1633 M68KMAKE_OP(and, 16, er, d)
\r
1635 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
\r
1637 FLAG_N = NFLAG_16(FLAG_Z);
\r
1638 FLAG_C = CFLAG_CLEAR;
\r
1639 FLAG_V = VFLAG_CLEAR;
\r
1643 M68KMAKE_OP(and, 16, er, .)
\r
1645 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
\r
1647 FLAG_N = NFLAG_16(FLAG_Z);
\r
1648 FLAG_C = CFLAG_CLEAR;
\r
1649 FLAG_V = VFLAG_CLEAR;
\r
1653 M68KMAKE_OP(and, 32, er, d)
\r
1655 FLAG_Z = DX &= DY;
\r
1657 FLAG_N = NFLAG_32(FLAG_Z);
\r
1658 FLAG_C = CFLAG_CLEAR;
\r
1659 FLAG_V = VFLAG_CLEAR;
\r
1663 M68KMAKE_OP(and, 32, er, .)
\r
1665 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
\r
1667 FLAG_N = NFLAG_32(FLAG_Z);
\r
1668 FLAG_C = CFLAG_CLEAR;
\r
1669 FLAG_V = VFLAG_CLEAR;
\r
1673 M68KMAKE_OP(and, 8, re, .)
\r
1675 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1676 uint res = DX & m68ki_read_8(ea);
\r
1678 FLAG_N = NFLAG_8(res);
\r
1679 FLAG_C = CFLAG_CLEAR;
\r
1680 FLAG_V = VFLAG_CLEAR;
\r
1681 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1683 m68ki_write_8(ea, FLAG_Z);
\r
1687 M68KMAKE_OP(and, 16, re, .)
\r
1689 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1690 uint res = DX & m68ki_read_16(ea);
\r
1692 FLAG_N = NFLAG_16(res);
\r
1693 FLAG_C = CFLAG_CLEAR;
\r
1694 FLAG_V = VFLAG_CLEAR;
\r
1695 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1697 m68ki_write_16(ea, FLAG_Z);
\r
1701 M68KMAKE_OP(and, 32, re, .)
\r
1703 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1704 uint res = DX & m68ki_read_32(ea);
\r
1706 FLAG_N = NFLAG_32(res);
\r
1708 FLAG_C = CFLAG_CLEAR;
\r
1709 FLAG_V = VFLAG_CLEAR;
\r
1711 m68ki_write_32(ea, res);
\r
1715 M68KMAKE_OP(andi, 8, ., d)
\r
1717 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
\r
1719 FLAG_N = NFLAG_8(FLAG_Z);
\r
1720 FLAG_C = CFLAG_CLEAR;
\r
1721 FLAG_V = VFLAG_CLEAR;
\r
1725 M68KMAKE_OP(andi, 8, ., .)
\r
1727 uint src = OPER_I_8();
\r
1728 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1729 uint res = src & m68ki_read_8(ea);
\r
1731 FLAG_N = NFLAG_8(res);
\r
1733 FLAG_C = CFLAG_CLEAR;
\r
1734 FLAG_V = VFLAG_CLEAR;
\r
1736 m68ki_write_8(ea, res);
\r
1740 M68KMAKE_OP(andi, 16, ., d)
\r
1742 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
\r
1744 FLAG_N = NFLAG_16(FLAG_Z);
\r
1745 FLAG_C = CFLAG_CLEAR;
\r
1746 FLAG_V = VFLAG_CLEAR;
\r
1750 M68KMAKE_OP(andi, 16, ., .)
\r
1752 uint src = OPER_I_16();
\r
1753 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1754 uint res = src & m68ki_read_16(ea);
\r
1756 FLAG_N = NFLAG_16(res);
\r
1758 FLAG_C = CFLAG_CLEAR;
\r
1759 FLAG_V = VFLAG_CLEAR;
\r
1761 m68ki_write_16(ea, res);
\r
1765 M68KMAKE_OP(andi, 32, ., d)
\r
1767 FLAG_Z = DY &= (OPER_I_32());
\r
1769 FLAG_N = NFLAG_32(FLAG_Z);
\r
1770 FLAG_C = CFLAG_CLEAR;
\r
1771 FLAG_V = VFLAG_CLEAR;
\r
1775 M68KMAKE_OP(andi, 32, ., .)
\r
1777 uint src = OPER_I_32();
\r
1778 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1779 uint res = src & m68ki_read_32(ea);
\r
1781 FLAG_N = NFLAG_32(res);
\r
1783 FLAG_C = CFLAG_CLEAR;
\r
1784 FLAG_V = VFLAG_CLEAR;
\r
1786 m68ki_write_32(ea, res);
\r
1790 M68KMAKE_OP(andi, 16, toc, .)
\r
1792 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
\r
1796 M68KMAKE_OP(andi, 16, tos, .)
\r
1800 uint src = OPER_I_16();
\r
1801 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
1802 m68ki_set_sr(m68ki_get_sr() & src);
\r
1805 m68ki_exception_privilege_violation();
\r
1809 M68KMAKE_OP(asr, 8, s, .)
\r
1811 uint* r_dst = &DY;
\r
1812 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1813 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
1814 uint res = src >> shift;
\r
1817 USE_CYCLES(shift<<CYC_SHIFT);
\r
1819 if(GET_MSB_8(src))
\r
1820 res |= m68ki_shift_8_table[shift];
\r
1822 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1824 FLAG_N = NFLAG_8(res);
\r
1826 FLAG_V = VFLAG_CLEAR;
\r
1827 FLAG_X = FLAG_C = src << (9-shift);
\r
1831 M68KMAKE_OP(asr, 16, s, .)
\r
1833 uint* r_dst = &DY;
\r
1834 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1835 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
1836 uint res = src >> shift;
\r
1839 USE_CYCLES(shift<<CYC_SHIFT);
\r
1841 if(GET_MSB_16(src))
\r
1842 res |= m68ki_shift_16_table[shift];
\r
1844 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1846 FLAG_N = NFLAG_16(res);
\r
1848 FLAG_V = VFLAG_CLEAR;
\r
1849 FLAG_X = FLAG_C = src << (9-shift);
\r
1853 M68KMAKE_OP(asr, 32, s, .)
\r
1855 uint* r_dst = &DY;
\r
1856 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1857 uint src = *r_dst;
\r
1858 uint res = src >> shift;
\r
1861 USE_CYCLES(shift<<CYC_SHIFT);
\r
1863 if(GET_MSB_32(src))
\r
1864 res |= m68ki_shift_32_table[shift];
\r
1868 FLAG_N = NFLAG_32(res);
\r
1870 FLAG_V = VFLAG_CLEAR;
\r
1871 FLAG_X = FLAG_C = src << (9-shift);
\r
1875 M68KMAKE_OP(asr, 8, r, .)
\r
1877 uint* r_dst = &DY;
\r
1878 uint shift = DX & 0x3f;
\r
1879 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
1880 uint res = src >> shift;
\r
1884 USE_CYCLES(shift<<CYC_SHIFT);
\r
1888 if(GET_MSB_8(src))
\r
1889 res |= m68ki_shift_8_table[shift];
\r
1891 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1893 FLAG_X = FLAG_C = src << (9-shift);
\r
1894 FLAG_N = NFLAG_8(res);
\r
1896 FLAG_V = VFLAG_CLEAR;
\r
1900 if(GET_MSB_8(src))
\r
1903 FLAG_C = CFLAG_SET;
\r
1904 FLAG_X = XFLAG_SET;
\r
1905 FLAG_N = NFLAG_SET;
\r
1906 FLAG_Z = ZFLAG_CLEAR;
\r
1907 FLAG_V = VFLAG_CLEAR;
\r
1911 *r_dst &= 0xffffff00;
\r
1912 FLAG_C = CFLAG_CLEAR;
\r
1913 FLAG_X = XFLAG_CLEAR;
\r
1914 FLAG_N = NFLAG_CLEAR;
\r
1915 FLAG_Z = ZFLAG_SET;
\r
1916 FLAG_V = VFLAG_CLEAR;
\r
1920 FLAG_C = CFLAG_CLEAR;
\r
1921 FLAG_N = NFLAG_8(src);
\r
1923 FLAG_V = VFLAG_CLEAR;
\r
1927 M68KMAKE_OP(asr, 16, r, .)
\r
1929 uint* r_dst = &DY;
\r
1930 uint shift = DX & 0x3f;
\r
1931 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
1932 uint res = src >> shift;
\r
1936 USE_CYCLES(shift<<CYC_SHIFT);
\r
1940 if(GET_MSB_16(src))
\r
1941 res |= m68ki_shift_16_table[shift];
\r
1943 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1945 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
1946 FLAG_N = NFLAG_16(res);
\r
1948 FLAG_V = VFLAG_CLEAR;
\r
1952 if(GET_MSB_16(src))
\r
1955 FLAG_C = CFLAG_SET;
\r
1956 FLAG_X = XFLAG_SET;
\r
1957 FLAG_N = NFLAG_SET;
\r
1958 FLAG_Z = ZFLAG_CLEAR;
\r
1959 FLAG_V = VFLAG_CLEAR;
\r
1963 *r_dst &= 0xffff0000;
\r
1964 FLAG_C = CFLAG_CLEAR;
\r
1965 FLAG_X = XFLAG_CLEAR;
\r
1966 FLAG_N = NFLAG_CLEAR;
\r
1967 FLAG_Z = ZFLAG_SET;
\r
1968 FLAG_V = VFLAG_CLEAR;
\r
1972 FLAG_C = CFLAG_CLEAR;
\r
1973 FLAG_N = NFLAG_16(src);
\r
1975 FLAG_V = VFLAG_CLEAR;
\r
1979 M68KMAKE_OP(asr, 32, r, .)
\r
1981 uint* r_dst = &DY;
\r
1982 uint shift = DX & 0x3f;
\r
1983 uint src = *r_dst;
\r
1984 uint res = src >> shift;
\r
1988 USE_CYCLES(shift<<CYC_SHIFT);
\r
1992 if(GET_MSB_32(src))
\r
1993 res |= m68ki_shift_32_table[shift];
\r
1997 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
1998 FLAG_N = NFLAG_32(res);
\r
2000 FLAG_V = VFLAG_CLEAR;
\r
2004 if(GET_MSB_32(src))
\r
2006 *r_dst = 0xffffffff;
\r
2007 FLAG_C = CFLAG_SET;
\r
2008 FLAG_X = XFLAG_SET;
\r
2009 FLAG_N = NFLAG_SET;
\r
2010 FLAG_Z = ZFLAG_CLEAR;
\r
2011 FLAG_V = VFLAG_CLEAR;
\r
2016 FLAG_C = CFLAG_CLEAR;
\r
2017 FLAG_X = XFLAG_CLEAR;
\r
2018 FLAG_N = NFLAG_CLEAR;
\r
2019 FLAG_Z = ZFLAG_SET;
\r
2020 FLAG_V = VFLAG_CLEAR;
\r
2024 FLAG_C = CFLAG_CLEAR;
\r
2025 FLAG_N = NFLAG_32(src);
\r
2027 FLAG_V = VFLAG_CLEAR;
\r
2031 M68KMAKE_OP(asr, 16, ., .)
\r
2033 uint ea = M68KMAKE_GET_EA_AY_16;
\r
2034 uint src = m68ki_read_16(ea);
\r
2035 uint res = src >> 1;
\r
2037 if(GET_MSB_16(src))
\r
2040 m68ki_write_16(ea, res);
\r
2042 FLAG_N = NFLAG_16(res);
\r
2044 FLAG_V = VFLAG_CLEAR;
\r
2045 FLAG_C = FLAG_X = src << 8;
\r
2049 M68KMAKE_OP(asl, 8, s, .)
\r
2051 uint* r_dst = &DY;
\r
2052 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2053 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
2054 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
2057 USE_CYCLES(shift<<CYC_SHIFT);
\r
2059 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
2061 FLAG_X = FLAG_C = src << shift;
\r
2062 FLAG_N = NFLAG_8(res);
\r
2064 src &= m68ki_shift_8_table[shift + 1];
\r
2065 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
\r
2069 M68KMAKE_OP(asl, 16, s, .)
\r
2071 uint* r_dst = &DY;
\r
2072 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2073 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
2074 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
2077 USE_CYCLES(shift<<CYC_SHIFT);
\r
2079 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
2081 FLAG_N = NFLAG_16(res);
\r
2083 FLAG_X = FLAG_C = src >> (8-shift);
\r
2084 src &= m68ki_shift_16_table[shift + 1];
\r
2085 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
\r
2089 M68KMAKE_OP(asl, 32, s, .)
\r
2091 uint* r_dst = &DY;
\r
2092 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2093 uint src = *r_dst;
\r
2094 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
2097 USE_CYCLES(shift<<CYC_SHIFT);
\r
2101 FLAG_N = NFLAG_32(res);
\r
2103 FLAG_X = FLAG_C = src >> (24-shift);
\r
2104 src &= m68ki_shift_32_table[shift + 1];
\r
2105 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
\r
2109 M68KMAKE_OP(asl, 8, r, .)
\r
2111 uint* r_dst = &DY;
\r
2112 uint shift = DX & 0x3f;
\r
2113 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
2114 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
2118 USE_CYCLES(shift<<CYC_SHIFT);
\r
2122 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
2123 FLAG_X = FLAG_C = src << shift;
\r
2124 FLAG_N = NFLAG_8(res);
\r
2126 src &= m68ki_shift_8_table[shift + 1];
\r
2127 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
\r
2131 *r_dst &= 0xffffff00;
\r
2132 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
\r
2133 FLAG_N = NFLAG_CLEAR;
\r
2134 FLAG_Z = ZFLAG_SET;
\r
2135 FLAG_V = (!(src == 0))<<7;
\r
2139 FLAG_C = CFLAG_CLEAR;
\r
2140 FLAG_N = NFLAG_8(src);
\r
2142 FLAG_V = VFLAG_CLEAR;
\r
2146 M68KMAKE_OP(asl, 16, r, .)
\r
2148 uint* r_dst = &DY;
\r
2149 uint shift = DX & 0x3f;
\r
2150 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
2151 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
2155 USE_CYCLES(shift<<CYC_SHIFT);
\r
2159 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
2160 FLAG_X = FLAG_C = (src << shift) >> 8;
\r
2161 FLAG_N = NFLAG_16(res);
\r
2163 src &= m68ki_shift_16_table[shift + 1];
\r
2164 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
\r
2168 *r_dst &= 0xffff0000;
\r
2169 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
\r
2170 FLAG_N = NFLAG_CLEAR;
\r
2171 FLAG_Z = ZFLAG_SET;
\r
2172 FLAG_V = (!(src == 0))<<7;
\r
2176 FLAG_C = CFLAG_CLEAR;
\r
2177 FLAG_N = NFLAG_16(src);
\r
2179 FLAG_V = VFLAG_CLEAR;
\r
2183 M68KMAKE_OP(asl, 32, r, .)
\r
2185 uint* r_dst = &DY;
\r
2186 uint shift = DX & 0x3f;
\r
2187 uint src = *r_dst;
\r
2188 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
2192 USE_CYCLES(shift<<CYC_SHIFT);
\r
2197 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
\r
2198 FLAG_N = NFLAG_32(res);
\r
2200 src &= m68ki_shift_32_table[shift + 1];
\r
2201 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
\r
2206 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
\r
2207 FLAG_N = NFLAG_CLEAR;
\r
2208 FLAG_Z = ZFLAG_SET;
\r
2209 FLAG_V = (!(src == 0))<<7;
\r
2213 FLAG_C = CFLAG_CLEAR;
\r
2214 FLAG_N = NFLAG_32(src);
\r
2216 FLAG_V = VFLAG_CLEAR;
\r
2220 M68KMAKE_OP(asl, 16, ., .)
\r
2222 uint ea = M68KMAKE_GET_EA_AY_16;
\r
2223 uint src = m68ki_read_16(ea);
\r
2224 uint res = MASK_OUT_ABOVE_16(src << 1);
\r
2226 m68ki_write_16(ea, res);
\r
2228 FLAG_N = NFLAG_16(res);
\r
2230 FLAG_X = FLAG_C = src >> 7;
\r
2232 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
\r
2236 M68KMAKE_OP(bcc, 8, ., .)
\r
2240 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2241 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
2244 USE_CYCLES(CYC_BCC_NOTAKE_B);
\r
2248 M68KMAKE_OP(bcc, 16, ., .)
\r
2252 uint offset = OPER_I_16();
\r
2254 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2255 m68ki_branch_16(offset);
\r
2259 USE_CYCLES(CYC_BCC_NOTAKE_W);
\r
2263 M68KMAKE_OP(bcc, 32, ., .)
\r
2265 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2269 uint offset = OPER_I_32();
\r
2271 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2272 m68ki_branch_32(offset);
\r
2282 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2283 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
2286 USE_CYCLES(CYC_BCC_NOTAKE_B);
\r
2291 M68KMAKE_OP(bchg, 32, r, d)
\r
2293 uint* r_dst = &DY;
\r
2294 uint mask = 1 << (DX & 0x1f);
\r
2296 FLAG_Z = *r_dst & mask;
\r
2301 M68KMAKE_OP(bchg, 8, r, .)
\r
2303 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2304 uint src = m68ki_read_8(ea);
\r
2305 uint mask = 1 << (DX & 7);
\r
2307 FLAG_Z = src & mask;
\r
2308 m68ki_write_8(ea, src ^ mask);
\r
2312 M68KMAKE_OP(bchg, 32, s, d)
\r
2314 uint* r_dst = &DY;
\r
2315 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
2317 FLAG_Z = *r_dst & mask;
\r
2322 M68KMAKE_OP(bchg, 8, s, .)
\r
2324 uint mask = 1 << (OPER_I_8() & 7);
\r
2325 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2326 uint src = m68ki_read_8(ea);
\r
2328 FLAG_Z = src & mask;
\r
2329 m68ki_write_8(ea, src ^ mask);
\r
2333 M68KMAKE_OP(bclr, 32, r, d)
\r
2335 uint* r_dst = &DY;
\r
2336 uint mask = 1 << (DX & 0x1f);
\r
2338 FLAG_Z = *r_dst & mask;
\r
2343 M68KMAKE_OP(bclr, 8, r, .)
\r
2345 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2346 uint src = m68ki_read_8(ea);
\r
2347 uint mask = 1 << (DX & 7);
\r
2349 FLAG_Z = src & mask;
\r
2350 m68ki_write_8(ea, src & ~mask);
\r
2354 M68KMAKE_OP(bclr, 32, s, d)
\r
2356 uint* r_dst = &DY;
\r
2357 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
2359 FLAG_Z = *r_dst & mask;
\r
2364 M68KMAKE_OP(bclr, 8, s, .)
\r
2366 uint mask = 1 << (OPER_I_8() & 7);
\r
2367 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2368 uint src = m68ki_read_8(ea);
\r
2370 FLAG_Z = src & mask;
\r
2371 m68ki_write_8(ea, src & ~mask);
\r
2375 M68KMAKE_OP(bfchg, 32, ., d)
\r
2377 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2379 uint word2 = OPER_I_16();
\r
2380 uint offset = (word2>>6)&31;
\r
2381 uint width = word2;
\r
2387 offset = REG_D[offset&7];
\r
2389 width = REG_D[width&7];
\r
2392 width = ((width-1) & 31) + 1;
\r
2394 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2395 mask = ROR_32(mask, offset);
\r
2397 FLAG_N = NFLAG_32(*data<<offset);
\r
2398 FLAG_Z = *data & mask;
\r
2399 FLAG_V = VFLAG_CLEAR;
\r
2400 FLAG_C = CFLAG_CLEAR;
\r
2406 m68ki_exception_illegal();
\r
2410 M68KMAKE_OP(bfchg, 32, ., .)
\r
2412 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2414 uint word2 = OPER_I_16();
\r
2415 sint offset = (word2>>6)&31;
\r
2416 uint width = word2;
\r
2420 uint data_byte = 0;
\r
2421 uint mask_byte = 0;
\r
2422 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2426 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2428 width = REG_D[width&7];
\r
2430 /* Offset is signed so we have to use ugly math =( */
\r
2438 width = ((width-1) & 31) + 1;
\r
2440 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2441 mask_long = mask_base >> offset;
\r
2443 data_long = m68ki_read_32(ea);
\r
2444 FLAG_N = NFLAG_32(data_long << offset);
\r
2445 FLAG_Z = data_long & mask_long;
\r
2446 FLAG_V = VFLAG_CLEAR;
\r
2447 FLAG_C = CFLAG_CLEAR;
\r
2449 m68ki_write_32(ea, data_long ^ mask_long);
\r
2451 if((width + offset) > 32)
\r
2453 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2454 data_byte = m68ki_read_8(ea+4);
\r
2455 FLAG_Z |= (data_byte & mask_byte);
\r
2456 m68ki_write_8(ea+4, data_byte ^ mask_byte);
\r
2460 m68ki_exception_illegal();
\r
2464 M68KMAKE_OP(bfclr, 32, ., d)
\r
2466 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2468 uint word2 = OPER_I_16();
\r
2469 uint offset = (word2>>6)&31;
\r
2470 uint width = word2;
\r
2476 offset = REG_D[offset&7];
\r
2478 width = REG_D[width&7];
\r
2482 width = ((width-1) & 31) + 1;
\r
2485 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2486 mask = ROR_32(mask, offset);
\r
2488 FLAG_N = NFLAG_32(*data<<offset);
\r
2489 FLAG_Z = *data & mask;
\r
2490 FLAG_V = VFLAG_CLEAR;
\r
2491 FLAG_C = CFLAG_CLEAR;
\r
2497 m68ki_exception_illegal();
\r
2501 M68KMAKE_OP(bfclr, 32, ., .)
\r
2503 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2505 uint word2 = OPER_I_16();
\r
2506 sint offset = (word2>>6)&31;
\r
2507 uint width = word2;
\r
2511 uint data_byte = 0;
\r
2512 uint mask_byte = 0;
\r
2513 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2517 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2519 width = REG_D[width&7];
\r
2521 /* Offset is signed so we have to use ugly math =( */
\r
2529 width = ((width-1) & 31) + 1;
\r
2531 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2532 mask_long = mask_base >> offset;
\r
2534 data_long = m68ki_read_32(ea);
\r
2535 FLAG_N = NFLAG_32(data_long << offset);
\r
2536 FLAG_Z = data_long & mask_long;
\r
2537 FLAG_V = VFLAG_CLEAR;
\r
2538 FLAG_C = CFLAG_CLEAR;
\r
2540 m68ki_write_32(ea, data_long & ~mask_long);
\r
2542 if((width + offset) > 32)
\r
2544 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2545 data_byte = m68ki_read_8(ea+4);
\r
2546 FLAG_Z |= (data_byte & mask_byte);
\r
2547 m68ki_write_8(ea+4, data_byte & ~mask_byte);
\r
2551 m68ki_exception_illegal();
\r
2555 M68KMAKE_OP(bfexts, 32, ., d)
\r
2557 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2559 uint word2 = OPER_I_16();
\r
2560 uint offset = (word2>>6)&31;
\r
2561 uint width = word2;
\r
2566 offset = REG_D[offset&7];
\r
2568 width = REG_D[width&7];
\r
2571 width = ((width-1) & 31) + 1;
\r
2573 data = ROL_32(data, offset);
\r
2574 FLAG_N = NFLAG_32(data);
\r
2575 data = MAKE_INT_32(data) >> (32 - width);
\r
2578 FLAG_V = VFLAG_CLEAR;
\r
2579 FLAG_C = CFLAG_CLEAR;
\r
2581 REG_D[(word2>>12)&7] = data;
\r
2585 m68ki_exception_illegal();
\r
2589 M68KMAKE_OP(bfexts, 32, ., .)
\r
2591 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2593 uint word2 = OPER_I_16();
\r
2594 sint offset = (word2>>6)&31;
\r
2595 uint width = word2;
\r
2597 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2601 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2603 width = REG_D[width&7];
\r
2605 /* Offset is signed so we have to use ugly math =( */
\r
2613 width = ((width-1) & 31) + 1;
\r
2615 data = m68ki_read_32(ea);
\r
2617 data = MASK_OUT_ABOVE_32(data<<offset);
\r
2619 if((offset+width) > 32)
\r
2620 data |= (m68ki_read_8(ea+4) << offset) >> 8;
\r
2622 FLAG_N = NFLAG_32(data);
\r
2623 data = MAKE_INT_32(data) >> (32 - width);
\r
2626 FLAG_V = VFLAG_CLEAR;
\r
2627 FLAG_C = CFLAG_CLEAR;
\r
2629 REG_D[(word2 >> 12) & 7] = data;
\r
2633 m68ki_exception_illegal();
\r
2637 M68KMAKE_OP(bfextu, 32, ., d)
\r
2639 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2641 uint word2 = OPER_I_16();
\r
2642 uint offset = (word2>>6)&31;
\r
2643 uint width = word2;
\r
2648 offset = REG_D[offset&7];
\r
2650 width = REG_D[width&7];
\r
2653 width = ((width-1) & 31) + 1;
\r
2655 data = ROL_32(data, offset);
\r
2656 FLAG_N = NFLAG_32(data);
\r
2657 data >>= 32 - width;
\r
2660 FLAG_V = VFLAG_CLEAR;
\r
2661 FLAG_C = CFLAG_CLEAR;
\r
2663 REG_D[(word2>>12)&7] = data;
\r
2667 m68ki_exception_illegal();
\r
2671 M68KMAKE_OP(bfextu, 32, ., .)
\r
2673 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2675 uint word2 = OPER_I_16();
\r
2676 sint offset = (word2>>6)&31;
\r
2677 uint width = word2;
\r
2679 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2683 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2685 width = REG_D[width&7];
\r
2687 /* Offset is signed so we have to use ugly math =( */
\r
2695 width = ((width-1) & 31) + 1;
\r
2697 data = m68ki_read_32(ea);
\r
2698 data = MASK_OUT_ABOVE_32(data<<offset);
\r
2700 if((offset+width) > 32)
\r
2701 data |= (m68ki_read_8(ea+4) << offset) >> 8;
\r
2703 FLAG_N = NFLAG_32(data);
\r
2704 data >>= (32 - width);
\r
2707 FLAG_V = VFLAG_CLEAR;
\r
2708 FLAG_C = CFLAG_CLEAR;
\r
2710 REG_D[(word2 >> 12) & 7] = data;
\r
2714 m68ki_exception_illegal();
\r
2718 M68KMAKE_OP(bfffo, 32, ., d)
\r
2720 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2722 uint word2 = OPER_I_16();
\r
2723 uint offset = (word2>>6)&31;
\r
2724 uint width = word2;
\r
2730 offset = REG_D[offset&7];
\r
2732 width = REG_D[width&7];
\r
2735 width = ((width-1) & 31) + 1;
\r
2737 data = ROL_32(data, offset);
\r
2738 FLAG_N = NFLAG_32(data);
\r
2739 data >>= 32 - width;
\r
2742 FLAG_V = VFLAG_CLEAR;
\r
2743 FLAG_C = CFLAG_CLEAR;
\r
2745 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
\r
2748 REG_D[(word2>>12)&7] = offset;
\r
2752 m68ki_exception_illegal();
\r
2756 M68KMAKE_OP(bfffo, 32, ., .)
\r
2758 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2760 uint word2 = OPER_I_16();
\r
2761 sint offset = (word2>>6)&31;
\r
2762 sint local_offset;
\r
2763 uint width = word2;
\r
2766 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2770 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2772 width = REG_D[width&7];
\r
2774 /* Offset is signed so we have to use ugly math =( */
\r
2776 local_offset = offset % 8;
\r
2777 if(local_offset < 0)
\r
2779 local_offset += 8;
\r
2782 width = ((width-1) & 31) + 1;
\r
2784 data = m68ki_read_32(ea);
\r
2785 data = MASK_OUT_ABOVE_32(data<<local_offset);
\r
2787 if((local_offset+width) > 32)
\r
2788 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
\r
2790 FLAG_N = NFLAG_32(data);
\r
2791 data >>= (32 - width);
\r
2794 FLAG_V = VFLAG_CLEAR;
\r
2795 FLAG_C = CFLAG_CLEAR;
\r
2797 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
\r
2800 REG_D[(word2>>12)&7] = offset;
\r
2804 m68ki_exception_illegal();
\r
2808 M68KMAKE_OP(bfins, 32, ., d)
\r
2810 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2812 uint word2 = OPER_I_16();
\r
2813 uint offset = (word2>>6)&31;
\r
2814 uint width = word2;
\r
2817 uint64 insert = REG_D[(word2>>12)&7];
\r
2821 offset = REG_D[offset&7];
\r
2823 width = REG_D[width&7];
\r
2827 width = ((width-1) & 31) + 1;
\r
2830 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2831 mask = ROR_32(mask, offset);
\r
2833 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
\r
2834 FLAG_N = NFLAG_32(insert);
\r
2836 insert = ROR_32(insert, offset);
\r
2838 FLAG_V = VFLAG_CLEAR;
\r
2839 FLAG_C = CFLAG_CLEAR;
\r
2846 m68ki_exception_illegal();
\r
2850 M68KMAKE_OP(bfins, 32, ., .)
\r
2852 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2854 uint word2 = OPER_I_16();
\r
2855 sint offset = (word2>>6)&31;
\r
2856 uint width = word2;
\r
2857 uint insert_base = REG_D[(word2>>12)&7];
\r
2863 uint data_byte = 0;
\r
2864 uint mask_byte = 0;
\r
2865 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2869 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2871 width = REG_D[width&7];
\r
2873 /* Offset is signed so we have to use ugly math =( */
\r
2881 width = ((width-1) & 31) + 1;
\r
2883 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2884 mask_long = mask_base >> offset;
\r
2886 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
\r
2887 FLAG_N = NFLAG_32(insert_base);
\r
2888 FLAG_Z = insert_base;
\r
2889 insert_long = insert_base >> offset;
\r
2891 data_long = m68ki_read_32(ea);
\r
2892 FLAG_V = VFLAG_CLEAR;
\r
2893 FLAG_C = CFLAG_CLEAR;
\r
2895 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
\r
2897 if((width + offset) > 32)
\r
2899 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2900 insert_byte = MASK_OUT_ABOVE_8(insert_base);
\r
2901 data_byte = m68ki_read_8(ea+4);
\r
2902 FLAG_Z |= (data_byte & mask_byte);
\r
2903 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
\r
2907 m68ki_exception_illegal();
\r
2911 M68KMAKE_OP(bfset, 32, ., d)
\r
2913 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2915 uint word2 = OPER_I_16();
\r
2916 uint offset = (word2>>6)&31;
\r
2917 uint width = word2;
\r
2923 offset = REG_D[offset&7];
\r
2925 width = REG_D[width&7];
\r
2929 width = ((width-1) & 31) + 1;
\r
2932 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2933 mask = ROR_32(mask, offset);
\r
2935 FLAG_N = NFLAG_32(*data<<offset);
\r
2936 FLAG_Z = *data & mask;
\r
2937 FLAG_V = VFLAG_CLEAR;
\r
2938 FLAG_C = CFLAG_CLEAR;
\r
2944 m68ki_exception_illegal();
\r
2948 M68KMAKE_OP(bfset, 32, ., .)
\r
2950 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2952 uint word2 = OPER_I_16();
\r
2953 sint offset = (word2>>6)&31;
\r
2954 uint width = word2;
\r
2958 uint data_byte = 0;
\r
2959 uint mask_byte = 0;
\r
2960 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2964 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2966 width = REG_D[width&7];
\r
2968 /* Offset is signed so we have to use ugly math =( */
\r
2976 width = ((width-1) & 31) + 1;
\r
2979 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2980 mask_long = mask_base >> offset;
\r
2982 data_long = m68ki_read_32(ea);
\r
2983 FLAG_N = NFLAG_32(data_long << offset);
\r
2984 FLAG_Z = data_long & mask_long;
\r
2985 FLAG_V = VFLAG_CLEAR;
\r
2986 FLAG_C = CFLAG_CLEAR;
\r
2988 m68ki_write_32(ea, data_long | mask_long);
\r
2990 if((width + offset) > 32)
\r
2992 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2993 data_byte = m68ki_read_8(ea+4);
\r
2994 FLAG_Z |= (data_byte & mask_byte);
\r
2995 m68ki_write_8(ea+4, data_byte | mask_byte);
\r
2999 m68ki_exception_illegal();
\r
3003 M68KMAKE_OP(bftst, 32, ., d)
\r
3005 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3007 uint word2 = OPER_I_16();
\r
3008 uint offset = (word2>>6)&31;
\r
3009 uint width = word2;
\r
3015 offset = REG_D[offset&7];
\r
3017 width = REG_D[width&7];
\r
3021 width = ((width-1) & 31) + 1;
\r
3024 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3025 mask = ROR_32(mask, offset);
\r
3027 FLAG_N = NFLAG_32(*data<<offset);
\r
3028 FLAG_Z = *data & mask;
\r
3029 FLAG_V = VFLAG_CLEAR;
\r
3030 FLAG_C = CFLAG_CLEAR;
\r
3034 m68ki_exception_illegal();
\r
3038 M68KMAKE_OP(bftst, 32, ., .)
\r
3040 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3042 uint word2 = OPER_I_16();
\r
3043 sint offset = (word2>>6)&31;
\r
3044 uint width = word2;
\r
3048 uint data_byte = 0;
\r
3049 uint mask_byte = 0;
\r
3050 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3053 offset = MAKE_INT_32(REG_D[offset&7]);
\r
3055 width = REG_D[width&7];
\r
3057 /* Offset is signed so we have to use ugly math =( */
\r
3065 width = ((width-1) & 31) + 1;
\r
3068 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3069 mask_long = mask_base >> offset;
\r
3071 data_long = m68ki_read_32(ea);
\r
3072 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
\r
3073 FLAG_Z = data_long & mask_long;
\r
3074 FLAG_V = VFLAG_CLEAR;
\r
3075 FLAG_C = CFLAG_CLEAR;
\r
3077 if((width + offset) > 32)
\r
3079 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
3080 data_byte = m68ki_read_8(ea+4);
\r
3081 FLAG_Z |= (data_byte & mask_byte);
\r
3085 m68ki_exception_illegal();
\r
3089 M68KMAKE_OP(bkpt, 0, ., .)
\r
3091 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
3093 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
\r
3095 m68ki_exception_illegal();
\r
3099 M68KMAKE_OP(bra, 8, ., .)
\r
3101 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3102 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3103 // if(REG_PC == REG_PPC)
\r
3104 // USE_ALL_CYCLES();
\r
3108 M68KMAKE_OP(bra, 16, ., .)
\r
3110 uint offset = OPER_I_16();
\r
3112 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3113 m68ki_branch_16(offset);
\r
3114 // if(REG_PC == REG_PPC)
\r
3115 // USE_ALL_CYCLES();
\r
3119 M68KMAKE_OP(bra, 32, ., .)
\r
3121 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3123 uint offset = OPER_I_32();
\r
3125 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3126 m68ki_branch_32(offset);
\r
3127 if(REG_PC == REG_PPC)
\r
3133 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3134 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3135 // if(REG_PC == REG_PPC)
\r
3136 // USE_ALL_CYCLES();
\r
3141 M68KMAKE_OP(bset, 32, r, d)
\r
3143 uint* r_dst = &DY;
\r
3144 uint mask = 1 << (DX & 0x1f);
\r
3146 FLAG_Z = *r_dst & mask;
\r
3151 M68KMAKE_OP(bset, 8, r, .)
\r
3153 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3154 uint src = m68ki_read_8(ea);
\r
3155 uint mask = 1 << (DX & 7);
\r
3157 FLAG_Z = src & mask;
\r
3158 m68ki_write_8(ea, src | mask);
\r
3162 M68KMAKE_OP(bset, 32, s, d)
\r
3164 uint* r_dst = &DY;
\r
3165 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
3167 FLAG_Z = *r_dst & mask;
\r
3172 M68KMAKE_OP(bset, 8, s, .)
\r
3174 uint mask = 1 << (OPER_I_8() & 7);
\r
3175 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3176 uint src = m68ki_read_8(ea);
\r
3178 FLAG_Z = src & mask;
\r
3179 m68ki_write_8(ea, src | mask);
\r
3183 M68KMAKE_OP(bsr, 8, ., .)
\r
3185 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3186 m68ki_push_32(REG_PC);
\r
3187 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3191 M68KMAKE_OP(bsr, 16, ., .)
\r
3193 uint offset = OPER_I_16();
\r
3194 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3195 m68ki_push_32(REG_PC);
\r
3197 m68ki_branch_16(offset);
\r
3201 M68KMAKE_OP(bsr, 32, ., .)
\r
3203 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3205 uint offset = OPER_I_32();
\r
3206 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3207 m68ki_push_32(REG_PC);
\r
3209 m68ki_branch_32(offset);
\r
3214 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3215 m68ki_push_32(REG_PC);
\r
3216 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3221 M68KMAKE_OP(btst, 32, r, d)
\r
3223 FLAG_Z = DY & (1 << (DX & 0x1f));
\r
3227 M68KMAKE_OP(btst, 8, r, .)
\r
3229 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
\r
3233 M68KMAKE_OP(btst, 32, s, d)
\r
3235 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
\r
3239 M68KMAKE_OP(btst, 8, s, .)
\r
3241 uint bit = OPER_I_8() & 7;
\r
3243 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
\r
3247 M68KMAKE_OP(callm, 32, ., .)
\r
3249 /* note: watch out for pcrelative modes */
\r
3250 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
3252 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3254 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3256 (void)ea; /* just to avoid an 'unused variable' warning */
\r
3257 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
3258 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
3259 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
3262 m68ki_exception_illegal();
\r
3266 M68KMAKE_OP(cas, 8, ., .)
\r
3268 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3270 uint word2 = OPER_I_16();
\r
3271 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3272 uint dest = m68ki_read_8(ea);
\r
3273 uint* compare = ®_D[word2 & 7];
\r
3274 uint res = dest - MASK_OUT_ABOVE_8(*compare);
\r
3276 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3277 FLAG_N = NFLAG_8(res);
\r
3278 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3279 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
\r
3280 FLAG_C = CFLAG_8(res);
\r
3283 *compare = MASK_OUT_BELOW_8(*compare) | dest;
\r
3287 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
\r
3291 m68ki_exception_illegal();
\r
3295 M68KMAKE_OP(cas, 16, ., .)
\r
3297 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3299 uint word2 = OPER_I_16();
\r
3300 uint ea = M68KMAKE_GET_EA_AY_16;
\r
3301 uint dest = m68ki_read_16(ea);
\r
3302 uint* compare = ®_D[word2 & 7];
\r
3303 uint res = dest - MASK_OUT_ABOVE_16(*compare);
\r
3305 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3306 FLAG_N = NFLAG_16(res);
\r
3307 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3308 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
\r
3309 FLAG_C = CFLAG_16(res);
\r
3312 *compare = MASK_OUT_BELOW_16(*compare) | dest;
\r
3316 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
\r
3320 m68ki_exception_illegal();
\r
3324 M68KMAKE_OP(cas, 32, ., .)
\r
3326 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3328 uint word2 = OPER_I_16();
\r
3329 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3330 uint dest = m68ki_read_32(ea);
\r
3331 uint* compare = ®_D[word2 & 7];
\r
3332 uint res = dest - *compare;
\r
3334 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3335 FLAG_N = NFLAG_32(res);
\r
3336 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3337 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
\r
3338 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
\r
3345 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
\r
3349 m68ki_exception_illegal();
\r
3353 M68KMAKE_OP(cas2, 16, ., .)
\r
3355 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3357 uint word2 = OPER_I_32();
\r
3358 uint* compare1 = ®_D[(word2 >> 16) & 7];
\r
3359 uint ea1 = REG_DA[(word2 >> 28) & 15];
\r
3360 uint dest1 = m68ki_read_16(ea1);
\r
3361 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
\r
3362 uint* compare2 = ®_D[word2 & 7];
\r
3363 uint ea2 = REG_DA[(word2 >> 12) & 15];
\r
3364 uint dest2 = m68ki_read_16(ea2);
\r
3367 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3368 FLAG_N = NFLAG_16(res1);
\r
3369 FLAG_Z = MASK_OUT_ABOVE_16(res1);
\r
3370 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
\r
3371 FLAG_C = CFLAG_16(res1);
\r
3375 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
\r
3377 FLAG_N = NFLAG_16(res2);
\r
3378 FLAG_Z = MASK_OUT_ABOVE_16(res2);
\r
3379 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
\r
3380 FLAG_C = CFLAG_16(res2);
\r
3385 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
\r
3386 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
\r
3390 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
\r
3391 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
\r
3394 m68ki_exception_illegal();
\r
3398 M68KMAKE_OP(cas2, 32, ., .)
\r
3400 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3402 uint word2 = OPER_I_32();
\r
3403 uint* compare1 = ®_D[(word2 >> 16) & 7];
\r
3404 uint ea1 = REG_DA[(word2 >> 28) & 15];
\r
3405 uint dest1 = m68ki_read_32(ea1);
\r
3406 uint res1 = dest1 - *compare1;
\r
3407 uint* compare2 = ®_D[word2 & 7];
\r
3408 uint ea2 = REG_DA[(word2 >> 12) & 15];
\r
3409 uint dest2 = m68ki_read_32(ea2);
\r
3412 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3413 FLAG_N = NFLAG_32(res1);
\r
3414 FLAG_Z = MASK_OUT_ABOVE_32(res1);
\r
3415 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
\r
3416 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
\r
3420 res2 = dest2 - *compare2;
\r
3422 FLAG_N = NFLAG_32(res2);
\r
3423 FLAG_Z = MASK_OUT_ABOVE_32(res2);
\r
3424 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
\r
3425 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
\r
3430 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
\r
3431 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
\r
3435 *compare1 = dest1;
\r
3436 *compare2 = dest2;
\r
3439 m68ki_exception_illegal();
\r
3443 M68KMAKE_OP(chk, 16, ., d)
\r
3445 sint src = MAKE_INT_16(DX);
\r
3446 sint bound = MAKE_INT_16(DY);
\r
3448 FLAG_Z = ZFLAG_16(src); /* Undocumented */
\r
3449 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3450 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3452 if(src >= 0 && src <= bound)
\r
3456 FLAG_N = (src < 0)<<7;
\r
3457 m68ki_exception_trap(EXCEPTION_CHK);
\r
3461 M68KMAKE_OP(chk, 16, ., .)
\r
3463 sint src = MAKE_INT_16(DX);
\r
3464 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
3466 FLAG_Z = ZFLAG_16(src); /* Undocumented */
\r
3467 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3468 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3470 if(src >= 0 && src <= bound)
\r
3474 FLAG_N = (src < 0)<<7;
\r
3475 m68ki_exception_trap(EXCEPTION_CHK);
\r
3479 M68KMAKE_OP(chk, 32, ., d)
\r
3481 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3483 sint src = MAKE_INT_32(DX);
\r
3484 sint bound = MAKE_INT_32(DY);
\r
3486 FLAG_Z = ZFLAG_32(src); /* Undocumented */
\r
3487 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3488 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3490 if(src >= 0 && src <= bound)
\r
3494 FLAG_N = (src < 0)<<7;
\r
3495 m68ki_exception_trap(EXCEPTION_CHK);
\r
3498 m68ki_exception_illegal();
\r
3502 M68KMAKE_OP(chk, 32, ., .)
\r
3504 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3506 sint src = MAKE_INT_32(DX);
\r
3507 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
\r
3509 FLAG_Z = ZFLAG_32(src); /* Undocumented */
\r
3510 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3511 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3513 if(src >= 0 && src <= bound)
\r
3517 FLAG_N = (src < 0)<<7;
\r
3518 m68ki_exception_trap(EXCEPTION_CHK);
\r
3521 m68ki_exception_illegal();
\r
3525 M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
\r
3527 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3529 uint word2 = OPER_I_16();
\r
3530 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3531 uint ea = EA_PCDI_8();
\r
3532 uint lower_bound = m68ki_read_pcrel_8(ea);
\r
3533 uint upper_bound = m68ki_read_pcrel_8(ea + 1);
\r
3536 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3538 FLAG_C = compare - lower_bound;
\r
3539 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3543 m68ki_exception_trap(EXCEPTION_CHK);
\r
3547 FLAG_C = upper_bound - compare;
\r
3548 if(COND_CS() && BIT_B(word2))
\r
3549 m68ki_exception_trap(EXCEPTION_CHK);
\r
3552 m68ki_exception_illegal();
\r
3556 M68KMAKE_OP(chk2cmp2, 8, ., pcix)
\r
3558 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3560 uint word2 = OPER_I_16();
\r
3561 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3562 uint ea = EA_PCIX_8();
\r
3563 uint lower_bound = m68ki_read_pcrel_8(ea);
\r
3564 uint upper_bound = m68ki_read_pcrel_8(ea + 1);
\r
3567 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3569 FLAG_C = compare - lower_bound;
\r
3570 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3574 m68ki_exception_trap(EXCEPTION_CHK);
\r
3578 FLAG_C = upper_bound - compare;
\r
3579 if(COND_CS() && BIT_B(word2))
\r
3580 m68ki_exception_trap(EXCEPTION_CHK);
\r
3583 m68ki_exception_illegal();
\r
3587 M68KMAKE_OP(chk2cmp2, 8, ., .)
\r
3589 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3591 uint word2 = OPER_I_16();
\r
3592 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3593 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3594 uint lower_bound = m68ki_read_8(ea);
\r
3595 uint upper_bound = m68ki_read_8(ea + 1);
\r
3598 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3600 FLAG_C = compare - lower_bound;
\r
3601 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3605 m68ki_exception_trap(EXCEPTION_CHK);
\r
3609 FLAG_C = upper_bound - compare;
\r
3610 if(COND_CS() && BIT_B(word2))
\r
3611 m68ki_exception_trap(EXCEPTION_CHK);
\r
3614 m68ki_exception_illegal();
\r
3618 M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
\r
3620 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3622 uint word2 = OPER_I_16();
\r
3623 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3624 uint ea = EA_PCDI_16();
\r
3625 uint lower_bound = m68ki_read_pcrel_16(ea);
\r
3626 uint upper_bound = m68ki_read_pcrel_16(ea + 2);
\r
3629 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3631 FLAG_C = compare - lower_bound;
\r
3632 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3633 FLAG_C = CFLAG_16(FLAG_C);
\r
3637 m68ki_exception_trap(EXCEPTION_CHK);
\r
3642 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3644 FLAG_C = upper_bound - compare;
\r
3645 FLAG_C = CFLAG_16(FLAG_C);
\r
3646 if(COND_CS() && BIT_B(word2))
\r
3647 m68ki_exception_trap(EXCEPTION_CHK);
\r
3650 m68ki_exception_illegal();
\r
3654 M68KMAKE_OP(chk2cmp2, 16, ., pcix)
\r
3656 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3658 uint word2 = OPER_I_16();
\r
3659 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3660 uint ea = EA_PCIX_16();
\r
3661 uint lower_bound = m68ki_read_pcrel_16(ea);
\r
3662 uint upper_bound = m68ki_read_pcrel_16(ea + 2);
\r
3665 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3667 FLAG_C = compare - lower_bound;
\r
3668 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3669 FLAG_C = CFLAG_16(FLAG_C);
\r
3673 m68ki_exception_trap(EXCEPTION_CHK);
\r
3678 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3680 FLAG_C = upper_bound - compare;
\r
3681 FLAG_C = CFLAG_16(FLAG_C);
\r
3682 if(COND_CS() && BIT_B(word2))
\r
3683 m68ki_exception_trap(EXCEPTION_CHK);
\r
3686 m68ki_exception_illegal();
\r
3690 M68KMAKE_OP(chk2cmp2, 16, ., .)
\r
3692 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3694 uint word2 = OPER_I_16();
\r
3695 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3696 uint ea = M68KMAKE_GET_EA_AY_16;
\r
3697 uint lower_bound = m68ki_read_16(ea);
\r
3698 uint upper_bound = m68ki_read_16(ea + 2);
\r
3701 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3703 FLAG_C = compare - lower_bound;
\r
3705 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3706 FLAG_C = CFLAG_16(FLAG_C);
\r
3710 m68ki_exception_trap(EXCEPTION_CHK);
\r
3714 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3716 FLAG_C = upper_bound - compare;
\r
3718 FLAG_C = CFLAG_16(FLAG_C);
\r
3719 if(COND_CS() && BIT_B(word2))
\r
3720 m68ki_exception_trap(EXCEPTION_CHK);
\r
3723 m68ki_exception_illegal();
\r
3727 M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
\r
3729 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3731 uint word2 = OPER_I_16();
\r
3732 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3733 uint ea = EA_PCDI_32();
\r
3734 uint lower_bound = m68ki_read_pcrel_32(ea);
\r
3735 uint upper_bound = m68ki_read_pcrel_32(ea + 4);
\r
3737 FLAG_C = compare - lower_bound;
\r
3738 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3739 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3743 m68ki_exception_trap(EXCEPTION_CHK);
\r
3747 FLAG_C = upper_bound - compare;
\r
3748 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3749 if(COND_CS() && BIT_B(word2))
\r
3750 m68ki_exception_trap(EXCEPTION_CHK);
\r
3753 m68ki_exception_illegal();
\r
3757 M68KMAKE_OP(chk2cmp2, 32, ., pcix)
\r
3759 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3761 uint word2 = OPER_I_16();
\r
3762 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3763 uint ea = EA_PCIX_32();
\r
3764 uint lower_bound = m68ki_read_pcrel_32(ea);
\r
3765 uint upper_bound = m68ki_read_pcrel_32(ea + 4);
\r
3767 FLAG_C = compare - lower_bound;
\r
3768 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3769 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3773 m68ki_exception_trap(EXCEPTION_CHK);
\r
3777 FLAG_C = upper_bound - compare;
\r
3778 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3779 if(COND_CS() && BIT_B(word2))
\r
3780 m68ki_exception_trap(EXCEPTION_CHK);
\r
3783 m68ki_exception_illegal();
\r
3787 M68KMAKE_OP(chk2cmp2, 32, ., .)
\r
3789 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3791 uint word2 = OPER_I_16();
\r
3792 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3793 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3794 uint lower_bound = m68ki_read_32(ea);
\r
3795 uint upper_bound = m68ki_read_32(ea + 4);
\r
3797 FLAG_C = compare - lower_bound;
\r
3798 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3799 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3803 m68ki_exception_trap(EXCEPTION_CHK);
\r
3807 FLAG_C = upper_bound - compare;
\r
3808 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3809 if(COND_CS() && BIT_B(word2))
\r
3810 m68ki_exception_trap(EXCEPTION_CHK);
\r
3813 m68ki_exception_illegal();
\r
3817 M68KMAKE_OP(clr, 8, ., d)
\r
3821 FLAG_N = NFLAG_CLEAR;
\r
3822 FLAG_V = VFLAG_CLEAR;
\r
3823 FLAG_C = CFLAG_CLEAR;
\r
3824 FLAG_Z = ZFLAG_SET;
\r
3828 M68KMAKE_OP(clr, 8, ., .)
\r
3830 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
\r
3832 FLAG_N = NFLAG_CLEAR;
\r
3833 FLAG_V = VFLAG_CLEAR;
\r
3834 FLAG_C = CFLAG_CLEAR;
\r
3835 FLAG_Z = ZFLAG_SET;
\r
3839 M68KMAKE_OP(clr, 16, ., d)
\r
3843 FLAG_N = NFLAG_CLEAR;
\r
3844 FLAG_V = VFLAG_CLEAR;
\r
3845 FLAG_C = CFLAG_CLEAR;
\r
3846 FLAG_Z = ZFLAG_SET;
\r
3850 M68KMAKE_OP(clr, 16, ., .)
\r
3852 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
\r
3854 FLAG_N = NFLAG_CLEAR;
\r
3855 FLAG_V = VFLAG_CLEAR;
\r
3856 FLAG_C = CFLAG_CLEAR;
\r
3857 FLAG_Z = ZFLAG_SET;
\r
3861 M68KMAKE_OP(clr, 32, ., d)
\r
3865 FLAG_N = NFLAG_CLEAR;
\r
3866 FLAG_V = VFLAG_CLEAR;
\r
3867 FLAG_C = CFLAG_CLEAR;
\r
3868 FLAG_Z = ZFLAG_SET;
\r
3872 M68KMAKE_OP(clr, 32, ., .)
\r
3874 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
\r
3876 FLAG_N = NFLAG_CLEAR;
\r
3877 FLAG_V = VFLAG_CLEAR;
\r
3878 FLAG_C = CFLAG_CLEAR;
\r
3879 FLAG_Z = ZFLAG_SET;
\r
3883 M68KMAKE_OP(cmp, 8, ., d)
\r
3885 uint src = MASK_OUT_ABOVE_8(DY);
\r
3886 uint dst = MASK_OUT_ABOVE_8(DX);
\r
3887 uint res = dst - src;
\r
3889 FLAG_N = NFLAG_8(res);
\r
3890 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3891 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3892 FLAG_C = CFLAG_8(res);
\r
3896 M68KMAKE_OP(cmp, 8, ., .)
\r
3898 uint src = M68KMAKE_GET_OPER_AY_8;
\r
3899 uint dst = MASK_OUT_ABOVE_8(DX);
\r
3900 uint res = dst - src;
\r
3902 FLAG_N = NFLAG_8(res);
\r
3903 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3904 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3905 FLAG_C = CFLAG_8(res);
\r
3909 M68KMAKE_OP(cmp, 16, ., d)
\r
3911 uint src = MASK_OUT_ABOVE_16(DY);
\r
3912 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3913 uint res = dst - src;
\r
3915 FLAG_N = NFLAG_16(res);
\r
3916 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3917 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3918 FLAG_C = CFLAG_16(res);
\r
3922 M68KMAKE_OP(cmp, 16, ., a)
\r
3924 uint src = MASK_OUT_ABOVE_16(AY);
\r
3925 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3926 uint res = dst - src;
\r
3928 FLAG_N = NFLAG_16(res);
\r
3929 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3930 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3931 FLAG_C = CFLAG_16(res);
\r
3935 M68KMAKE_OP(cmp, 16, ., .)
\r
3937 uint src = M68KMAKE_GET_OPER_AY_16;
\r
3938 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3939 uint res = dst - src;
\r
3941 FLAG_N = NFLAG_16(res);
\r
3942 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3943 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3944 FLAG_C = CFLAG_16(res);
\r
3948 M68KMAKE_OP(cmp, 32, ., d)
\r
3952 uint res = dst - src;
\r
3954 FLAG_N = NFLAG_32(res);
\r
3955 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3956 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3957 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3961 M68KMAKE_OP(cmp, 32, ., a)
\r
3965 uint res = dst - src;
\r
3967 FLAG_N = NFLAG_32(res);
\r
3968 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3969 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3970 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3974 M68KMAKE_OP(cmp, 32, ., .)
\r
3976 uint src = M68KMAKE_GET_OPER_AY_32;
\r
3978 uint res = dst - src;
\r
3980 FLAG_N = NFLAG_32(res);
\r
3981 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3982 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3983 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3987 M68KMAKE_OP(cmpa, 16, ., d)
\r
3989 uint src = MAKE_INT_16(DY);
\r
3991 uint res = dst - src;
\r
3993 FLAG_N = NFLAG_32(res);
\r
3994 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3995 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3996 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4000 M68KMAKE_OP(cmpa, 16, ., a)
\r
4002 uint src = MAKE_INT_16(AY);
\r
4004 uint res = dst - src;
\r
4006 FLAG_N = NFLAG_32(res);
\r
4007 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4008 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4009 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4013 M68KMAKE_OP(cmpa, 16, ., .)
\r
4015 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
4017 uint res = dst - src;
\r
4019 FLAG_N = NFLAG_32(res);
\r
4020 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4021 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4022 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4026 M68KMAKE_OP(cmpa, 32, ., d)
\r
4030 uint res = dst - src;
\r
4032 FLAG_N = NFLAG_32(res);
\r
4033 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4034 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4035 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4039 M68KMAKE_OP(cmpa, 32, ., a)
\r
4043 uint res = dst - src;
\r
4045 FLAG_N = NFLAG_32(res);
\r
4046 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4047 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4048 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4052 M68KMAKE_OP(cmpa, 32, ., .)
\r
4054 uint src = M68KMAKE_GET_OPER_AY_32;
\r
4056 uint res = dst - src;
\r
4058 FLAG_N = NFLAG_32(res);
\r
4059 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4060 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4061 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4065 M68KMAKE_OP(cmpi, 8, ., d)
\r
4067 uint src = OPER_I_8();
\r
4068 uint dst = MASK_OUT_ABOVE_8(DY);
\r
4069 uint res = dst - src;
\r
4071 FLAG_N = NFLAG_8(res);
\r
4072 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4073 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4074 FLAG_C = CFLAG_8(res);
\r
4078 M68KMAKE_OP(cmpi, 8, ., .)
\r
4080 uint src = OPER_I_8();
\r
4081 uint dst = M68KMAKE_GET_OPER_AY_8;
\r
4082 uint res = dst - src;
\r
4084 FLAG_N = NFLAG_8(res);
\r
4085 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4086 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4087 FLAG_C = CFLAG_8(res);
\r
4091 M68KMAKE_OP(cmpi, 8, ., pcdi)
\r
4093 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4095 uint src = OPER_I_8();
\r
4096 uint dst = OPER_PCDI_8();
\r
4097 uint res = dst - src;
\r
4099 FLAG_N = NFLAG_8(res);
\r
4100 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4101 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4102 FLAG_C = CFLAG_8(res);
\r
4105 m68ki_exception_illegal();
\r
4109 M68KMAKE_OP(cmpi, 8, ., pcix)
\r
4111 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4113 uint src = OPER_I_8();
\r
4114 uint dst = OPER_PCIX_8();
\r
4115 uint res = dst - src;
\r
4117 FLAG_N = NFLAG_8(res);
\r
4118 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4119 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4120 FLAG_C = CFLAG_8(res);
\r
4123 m68ki_exception_illegal();
\r
4127 M68KMAKE_OP(cmpi, 16, ., d)
\r
4129 uint src = OPER_I_16();
\r
4130 uint dst = MASK_OUT_ABOVE_16(DY);
\r
4131 uint res = dst - src;
\r
4133 FLAG_N = NFLAG_16(res);
\r
4134 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4135 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4136 FLAG_C = CFLAG_16(res);
\r
4140 M68KMAKE_OP(cmpi, 16, ., .)
\r
4142 uint src = OPER_I_16();
\r
4143 uint dst = M68KMAKE_GET_OPER_AY_16;
\r
4144 uint res = dst - src;
\r
4146 FLAG_N = NFLAG_16(res);
\r
4147 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4148 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4149 FLAG_C = CFLAG_16(res);
\r
4153 M68KMAKE_OP(cmpi, 16, ., pcdi)
\r
4155 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4157 uint src = OPER_I_16();
\r
4158 uint dst = OPER_PCDI_16();
\r
4159 uint res = dst - src;
\r
4161 FLAG_N = NFLAG_16(res);
\r
4162 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4163 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4164 FLAG_C = CFLAG_16(res);
\r
4167 m68ki_exception_illegal();
\r
4171 M68KMAKE_OP(cmpi, 16, ., pcix)
\r
4173 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4175 uint src = OPER_I_16();
\r
4176 uint dst = OPER_PCIX_16();
\r
4177 uint res = dst - src;
\r
4179 FLAG_N = NFLAG_16(res);
\r
4180 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4181 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4182 FLAG_C = CFLAG_16(res);
\r
4185 m68ki_exception_illegal();
\r
4189 M68KMAKE_OP(cmpi, 32, ., d)
\r
4191 uint src = OPER_I_32();
\r
4193 uint res = dst - src;
\r
4195 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */
\r
4197 FLAG_N = NFLAG_32(res);
\r
4198 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4199 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4200 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4204 M68KMAKE_OP(cmpi, 32, ., .)
\r
4206 uint src = OPER_I_32();
\r
4207 uint dst = M68KMAKE_GET_OPER_AY_32;
\r
4208 uint res = dst - src;
\r
4210 FLAG_N = NFLAG_32(res);
\r
4211 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4212 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4213 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4217 M68KMAKE_OP(cmpi, 32, ., pcdi)
\r
4219 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4221 uint src = OPER_I_32();
\r
4222 uint dst = OPER_PCDI_32();
\r
4223 uint res = dst - src;
\r
4225 FLAG_N = NFLAG_32(res);
\r
4226 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4227 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4228 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4231 m68ki_exception_illegal();
\r
4235 M68KMAKE_OP(cmpi, 32, ., pcix)
\r
4237 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4239 uint src = OPER_I_32();
\r
4240 uint dst = OPER_PCIX_32();
\r
4241 uint res = dst - src;
\r
4243 FLAG_N = NFLAG_32(res);
\r
4244 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4245 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4246 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4249 m68ki_exception_illegal();
\r
4253 M68KMAKE_OP(cmpm, 8, ., ax7)
\r
4255 uint src = OPER_AY_PI_8();
\r
4256 uint dst = OPER_A7_PI_8();
\r
4257 uint res = dst - src;
\r
4259 FLAG_N = NFLAG_8(res);
\r
4260 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4261 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4262 FLAG_C = CFLAG_8(res);
\r
4266 M68KMAKE_OP(cmpm, 8, ., ay7)
\r
4268 uint src = OPER_A7_PI_8();
\r
4269 uint dst = OPER_AX_PI_8();
\r
4270 uint res = dst - src;
\r
4272 FLAG_N = NFLAG_8(res);
\r
4273 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4274 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4275 FLAG_C = CFLAG_8(res);
\r
4279 M68KMAKE_OP(cmpm, 8, ., axy7)
\r
4281 uint src = OPER_A7_PI_8();
\r
4282 uint dst = OPER_A7_PI_8();
\r
4283 uint res = dst - src;
\r
4285 FLAG_N = NFLAG_8(res);
\r
4286 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4287 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4288 FLAG_C = CFLAG_8(res);
\r
4292 M68KMAKE_OP(cmpm, 8, ., .)
\r
4294 uint src = OPER_AY_PI_8();
\r
4295 uint dst = OPER_AX_PI_8();
\r
4296 uint res = dst - src;
\r
4298 FLAG_N = NFLAG_8(res);
\r
4299 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4300 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4301 FLAG_C = CFLAG_8(res);
\r
4305 M68KMAKE_OP(cmpm, 16, ., .)
\r
4307 uint src = OPER_AY_PI_16();
\r
4308 uint dst = OPER_AX_PI_16();
\r
4309 uint res = dst - src;
\r
4311 FLAG_N = NFLAG_16(res);
\r
4312 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4313 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4314 FLAG_C = CFLAG_16(res);
\r
4318 M68KMAKE_OP(cmpm, 32, ., .)
\r
4320 uint src = OPER_AY_PI_32();
\r
4321 uint dst = OPER_AX_PI_32();
\r
4322 uint res = dst - src;
\r
4324 FLAG_N = NFLAG_32(res);
\r
4325 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4326 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4327 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4331 M68KMAKE_OP(cpbcc, 32, ., .)
\r
4333 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4335 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4336 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4337 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4340 m68ki_exception_1111();
\r
4344 M68KMAKE_OP(cpdbcc, 32, ., .)
\r
4346 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4348 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4349 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4350 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4353 m68ki_exception_1111();
\r
4357 M68KMAKE_OP(cpgen, 32, ., .)
\r
4359 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4361 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4362 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4363 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4366 m68ki_exception_1111();
\r
4370 M68KMAKE_OP(cpscc, 32, ., .)
\r
4372 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4374 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4375 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4376 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4379 m68ki_exception_1111();
\r
4383 M68KMAKE_OP(cptrapcc, 32, ., .)
\r
4385 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4387 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4388 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4389 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4392 m68ki_exception_1111();
\r
4396 M68KMAKE_OP(dbt, 16, ., .)
\r
4402 M68KMAKE_OP(dbf, 16, ., .)
\r
4404 uint* r_dst = &DY;
\r
4405 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
\r
4407 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
4410 uint offset = OPER_I_16();
\r
4412 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4413 m68ki_branch_16(offset);
\r
4414 USE_CYCLES(CYC_DBCC_F_NOEXP);
\r
4418 USE_CYCLES(CYC_DBCC_F_EXP);
\r
4422 M68KMAKE_OP(dbcc, 16, ., .)
\r
4424 if(M68KMAKE_NOT_CC)
\r
4426 uint* r_dst = &DY;
\r
4427 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
\r
4429 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
4432 uint offset = OPER_I_16();
\r
4434 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4435 m68ki_branch_16(offset);
\r
4436 USE_CYCLES(CYC_DBCC_F_NOEXP);
\r
4440 USE_CYCLES(CYC_DBCC_F_EXP);
\r
4447 M68KMAKE_OP(divs, 16, ., d)
\r
4449 uint* r_dst = &DX;
\r
4450 sint src = MAKE_INT_16(DY);
\r
4456 if((uint32)*r_dst == 0x80000000 && src == -1)
\r
4459 FLAG_N = NFLAG_CLEAR;
\r
4460 FLAG_V = VFLAG_CLEAR;
\r
4461 FLAG_C = CFLAG_CLEAR;
\r
4466 quotient = MAKE_INT_32(*r_dst) / src;
\r
4467 remainder = MAKE_INT_32(*r_dst) % src;
\r
4469 if(quotient == MAKE_INT_16(quotient))
\r
4471 FLAG_Z = quotient;
\r
4472 FLAG_N = NFLAG_16(quotient);
\r
4473 FLAG_V = VFLAG_CLEAR;
\r
4474 FLAG_C = CFLAG_CLEAR;
\r
4475 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4478 FLAG_V = VFLAG_SET;
\r
4481 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4485 M68KMAKE_OP(divs, 16, ., .)
\r
4487 uint* r_dst = &DX;
\r
4488 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
4494 if((uint32)*r_dst == 0x80000000 && src == -1)
\r
4497 FLAG_N = NFLAG_CLEAR;
\r
4498 FLAG_V = VFLAG_CLEAR;
\r
4499 FLAG_C = CFLAG_CLEAR;
\r
4504 quotient = MAKE_INT_32(*r_dst) / src;
\r
4505 remainder = MAKE_INT_32(*r_dst) % src;
\r
4507 if(quotient == MAKE_INT_16(quotient))
\r
4509 FLAG_Z = quotient;
\r
4510 FLAG_N = NFLAG_16(quotient);
\r
4511 FLAG_V = VFLAG_CLEAR;
\r
4512 FLAG_C = CFLAG_CLEAR;
\r
4513 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4516 FLAG_V = VFLAG_SET;
\r
4519 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4523 M68KMAKE_OP(divu, 16, ., d)
\r
4525 uint* r_dst = &DX;
\r
4526 uint src = MASK_OUT_ABOVE_16(DY);
\r
4530 uint quotient = *r_dst / src;
\r
4531 uint remainder = *r_dst % src;
\r
4533 if(quotient < 0x10000)
\r
4535 FLAG_Z = quotient;
\r
4536 FLAG_N = NFLAG_16(quotient);
\r
4537 FLAG_V = VFLAG_CLEAR;
\r
4538 FLAG_C = CFLAG_CLEAR;
\r
4539 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4542 FLAG_V = VFLAG_SET;
\r
4545 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4549 M68KMAKE_OP(divu, 16, ., .)
\r
4551 uint* r_dst = &DX;
\r
4552 uint src = M68KMAKE_GET_OPER_AY_16;
\r
4556 uint quotient = *r_dst / src;
\r
4557 uint remainder = *r_dst % src;
\r
4559 if(quotient < 0x10000)
\r
4561 FLAG_Z = quotient;
\r
4562 FLAG_N = NFLAG_16(quotient);
\r
4563 FLAG_V = VFLAG_CLEAR;
\r
4564 FLAG_C = CFLAG_CLEAR;
\r
4565 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4568 FLAG_V = VFLAG_SET;
\r
4571 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4575 M68KMAKE_OP(divl, 32, ., d)
\r
4577 #if M68K_USE_64_BIT
\r
4579 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4581 uint word2 = OPER_I_16();
\r
4582 uint64 divisor = DY;
\r
4583 uint64 dividend = 0;
\r
4584 uint64 quotient = 0;
\r
4585 uint64 remainder = 0;
\r
4589 if(BIT_A(word2)) /* 64 bit */
\r
4591 dividend = REG_D[word2 & 7];
\r
4593 dividend |= REG_D[(word2 >> 12) & 7];
\r
4595 if(BIT_B(word2)) /* signed */
\r
4597 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
\r
4598 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
\r
4599 if((sint64)quotient != (sint64)((sint32)quotient))
\r
4601 FLAG_V = VFLAG_SET;
\r
4605 else /* unsigned */
\r
4607 quotient = dividend / divisor;
\r
4608 if(quotient > 0xffffffff)
\r
4610 FLAG_V = VFLAG_SET;
\r
4613 remainder = dividend % divisor;
\r
4618 dividend = REG_D[(word2 >> 12) & 7];
\r
4619 if(BIT_B(word2)) /* signed */
\r
4621 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
\r
4622 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
\r
4624 else /* unsigned */
\r
4626 quotient = dividend / divisor;
\r
4627 remainder = dividend % divisor;
\r
4631 REG_D[word2 & 7] = remainder;
\r
4632 REG_D[(word2 >> 12) & 7] = quotient;
\r
4634 FLAG_N = NFLAG_32(quotient);
\r
4635 FLAG_Z = quotient;
\r
4636 FLAG_V = VFLAG_CLEAR;
\r
4637 FLAG_C = CFLAG_CLEAR;
\r
4640 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4643 m68ki_exception_illegal();
\r
4647 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4649 uint word2 = OPER_I_16();
\r
4650 uint divisor = DY;
\r
4651 uint dividend_hi = REG_D[word2 & 7];
\r
4652 uint dividend_lo = REG_D[(word2 >> 12) & 7];
\r
4653 uint quotient = 0;
\r
4654 uint remainder = 0;
\r
4655 uint dividend_neg = 0;
\r
4656 uint divisor_neg = 0;
\r
4662 /* quad / long : long quotient, long remainder */
\r
4665 if(BIT_B(word2)) /* signed */
\r
4667 /* special case in signed divide */
\r
4668 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4670 REG_D[word2 & 7] = 0;
\r
4671 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4673 FLAG_N = NFLAG_SET;
\r
4674 FLAG_Z = ZFLAG_CLEAR;
\r
4675 FLAG_V = VFLAG_CLEAR;
\r
4676 FLAG_C = CFLAG_CLEAR;
\r
4679 if(GET_MSB_32(dividend_hi))
\r
4682 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
\r
4683 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
\r
4685 if(GET_MSB_32(divisor))
\r
4688 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
\r
4693 /* if the upper long is greater than the divisor, we're overflowing. */
\r
4694 if(dividend_hi >= divisor)
\r
4696 FLAG_V = VFLAG_SET;
\r
4700 for(i = 31; i >= 0; i--)
\r
4703 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
\r
4704 if(remainder >= divisor)
\r
4706 remainder -= divisor;
\r
4710 for(i = 31; i >= 0; i--)
\r
4713 overflow = GET_MSB_32(remainder);
\r
4714 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
\r
4715 if(remainder >= divisor || overflow)
\r
4717 remainder -= divisor;
\r
4722 if(BIT_B(word2)) /* signed */
\r
4724 if(quotient > 0x7fffffff)
\r
4726 FLAG_V = VFLAG_SET;
\r
4731 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
\r
4732 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4735 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4738 REG_D[word2 & 7] = remainder;
\r
4739 REG_D[(word2 >> 12) & 7] = quotient;
\r
4741 FLAG_N = NFLAG_32(quotient);
\r
4742 FLAG_Z = quotient;
\r
4743 FLAG_V = VFLAG_CLEAR;
\r
4744 FLAG_C = CFLAG_CLEAR;
\r
4748 /* long / long: long quotient, maybe long remainder */
\r
4749 if(BIT_B(word2)) /* signed */
\r
4751 /* Special case in divide */
\r
4752 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4754 FLAG_N = NFLAG_SET;
\r
4755 FLAG_Z = ZFLAG_CLEAR;
\r
4756 FLAG_V = VFLAG_CLEAR;
\r
4757 FLAG_C = CFLAG_CLEAR;
\r
4758 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4759 REG_D[word2 & 7] = 0;
\r
4762 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
\r
4763 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
\r
4767 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
\r
4768 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
\r
4771 FLAG_N = NFLAG_32(quotient);
\r
4772 FLAG_Z = quotient;
\r
4773 FLAG_V = VFLAG_CLEAR;
\r
4774 FLAG_C = CFLAG_CLEAR;
\r
4777 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4780 m68ki_exception_illegal();
\r
4786 M68KMAKE_OP(divl, 32, ., .)
\r
4788 #if M68K_USE_64_BIT
\r
4790 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4792 uint word2 = OPER_I_16();
\r
4793 uint64 divisor = M68KMAKE_GET_OPER_AY_32;
\r
4794 uint64 dividend = 0;
\r
4795 uint64 quotient = 0;
\r
4796 uint64 remainder = 0;
\r
4800 if(BIT_A(word2)) /* 64 bit */
\r
4802 dividend = REG_D[word2 & 7];
\r
4804 dividend |= REG_D[(word2 >> 12) & 7];
\r
4806 if(BIT_B(word2)) /* signed */
\r
4808 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
\r
4809 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
\r
4810 if((sint64)quotient != (sint64)((sint32)quotient))
\r
4812 FLAG_V = VFLAG_SET;
\r
4816 else /* unsigned */
\r
4818 quotient = dividend / divisor;
\r
4819 if(quotient > 0xffffffff)
\r
4821 FLAG_V = VFLAG_SET;
\r
4824 remainder = dividend % divisor;
\r
4829 dividend = REG_D[(word2 >> 12) & 7];
\r
4830 if(BIT_B(word2)) /* signed */
\r
4832 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
\r
4833 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
\r
4835 else /* unsigned */
\r
4837 quotient = dividend / divisor;
\r
4838 remainder = dividend % divisor;
\r
4842 REG_D[word2 & 7] = remainder;
\r
4843 REG_D[(word2 >> 12) & 7] = quotient;
\r
4845 FLAG_N = NFLAG_32(quotient);
\r
4846 FLAG_Z = quotient;
\r
4847 FLAG_V = VFLAG_CLEAR;
\r
4848 FLAG_C = CFLAG_CLEAR;
\r
4851 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4854 m68ki_exception_illegal();
\r
4858 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4860 uint word2 = OPER_I_16();
\r
4861 uint divisor = M68KMAKE_GET_OPER_AY_32;
\r
4862 uint dividend_hi = REG_D[word2 & 7];
\r
4863 uint dividend_lo = REG_D[(word2 >> 12) & 7];
\r
4864 uint quotient = 0;
\r
4865 uint remainder = 0;
\r
4866 uint dividend_neg = 0;
\r
4867 uint divisor_neg = 0;
\r
4873 /* quad / long : long quotient, long remainder */
\r
4876 if(BIT_B(word2)) /* signed */
\r
4878 /* special case in signed divide */
\r
4879 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4881 REG_D[word2 & 7] = 0;
\r
4882 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4884 FLAG_N = NFLAG_SET;
\r
4885 FLAG_Z = ZFLAG_CLEAR;
\r
4886 FLAG_V = VFLAG_CLEAR;
\r
4887 FLAG_C = CFLAG_CLEAR;
\r
4890 if(GET_MSB_32(dividend_hi))
\r
4893 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
\r
4894 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
\r
4896 if(GET_MSB_32(divisor))
\r
4899 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
\r
4904 /* if the upper long is greater than the divisor, we're overflowing. */
\r
4905 if(dividend_hi >= divisor)
\r
4907 FLAG_V = VFLAG_SET;
\r
4911 for(i = 31; i >= 0; i--)
\r
4914 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
\r
4915 if(remainder >= divisor)
\r
4917 remainder -= divisor;
\r
4921 for(i = 31; i >= 0; i--)
\r
4924 overflow = GET_MSB_32(remainder);
\r
4925 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
\r
4926 if(remainder >= divisor || overflow)
\r
4928 remainder -= divisor;
\r
4933 if(BIT_B(word2)) /* signed */
\r
4935 if(quotient > 0x7fffffff)
\r
4937 FLAG_V = VFLAG_SET;
\r
4942 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
\r
4943 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4946 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4949 REG_D[word2 & 7] = remainder;
\r
4950 REG_D[(word2 >> 12) & 7] = quotient;
\r
4952 FLAG_N = NFLAG_32(quotient);
\r
4953 FLAG_Z = quotient;
\r
4954 FLAG_V = VFLAG_CLEAR;
\r
4955 FLAG_C = CFLAG_CLEAR;
\r
4959 /* long / long: long quotient, maybe long remainder */
\r
4960 if(BIT_B(word2)) /* signed */
\r
4962 /* Special case in divide */
\r
4963 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4965 FLAG_N = NFLAG_SET;
\r
4966 FLAG_Z = ZFLAG_CLEAR;
\r
4967 FLAG_V = VFLAG_CLEAR;
\r
4968 FLAG_C = CFLAG_CLEAR;
\r
4969 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4970 REG_D[word2 & 7] = 0;
\r
4973 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
\r
4974 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
\r
4978 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
\r
4979 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
\r
4982 FLAG_N = NFLAG_32(quotient);
\r
4983 FLAG_Z = quotient;
\r
4984 FLAG_V = VFLAG_CLEAR;
\r
4985 FLAG_C = CFLAG_CLEAR;
\r
4988 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4991 m68ki_exception_illegal();
\r
4997 M68KMAKE_OP(eor, 8, ., d)
\r
4999 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
\r
5001 FLAG_N = NFLAG_8(res);
\r
5003 FLAG_C = CFLAG_CLEAR;
\r
5004 FLAG_V = VFLAG_CLEAR;
\r
5008 M68KMAKE_OP(eor, 8, ., .)
\r
5010 uint ea = M68KMAKE_GET_EA_AY_8;
\r
5011 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
\r
5013 m68ki_write_8(ea, res);
\r
5015 FLAG_N = NFLAG_8(res);
\r
5017 FLAG_C = CFLAG_CLEAR;
\r
5018 FLAG_V = VFLAG_CLEAR;
\r
5022 M68KMAKE_OP(eor, 16, ., d)
\r
5024 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
\r
5026 FLAG_N = NFLAG_16(res);
\r
5028 FLAG_C = CFLAG_CLEAR;
\r
5029 FLAG_V = VFLAG_CLEAR;
\r
5033 M68KMAKE_OP(eor, 16, ., .)
\r
5035 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5036 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
\r
5038 m68ki_write_16(ea, res);
\r
5040 FLAG_N = NFLAG_16(res);
\r
5042 FLAG_C = CFLAG_CLEAR;
\r
5043 FLAG_V = VFLAG_CLEAR;
\r
5047 M68KMAKE_OP(eor, 32, ., d)
\r
5049 uint res = DY ^= DX;
\r
5051 FLAG_N = NFLAG_32(res);
\r
5053 FLAG_C = CFLAG_CLEAR;
\r
5054 FLAG_V = VFLAG_CLEAR;
\r
5058 M68KMAKE_OP(eor, 32, ., .)
\r
5060 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5061 uint res = DX ^ m68ki_read_32(ea);
\r
5063 m68ki_write_32(ea, res);
\r
5065 FLAG_N = NFLAG_32(res);
\r
5067 FLAG_C = CFLAG_CLEAR;
\r
5068 FLAG_V = VFLAG_CLEAR;
\r
5072 M68KMAKE_OP(eori, 8, ., d)
\r
5074 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
\r
5076 FLAG_N = NFLAG_8(res);
\r
5078 FLAG_C = CFLAG_CLEAR;
\r
5079 FLAG_V = VFLAG_CLEAR;
\r
5083 M68KMAKE_OP(eori, 8, ., .)
\r
5085 uint src = OPER_I_8();
\r
5086 uint ea = M68KMAKE_GET_EA_AY_8;
\r
5087 uint res = src ^ m68ki_read_8(ea);
\r
5089 m68ki_write_8(ea, res);
\r
5091 FLAG_N = NFLAG_8(res);
\r
5093 FLAG_C = CFLAG_CLEAR;
\r
5094 FLAG_V = VFLAG_CLEAR;
\r
5098 M68KMAKE_OP(eori, 16, ., d)
\r
5100 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
\r
5102 FLAG_N = NFLAG_16(res);
\r
5104 FLAG_C = CFLAG_CLEAR;
\r
5105 FLAG_V = VFLAG_CLEAR;
\r
5109 M68KMAKE_OP(eori, 16, ., .)
\r
5111 uint src = OPER_I_16();
\r
5112 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5113 uint res = src ^ m68ki_read_16(ea);
\r
5115 m68ki_write_16(ea, res);
\r
5117 FLAG_N = NFLAG_16(res);
\r
5119 FLAG_C = CFLAG_CLEAR;
\r
5120 FLAG_V = VFLAG_CLEAR;
\r
5124 M68KMAKE_OP(eori, 32, ., d)
\r
5126 uint res = DY ^= OPER_I_32();
\r
5128 FLAG_N = NFLAG_32(res);
\r
5130 FLAG_C = CFLAG_CLEAR;
\r
5131 FLAG_V = VFLAG_CLEAR;
\r
5135 M68KMAKE_OP(eori, 32, ., .)
\r
5137 uint src = OPER_I_32();
\r
5138 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5139 uint res = src ^ m68ki_read_32(ea);
\r
5141 m68ki_write_32(ea, res);
\r
5143 FLAG_N = NFLAG_32(res);
\r
5145 FLAG_C = CFLAG_CLEAR;
\r
5146 FLAG_V = VFLAG_CLEAR;
\r
5150 M68KMAKE_OP(eori, 16, toc, .)
\r
5152 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
\r
5156 M68KMAKE_OP(eori, 16, tos, .)
\r
5160 uint src = OPER_I_16();
\r
5161 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5162 m68ki_set_sr(m68ki_get_sr() ^ src);
\r
5165 m68ki_exception_privilege_violation();
\r
5169 M68KMAKE_OP(exg, 32, dd, .)
\r
5171 uint* reg_a = &DX;
\r
5172 uint* reg_b = &DY;
\r
5173 uint tmp = *reg_a;
\r
5179 M68KMAKE_OP(exg, 32, aa, .)
\r
5181 uint* reg_a = &AX;
\r
5182 uint* reg_b = &AY;
\r
5183 uint tmp = *reg_a;
\r
5189 M68KMAKE_OP(exg, 32, da, .)
\r
5191 uint* reg_a = &DX;
\r
5192 uint* reg_b = &AY;
\r
5193 uint tmp = *reg_a;
\r
5199 M68KMAKE_OP(ext, 16, ., .)
\r
5201 uint* r_dst = &DY;
\r
5203 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
\r
5205 FLAG_N = NFLAG_16(*r_dst);
\r
5206 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
5207 FLAG_V = VFLAG_CLEAR;
\r
5208 FLAG_C = CFLAG_CLEAR;
\r
5212 M68KMAKE_OP(ext, 32, ., .)
\r
5214 uint* r_dst = &DY;
\r
5216 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
\r
5218 FLAG_N = NFLAG_32(*r_dst);
\r
5220 FLAG_V = VFLAG_CLEAR;
\r
5221 FLAG_C = CFLAG_CLEAR;
\r
5225 M68KMAKE_OP(extb, 32, ., .)
\r
5227 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5229 uint* r_dst = &DY;
\r
5231 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
\r
5233 FLAG_N = NFLAG_32(*r_dst);
\r
5235 FLAG_V = VFLAG_CLEAR;
\r
5236 FLAG_C = CFLAG_CLEAR;
\r
5239 m68ki_exception_illegal();
\r
5243 M68KMAKE_OP(illegal, 0, ., .)
\r
5245 m68ki_exception_illegal();
\r
5248 M68KMAKE_OP(jmp, 32, ., .)
\r
5250 m68ki_jump(M68KMAKE_GET_EA_AY_32);
\r
5251 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5252 if(REG_PC == REG_PPC)
\r
5257 M68KMAKE_OP(jsr, 32, ., .)
\r
5259 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5260 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5261 m68ki_push_32(MAKE_INT_24(REG_PC)); // notaz: Cyclone can't handle 32bit PC and I neet to debug it
\r
5266 M68KMAKE_OP(lea, 32, ., .)
\r
5268 AX = M68KMAKE_GET_EA_AY_32;
\r
5272 M68KMAKE_OP(link, 16, ., a7)
\r
5275 m68ki_write_32(REG_A[7], REG_A[7]);
\r
5276 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
5280 M68KMAKE_OP(link, 16, ., .)
\r
5282 uint* r_dst = &AY;
\r
5284 m68ki_push_32(*r_dst);
\r
5285 *r_dst = REG_A[7];
\r
5286 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
5290 M68KMAKE_OP(link, 32, ., a7)
\r
5292 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5295 m68ki_write_32(REG_A[7], REG_A[7]);
\r
5296 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
\r
5299 m68ki_exception_illegal();
\r
5303 M68KMAKE_OP(link, 32, ., .)
\r
5305 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5307 uint* r_dst = &AY;
\r
5309 m68ki_push_32(*r_dst);
\r
5310 *r_dst = REG_A[7];
\r
5311 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
\r
5314 m68ki_exception_illegal();
\r
5318 M68KMAKE_OP(lsr, 8, s, .)
\r
5320 uint* r_dst = &DY;
\r
5321 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5322 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5323 uint res = src >> shift;
\r
5326 USE_CYCLES(shift<<CYC_SHIFT);
\r
5328 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5330 FLAG_N = NFLAG_CLEAR;
\r
5332 FLAG_X = FLAG_C = src << (9-shift);
\r
5333 FLAG_V = VFLAG_CLEAR;
\r
5337 M68KMAKE_OP(lsr, 16, s, .)
\r
5339 uint* r_dst = &DY;
\r
5340 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5341 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5342 uint res = src >> shift;
\r
5345 USE_CYCLES(shift<<CYC_SHIFT);
\r
5347 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5349 FLAG_N = NFLAG_CLEAR;
\r
5351 FLAG_X = FLAG_C = src << (9-shift);
\r
5352 FLAG_V = VFLAG_CLEAR;
\r
5356 M68KMAKE_OP(lsr, 32, s, .)
\r
5358 uint* r_dst = &DY;
\r
5359 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5360 uint src = *r_dst;
\r
5361 uint res = src >> shift;
\r
5364 USE_CYCLES(shift<<CYC_SHIFT);
\r
5368 FLAG_N = NFLAG_CLEAR;
\r
5370 FLAG_X = FLAG_C = src << (9-shift);
\r
5371 FLAG_V = VFLAG_CLEAR;
\r
5375 M68KMAKE_OP(lsr, 8, r, .)
\r
5377 uint* r_dst = &DY;
\r
5378 uint shift = DX & 0x3f;
\r
5379 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5380 uint res = src >> shift;
\r
5384 USE_CYCLES(shift<<CYC_SHIFT);
\r
5388 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5389 FLAG_X = FLAG_C = src << (9-shift);
\r
5390 FLAG_N = NFLAG_CLEAR;
\r
5392 FLAG_V = VFLAG_CLEAR;
\r
5396 *r_dst &= 0xffffff00;
\r
5397 FLAG_X = XFLAG_CLEAR;
\r
5398 FLAG_C = CFLAG_CLEAR;
\r
5399 FLAG_N = NFLAG_CLEAR;
\r
5400 FLAG_Z = ZFLAG_SET;
\r
5401 FLAG_V = VFLAG_CLEAR;
\r
5405 FLAG_C = CFLAG_CLEAR;
\r
5406 FLAG_N = NFLAG_8(src);
\r
5408 FLAG_V = VFLAG_CLEAR;
\r
5412 M68KMAKE_OP(lsr, 16, r, .)
\r
5414 uint* r_dst = &DY;
\r
5415 uint shift = DX & 0x3f;
\r
5416 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5417 uint res = src >> shift;
\r
5421 USE_CYCLES(shift<<CYC_SHIFT);
\r
5425 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5426 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
5427 FLAG_N = NFLAG_CLEAR;
\r
5429 FLAG_V = VFLAG_CLEAR;
\r
5433 *r_dst &= 0xffff0000;
\r
5434 FLAG_X = XFLAG_CLEAR;
\r
5435 FLAG_C = CFLAG_CLEAR;
\r
5436 FLAG_N = NFLAG_CLEAR;
\r
5437 FLAG_Z = ZFLAG_SET;
\r
5438 FLAG_V = VFLAG_CLEAR;
\r
5442 FLAG_C = CFLAG_CLEAR;
\r
5443 FLAG_N = NFLAG_16(src);
\r
5445 FLAG_V = VFLAG_CLEAR;
\r
5449 M68KMAKE_OP(lsr, 32, r, .)
\r
5451 uint* r_dst = &DY;
\r
5452 uint shift = DX & 0x3f;
\r
5453 uint src = *r_dst;
\r
5454 uint res = src >> shift;
\r
5458 USE_CYCLES(shift<<CYC_SHIFT);
\r
5463 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
5464 FLAG_N = NFLAG_CLEAR;
\r
5466 FLAG_V = VFLAG_CLEAR;
\r
5471 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
\r
5472 FLAG_N = NFLAG_CLEAR;
\r
5473 FLAG_Z = ZFLAG_SET;
\r
5474 FLAG_V = VFLAG_CLEAR;
\r
5478 FLAG_C = CFLAG_CLEAR;
\r
5479 FLAG_N = NFLAG_32(src);
\r
5481 FLAG_V = VFLAG_CLEAR;
\r
5485 M68KMAKE_OP(lsr, 16, ., .)
\r
5487 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5488 uint src = m68ki_read_16(ea);
\r
5489 uint res = src >> 1;
\r
5491 m68ki_write_16(ea, res);
\r
5493 FLAG_N = NFLAG_CLEAR;
\r
5495 FLAG_C = FLAG_X = src << 8;
\r
5496 FLAG_V = VFLAG_CLEAR;
\r
5500 M68KMAKE_OP(lsl, 8, s, .)
\r
5502 uint* r_dst = &DY;
\r
5503 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5504 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5505 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
5508 USE_CYCLES(shift<<CYC_SHIFT);
\r
5510 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5512 FLAG_N = NFLAG_8(res);
\r
5514 FLAG_X = FLAG_C = src << shift;
\r
5515 FLAG_V = VFLAG_CLEAR;
\r
5519 M68KMAKE_OP(lsl, 16, s, .)
\r
5521 uint* r_dst = &DY;
\r
5522 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5523 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5524 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
5527 USE_CYCLES(shift<<CYC_SHIFT);
\r
5529 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5531 FLAG_N = NFLAG_16(res);
\r
5533 FLAG_X = FLAG_C = src >> (8-shift);
\r
5534 FLAG_V = VFLAG_CLEAR;
\r
5538 M68KMAKE_OP(lsl, 32, s, .)
\r
5540 uint* r_dst = &DY;
\r
5541 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5542 uint src = *r_dst;
\r
5543 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
5546 USE_CYCLES(shift<<CYC_SHIFT);
\r
5550 FLAG_N = NFLAG_32(res);
\r
5552 FLAG_X = FLAG_C = src >> (24-shift);
\r
5553 FLAG_V = VFLAG_CLEAR;
\r
5557 M68KMAKE_OP(lsl, 8, r, .)
\r
5559 uint* r_dst = &DY;
\r
5560 uint shift = DX & 0x3f;
\r
5561 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5562 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
5566 USE_CYCLES(shift<<CYC_SHIFT);
\r
5570 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5571 FLAG_X = FLAG_C = src << shift;
\r
5572 FLAG_N = NFLAG_8(res);
\r
5574 FLAG_V = VFLAG_CLEAR;
\r
5578 *r_dst &= 0xffffff00;
\r
5579 FLAG_X = XFLAG_CLEAR;
\r
5580 FLAG_C = CFLAG_CLEAR;
\r
5581 FLAG_N = NFLAG_CLEAR;
\r
5582 FLAG_Z = ZFLAG_SET;
\r
5583 FLAG_V = VFLAG_CLEAR;
\r
5587 FLAG_C = CFLAG_CLEAR;
\r
5588 FLAG_N = NFLAG_8(src);
\r
5590 FLAG_V = VFLAG_CLEAR;
\r
5594 M68KMAKE_OP(lsl, 16, r, .)
\r
5596 uint* r_dst = &DY;
\r
5597 uint shift = DX & 0x3f;
\r
5598 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5599 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
5603 USE_CYCLES(shift<<CYC_SHIFT);
\r
5607 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5608 FLAG_X = FLAG_C = (src << shift) >> 8;
\r
5609 FLAG_N = NFLAG_16(res);
\r
5611 FLAG_V = VFLAG_CLEAR;
\r
5615 *r_dst &= 0xffff0000;
\r
5616 FLAG_X = XFLAG_CLEAR;
\r
5617 FLAG_C = CFLAG_CLEAR;
\r
5618 FLAG_N = NFLAG_CLEAR;
\r
5619 FLAG_Z = ZFLAG_SET;
\r
5620 FLAG_V = VFLAG_CLEAR;
\r
5624 FLAG_C = CFLAG_CLEAR;
\r
5625 FLAG_N = NFLAG_16(src);
\r
5627 FLAG_V = VFLAG_CLEAR;
\r
5631 M68KMAKE_OP(lsl, 32, r, .)
\r
5633 uint* r_dst = &DY;
\r
5634 uint shift = DX & 0x3f;
\r
5635 uint src = *r_dst;
\r
5636 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
5640 USE_CYCLES(shift<<CYC_SHIFT);
\r
5645 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
\r
5646 FLAG_N = NFLAG_32(res);
\r
5648 FLAG_V = VFLAG_CLEAR;
\r
5653 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
\r
5654 FLAG_N = NFLAG_CLEAR;
\r
5655 FLAG_Z = ZFLAG_SET;
\r
5656 FLAG_V = VFLAG_CLEAR;
\r
5660 FLAG_C = CFLAG_CLEAR;
\r
5661 FLAG_N = NFLAG_32(src);
\r
5663 FLAG_V = VFLAG_CLEAR;
\r
5667 M68KMAKE_OP(lsl, 16, ., .)
\r
5669 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5670 uint src = m68ki_read_16(ea);
\r
5671 uint res = MASK_OUT_ABOVE_16(src << 1);
\r
5673 m68ki_write_16(ea, res);
\r
5675 FLAG_N = NFLAG_16(res);
\r
5677 FLAG_X = FLAG_C = src >> 7;
\r
5678 FLAG_V = VFLAG_CLEAR;
\r
5682 M68KMAKE_OP(move, 8, d, d)
\r
5684 uint res = MASK_OUT_ABOVE_8(DY);
\r
5685 uint* r_dst = &DX;
\r
5687 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5689 FLAG_N = NFLAG_8(res);
\r
5691 FLAG_V = VFLAG_CLEAR;
\r
5692 FLAG_C = CFLAG_CLEAR;
\r
5696 M68KMAKE_OP(move, 8, d, .)
\r
5698 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5699 uint* r_dst = &DX;
\r
5701 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5703 FLAG_N = NFLAG_8(res);
\r
5705 FLAG_V = VFLAG_CLEAR;
\r
5706 FLAG_C = CFLAG_CLEAR;
\r
5710 M68KMAKE_OP(move, 8, ai, d)
\r
5712 uint res = MASK_OUT_ABOVE_8(DY);
\r
5713 uint ea = EA_AX_AI_8();
\r
5715 m68ki_write_8(ea, res);
\r
5717 FLAG_N = NFLAG_8(res);
\r
5719 FLAG_V = VFLAG_CLEAR;
\r
5720 FLAG_C = CFLAG_CLEAR;
\r
5724 M68KMAKE_OP(move, 8, ai, .)
\r
5726 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5727 uint ea = EA_AX_AI_8();
\r
5729 m68ki_write_8(ea, res);
\r
5731 FLAG_N = NFLAG_8(res);
\r
5733 FLAG_V = VFLAG_CLEAR;
\r
5734 FLAG_C = CFLAG_CLEAR;
\r
5738 M68KMAKE_OP(move, 8, pi7, d)
\r
5740 uint res = MASK_OUT_ABOVE_8(DY);
\r
5741 uint ea = EA_A7_PI_8();
\r
5743 m68ki_write_8(ea, res);
\r
5745 FLAG_N = NFLAG_8(res);
\r
5747 FLAG_V = VFLAG_CLEAR;
\r
5748 FLAG_C = CFLAG_CLEAR;
\r
5752 M68KMAKE_OP(move, 8, pi, d)
\r
5754 uint res = MASK_OUT_ABOVE_8(DY);
\r
5755 uint ea = EA_AX_PI_8();
\r
5757 m68ki_write_8(ea, res);
\r
5759 FLAG_N = NFLAG_8(res);
\r
5761 FLAG_V = VFLAG_CLEAR;
\r
5762 FLAG_C = CFLAG_CLEAR;
\r
5766 M68KMAKE_OP(move, 8, pi7, .)
\r
5768 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5769 uint ea = EA_A7_PI_8();
\r
5771 m68ki_write_8(ea, res);
\r
5773 FLAG_N = NFLAG_8(res);
\r
5775 FLAG_V = VFLAG_CLEAR;
\r
5776 FLAG_C = CFLAG_CLEAR;
\r
5780 M68KMAKE_OP(move, 8, pi, .)
\r
5782 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5783 uint ea = EA_AX_PI_8();
\r
5785 m68ki_write_8(ea, res);
\r
5787 FLAG_N = NFLAG_8(res);
\r
5789 FLAG_V = VFLAG_CLEAR;
\r
5790 FLAG_C = CFLAG_CLEAR;
\r
5794 M68KMAKE_OP(move, 8, pd7, d)
\r
5796 uint res = MASK_OUT_ABOVE_8(DY);
\r
5797 uint ea = EA_A7_PD_8();
\r
5799 m68ki_write_8(ea, res);
\r
5801 FLAG_N = NFLAG_8(res);
\r
5803 FLAG_V = VFLAG_CLEAR;
\r
5804 FLAG_C = CFLAG_CLEAR;
\r
5808 M68KMAKE_OP(move, 8, pd, d)
\r
5810 uint res = MASK_OUT_ABOVE_8(DY);
\r
5811 uint ea = EA_AX_PD_8();
\r
5813 m68ki_write_8(ea, res);
\r
5815 FLAG_N = NFLAG_8(res);
\r
5817 FLAG_V = VFLAG_CLEAR;
\r
5818 FLAG_C = CFLAG_CLEAR;
\r
5822 M68KMAKE_OP(move, 8, pd7, .)
\r
5824 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5825 uint ea = EA_A7_PD_8();
\r
5827 m68ki_write_8(ea, res);
\r
5829 FLAG_N = NFLAG_8(res);
\r
5831 FLAG_V = VFLAG_CLEAR;
\r
5832 FLAG_C = CFLAG_CLEAR;
\r
5836 M68KMAKE_OP(move, 8, pd, .)
\r
5838 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5839 uint ea = EA_AX_PD_8();
\r
5841 m68ki_write_8(ea, res);
\r
5843 FLAG_N = NFLAG_8(res);
\r
5845 FLAG_V = VFLAG_CLEAR;
\r
5846 FLAG_C = CFLAG_CLEAR;
\r
5850 M68KMAKE_OP(move, 8, di, d)
\r
5852 uint res = MASK_OUT_ABOVE_8(DY);
\r
5853 uint ea = EA_AX_DI_8();
\r
5855 m68ki_write_8(ea, res);
\r
5857 FLAG_N = NFLAG_8(res);
\r
5859 FLAG_V = VFLAG_CLEAR;
\r
5860 FLAG_C = CFLAG_CLEAR;
\r
5864 M68KMAKE_OP(move, 8, di, .)
\r
5866 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5867 uint ea = EA_AX_DI_8();
\r
5869 m68ki_write_8(ea, res);
\r
5871 FLAG_N = NFLAG_8(res);
\r
5873 FLAG_V = VFLAG_CLEAR;
\r
5874 FLAG_C = CFLAG_CLEAR;
\r
5878 M68KMAKE_OP(move, 8, ix, d)
\r
5880 uint res = MASK_OUT_ABOVE_8(DY);
\r
5881 uint ea = EA_AX_IX_8();
\r
5883 m68ki_write_8(ea, res);
\r
5885 FLAG_N = NFLAG_8(res);
\r
5887 FLAG_V = VFLAG_CLEAR;
\r
5888 FLAG_C = CFLAG_CLEAR;
\r
5892 M68KMAKE_OP(move, 8, ix, .)
\r
5894 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5895 uint ea = EA_AX_IX_8();
\r
5897 m68ki_write_8(ea, res);
\r
5899 FLAG_N = NFLAG_8(res);
\r
5901 FLAG_V = VFLAG_CLEAR;
\r
5902 FLAG_C = CFLAG_CLEAR;
\r
5906 M68KMAKE_OP(move, 8, aw, d)
\r
5908 uint res = MASK_OUT_ABOVE_8(DY);
\r
5909 uint ea = EA_AW_8();
\r
5911 m68ki_write_8(ea, res);
\r
5913 FLAG_N = NFLAG_8(res);
\r
5915 FLAG_V = VFLAG_CLEAR;
\r
5916 FLAG_C = CFLAG_CLEAR;
\r
5920 M68KMAKE_OP(move, 8, aw, .)
\r
5922 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5923 uint ea = EA_AW_8();
\r
5925 m68ki_write_8(ea, res);
\r
5927 FLAG_N = NFLAG_8(res);
\r
5929 FLAG_V = VFLAG_CLEAR;
\r
5930 FLAG_C = CFLAG_CLEAR;
\r
5934 M68KMAKE_OP(move, 8, al, d)
\r
5936 uint res = MASK_OUT_ABOVE_8(DY);
\r
5937 uint ea = EA_AL_8();
\r
5939 m68ki_write_8(ea, res);
\r
5941 FLAG_N = NFLAG_8(res);
\r
5943 FLAG_V = VFLAG_CLEAR;
\r
5944 FLAG_C = CFLAG_CLEAR;
\r
5948 M68KMAKE_OP(move, 8, al, .)
\r
5950 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5951 uint ea = EA_AL_8();
\r
5953 m68ki_write_8(ea, res);
\r
5955 FLAG_N = NFLAG_8(res);
\r
5957 FLAG_V = VFLAG_CLEAR;
\r
5958 FLAG_C = CFLAG_CLEAR;
\r
5962 M68KMAKE_OP(move, 16, d, d)
\r
5964 uint res = MASK_OUT_ABOVE_16(DY);
\r
5965 uint* r_dst = &DX;
\r
5967 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5969 FLAG_N = NFLAG_16(res);
\r
5971 FLAG_V = VFLAG_CLEAR;
\r
5972 FLAG_C = CFLAG_CLEAR;
\r
5976 M68KMAKE_OP(move, 16, d, a)
\r
5978 uint res = MASK_OUT_ABOVE_16(AY);
\r
5979 uint* r_dst = &DX;
\r
5981 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5983 FLAG_N = NFLAG_16(res);
\r
5985 FLAG_V = VFLAG_CLEAR;
\r
5986 FLAG_C = CFLAG_CLEAR;
\r
5990 M68KMAKE_OP(move, 16, d, .)
\r
5992 uint res = M68KMAKE_GET_OPER_AY_16;
\r
5993 uint* r_dst = &DX;
\r
5995 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5997 FLAG_N = NFLAG_16(res);
\r
5999 FLAG_V = VFLAG_CLEAR;
\r
6000 FLAG_C = CFLAG_CLEAR;
\r
6004 M68KMAKE_OP(move, 16, ai, d)
\r
6006 uint res = MASK_OUT_ABOVE_16(DY);
\r
6007 uint ea = EA_AX_AI_16();
\r
6009 m68ki_write_16(ea, res);
\r
6011 FLAG_N = NFLAG_16(res);
\r
6013 FLAG_V = VFLAG_CLEAR;
\r
6014 FLAG_C = CFLAG_CLEAR;
\r
6018 M68KMAKE_OP(move, 16, ai, a)
\r
6020 uint res = MASK_OUT_ABOVE_16(AY);
\r
6021 uint ea = EA_AX_AI_16();
\r
6023 m68ki_write_16(ea, res);
\r
6025 FLAG_N = NFLAG_16(res);
\r
6027 FLAG_V = VFLAG_CLEAR;
\r
6028 FLAG_C = CFLAG_CLEAR;
\r
6032 M68KMAKE_OP(move, 16, ai, .)
\r
6034 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6035 uint ea = EA_AX_AI_16();
\r
6037 m68ki_write_16(ea, res);
\r
6039 FLAG_N = NFLAG_16(res);
\r
6041 FLAG_V = VFLAG_CLEAR;
\r
6042 FLAG_C = CFLAG_CLEAR;
\r
6046 M68KMAKE_OP(move, 16, pi, d)
\r
6048 uint res = MASK_OUT_ABOVE_16(DY);
\r
6049 uint ea = EA_AX_PI_16();
\r
6051 m68ki_write_16(ea, res);
\r
6053 FLAG_N = NFLAG_16(res);
\r
6055 FLAG_V = VFLAG_CLEAR;
\r
6056 FLAG_C = CFLAG_CLEAR;
\r
6060 M68KMAKE_OP(move, 16, pi, a)
\r
6062 uint res = MASK_OUT_ABOVE_16(AY);
\r
6063 uint ea = EA_AX_PI_16();
\r
6065 m68ki_write_16(ea, res);
\r
6067 FLAG_N = NFLAG_16(res);
\r
6069 FLAG_V = VFLAG_CLEAR;
\r
6070 FLAG_C = CFLAG_CLEAR;
\r
6074 M68KMAKE_OP(move, 16, pi, .)
\r
6076 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6077 uint ea = EA_AX_PI_16();
\r
6079 m68ki_write_16(ea, res);
\r
6081 FLAG_N = NFLAG_16(res);
\r
6083 FLAG_V = VFLAG_CLEAR;
\r
6084 FLAG_C = CFLAG_CLEAR;
\r
6088 M68KMAKE_OP(move, 16, pd, d)
\r
6090 uint res = MASK_OUT_ABOVE_16(DY);
\r
6091 uint ea = EA_AX_PD_16();
\r
6093 m68ki_write_16(ea, res);
\r
6095 FLAG_N = NFLAG_16(res);
\r
6097 FLAG_V = VFLAG_CLEAR;
\r
6098 FLAG_C = CFLAG_CLEAR;
\r
6102 M68KMAKE_OP(move, 16, pd, a)
\r
6104 uint res = MASK_OUT_ABOVE_16(AY);
\r
6105 uint ea = EA_AX_PD_16();
\r
6107 m68ki_write_16(ea, res);
\r
6109 FLAG_N = NFLAG_16(res);
\r
6111 FLAG_V = VFLAG_CLEAR;
\r
6112 FLAG_C = CFLAG_CLEAR;
\r
6116 M68KMAKE_OP(move, 16, pd, .)
\r
6118 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6119 uint ea = EA_AX_PD_16();
\r
6121 m68ki_write_16(ea, res);
\r
6123 FLAG_N = NFLAG_16(res);
\r
6125 FLAG_V = VFLAG_CLEAR;
\r
6126 FLAG_C = CFLAG_CLEAR;
\r
6130 M68KMAKE_OP(move, 16, di, d)
\r
6132 uint res = MASK_OUT_ABOVE_16(DY);
\r
6133 uint ea = EA_AX_DI_16();
\r
6135 m68ki_write_16(ea, res);
\r
6137 FLAG_N = NFLAG_16(res);
\r
6139 FLAG_V = VFLAG_CLEAR;
\r
6140 FLAG_C = CFLAG_CLEAR;
\r
6144 M68KMAKE_OP(move, 16, di, a)
\r
6146 uint res = MASK_OUT_ABOVE_16(AY);
\r
6147 uint ea = EA_AX_DI_16();
\r
6149 m68ki_write_16(ea, res);
\r
6151 FLAG_N = NFLAG_16(res);
\r
6153 FLAG_V = VFLAG_CLEAR;
\r
6154 FLAG_C = CFLAG_CLEAR;
\r
6158 M68KMAKE_OP(move, 16, di, .)
\r
6160 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6161 uint ea = EA_AX_DI_16();
\r
6163 m68ki_write_16(ea, res);
\r
6165 FLAG_N = NFLAG_16(res);
\r
6167 FLAG_V = VFLAG_CLEAR;
\r
6168 FLAG_C = CFLAG_CLEAR;
\r
6172 M68KMAKE_OP(move, 16, ix, d)
\r
6174 uint res = MASK_OUT_ABOVE_16(DY);
\r
6175 uint ea = EA_AX_IX_16();
\r
6177 m68ki_write_16(ea, res);
\r
6179 FLAG_N = NFLAG_16(res);
\r
6181 FLAG_V = VFLAG_CLEAR;
\r
6182 FLAG_C = CFLAG_CLEAR;
\r
6186 M68KMAKE_OP(move, 16, ix, a)
\r
6188 uint res = MASK_OUT_ABOVE_16(AY);
\r
6189 uint ea = EA_AX_IX_16();
\r
6191 m68ki_write_16(ea, res);
\r
6193 FLAG_N = NFLAG_16(res);
\r
6195 FLAG_V = VFLAG_CLEAR;
\r
6196 FLAG_C = CFLAG_CLEAR;
\r
6200 M68KMAKE_OP(move, 16, ix, .)
\r
6202 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6203 uint ea = EA_AX_IX_16();
\r
6205 m68ki_write_16(ea, res);
\r
6207 FLAG_N = NFLAG_16(res);
\r
6209 FLAG_V = VFLAG_CLEAR;
\r
6210 FLAG_C = CFLAG_CLEAR;
\r
6214 M68KMAKE_OP(move, 16, aw, d)
\r
6216 uint res = MASK_OUT_ABOVE_16(DY);
\r
6217 uint ea = EA_AW_16();
\r
6219 m68ki_write_16(ea, res);
\r
6221 FLAG_N = NFLAG_16(res);
\r
6223 FLAG_V = VFLAG_CLEAR;
\r
6224 FLAG_C = CFLAG_CLEAR;
\r
6228 M68KMAKE_OP(move, 16, aw, a)
\r
6230 uint res = MASK_OUT_ABOVE_16(AY);
\r
6231 uint ea = EA_AW_16();
\r
6233 m68ki_write_16(ea, res);
\r
6235 FLAG_N = NFLAG_16(res);
\r
6237 FLAG_V = VFLAG_CLEAR;
\r
6238 FLAG_C = CFLAG_CLEAR;
\r
6242 M68KMAKE_OP(move, 16, aw, .)
\r
6244 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6245 uint ea = EA_AW_16();
\r
6247 m68ki_write_16(ea, res);
\r
6249 FLAG_N = NFLAG_16(res);
\r
6251 FLAG_V = VFLAG_CLEAR;
\r
6252 FLAG_C = CFLAG_CLEAR;
\r
6256 M68KMAKE_OP(move, 16, al, d)
\r
6258 uint res = MASK_OUT_ABOVE_16(DY);
\r
6259 uint ea = EA_AL_16();
\r
6261 m68ki_write_16(ea, res);
\r
6263 FLAG_N = NFLAG_16(res);
\r
6265 FLAG_V = VFLAG_CLEAR;
\r
6266 FLAG_C = CFLAG_CLEAR;
\r
6270 M68KMAKE_OP(move, 16, al, a)
\r
6272 uint res = MASK_OUT_ABOVE_16(AY);
\r
6273 uint ea = EA_AL_16();
\r
6275 m68ki_write_16(ea, res);
\r
6277 FLAG_N = NFLAG_16(res);
\r
6279 FLAG_V = VFLAG_CLEAR;
\r
6280 FLAG_C = CFLAG_CLEAR;
\r
6284 M68KMAKE_OP(move, 16, al, .)
\r
6286 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6287 uint ea = EA_AL_16();
\r
6289 m68ki_write_16(ea, res);
\r
6291 FLAG_N = NFLAG_16(res);
\r
6293 FLAG_V = VFLAG_CLEAR;
\r
6294 FLAG_C = CFLAG_CLEAR;
\r
6298 M68KMAKE_OP(move, 32, d, d)
\r
6301 uint* r_dst = &DX;
\r
6305 FLAG_N = NFLAG_32(res);
\r
6307 FLAG_V = VFLAG_CLEAR;
\r
6308 FLAG_C = CFLAG_CLEAR;
\r
6312 M68KMAKE_OP(move, 32, d, a)
\r
6315 uint* r_dst = &DX;
\r
6319 FLAG_N = NFLAG_32(res);
\r
6321 FLAG_V = VFLAG_CLEAR;
\r
6322 FLAG_C = CFLAG_CLEAR;
\r
6326 M68KMAKE_OP(move, 32, d, .)
\r
6328 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6329 uint* r_dst = &DX;
\r
6333 FLAG_N = NFLAG_32(res);
\r
6335 FLAG_V = VFLAG_CLEAR;
\r
6336 FLAG_C = CFLAG_CLEAR;
\r
6340 M68KMAKE_OP(move, 32, ai, d)
\r
6343 uint ea = EA_AX_AI_32();
\r
6345 m68ki_write_32(ea, res);
\r
6347 FLAG_N = NFLAG_32(res);
\r
6349 FLAG_V = VFLAG_CLEAR;
\r
6350 FLAG_C = CFLAG_CLEAR;
\r
6354 M68KMAKE_OP(move, 32, ai, a)
\r
6357 uint ea = EA_AX_AI_32();
\r
6359 m68ki_write_32(ea, res);
\r
6361 FLAG_N = NFLAG_32(res);
\r
6363 FLAG_V = VFLAG_CLEAR;
\r
6364 FLAG_C = CFLAG_CLEAR;
\r
6368 M68KMAKE_OP(move, 32, ai, .)
\r
6370 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6371 uint ea = EA_AX_AI_32();
\r
6373 m68ki_write_32(ea, res);
\r
6375 FLAG_N = NFLAG_32(res);
\r
6377 FLAG_V = VFLAG_CLEAR;
\r
6378 FLAG_C = CFLAG_CLEAR;
\r
6382 M68KMAKE_OP(move, 32, pi, d)
\r
6385 uint ea = EA_AX_PI_32();
\r
6387 m68ki_write_32(ea, res);
\r
6389 FLAG_N = NFLAG_32(res);
\r
6391 FLAG_V = VFLAG_CLEAR;
\r
6392 FLAG_C = CFLAG_CLEAR;
\r
6396 M68KMAKE_OP(move, 32, pi, a)
\r
6399 uint ea = EA_AX_PI_32();
\r
6401 m68ki_write_32(ea, res);
\r
6403 FLAG_N = NFLAG_32(res);
\r
6405 FLAG_V = VFLAG_CLEAR;
\r
6406 FLAG_C = CFLAG_CLEAR;
\r
6410 M68KMAKE_OP(move, 32, pi, .)
\r
6412 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6413 uint ea = EA_AX_PI_32();
\r
6415 m68ki_write_32(ea, res);
\r
6417 FLAG_N = NFLAG_32(res);
\r
6419 FLAG_V = VFLAG_CLEAR;
\r
6420 FLAG_C = CFLAG_CLEAR;
\r
6424 M68KMAKE_OP(move, 32, pd, d)
\r
6427 uint ea = EA_AX_PD_32();
\r
6429 m68ki_write_32(ea, res);
\r
6431 FLAG_N = NFLAG_32(res);
\r
6433 FLAG_V = VFLAG_CLEAR;
\r
6434 FLAG_C = CFLAG_CLEAR;
\r
6438 M68KMAKE_OP(move, 32, pd, a)
\r
6441 uint ea = EA_AX_PD_32();
\r
6443 m68ki_write_32(ea, res);
\r
6445 FLAG_N = NFLAG_32(res);
\r
6447 FLAG_V = VFLAG_CLEAR;
\r
6448 FLAG_C = CFLAG_CLEAR;
\r
6452 M68KMAKE_OP(move, 32, pd, .)
\r
6454 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6455 uint ea = EA_AX_PD_32();
\r
6457 m68ki_write_32(ea, res);
\r
6459 FLAG_N = NFLAG_32(res);
\r
6461 FLAG_V = VFLAG_CLEAR;
\r
6462 FLAG_C = CFLAG_CLEAR;
\r
6466 M68KMAKE_OP(move, 32, di, d)
\r
6469 uint ea = EA_AX_DI_32();
\r
6471 m68ki_write_32(ea, res);
\r
6473 FLAG_N = NFLAG_32(res);
\r
6475 FLAG_V = VFLAG_CLEAR;
\r
6476 FLAG_C = CFLAG_CLEAR;
\r
6480 M68KMAKE_OP(move, 32, di, a)
\r
6483 uint ea = EA_AX_DI_32();
\r
6485 m68ki_write_32(ea, res);
\r
6487 FLAG_N = NFLAG_32(res);
\r
6489 FLAG_V = VFLAG_CLEAR;
\r
6490 FLAG_C = CFLAG_CLEAR;
\r
6494 M68KMAKE_OP(move, 32, di, .)
\r
6496 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6497 uint ea = EA_AX_DI_32();
\r
6499 m68ki_write_32(ea, res);
\r
6501 FLAG_N = NFLAG_32(res);
\r
6503 FLAG_V = VFLAG_CLEAR;
\r
6504 FLAG_C = CFLAG_CLEAR;
\r
6508 M68KMAKE_OP(move, 32, ix, d)
\r
6511 uint ea = EA_AX_IX_32();
\r
6513 m68ki_write_32(ea, res);
\r
6515 FLAG_N = NFLAG_32(res);
\r
6517 FLAG_V = VFLAG_CLEAR;
\r
6518 FLAG_C = CFLAG_CLEAR;
\r
6522 M68KMAKE_OP(move, 32, ix, a)
\r
6525 uint ea = EA_AX_IX_32();
\r
6527 m68ki_write_32(ea, res);
\r
6529 FLAG_N = NFLAG_32(res);
\r
6531 FLAG_V = VFLAG_CLEAR;
\r
6532 FLAG_C = CFLAG_CLEAR;
\r
6536 M68KMAKE_OP(move, 32, ix, .)
\r
6538 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6539 uint ea = EA_AX_IX_32();
\r
6541 m68ki_write_32(ea, res);
\r
6543 FLAG_N = NFLAG_32(res);
\r
6545 FLAG_V = VFLAG_CLEAR;
\r
6546 FLAG_C = CFLAG_CLEAR;
\r
6550 M68KMAKE_OP(move, 32, aw, d)
\r
6553 uint ea = EA_AW_32();
\r
6555 m68ki_write_32(ea, res);
\r
6557 FLAG_N = NFLAG_32(res);
\r
6559 FLAG_V = VFLAG_CLEAR;
\r
6560 FLAG_C = CFLAG_CLEAR;
\r
6564 M68KMAKE_OP(move, 32, aw, a)
\r
6567 uint ea = EA_AW_32();
\r
6569 m68ki_write_32(ea, res);
\r
6571 FLAG_N = NFLAG_32(res);
\r
6573 FLAG_V = VFLAG_CLEAR;
\r
6574 FLAG_C = CFLAG_CLEAR;
\r
6578 M68KMAKE_OP(move, 32, aw, .)
\r
6580 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6581 uint ea = EA_AW_32();
\r
6583 m68ki_write_32(ea, res);
\r
6585 FLAG_N = NFLAG_32(res);
\r
6587 FLAG_V = VFLAG_CLEAR;
\r
6588 FLAG_C = CFLAG_CLEAR;
\r
6592 M68KMAKE_OP(move, 32, al, d)
\r
6595 uint ea = EA_AL_32();
\r
6597 m68ki_write_32(ea, res);
\r
6599 FLAG_N = NFLAG_32(res);
\r
6601 FLAG_V = VFLAG_CLEAR;
\r
6602 FLAG_C = CFLAG_CLEAR;
\r
6606 M68KMAKE_OP(move, 32, al, a)
\r
6609 uint ea = EA_AL_32();
\r
6611 m68ki_write_32(ea, res);
\r
6613 FLAG_N = NFLAG_32(res);
\r
6615 FLAG_V = VFLAG_CLEAR;
\r
6616 FLAG_C = CFLAG_CLEAR;
\r
6620 M68KMAKE_OP(move, 32, al, .)
\r
6622 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6623 uint ea = EA_AL_32();
\r
6625 m68ki_write_32(ea, res);
\r
6627 FLAG_N = NFLAG_32(res);
\r
6629 FLAG_V = VFLAG_CLEAR;
\r
6630 FLAG_C = CFLAG_CLEAR;
\r
6634 M68KMAKE_OP(movea, 16, ., d)
\r
6636 AX = MAKE_INT_16(DY);
\r
6640 M68KMAKE_OP(movea, 16, ., a)
\r
6642 AX = MAKE_INT_16(AY);
\r
6646 M68KMAKE_OP(movea, 16, ., .)
\r
6648 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
6652 M68KMAKE_OP(movea, 32, ., d)
\r
6658 M68KMAKE_OP(movea, 32, ., a)
\r
6664 M68KMAKE_OP(movea, 32, ., .)
\r
6666 AX = M68KMAKE_GET_OPER_AY_32;
\r
6670 M68KMAKE_OP(move, 16, frc, d)
\r
6672 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6674 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
\r
6677 m68ki_exception_illegal();
\r
6681 M68KMAKE_OP(move, 16, frc, .)
\r
6683 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6685 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
\r
6688 m68ki_exception_illegal();
\r
6692 M68KMAKE_OP(move, 16, toc, d)
\r
6694 m68ki_set_ccr(DY);
\r
6698 M68KMAKE_OP(move, 16, toc, .)
\r
6700 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
\r
6704 M68KMAKE_OP(move, 16, frs, d)
\r
6706 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
\r
6708 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
\r
6711 m68ki_exception_privilege_violation();
\r
6715 M68KMAKE_OP(move, 16, frs, .)
\r
6717 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
\r
6719 uint ea = M68KMAKE_GET_EA_AY_16;
\r
6720 m68ki_write_16(ea, m68ki_get_sr());
\r
6723 m68ki_exception_privilege_violation();
\r
6727 M68KMAKE_OP(move, 16, tos, d)
\r
6734 m68ki_exception_privilege_violation();
\r
6738 M68KMAKE_OP(move, 16, tos, .)
\r
6742 uint new_sr = M68KMAKE_GET_OPER_AY_16;
\r
6743 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6744 m68ki_set_sr(new_sr);
\r
6747 m68ki_exception_privilege_violation();
\r
6751 M68KMAKE_OP(move, 32, fru, .)
\r
6758 m68ki_exception_privilege_violation();
\r
6762 M68KMAKE_OP(move, 32, tou, .)
\r
6766 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6770 m68ki_exception_privilege_violation();
\r
6774 M68KMAKE_OP(movec, 32, cr, .)
\r
6776 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6780 uint word2 = OPER_I_16();
\r
6782 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6783 switch (word2 & 0xfff)
\r
6785 case 0x000: /* SFC */
\r
6786 REG_DA[(word2 >> 12) & 15] = REG_SFC;
\r
6788 case 0x001: /* DFC */
\r
6789 REG_DA[(word2 >> 12) & 15] = REG_DFC;
\r
6791 case 0x002: /* CACR */
\r
6792 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6794 REG_DA[(word2 >> 12) & 15] = REG_CACR;
\r
6798 case 0x800: /* USP */
\r
6799 REG_DA[(word2 >> 12) & 15] = REG_USP;
\r
6801 case 0x801: /* VBR */
\r
6802 REG_DA[(word2 >> 12) & 15] = REG_VBR;
\r
6804 case 0x802: /* CAAR */
\r
6805 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6807 REG_DA[(word2 >> 12) & 15] = REG_CAAR;
\r
6810 m68ki_exception_illegal();
\r
6812 case 0x803: /* MSP */
\r
6813 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6815 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
\r
6818 m68ki_exception_illegal();
\r
6820 case 0x804: /* ISP */
\r
6821 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6823 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
\r
6826 m68ki_exception_illegal();
\r
6828 case 0x003: /* TC */
\r
6829 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6834 m68ki_exception_illegal();
\r
6836 case 0x004: /* ITT0 */
\r
6837 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6842 m68ki_exception_illegal();
\r
6844 case 0x005: /* ITT1 */
\r
6845 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6850 m68ki_exception_illegal();
\r
6852 case 0x006: /* DTT0 */
\r
6853 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6858 m68ki_exception_illegal();
\r
6860 case 0x007: /* DTT1 */
\r
6861 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6866 m68ki_exception_illegal();
\r
6868 case 0x805: /* MMUSR */
\r
6869 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6874 m68ki_exception_illegal();
\r
6876 case 0x806: /* URP */
\r
6877 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6882 m68ki_exception_illegal();
\r
6884 case 0x807: /* SRP */
\r
6885 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6890 m68ki_exception_illegal();
\r
6893 m68ki_exception_illegal();
\r
6897 m68ki_exception_privilege_violation();
\r
6900 m68ki_exception_illegal();
\r
6904 M68KMAKE_OP(movec, 32, rc, .)
\r
6906 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6910 uint word2 = OPER_I_16();
\r
6912 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6913 switch (word2 & 0xfff)
\r
6915 case 0x000: /* SFC */
\r
6916 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
\r
6918 case 0x001: /* DFC */
\r
6919 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
\r
6921 case 0x002: /* CACR */
\r
6922 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6924 REG_CACR = REG_DA[(word2 >> 12) & 15];
\r
6927 m68ki_exception_illegal();
\r
6929 case 0x800: /* USP */
\r
6930 REG_USP = REG_DA[(word2 >> 12) & 15];
\r
6932 case 0x801: /* VBR */
\r
6933 REG_VBR = REG_DA[(word2 >> 12) & 15];
\r
6935 case 0x802: /* CAAR */
\r
6936 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6938 REG_CAAR = REG_DA[(word2 >> 12) & 15];
\r
6941 m68ki_exception_illegal();
\r
6943 case 0x803: /* MSP */
\r
6944 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6946 /* we are in supervisor mode so just check for M flag */
\r
6949 REG_MSP = REG_DA[(word2 >> 12) & 15];
\r
6952 REG_SP = REG_DA[(word2 >> 12) & 15];
\r
6955 m68ki_exception_illegal();
\r
6957 case 0x804: /* ISP */
\r
6958 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6962 REG_SP = REG_DA[(word2 >> 12) & 15];
\r
6965 REG_ISP = REG_DA[(word2 >> 12) & 15];
\r
6968 m68ki_exception_illegal();
\r
6970 case 0x003: /* TC */
\r
6971 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6976 m68ki_exception_illegal();
\r
6978 case 0x004: /* ITT0 */
\r
6979 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6984 m68ki_exception_illegal();
\r
6986 case 0x005: /* ITT1 */
\r
6987 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6992 m68ki_exception_illegal();
\r
6994 case 0x006: /* DTT0 */
\r
6995 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7000 m68ki_exception_illegal();
\r
7002 case 0x007: /* DTT1 */
\r
7003 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7008 m68ki_exception_illegal();
\r
7010 case 0x805: /* MMUSR */
\r
7011 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7016 m68ki_exception_illegal();
\r
7018 case 0x806: /* URP */
\r
7019 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7024 m68ki_exception_illegal();
\r
7026 case 0x807: /* SRP */
\r
7027 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7032 m68ki_exception_illegal();
\r
7035 m68ki_exception_illegal();
\r
7039 m68ki_exception_privilege_violation();
\r
7042 m68ki_exception_illegal();
\r
7046 M68KMAKE_OP(movem, 16, re, pd)
\r
7049 uint register_list = OPER_I_16();
\r
7053 for(; i < 16; i++)
\r
7054 if(register_list & (1 << i))
\r
7057 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
\r
7062 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7066 M68KMAKE_OP(movem, 16, re, .)
\r
7069 uint register_list = OPER_I_16();
\r
7070 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7073 for(; i < 16; i++)
\r
7074 if(register_list & (1 << i))
\r
7076 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
\r
7081 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7085 M68KMAKE_OP(movem, 32, re, pd)
\r
7088 uint register_list = OPER_I_16();
\r
7092 for(; i < 16; i++)
\r
7093 if(register_list & (1 << i))
\r
7096 m68ki_write_32(ea, REG_DA[15-i]);
\r
7101 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7105 M68KMAKE_OP(movem, 32, re, .)
\r
7108 uint register_list = OPER_I_16();
\r
7109 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7112 for(; i < 16; i++)
\r
7113 if(register_list & (1 << i))
\r
7115 m68ki_write_32(ea, REG_DA[i]);
\r
7120 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7124 M68KMAKE_OP(movem, 16, er, pi)
\r
7127 uint register_list = OPER_I_16();
\r
7131 for(; i < 16; i++)
\r
7132 if(register_list & (1 << i))
\r
7134 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
\r
7140 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7144 M68KMAKE_OP(movem, 16, er, pcdi)
\r
7147 uint register_list = OPER_I_16();
\r
7148 uint ea = EA_PCDI_16();
\r
7151 for(; i < 16; i++)
\r
7152 if(register_list & (1 << i))
\r
7154 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
\r
7159 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7163 M68KMAKE_OP(movem, 16, er, pcix)
\r
7166 uint register_list = OPER_I_16();
\r
7167 uint ea = EA_PCIX_16();
\r
7170 for(; i < 16; i++)
\r
7171 if(register_list & (1 << i))
\r
7173 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
\r
7178 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7182 M68KMAKE_OP(movem, 16, er, .)
\r
7185 uint register_list = OPER_I_16();
\r
7186 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7189 for(; i < 16; i++)
\r
7190 if(register_list & (1 << i))
\r
7192 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
\r
7197 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7201 M68KMAKE_OP(movem, 32, er, pi)
\r
7204 uint register_list = OPER_I_16();
\r
7208 for(; i < 16; i++)
\r
7209 if(register_list & (1 << i))
\r
7211 REG_DA[i] = m68ki_read_32(ea);
\r
7217 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7221 M68KMAKE_OP(movem, 32, er, pcdi)
\r
7224 uint register_list = OPER_I_16();
\r
7225 uint ea = EA_PCDI_32();
\r
7228 for(; i < 16; i++)
\r
7229 if(register_list & (1 << i))
\r
7231 REG_DA[i] = m68ki_read_pcrel_32(ea);
\r
7236 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7240 M68KMAKE_OP(movem, 32, er, pcix)
\r
7243 uint register_list = OPER_I_16();
\r
7244 uint ea = EA_PCIX_32();
\r
7247 for(; i < 16; i++)
\r
7248 if(register_list & (1 << i))
\r
7250 REG_DA[i] = m68ki_read_pcrel_32(ea);
\r
7255 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7259 M68KMAKE_OP(movem, 32, er, .)
\r
7262 uint register_list = OPER_I_16();
\r
7263 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7266 for(; i < 16; i++)
\r
7267 if(register_list & (1 << i))
\r
7269 REG_DA[i] = m68ki_read_32(ea);
\r
7274 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7278 M68KMAKE_OP(movep, 16, re, .)
\r
7280 uint ea = EA_AY_DI_16();
\r
7283 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
\r
7284 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
\r
7288 M68KMAKE_OP(movep, 32, re, .)
\r
7290 uint ea = EA_AY_DI_32();
\r
7293 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
\r
7294 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
\r
7295 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
\r
7296 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
\r
7300 M68KMAKE_OP(movep, 16, er, .)
\r
7302 uint ea = EA_AY_DI_16();
\r
7303 uint* r_dst = &DX;
\r
7305 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
\r
7309 M68KMAKE_OP(movep, 32, er, .)
\r
7311 uint ea = EA_AY_DI_32();
\r
7313 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
\r
7314 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
\r
7318 M68KMAKE_OP(moves, 8, ., .)
\r
7320 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7324 uint word2 = OPER_I_16();
\r
7325 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7327 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7328 if(BIT_B(word2)) /* Register to memory */
\r
7330 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
\r
7333 if(BIT_F(word2)) /* Memory to address register */
\r
7335 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
\r
7336 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7340 /* Memory to data register */
\r
7341 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
\r
7342 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7346 m68ki_exception_privilege_violation();
\r
7349 m68ki_exception_illegal();
\r
7353 M68KMAKE_OP(moves, 16, ., .)
\r
7355 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7359 uint word2 = OPER_I_16();
\r
7360 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7362 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7363 if(BIT_B(word2)) /* Register to memory */
\r
7365 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
\r
7368 if(BIT_F(word2)) /* Memory to address register */
\r
7370 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
\r
7371 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7375 /* Memory to data register */
\r
7376 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
\r
7377 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7381 m68ki_exception_privilege_violation();
\r
7384 m68ki_exception_illegal();
\r
7388 M68KMAKE_OP(moves, 32, ., .)
\r
7390 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7394 uint word2 = OPER_I_16();
\r
7395 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7397 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7398 if(BIT_B(word2)) /* Register to memory */
\r
7400 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
\r
7401 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7405 /* Memory to register */
\r
7406 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
\r
7407 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7411 m68ki_exception_privilege_violation();
\r
7414 m68ki_exception_illegal();
\r
7418 M68KMAKE_OP(moveq, 32, ., .)
\r
7420 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
\r
7422 FLAG_N = NFLAG_32(res);
\r
7424 FLAG_V = VFLAG_CLEAR;
\r
7425 FLAG_C = CFLAG_CLEAR;
\r
7429 M68KMAKE_OP(move16, 32, ., .)
\r
7431 UINT16 w2 = OPER_I_16();
\r
7432 int ax = REG_IR & 7;
\r
7433 int ay = (w2 >> 12) & 7;
\r
7435 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));
\r
7436 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));
\r
7437 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));
\r
7438 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));
\r
7445 M68KMAKE_OP(muls, 16, ., d)
\r
7447 uint* r_dst = &DX;
\r
7448 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
\r
7453 FLAG_N = NFLAG_32(res);
\r
7454 FLAG_V = VFLAG_CLEAR;
\r
7455 FLAG_C = CFLAG_CLEAR;
\r
7459 M68KMAKE_OP(muls, 16, ., .)
\r
7461 uint* r_dst = &DX;
\r
7462 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
\r
7467 FLAG_N = NFLAG_32(res);
\r
7468 FLAG_V = VFLAG_CLEAR;
\r
7469 FLAG_C = CFLAG_CLEAR;
\r
7473 M68KMAKE_OP(mulu, 16, ., d)
\r
7475 uint* r_dst = &DX;
\r
7476 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
\r
7481 FLAG_N = NFLAG_32(res);
\r
7482 FLAG_V = VFLAG_CLEAR;
\r
7483 FLAG_C = CFLAG_CLEAR;
\r
7487 M68KMAKE_OP(mulu, 16, ., .)
\r
7489 uint* r_dst = &DX;
\r
7490 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
\r
7495 FLAG_N = NFLAG_32(res);
\r
7496 FLAG_V = VFLAG_CLEAR;
\r
7497 FLAG_C = CFLAG_CLEAR;
\r
7501 M68KMAKE_OP(mull, 32, ., d)
\r
7503 #if M68K_USE_64_BIT
\r
7505 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7507 uint word2 = OPER_I_16();
\r
7509 uint64 dst = REG_D[(word2 >> 12) & 7];
\r
7512 FLAG_C = CFLAG_CLEAR;
\r
7514 if(BIT_B(word2)) /* signed */
\r
7516 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
\r
7519 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7520 FLAG_N = NFLAG_32(res);
\r
7521 FLAG_V = ((sint64)res != (sint32)res)<<7;
\r
7522 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7525 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7526 FLAG_N = NFLAG_64(res);
\r
7527 FLAG_V = VFLAG_CLEAR;
\r
7528 REG_D[word2 & 7] = (res >> 32);
\r
7529 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7536 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7537 FLAG_N = NFLAG_32(res);
\r
7538 FLAG_V = (res > 0xffffffff)<<7;
\r
7539 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7542 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7543 FLAG_N = NFLAG_64(res);
\r
7544 FLAG_V = VFLAG_CLEAR;
\r
7545 REG_D[word2 & 7] = (res >> 32);
\r
7546 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7549 m68ki_exception_illegal();
\r
7553 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7555 uint word2 = OPER_I_16();
\r
7557 uint dst = REG_D[(word2 >> 12) & 7];
\r
7558 uint neg = GET_MSB_32(src ^ dst);
\r
7570 FLAG_C = CFLAG_CLEAR;
\r
7572 if(BIT_B(word2)) /* signed */
\r
7574 if(GET_MSB_32(src))
\r
7575 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
\r
7576 if(GET_MSB_32(dst))
\r
7577 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
\r
7580 src1 = MASK_OUT_ABOVE_16(src);
\r
7582 dst1 = MASK_OUT_ABOVE_16(dst);
\r
7591 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
\r
7592 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
\r
7594 if(BIT_B(word2) && neg)
\r
7596 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
\r
7597 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
\r
7602 REG_D[word2 & 7] = hi;
\r
7603 REG_D[(word2 >> 12) & 7] = lo;
\r
7604 FLAG_N = NFLAG_32(hi);
\r
7606 FLAG_V = VFLAG_CLEAR;
\r
7610 REG_D[(word2 >> 12) & 7] = lo;
\r
7611 FLAG_N = NFLAG_32(lo);
\r
7614 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
\r
7616 FLAG_V = (hi != 0) << 7;
\r
7619 m68ki_exception_illegal();
\r
7625 M68KMAKE_OP(mull, 32, ., .)
\r
7627 #if M68K_USE_64_BIT
\r
7629 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7631 uint word2 = OPER_I_16();
\r
7632 uint64 src = M68KMAKE_GET_OPER_AY_32;
\r
7633 uint64 dst = REG_D[(word2 >> 12) & 7];
\r
7636 FLAG_C = CFLAG_CLEAR;
\r
7638 if(BIT_B(word2)) /* signed */
\r
7640 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
\r
7643 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7644 FLAG_N = NFLAG_32(res);
\r
7645 FLAG_V = ((sint64)res != (sint32)res)<<7;
\r
7646 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7649 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7650 FLAG_N = NFLAG_64(res);
\r
7651 FLAG_V = VFLAG_CLEAR;
\r
7652 REG_D[word2 & 7] = (res >> 32);
\r
7653 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7660 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7661 FLAG_N = NFLAG_32(res);
\r
7662 FLAG_V = (res > 0xffffffff)<<7;
\r
7663 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7666 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7667 FLAG_N = NFLAG_64(res);
\r
7668 FLAG_V = VFLAG_CLEAR;
\r
7669 REG_D[word2 & 7] = (res >> 32);
\r
7670 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7673 m68ki_exception_illegal();
\r
7677 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7679 uint word2 = OPER_I_16();
\r
7680 uint src = M68KMAKE_GET_OPER_AY_32;
\r
7681 uint dst = REG_D[(word2 >> 12) & 7];
\r
7682 uint neg = GET_MSB_32(src ^ dst);
\r
7694 FLAG_C = CFLAG_CLEAR;
\r
7696 if(BIT_B(word2)) /* signed */
\r
7698 if(GET_MSB_32(src))
\r
7699 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
\r
7700 if(GET_MSB_32(dst))
\r
7701 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
\r
7704 src1 = MASK_OUT_ABOVE_16(src);
\r
7706 dst1 = MASK_OUT_ABOVE_16(dst);
\r
7715 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
\r
7716 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
\r
7718 if(BIT_B(word2) && neg)
\r
7720 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
\r
7721 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
\r
7726 REG_D[word2 & 7] = hi;
\r
7727 REG_D[(word2 >> 12) & 7] = lo;
\r
7728 FLAG_N = NFLAG_32(hi);
\r
7730 FLAG_V = VFLAG_CLEAR;
\r
7734 REG_D[(word2 >> 12) & 7] = lo;
\r
7735 FLAG_N = NFLAG_32(lo);
\r
7738 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
\r
7740 FLAG_V = (hi != 0) << 7;
\r
7743 m68ki_exception_illegal();
\r
7749 M68KMAKE_OP(nbcd, 8, ., d)
\r
7751 uint* r_dst = &DY;
\r
7752 uint dst = *r_dst;
\r
7753 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
\r
7757 FLAG_V = ~res; /* Undefined V behavior */
\r
7759 if((res & 0x0f) == 0xa)
\r
7760 res = (res & 0xf0) + 0x10;
\r
7762 res = MASK_OUT_ABOVE_8(res);
\r
7764 FLAG_V &= res; /* Undefined V behavior part II */
\r
7766 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7769 FLAG_C = CFLAG_SET;
\r
7770 FLAG_X = XFLAG_SET;
\r
7774 FLAG_V = VFLAG_CLEAR;
\r
7775 FLAG_C = CFLAG_CLEAR;
\r
7776 FLAG_X = XFLAG_CLEAR;
\r
7778 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
7782 M68KMAKE_OP(nbcd, 8, ., .)
\r
7784 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7785 uint dst = m68ki_read_8(ea);
\r
7786 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
\r
7790 FLAG_V = ~res; /* Undefined V behavior */
\r
7792 if((res & 0x0f) == 0xa)
\r
7793 res = (res & 0xf0) + 0x10;
\r
7795 res = MASK_OUT_ABOVE_8(res);
\r
7797 FLAG_V &= res; /* Undefined V behavior part II */
\r
7799 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
\r
7802 FLAG_C = CFLAG_SET;
\r
7803 FLAG_X = XFLAG_SET;
\r
7807 FLAG_V = VFLAG_CLEAR;
\r
7808 FLAG_C = CFLAG_CLEAR;
\r
7809 FLAG_X = XFLAG_CLEAR;
\r
7811 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
7815 M68KMAKE_OP(neg, 8, ., d)
\r
7817 uint* r_dst = &DY;
\r
7818 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
\r
7820 FLAG_N = NFLAG_8(res);
\r
7821 FLAG_C = FLAG_X = CFLAG_8(res);
\r
7822 FLAG_V = *r_dst & res;
\r
7823 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
7825 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
7829 M68KMAKE_OP(neg, 8, ., .)
\r
7831 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7832 uint src = m68ki_read_8(ea);
\r
7833 uint res = 0 - src;
\r
7835 FLAG_N = NFLAG_8(res);
\r
7836 FLAG_C = FLAG_X = CFLAG_8(res);
\r
7837 FLAG_V = src & res;
\r
7838 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
7840 m68ki_write_8(ea, FLAG_Z);
\r
7844 M68KMAKE_OP(neg, 16, ., d)
\r
7846 uint* r_dst = &DY;
\r
7847 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
\r
7849 FLAG_N = NFLAG_16(res);
\r
7850 FLAG_C = FLAG_X = CFLAG_16(res);
\r
7851 FLAG_V = (*r_dst & res)>>8;
\r
7852 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
7854 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
7858 M68KMAKE_OP(neg, 16, ., .)
\r
7860 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7861 uint src = m68ki_read_16(ea);
\r
7862 uint res = 0 - src;
\r
7864 FLAG_N = NFLAG_16(res);
\r
7865 FLAG_C = FLAG_X = CFLAG_16(res);
\r
7866 FLAG_V = (src & res)>>8;
\r
7867 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
7869 m68ki_write_16(ea, FLAG_Z);
\r
7873 M68KMAKE_OP(neg, 32, ., d)
\r
7875 uint* r_dst = &DY;
\r
7876 uint res = 0 - *r_dst;
\r
7878 FLAG_N = NFLAG_32(res);
\r
7879 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
\r
7880 FLAG_V = (*r_dst & res)>>24;
\r
7881 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7887 M68KMAKE_OP(neg, 32, ., .)
\r
7889 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7890 uint src = m68ki_read_32(ea);
\r
7891 uint res = 0 - src;
\r
7893 FLAG_N = NFLAG_32(res);
\r
7894 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
\r
7895 FLAG_V = (src & res)>>24;
\r
7896 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7898 m68ki_write_32(ea, FLAG_Z);
\r
7902 M68KMAKE_OP(negx, 8, ., d)
\r
7904 uint* r_dst = &DY;
\r
7905 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
\r
7907 FLAG_N = NFLAG_8(res);
\r
7908 FLAG_X = FLAG_C = CFLAG_8(res);
\r
7909 FLAG_V = *r_dst & res;
\r
7911 res = MASK_OUT_ABOVE_8(res);
\r
7914 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7918 M68KMAKE_OP(negx, 8, ., .)
\r
7920 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7921 uint src = m68ki_read_8(ea);
\r
7922 uint res = 0 - src - XFLAG_AS_1();
\r
7924 FLAG_N = NFLAG_8(res);
\r
7925 FLAG_X = FLAG_C = CFLAG_8(res);
\r
7926 FLAG_V = src & res;
\r
7928 res = MASK_OUT_ABOVE_8(res);
\r
7931 m68ki_write_8(ea, res);
\r
7935 M68KMAKE_OP(negx, 16, ., d)
\r
7937 uint* r_dst = &DY;
\r
7938 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
\r
7940 FLAG_N = NFLAG_16(res);
\r
7941 FLAG_X = FLAG_C = CFLAG_16(res);
\r
7942 FLAG_V = (*r_dst & res)>>8;
\r
7944 res = MASK_OUT_ABOVE_16(res);
\r
7947 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
7951 M68KMAKE_OP(negx, 16, ., .)
\r
7953 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7954 uint src = m68ki_read_16(ea);
\r
7955 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
\r
7957 FLAG_N = NFLAG_16(res);
\r
7958 FLAG_X = FLAG_C = CFLAG_16(res);
\r
7959 FLAG_V = (src & res)>>8;
\r
7961 res = MASK_OUT_ABOVE_16(res);
\r
7964 m68ki_write_16(ea, res);
\r
7968 M68KMAKE_OP(negx, 32, ., d)
\r
7970 uint* r_dst = &DY;
\r
7971 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
\r
7973 FLAG_N = NFLAG_32(res);
\r
7974 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
\r
7975 FLAG_V = (*r_dst & res)>>24;
\r
7977 res = MASK_OUT_ABOVE_32(res);
\r
7984 M68KMAKE_OP(negx, 32, ., .)
\r
7986 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7987 uint src = m68ki_read_32(ea);
\r
7988 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
\r
7990 FLAG_N = NFLAG_32(res);
\r
7991 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
\r
7992 FLAG_V = (src & res)>>24;
\r
7994 res = MASK_OUT_ABOVE_32(res);
\r
7997 m68ki_write_32(ea, res);
\r
8001 M68KMAKE_OP(nop, 0, ., .)
\r
8003 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8007 M68KMAKE_OP(not, 8, ., d)
\r
8009 uint* r_dst = &DY;
\r
8010 uint res = MASK_OUT_ABOVE_8(~*r_dst);
\r
8012 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8014 FLAG_N = NFLAG_8(res);
\r
8016 FLAG_C = CFLAG_CLEAR;
\r
8017 FLAG_V = VFLAG_CLEAR;
\r
8021 M68KMAKE_OP(not, 8, ., .)
\r
8023 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8024 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
\r
8026 m68ki_write_8(ea, res);
\r
8028 FLAG_N = NFLAG_8(res);
\r
8030 FLAG_C = CFLAG_CLEAR;
\r
8031 FLAG_V = VFLAG_CLEAR;
\r
8035 M68KMAKE_OP(not, 16, ., d)
\r
8037 uint* r_dst = &DY;
\r
8038 uint res = MASK_OUT_ABOVE_16(~*r_dst);
\r
8040 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8042 FLAG_N = NFLAG_16(res);
\r
8044 FLAG_C = CFLAG_CLEAR;
\r
8045 FLAG_V = VFLAG_CLEAR;
\r
8049 M68KMAKE_OP(not, 16, ., .)
\r
8051 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8052 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
\r
8054 m68ki_write_16(ea, res);
\r
8056 FLAG_N = NFLAG_16(res);
\r
8058 FLAG_C = CFLAG_CLEAR;
\r
8059 FLAG_V = VFLAG_CLEAR;
\r
8063 M68KMAKE_OP(not, 32, ., d)
\r
8065 uint* r_dst = &DY;
\r
8066 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
\r
8068 FLAG_N = NFLAG_32(res);
\r
8070 FLAG_C = CFLAG_CLEAR;
\r
8071 FLAG_V = VFLAG_CLEAR;
\r
8075 M68KMAKE_OP(not, 32, ., .)
\r
8077 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8078 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
\r
8080 m68ki_write_32(ea, res);
\r
8082 FLAG_N = NFLAG_32(res);
\r
8084 FLAG_C = CFLAG_CLEAR;
\r
8085 FLAG_V = VFLAG_CLEAR;
\r
8089 M68KMAKE_OP(or, 8, er, d)
\r
8091 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
\r
8093 FLAG_N = NFLAG_8(res);
\r
8095 FLAG_C = CFLAG_CLEAR;
\r
8096 FLAG_V = VFLAG_CLEAR;
\r
8100 M68KMAKE_OP(or, 8, er, .)
\r
8102 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
\r
8104 FLAG_N = NFLAG_8(res);
\r
8106 FLAG_C = CFLAG_CLEAR;
\r
8107 FLAG_V = VFLAG_CLEAR;
\r
8111 M68KMAKE_OP(or, 16, er, d)
\r
8113 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
\r
8115 FLAG_N = NFLAG_16(res);
\r
8117 FLAG_C = CFLAG_CLEAR;
\r
8118 FLAG_V = VFLAG_CLEAR;
\r
8122 M68KMAKE_OP(or, 16, er, .)
\r
8124 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
\r
8126 FLAG_N = NFLAG_16(res);
\r
8128 FLAG_C = CFLAG_CLEAR;
\r
8129 FLAG_V = VFLAG_CLEAR;
\r
8133 M68KMAKE_OP(or, 32, er, d)
\r
8135 uint res = DX |= DY;
\r
8137 FLAG_N = NFLAG_32(res);
\r
8139 FLAG_C = CFLAG_CLEAR;
\r
8140 FLAG_V = VFLAG_CLEAR;
\r
8144 M68KMAKE_OP(or, 32, er, .)
\r
8146 uint res = DX |= M68KMAKE_GET_OPER_AY_32;
\r
8148 FLAG_N = NFLAG_32(res);
\r
8150 FLAG_C = CFLAG_CLEAR;
\r
8151 FLAG_V = VFLAG_CLEAR;
\r
8155 M68KMAKE_OP(or, 8, re, .)
\r
8157 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8158 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
\r
8160 m68ki_write_8(ea, res);
\r
8162 FLAG_N = NFLAG_8(res);
\r
8164 FLAG_C = CFLAG_CLEAR;
\r
8165 FLAG_V = VFLAG_CLEAR;
\r
8169 M68KMAKE_OP(or, 16, re, .)
\r
8171 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8172 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
\r
8174 m68ki_write_16(ea, res);
\r
8176 FLAG_N = NFLAG_16(res);
\r
8178 FLAG_C = CFLAG_CLEAR;
\r
8179 FLAG_V = VFLAG_CLEAR;
\r
8183 M68KMAKE_OP(or, 32, re, .)
\r
8185 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8186 uint res = DX | m68ki_read_32(ea);
\r
8188 m68ki_write_32(ea, res);
\r
8190 FLAG_N = NFLAG_32(res);
\r
8192 FLAG_C = CFLAG_CLEAR;
\r
8193 FLAG_V = VFLAG_CLEAR;
\r
8197 M68KMAKE_OP(ori, 8, ., d)
\r
8199 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
\r
8201 FLAG_N = NFLAG_8(res);
\r
8203 FLAG_C = CFLAG_CLEAR;
\r
8204 FLAG_V = VFLAG_CLEAR;
\r
8208 M68KMAKE_OP(ori, 8, ., .)
\r
8210 uint src = OPER_I_8();
\r
8211 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8212 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
\r
8214 m68ki_write_8(ea, res);
\r
8216 FLAG_N = NFLAG_8(res);
\r
8218 FLAG_C = CFLAG_CLEAR;
\r
8219 FLAG_V = VFLAG_CLEAR;
\r
8223 M68KMAKE_OP(ori, 16, ., d)
\r
8225 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
\r
8227 FLAG_N = NFLAG_16(res);
\r
8229 FLAG_C = CFLAG_CLEAR;
\r
8230 FLAG_V = VFLAG_CLEAR;
\r
8234 M68KMAKE_OP(ori, 16, ., .)
\r
8236 uint src = OPER_I_16();
\r
8237 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8238 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
\r
8240 m68ki_write_16(ea, res);
\r
8242 FLAG_N = NFLAG_16(res);
\r
8244 FLAG_C = CFLAG_CLEAR;
\r
8245 FLAG_V = VFLAG_CLEAR;
\r
8249 M68KMAKE_OP(ori, 32, ., d)
\r
8251 uint res = DY |= OPER_I_32();
\r
8253 FLAG_N = NFLAG_32(res);
\r
8255 FLAG_C = CFLAG_CLEAR;
\r
8256 FLAG_V = VFLAG_CLEAR;
\r
8260 M68KMAKE_OP(ori, 32, ., .)
\r
8262 uint src = OPER_I_32();
\r
8263 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8264 uint res = src | m68ki_read_32(ea);
\r
8266 m68ki_write_32(ea, res);
\r
8268 FLAG_N = NFLAG_32(res);
\r
8270 FLAG_C = CFLAG_CLEAR;
\r
8271 FLAG_V = VFLAG_CLEAR;
\r
8275 M68KMAKE_OP(ori, 16, toc, .)
\r
8277 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
\r
8281 M68KMAKE_OP(ori, 16, tos, .)
\r
8285 uint src = OPER_I_16();
\r
8286 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8287 m68ki_set_sr(m68ki_get_sr() | src);
\r
8290 m68ki_exception_privilege_violation();
\r
8294 M68KMAKE_OP(pack, 16, rr, .)
\r
8296 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8298 /* Note: DX and DY are reversed in Motorola's docs */
\r
8299 uint src = DY + OPER_I_16();
\r
8300 uint* r_dst = &DX;
\r
8302 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
\r
8305 m68ki_exception_illegal();
\r
8309 M68KMAKE_OP(pack, 16, mm, ax7)
\r
8311 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8313 /* Note: AX and AY are reversed in Motorola's docs */
\r
8314 uint ea_src = EA_AY_PD_8();
\r
8315 uint src = m68ki_read_8(ea_src);
\r
8316 ea_src = EA_AY_PD_8();
\r
8317 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8319 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8322 m68ki_exception_illegal();
\r
8326 M68KMAKE_OP(pack, 16, mm, ay7)
\r
8328 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8330 /* Note: AX and AY are reversed in Motorola's docs */
\r
8331 uint ea_src = EA_A7_PD_8();
\r
8332 uint src = m68ki_read_8(ea_src);
\r
8333 ea_src = EA_A7_PD_8();
\r
8334 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8336 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8339 m68ki_exception_illegal();
\r
8343 M68KMAKE_OP(pack, 16, mm, axy7)
\r
8345 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8347 uint ea_src = EA_A7_PD_8();
\r
8348 uint src = m68ki_read_8(ea_src);
\r
8349 ea_src = EA_A7_PD_8();
\r
8350 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8352 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8355 m68ki_exception_illegal();
\r
8359 M68KMAKE_OP(pack, 16, mm, .)
\r
8361 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8363 /* Note: AX and AY are reversed in Motorola's docs */
\r
8364 uint ea_src = EA_AY_PD_8();
\r
8365 uint src = m68ki_read_8(ea_src);
\r
8366 ea_src = EA_AY_PD_8();
\r
8367 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8369 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8372 m68ki_exception_illegal();
\r
8376 M68KMAKE_OP(pea, 32, ., .)
\r
8378 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8380 m68ki_push_32(ea);
\r
8384 M68KMAKE_OP(pflush, 32, ., .)
\r
8386 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
8388 // Nothing to do, unless address translation cache is emulated
\r
8391 m68ki_exception_illegal();
\r
8395 M68KMAKE_OP(reset, 0, ., .)
\r
8399 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
\r
8400 USE_CYCLES(CYC_RESET);
\r
8403 m68ki_exception_privilege_violation();
\r
8407 M68KMAKE_OP(ror, 8, s, .)
\r
8409 uint* r_dst = &DY;
\r
8410 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8411 uint shift = orig_shift & 7;
\r
8412 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8413 uint res = ROR_8(src, shift);
\r
8415 if(orig_shift != 0)
\r
8416 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8418 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8420 FLAG_N = NFLAG_8(res);
\r
8422 FLAG_C = src << (9-orig_shift);
\r
8423 FLAG_V = VFLAG_CLEAR;
\r
8427 M68KMAKE_OP(ror, 16, s, .)
\r
8429 uint* r_dst = &DY;
\r
8430 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8431 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8432 uint res = ROR_16(src, shift);
\r
8435 USE_CYCLES(shift<<CYC_SHIFT);
\r
8437 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8439 FLAG_N = NFLAG_16(res);
\r
8441 FLAG_C = src << (9-shift);
\r
8442 FLAG_V = VFLAG_CLEAR;
\r
8446 M68KMAKE_OP(ror, 32, s, .)
\r
8448 uint* r_dst = &DY;
\r
8449 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8450 uint64 src = *r_dst;
\r
8451 uint res = ROR_32(src, shift);
\r
8454 USE_CYCLES(shift<<CYC_SHIFT);
\r
8458 FLAG_N = NFLAG_32(res);
\r
8460 FLAG_C = src << (9-shift);
\r
8461 FLAG_V = VFLAG_CLEAR;
\r
8465 M68KMAKE_OP(ror, 8, r, .)
\r
8467 uint* r_dst = &DY;
\r
8468 uint orig_shift = DX & 0x3f;
\r
8469 uint shift = orig_shift & 7;
\r
8470 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8471 uint res = ROR_8(src, shift);
\r
8473 if(orig_shift != 0)
\r
8475 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8477 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8478 FLAG_C = src << (8-((shift-1)&7));
\r
8479 FLAG_N = NFLAG_8(res);
\r
8481 FLAG_V = VFLAG_CLEAR;
\r
8485 FLAG_C = CFLAG_CLEAR;
\r
8486 FLAG_N = NFLAG_8(src);
\r
8488 FLAG_V = VFLAG_CLEAR;
\r
8492 M68KMAKE_OP(ror, 16, r, .)
\r
8494 uint* r_dst = &DY;
\r
8495 uint orig_shift = DX & 0x3f;
\r
8496 uint shift = orig_shift & 15;
\r
8497 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8498 uint res = ROR_16(src, shift);
\r
8500 if(orig_shift != 0)
\r
8502 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8504 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8505 FLAG_C = (src >> ((shift - 1) & 15)) << 8;
\r
8506 FLAG_N = NFLAG_16(res);
\r
8508 FLAG_V = VFLAG_CLEAR;
\r
8512 FLAG_C = CFLAG_CLEAR;
\r
8513 FLAG_N = NFLAG_16(src);
\r
8515 FLAG_V = VFLAG_CLEAR;
\r
8519 M68KMAKE_OP(ror, 32, r, .)
\r
8521 uint* r_dst = &DY;
\r
8522 uint orig_shift = DX & 0x3f;
\r
8523 uint shift = orig_shift & 31;
\r
8524 uint64 src = *r_dst;
\r
8525 uint res = ROR_32(src, shift);
\r
8527 if(orig_shift != 0)
\r
8529 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8532 FLAG_C = (src >> ((shift - 1) & 31)) << 8;
\r
8533 FLAG_N = NFLAG_32(res);
\r
8535 FLAG_V = VFLAG_CLEAR;
\r
8539 FLAG_C = CFLAG_CLEAR;
\r
8540 FLAG_N = NFLAG_32(src);
\r
8542 FLAG_V = VFLAG_CLEAR;
\r
8546 M68KMAKE_OP(ror, 16, ., .)
\r
8548 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8549 uint src = m68ki_read_16(ea);
\r
8550 uint res = ROR_16(src, 1);
\r
8552 m68ki_write_16(ea, res);
\r
8554 FLAG_N = NFLAG_16(res);
\r
8556 FLAG_C = src << 8;
\r
8557 FLAG_V = VFLAG_CLEAR;
\r
8561 M68KMAKE_OP(rol, 8, s, .)
\r
8563 uint* r_dst = &DY;
\r
8564 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8565 uint shift = orig_shift & 7;
\r
8566 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8567 uint res = ROL_8(src, shift);
\r
8569 if(orig_shift != 0)
\r
8570 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8572 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8574 FLAG_N = NFLAG_8(res);
\r
8576 FLAG_C = src << orig_shift;
\r
8577 FLAG_V = VFLAG_CLEAR;
\r
8581 M68KMAKE_OP(rol, 16, s, .)
\r
8583 uint* r_dst = &DY;
\r
8584 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8585 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8586 uint res = ROL_16(src, shift);
\r
8589 USE_CYCLES(shift<<CYC_SHIFT);
\r
8591 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8593 FLAG_N = NFLAG_16(res);
\r
8595 FLAG_C = src >> (8-shift);
\r
8596 FLAG_V = VFLAG_CLEAR;
\r
8600 M68KMAKE_OP(rol, 32, s, .)
\r
8602 uint* r_dst = &DY;
\r
8603 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8604 uint64 src = *r_dst;
\r
8605 uint res = ROL_32(src, shift);
\r
8608 USE_CYCLES(shift<<CYC_SHIFT);
\r
8612 FLAG_N = NFLAG_32(res);
\r
8614 FLAG_C = src >> (24-shift);
\r
8615 FLAG_V = VFLAG_CLEAR;
\r
8619 M68KMAKE_OP(rol, 8, r, .)
\r
8621 uint* r_dst = &DY;
\r
8622 uint orig_shift = DX & 0x3f;
\r
8623 uint shift = orig_shift & 7;
\r
8624 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8625 uint res = ROL_8(src, shift);
\r
8627 if(orig_shift != 0)
\r
8629 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8633 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8634 FLAG_C = src << shift;
\r
8635 FLAG_N = NFLAG_8(res);
\r
8637 FLAG_V = VFLAG_CLEAR;
\r
8640 FLAG_C = (src & 1)<<8;
\r
8641 FLAG_N = NFLAG_8(src);
\r
8643 FLAG_V = VFLAG_CLEAR;
\r
8647 FLAG_C = CFLAG_CLEAR;
\r
8648 FLAG_N = NFLAG_8(src);
\r
8650 FLAG_V = VFLAG_CLEAR;
\r
8654 M68KMAKE_OP(rol, 16, r, .)
\r
8656 uint* r_dst = &DY;
\r
8657 uint orig_shift = DX & 0x3f;
\r
8658 uint shift = orig_shift & 15;
\r
8659 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8660 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
\r
8662 if(orig_shift != 0)
\r
8664 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8668 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8669 FLAG_C = (src << shift) >> 8;
\r
8670 FLAG_N = NFLAG_16(res);
\r
8672 FLAG_V = VFLAG_CLEAR;
\r
8675 FLAG_C = (src & 1)<<8;
\r
8676 FLAG_N = NFLAG_16(src);
\r
8678 FLAG_V = VFLAG_CLEAR;
\r
8682 FLAG_C = CFLAG_CLEAR;
\r
8683 FLAG_N = NFLAG_16(src);
\r
8685 FLAG_V = VFLAG_CLEAR;
\r
8689 M68KMAKE_OP(rol, 32, r, .)
\r
8691 uint* r_dst = &DY;
\r
8692 uint orig_shift = DX & 0x3f;
\r
8693 uint shift = orig_shift & 31;
\r
8694 uint64 src = *r_dst;
\r
8695 uint res = ROL_32(src, shift);
\r
8697 if(orig_shift != 0)
\r
8699 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8703 FLAG_C = (src >> (32 - shift)) << 8;
\r
8704 FLAG_N = NFLAG_32(res);
\r
8706 FLAG_V = VFLAG_CLEAR;
\r
8710 FLAG_C = CFLAG_CLEAR;
\r
8711 FLAG_N = NFLAG_32(src);
\r
8713 FLAG_V = VFLAG_CLEAR;
\r
8717 M68KMAKE_OP(rol, 16, ., .)
\r
8719 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8720 uint src = m68ki_read_16(ea);
\r
8721 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
\r
8723 m68ki_write_16(ea, res);
\r
8725 FLAG_N = NFLAG_16(res);
\r
8727 FLAG_C = src >> 7;
\r
8728 FLAG_V = VFLAG_CLEAR;
\r
8732 M68KMAKE_OP(roxr, 8, s, .)
\r
8734 uint* r_dst = &DY;
\r
8735 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8736 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8737 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
\r
8740 USE_CYCLES(shift<<CYC_SHIFT);
\r
8742 FLAG_C = FLAG_X = res;
\r
8743 res = MASK_OUT_ABOVE_8(res);
\r
8745 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8747 FLAG_N = NFLAG_8(res);
\r
8749 FLAG_V = VFLAG_CLEAR;
\r
8753 M68KMAKE_OP(roxr, 16, s, .)
\r
8755 uint* r_dst = &DY;
\r
8756 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8757 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8758 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
\r
8761 USE_CYCLES(shift<<CYC_SHIFT);
\r
8763 FLAG_C = FLAG_X = res >> 8;
\r
8764 res = MASK_OUT_ABOVE_16(res);
\r
8766 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8768 FLAG_N = NFLAG_16(res);
\r
8770 FLAG_V = VFLAG_CLEAR;
\r
8774 M68KMAKE_OP(roxr, 32, s, .)
\r
8776 #if M68K_USE_64_BIT
\r
8778 uint* r_dst = &DY;
\r
8779 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8780 uint64 src = *r_dst;
\r
8781 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
8784 USE_CYCLES(shift<<CYC_SHIFT);
\r
8786 res = ROR_33_64(res, shift);
\r
8788 FLAG_C = FLAG_X = res >> 24;
\r
8789 res = MASK_OUT_ABOVE_32(res);
\r
8793 FLAG_N = NFLAG_32(res);
\r
8795 FLAG_V = VFLAG_CLEAR;
\r
8799 uint* r_dst = &DY;
\r
8800 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8801 uint src = *r_dst;
\r
8802 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
\r
8803 uint new_x_flag = src & (1 << (shift - 1));
\r
8806 USE_CYCLES(shift<<CYC_SHIFT);
\r
8810 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
\r
8811 FLAG_N = NFLAG_32(res);
\r
8813 FLAG_V = VFLAG_CLEAR;
\r
8819 M68KMAKE_OP(roxr, 8, r, .)
\r
8821 uint* r_dst = &DY;
\r
8822 uint orig_shift = DX & 0x3f;
\r
8824 if(orig_shift != 0)
\r
8826 uint shift = orig_shift % 9;
\r
8827 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8828 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
\r
8830 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8832 FLAG_C = FLAG_X = res;
\r
8833 res = MASK_OUT_ABOVE_8(res);
\r
8835 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8836 FLAG_N = NFLAG_8(res);
\r
8838 FLAG_V = VFLAG_CLEAR;
\r
8843 FLAG_N = NFLAG_8(*r_dst);
\r
8844 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
8845 FLAG_V = VFLAG_CLEAR;
\r
8849 M68KMAKE_OP(roxr, 16, r, .)
\r
8851 uint* r_dst = &DY;
\r
8852 uint orig_shift = DX & 0x3f;
\r
8854 if(orig_shift != 0)
\r
8856 uint shift = orig_shift % 17;
\r
8857 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8858 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
\r
8860 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8862 FLAG_C = FLAG_X = res >> 8;
\r
8863 res = MASK_OUT_ABOVE_16(res);
\r
8865 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8866 FLAG_N = NFLAG_16(res);
\r
8868 FLAG_V = VFLAG_CLEAR;
\r
8873 FLAG_N = NFLAG_16(*r_dst);
\r
8874 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
8875 FLAG_V = VFLAG_CLEAR;
\r
8879 M68KMAKE_OP(roxr, 32, r, .)
\r
8881 #if M68K_USE_64_BIT
\r
8883 uint* r_dst = &DY;
\r
8884 uint orig_shift = DX & 0x3f;
\r
8886 if(orig_shift != 0)
\r
8888 uint shift = orig_shift % 33;
\r
8889 uint64 src = *r_dst;
\r
8890 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
8892 res = ROR_33_64(res, shift);
\r
8894 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8896 FLAG_C = FLAG_X = res >> 24;
\r
8897 res = MASK_OUT_ABOVE_32(res);
\r
8900 FLAG_N = NFLAG_32(res);
\r
8902 FLAG_V = VFLAG_CLEAR;
\r
8907 FLAG_N = NFLAG_32(*r_dst);
\r
8909 FLAG_V = VFLAG_CLEAR;
\r
8913 uint* r_dst = &DY;
\r
8914 uint orig_shift = DX & 0x3f;
\r
8915 uint shift = orig_shift % 33;
\r
8916 uint src = *r_dst;
\r
8917 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
\r
8918 uint new_x_flag = src & (1 << (shift - 1));
\r
8920 if(orig_shift != 0)
\r
8921 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8926 FLAG_X = (new_x_flag != 0)<<8;
\r
8931 FLAG_N = NFLAG_32(res);
\r
8933 FLAG_V = VFLAG_CLEAR;
\r
8939 M68KMAKE_OP(roxr, 16, ., .)
\r
8941 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8942 uint src = m68ki_read_16(ea);
\r
8943 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
\r
8945 FLAG_C = FLAG_X = res >> 8;
\r
8946 res = MASK_OUT_ABOVE_16(res);
\r
8948 m68ki_write_16(ea, res);
\r
8950 FLAG_N = NFLAG_16(res);
\r
8952 FLAG_V = VFLAG_CLEAR;
\r
8956 M68KMAKE_OP(roxl, 8, s, .)
\r
8958 uint* r_dst = &DY;
\r
8959 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8960 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8961 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
\r
8964 USE_CYCLES(shift<<CYC_SHIFT);
\r
8966 FLAG_C = FLAG_X = res;
\r
8967 res = MASK_OUT_ABOVE_8(res);
\r
8969 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8971 FLAG_N = NFLAG_8(res);
\r
8973 FLAG_V = VFLAG_CLEAR;
\r
8977 M68KMAKE_OP(roxl, 16, s, .)
\r
8979 uint* r_dst = &DY;
\r
8980 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8981 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8982 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
\r
8985 USE_CYCLES(shift<<CYC_SHIFT);
\r
8987 FLAG_C = FLAG_X = res >> 8;
\r
8988 res = MASK_OUT_ABOVE_16(res);
\r
8990 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8992 FLAG_N = NFLAG_16(res);
\r
8994 FLAG_V = VFLAG_CLEAR;
\r
8998 M68KMAKE_OP(roxl, 32, s, .)
\r
9000 #if M68K_USE_64_BIT
\r
9002 uint* r_dst = &DY;
\r
9003 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9004 uint64 src = *r_dst;
\r
9005 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
9008 USE_CYCLES(shift<<CYC_SHIFT);
\r
9010 res = ROL_33_64(res, shift);
\r
9012 FLAG_C = FLAG_X = res >> 24;
\r
9013 res = MASK_OUT_ABOVE_32(res);
\r
9017 FLAG_N = NFLAG_32(res);
\r
9019 FLAG_V = VFLAG_CLEAR;
\r
9023 uint* r_dst = &DY;
\r
9024 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9025 uint src = *r_dst;
\r
9026 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
\r
9027 uint new_x_flag = src & (1 << (32 - shift));
\r
9030 USE_CYCLES(shift<<CYC_SHIFT);
\r
9034 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
\r
9035 FLAG_N = NFLAG_32(res);
\r
9037 FLAG_V = VFLAG_CLEAR;
\r
9043 M68KMAKE_OP(roxl, 8, r, .)
\r
9045 uint* r_dst = &DY;
\r
9046 uint orig_shift = DX & 0x3f;
\r
9049 if(orig_shift != 0)
\r
9051 uint shift = orig_shift % 9;
\r
9052 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
9053 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
\r
9055 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9057 FLAG_C = FLAG_X = res;
\r
9058 res = MASK_OUT_ABOVE_8(res);
\r
9060 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9061 FLAG_N = NFLAG_8(res);
\r
9063 FLAG_V = VFLAG_CLEAR;
\r
9068 FLAG_N = NFLAG_8(*r_dst);
\r
9069 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
9070 FLAG_V = VFLAG_CLEAR;
\r
9074 M68KMAKE_OP(roxl, 16, r, .)
\r
9076 uint* r_dst = &DY;
\r
9077 uint orig_shift = DX & 0x3f;
\r
9079 if(orig_shift != 0)
\r
9081 uint shift = orig_shift % 17;
\r
9082 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
9083 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
\r
9085 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9087 FLAG_C = FLAG_X = res >> 8;
\r
9088 res = MASK_OUT_ABOVE_16(res);
\r
9090 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
9091 FLAG_N = NFLAG_16(res);
\r
9093 FLAG_V = VFLAG_CLEAR;
\r
9098 FLAG_N = NFLAG_16(*r_dst);
\r
9099 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
9100 FLAG_V = VFLAG_CLEAR;
\r
9104 M68KMAKE_OP(roxl, 32, r, .)
\r
9106 #if M68K_USE_64_BIT
\r
9108 uint* r_dst = &DY;
\r
9109 uint orig_shift = DX & 0x3f;
\r
9111 if(orig_shift != 0)
\r
9113 uint shift = orig_shift % 33;
\r
9114 uint64 src = *r_dst;
\r
9115 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
9117 res = ROL_33_64(res, shift);
\r
9119 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9121 FLAG_C = FLAG_X = res >> 24;
\r
9122 res = MASK_OUT_ABOVE_32(res);
\r
9125 FLAG_N = NFLAG_32(res);
\r
9127 FLAG_V = VFLAG_CLEAR;
\r
9132 FLAG_N = NFLAG_32(*r_dst);
\r
9134 FLAG_V = VFLAG_CLEAR;
\r
9138 uint* r_dst = &DY;
\r
9139 uint orig_shift = DX & 0x3f;
\r
9140 uint shift = orig_shift % 33;
\r
9141 uint src = *r_dst;
\r
9142 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
\r
9143 uint new_x_flag = src & (1 << (32 - shift));
\r
9145 if(orig_shift != 0)
\r
9146 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9151 FLAG_X = (new_x_flag != 0)<<8;
\r
9156 FLAG_N = NFLAG_32(res);
\r
9158 FLAG_V = VFLAG_CLEAR;
\r
9164 M68KMAKE_OP(roxl, 16, ., .)
\r
9166 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9167 uint src = m68ki_read_16(ea);
\r
9168 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
\r
9170 FLAG_C = FLAG_X = res >> 8;
\r
9171 res = MASK_OUT_ABOVE_16(res);
\r
9173 m68ki_write_16(ea, res);
\r
9175 FLAG_N = NFLAG_16(res);
\r
9177 FLAG_V = VFLAG_CLEAR;
\r
9181 M68KMAKE_OP(rtd, 32, ., .)
\r
9183 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
9185 uint new_pc = m68ki_pull_32();
\r
9187 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9188 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
9189 m68ki_jump(new_pc);
\r
9192 m68ki_exception_illegal();
\r
9196 M68KMAKE_OP(rte, 32, ., .)
\r
9204 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */
\r
9205 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9207 if(CPU_TYPE_IS_000(CPU_TYPE))
\r
9209 new_sr = m68ki_pull_16();
\r
9210 new_pc = m68ki_pull_32();
\r
9211 m68ki_jump(new_pc);
\r
9212 m68ki_set_sr(new_sr);
\r
9214 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9215 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9220 if(CPU_TYPE_IS_010(CPU_TYPE))
\r
9222 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
\r
9223 if(format_word == 0)
\r
9225 new_sr = m68ki_pull_16();
\r
9226 new_pc = m68ki_pull_32();
\r
9227 m68ki_fake_pull_16(); /* format word */
\r
9228 m68ki_jump(new_pc);
\r
9229 m68ki_set_sr(new_sr);
\r
9230 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9231 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9234 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9235 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9236 /* Not handling bus fault (9) */
\r
9237 m68ki_exception_format_error();
\r
9241 /* Otherwise it's 020 */
\r
9243 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
\r
9244 switch(format_word)
\r
9246 case 0: /* Normal */
\r
9247 new_sr = m68ki_pull_16();
\r
9248 new_pc = m68ki_pull_32();
\r
9249 m68ki_fake_pull_16(); /* format word */
\r
9250 m68ki_jump(new_pc);
\r
9251 m68ki_set_sr(new_sr);
\r
9252 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9253 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9255 case 1: /* Throwaway */
\r
9256 new_sr = m68ki_pull_16();
\r
9257 m68ki_fake_pull_32(); /* program counter */
\r
9258 m68ki_fake_pull_16(); /* format word */
\r
9259 m68ki_set_sr_noint(new_sr);
\r
9261 case 2: /* Trap */
\r
9262 new_sr = m68ki_pull_16();
\r
9263 new_pc = m68ki_pull_32();
\r
9264 m68ki_fake_pull_16(); /* format word */
\r
9265 m68ki_fake_pull_32(); /* address */
\r
9266 m68ki_jump(new_pc);
\r
9267 m68ki_set_sr(new_sr);
\r
9268 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9269 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9272 /* Not handling long or short bus fault */
\r
9273 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9274 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9275 m68ki_exception_format_error();
\r
9278 m68ki_exception_privilege_violation();
\r
9282 M68KMAKE_OP(rtm, 32, ., .)
\r
9284 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
9286 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9287 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
9288 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
9289 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
9292 m68ki_exception_illegal();
\r
9296 M68KMAKE_OP(rtr, 32, ., .)
\r
9298 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9299 m68ki_set_ccr(m68ki_pull_16());
\r
9300 m68ki_jump(m68ki_pull_32());
\r
9304 M68KMAKE_OP(rts, 32, ., .)
\r
9306 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9307 m68ki_jump(m68ki_pull_32());
\r
9311 M68KMAKE_OP(sbcd, 8, rr, .)
\r
9313 uint* r_dst = &DX;
\r
9315 uint dst = *r_dst;
\r
9316 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9318 // FLAG_V = ~res; /* Undefined V behavior */
\r
9319 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to assume cleared. */
\r
9323 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9327 FLAG_X = FLAG_C = CFLAG_SET;
\r
9328 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9331 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9333 res = MASK_OUT_ABOVE_8(res);
\r
9335 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9336 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9339 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9343 M68KMAKE_OP(sbcd, 8, mm, ax7)
\r
9345 uint src = OPER_AY_PD_8();
\r
9346 uint ea = EA_A7_PD_8();
\r
9347 uint dst = m68ki_read_8(ea);
\r
9348 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9350 // FLAG_V = ~res; /* Undefined V behavior */
\r
9351 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
\r
9355 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9359 FLAG_X = FLAG_C = CFLAG_SET;
\r
9360 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9363 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9365 res = MASK_OUT_ABOVE_8(res);
\r
9367 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9368 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9371 m68ki_write_8(ea, res);
\r
9375 M68KMAKE_OP(sbcd, 8, mm, ay7)
\r
9377 uint src = OPER_A7_PD_8();
\r
9378 uint ea = EA_AX_PD_8();
\r
9379 uint dst = m68ki_read_8(ea);
\r
9380 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9382 // FLAG_V = ~res; /* Undefined V behavior */
\r
9383 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
\r
9387 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9391 FLAG_X = FLAG_C = CFLAG_SET;
\r
9392 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9395 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9397 res = MASK_OUT_ABOVE_8(res);
\r
9399 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9400 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9403 m68ki_write_8(ea, res);
\r
9407 M68KMAKE_OP(sbcd, 8, mm, axy7)
\r
9409 uint src = OPER_A7_PD_8();
\r
9410 uint ea = EA_A7_PD_8();
\r
9411 uint dst = m68ki_read_8(ea);
\r
9412 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9414 // FLAG_V = ~res; /* Undefined V behavior */
\r
9415 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
\r
9419 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9423 FLAG_X = FLAG_C = CFLAG_SET;
\r
9424 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9427 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9429 res = MASK_OUT_ABOVE_8(res);
\r
9431 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9432 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9435 m68ki_write_8(ea, res);
\r
9439 M68KMAKE_OP(sbcd, 8, mm, .)
\r
9441 uint src = OPER_AY_PD_8();
\r
9442 uint ea = EA_AX_PD_8();
\r
9443 uint dst = m68ki_read_8(ea);
\r
9444 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9446 // FLAG_V = ~res; /* Undefined V behavior */
\r
9447 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
\r
9451 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9455 FLAG_X = FLAG_C = CFLAG_SET;
\r
9456 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9459 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9461 res = MASK_OUT_ABOVE_8(res);
\r
9463 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9464 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9467 m68ki_write_8(ea, res);
\r
9471 M68KMAKE_OP(st, 8, ., d)
\r
9477 M68KMAKE_OP(st, 8, ., .)
\r
9479 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
\r
9483 M68KMAKE_OP(sf, 8, ., d)
\r
9489 M68KMAKE_OP(sf, 8, ., .)
\r
9491 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
\r
9495 M68KMAKE_OP(scc, 8, ., d)
\r
9500 USE_CYCLES(CYC_SCC_R_TRUE);
\r
9507 M68KMAKE_OP(scc, 8, ., .)
\r
9509 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
\r
9513 M68KMAKE_OP(stop, 0, ., .)
\r
9517 uint new_sr = OPER_I_16();
\r
9518 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9519 CPU_STOPPED |= STOP_LEVEL_STOP;
\r
9520 m68ki_set_sr(new_sr);
\r
9521 m68ki_remaining_cycles = 0;
\r
9524 m68ki_exception_privilege_violation();
\r
9528 M68KMAKE_OP(sub, 8, er, d)
\r
9530 uint* r_dst = &DX;
\r
9531 uint src = MASK_OUT_ABOVE_8(DY);
\r
9532 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9533 uint res = dst - src;
\r
9535 FLAG_N = NFLAG_8(res);
\r
9536 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9537 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9538 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9540 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9544 M68KMAKE_OP(sub, 8, er, .)
\r
9546 uint* r_dst = &DX;
\r
9547 uint src = M68KMAKE_GET_OPER_AY_8;
\r
9548 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9549 uint res = dst - src;
\r
9551 FLAG_N = NFLAG_8(res);
\r
9552 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9553 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9554 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9556 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9560 M68KMAKE_OP(sub, 16, er, d)
\r
9562 uint* r_dst = &DX;
\r
9563 uint src = MASK_OUT_ABOVE_16(DY);
\r
9564 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9565 uint res = dst - src;
\r
9567 FLAG_N = NFLAG_16(res);
\r
9568 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9569 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9570 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9572 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9576 M68KMAKE_OP(sub, 16, er, a)
\r
9578 uint* r_dst = &DX;
\r
9579 uint src = MASK_OUT_ABOVE_16(AY);
\r
9580 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9581 uint res = dst - src;
\r
9583 FLAG_N = NFLAG_16(res);
\r
9584 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9585 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9586 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9588 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9592 M68KMAKE_OP(sub, 16, er, .)
\r
9594 uint* r_dst = &DX;
\r
9595 uint src = M68KMAKE_GET_OPER_AY_16;
\r
9596 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9597 uint res = dst - src;
\r
9599 FLAG_N = NFLAG_16(res);
\r
9600 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9601 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9602 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9604 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9608 M68KMAKE_OP(sub, 32, er, d)
\r
9610 uint* r_dst = &DX;
\r
9612 uint dst = *r_dst;
\r
9613 uint res = dst - src;
\r
9615 FLAG_N = NFLAG_32(res);
\r
9616 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9617 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9618 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9624 M68KMAKE_OP(sub, 32, er, a)
\r
9626 uint* r_dst = &DX;
\r
9628 uint dst = *r_dst;
\r
9629 uint res = dst - src;
\r
9631 FLAG_N = NFLAG_32(res);
\r
9632 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9633 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9634 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9640 M68KMAKE_OP(sub, 32, er, .)
\r
9642 uint* r_dst = &DX;
\r
9643 uint src = M68KMAKE_GET_OPER_AY_32;
\r
9644 uint dst = *r_dst;
\r
9645 uint res = dst - src;
\r
9647 FLAG_N = NFLAG_32(res);
\r
9648 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9649 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9650 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9656 M68KMAKE_OP(sub, 8, re, .)
\r
9658 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9659 uint src = MASK_OUT_ABOVE_8(DX);
\r
9660 uint dst = m68ki_read_8(ea);
\r
9661 uint res = dst - src;
\r
9663 FLAG_N = NFLAG_8(res);
\r
9664 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9665 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9666 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9668 m68ki_write_8(ea, FLAG_Z);
\r
9672 M68KMAKE_OP(sub, 16, re, .)
\r
9674 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9675 uint src = MASK_OUT_ABOVE_16(DX);
\r
9676 uint dst = m68ki_read_16(ea);
\r
9677 uint res = dst - src;
\r
9679 FLAG_N = NFLAG_16(res);
\r
9680 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9681 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9682 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9684 m68ki_write_16(ea, FLAG_Z);
\r
9688 M68KMAKE_OP(sub, 32, re, .)
\r
9690 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9692 uint dst = m68ki_read_32(ea);
\r
9693 uint res = dst - src;
\r
9695 FLAG_N = NFLAG_32(res);
\r
9696 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9697 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9698 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9700 m68ki_write_32(ea, FLAG_Z);
\r
9704 M68KMAKE_OP(suba, 16, ., d)
\r
9706 uint* r_dst = &AX;
\r
9708 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
\r
9712 M68KMAKE_OP(suba, 16, ., a)
\r
9714 uint* r_dst = &AX;
\r
9716 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
\r
9720 M68KMAKE_OP(suba, 16, ., .)
\r
9722 uint* r_dst = &AX;
\r
9724 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(M68KMAKE_GET_OPER_AY_16));
\r
9728 M68KMAKE_OP(suba, 32, ., d)
\r
9730 uint* r_dst = &AX;
\r
9732 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
\r
9736 M68KMAKE_OP(suba, 32, ., a)
\r
9738 uint* r_dst = &AX;
\r
9740 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
\r
9744 M68KMAKE_OP(suba, 32, ., .)
\r
9746 uint* r_dst = &AX;
\r
9748 *r_dst = MASK_OUT_ABOVE_32(*r_dst - M68KMAKE_GET_OPER_AY_32);
\r
9752 M68KMAKE_OP(subi, 8, ., d)
\r
9754 uint* r_dst = &DY;
\r
9755 uint src = OPER_I_8();
\r
9756 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9757 uint res = dst - src;
\r
9759 FLAG_N = NFLAG_8(res);
\r
9760 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9761 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9762 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9764 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9768 M68KMAKE_OP(subi, 8, ., .)
\r
9770 uint src = OPER_I_8();
\r
9771 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9772 uint dst = m68ki_read_8(ea);
\r
9773 uint res = dst - src;
\r
9775 FLAG_N = NFLAG_8(res);
\r
9776 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9777 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9778 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9780 m68ki_write_8(ea, FLAG_Z);
\r
9784 M68KMAKE_OP(subi, 16, ., d)
\r
9786 uint* r_dst = &DY;
\r
9787 uint src = OPER_I_16();
\r
9788 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9789 uint res = dst - src;
\r
9791 FLAG_N = NFLAG_16(res);
\r
9792 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9793 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9794 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9796 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9800 M68KMAKE_OP(subi, 16, ., .)
\r
9802 uint src = OPER_I_16();
\r
9803 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9804 uint dst = m68ki_read_16(ea);
\r
9805 uint res = dst - src;
\r
9807 FLAG_N = NFLAG_16(res);
\r
9808 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9809 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9810 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9812 m68ki_write_16(ea, FLAG_Z);
\r
9816 M68KMAKE_OP(subi, 32, ., d)
\r
9818 uint* r_dst = &DY;
\r
9819 uint src = OPER_I_32();
\r
9820 uint dst = *r_dst;
\r
9821 uint res = dst - src;
\r
9823 FLAG_N = NFLAG_32(res);
\r
9824 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9825 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9826 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9832 M68KMAKE_OP(subi, 32, ., .)
\r
9834 uint src = OPER_I_32();
\r
9835 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9836 uint dst = m68ki_read_32(ea);
\r
9837 uint res = dst - src;
\r
9839 FLAG_N = NFLAG_32(res);
\r
9840 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9841 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9842 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9844 m68ki_write_32(ea, FLAG_Z);
\r
9848 M68KMAKE_OP(subq, 8, ., d)
\r
9850 uint* r_dst = &DY;
\r
9851 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9852 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9853 uint res = dst - src;
\r
9855 FLAG_N = NFLAG_8(res);
\r
9856 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9857 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9858 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9860 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9864 M68KMAKE_OP(subq, 8, ., .)
\r
9866 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9867 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9868 uint dst = m68ki_read_8(ea);
\r
9869 uint res = dst - src;
\r
9871 FLAG_N = NFLAG_8(res);
\r
9872 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9873 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9874 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9876 m68ki_write_8(ea, FLAG_Z);
\r
9880 M68KMAKE_OP(subq, 16, ., d)
\r
9882 uint* r_dst = &DY;
\r
9883 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9884 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9885 uint res = dst - src;
\r
9887 FLAG_N = NFLAG_16(res);
\r
9888 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9889 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9890 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9892 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9896 M68KMAKE_OP(subq, 16, ., a)
\r
9898 uint* r_dst = &AY;
\r
9900 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
\r
9904 M68KMAKE_OP(subq, 16, ., .)
\r
9906 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9907 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9908 uint dst = m68ki_read_16(ea);
\r
9909 uint res = dst - src;
\r
9911 FLAG_N = NFLAG_16(res);
\r
9912 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9913 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9914 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9916 m68ki_write_16(ea, FLAG_Z);
\r
9920 M68KMAKE_OP(subq, 32, ., d)
\r
9922 uint* r_dst = &DY;
\r
9923 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9924 uint dst = *r_dst;
\r
9925 uint res = dst - src;
\r
9927 FLAG_N = NFLAG_32(res);
\r
9928 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9929 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9930 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9936 M68KMAKE_OP(subq, 32, ., a)
\r
9938 uint* r_dst = &AY;
\r
9940 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
\r
9944 M68KMAKE_OP(subq, 32, ., .)
\r
9946 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9947 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9948 uint dst = m68ki_read_32(ea);
\r
9949 uint res = dst - src;
\r
9951 FLAG_N = NFLAG_32(res);
\r
9952 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9953 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9954 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9956 m68ki_write_32(ea, FLAG_Z);
\r
9960 M68KMAKE_OP(subx, 8, rr, .)
\r
9962 uint* r_dst = &DX;
\r
9963 uint src = MASK_OUT_ABOVE_8(DY);
\r
9964 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9965 uint res = dst - src - XFLAG_AS_1();
\r
9967 FLAG_N = NFLAG_8(res);
\r
9968 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9969 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9971 res = MASK_OUT_ABOVE_8(res);
\r
9974 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9978 M68KMAKE_OP(subx, 16, rr, .)
\r
9980 uint* r_dst = &DX;
\r
9981 uint src = MASK_OUT_ABOVE_16(DY);
\r
9982 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9983 uint res = dst - src - XFLAG_AS_1();
\r
9985 FLAG_N = NFLAG_16(res);
\r
9986 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9987 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9989 res = MASK_OUT_ABOVE_16(res);
\r
9992 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
9996 M68KMAKE_OP(subx, 32, rr, .)
\r
9998 uint* r_dst = &DX;
\r
10000 uint dst = *r_dst;
\r
10001 uint res = dst - src - XFLAG_AS_1();
\r
10003 FLAG_N = NFLAG_32(res);
\r
10004 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10005 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10007 res = MASK_OUT_ABOVE_32(res);
\r
10014 M68KMAKE_OP(subx, 8, mm, ax7)
\r
10016 uint src = OPER_AY_PD_8();
\r
10017 uint ea = EA_A7_PD_8();
\r
10018 uint dst = m68ki_read_8(ea);
\r
10019 uint res = dst - src - XFLAG_AS_1();
\r
10021 FLAG_N = NFLAG_8(res);
\r
10022 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10023 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10025 res = MASK_OUT_ABOVE_8(res);
\r
10028 m68ki_write_8(ea, res);
\r
10032 M68KMAKE_OP(subx, 8, mm, ay7)
\r
10034 uint src = OPER_A7_PD_8();
\r
10035 uint ea = EA_AX_PD_8();
\r
10036 uint dst = m68ki_read_8(ea);
\r
10037 uint res = dst - src - XFLAG_AS_1();
\r
10039 FLAG_N = NFLAG_8(res);
\r
10040 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10041 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10043 res = MASK_OUT_ABOVE_8(res);
\r
10046 m68ki_write_8(ea, res);
\r
10050 M68KMAKE_OP(subx, 8, mm, axy7)
\r
10052 uint src = OPER_A7_PD_8();
\r
10053 uint ea = EA_A7_PD_8();
\r
10054 uint dst = m68ki_read_8(ea);
\r
10055 uint res = dst - src - XFLAG_AS_1();
\r
10057 FLAG_N = NFLAG_8(res);
\r
10058 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10059 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10061 res = MASK_OUT_ABOVE_8(res);
\r
10064 m68ki_write_8(ea, res);
\r
10068 M68KMAKE_OP(subx, 8, mm, .)
\r
10070 uint src = OPER_AY_PD_8();
\r
10071 uint ea = EA_AX_PD_8();
\r
10072 uint dst = m68ki_read_8(ea);
\r
10073 uint res = dst - src - XFLAG_AS_1();
\r
10075 FLAG_N = NFLAG_8(res);
\r
10076 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10077 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10079 res = MASK_OUT_ABOVE_8(res);
\r
10082 m68ki_write_8(ea, res);
\r
10086 M68KMAKE_OP(subx, 16, mm, .)
\r
10088 uint src = OPER_AY_PD_16();
\r
10089 uint ea = EA_AX_PD_16();
\r
10090 uint dst = m68ki_read_16(ea);
\r
10091 uint res = dst - src - XFLAG_AS_1();
\r
10093 FLAG_N = NFLAG_16(res);
\r
10094 FLAG_X = FLAG_C = CFLAG_16(res);
\r
10095 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
10097 res = MASK_OUT_ABOVE_16(res);
\r
10100 m68ki_write_16(ea, res);
\r
10104 M68KMAKE_OP(subx, 32, mm, .)
\r
10106 uint src = OPER_AY_PD_32();
\r
10107 uint ea = EA_AX_PD_32();
\r
10108 uint dst = m68ki_read_32(ea);
\r
10109 uint res = dst - src - XFLAG_AS_1();
\r
10111 FLAG_N = NFLAG_32(res);
\r
10112 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10113 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10115 res = MASK_OUT_ABOVE_32(res);
\r
10118 m68ki_write_32(ea, res);
\r
10122 M68KMAKE_OP(swap, 32, ., .)
\r
10124 uint* r_dst = &DY;
\r
10126 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
\r
10127 *r_dst = (*r_dst>>16) | FLAG_Z;
\r
10130 FLAG_N = NFLAG_32(*r_dst);
\r
10131 FLAG_C = CFLAG_CLEAR;
\r
10132 FLAG_V = VFLAG_CLEAR;
\r
10136 M68KMAKE_OP(tas, 8, ., d)
\r
10138 uint* r_dst = &DY;
\r
10140 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
10141 FLAG_N = NFLAG_8(*r_dst);
\r
10142 FLAG_V = VFLAG_CLEAR;
\r
10143 FLAG_C = CFLAG_CLEAR;
\r
10148 M68KMAKE_OP(tas, 8, ., .)
\r
10150 uint ea = M68KMAKE_GET_EA_AY_8;
\r
10151 uint dst = m68ki_read_8(ea);
\r
10154 FLAG_N = NFLAG_8(dst);
\r
10155 FLAG_V = VFLAG_CLEAR;
\r
10156 FLAG_C = CFLAG_CLEAR;
\r
10157 // m68ki_write_8(ea, dst | 0x80); // notaz: genesis, but only to mem
\r
10161 M68KMAKE_OP(trap, 0, ., .)
\r
10163 /* Trap#n stacks exception frame type 0 */
\r
10164 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
\r
10168 M68KMAKE_OP(trapt, 0, ., .)
\r
10170 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10172 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10175 m68ki_exception_illegal();
\r
10179 M68KMAKE_OP(trapt, 16, ., .)
\r
10181 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10183 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10186 m68ki_exception_illegal();
\r
10190 M68KMAKE_OP(trapt, 32, ., .)
\r
10192 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10194 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10197 m68ki_exception_illegal();
\r
10201 M68KMAKE_OP(trapf, 0, ., .)
\r
10203 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10207 m68ki_exception_illegal();
\r
10211 M68KMAKE_OP(trapf, 16, ., .)
\r
10213 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10218 m68ki_exception_illegal();
\r
10222 M68KMAKE_OP(trapf, 32, ., .)
\r
10224 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10229 m68ki_exception_illegal();
\r
10233 M68KMAKE_OP(trapcc, 0, ., .)
\r
10235 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10238 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10241 m68ki_exception_illegal();
\r
10245 M68KMAKE_OP(trapcc, 16, ., .)
\r
10247 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10251 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10257 m68ki_exception_illegal();
\r
10261 M68KMAKE_OP(trapcc, 32, ., .)
\r
10263 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10267 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10273 m68ki_exception_illegal();
\r
10277 M68KMAKE_OP(trapv, 0, ., .)
\r
10283 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10287 M68KMAKE_OP(tst, 8, ., d)
\r
10289 uint res = MASK_OUT_ABOVE_8(DY);
\r
10291 FLAG_N = NFLAG_8(res);
\r
10293 FLAG_V = VFLAG_CLEAR;
\r
10294 FLAG_C = CFLAG_CLEAR;
\r
10298 M68KMAKE_OP(tst, 8, ., .)
\r
10300 uint res = M68KMAKE_GET_OPER_AY_8;
\r
10302 FLAG_N = NFLAG_8(res);
\r
10304 FLAG_V = VFLAG_CLEAR;
\r
10305 FLAG_C = CFLAG_CLEAR;
\r
10309 M68KMAKE_OP(tst, 8, ., pcdi)
\r
10311 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10313 uint res = OPER_PCDI_8();
\r
10315 FLAG_N = NFLAG_8(res);
\r
10317 FLAG_V = VFLAG_CLEAR;
\r
10318 FLAG_C = CFLAG_CLEAR;
\r
10321 m68ki_exception_illegal();
\r
10325 M68KMAKE_OP(tst, 8, ., pcix)
\r
10327 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10329 uint res = OPER_PCIX_8();
\r
10331 FLAG_N = NFLAG_8(res);
\r
10333 FLAG_V = VFLAG_CLEAR;
\r
10334 FLAG_C = CFLAG_CLEAR;
\r
10337 m68ki_exception_illegal();
\r
10341 M68KMAKE_OP(tst, 8, ., i)
\r
10343 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10345 uint res = OPER_I_8();
\r
10347 FLAG_N = NFLAG_8(res);
\r
10349 FLAG_V = VFLAG_CLEAR;
\r
10350 FLAG_C = CFLAG_CLEAR;
\r
10353 m68ki_exception_illegal();
\r
10357 M68KMAKE_OP(tst, 16, ., d)
\r
10359 uint res = MASK_OUT_ABOVE_16(DY);
\r
10361 FLAG_N = NFLAG_16(res);
\r
10363 FLAG_V = VFLAG_CLEAR;
\r
10364 FLAG_C = CFLAG_CLEAR;
\r
10368 M68KMAKE_OP(tst, 16, ., a)
\r
10370 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10372 uint res = MAKE_INT_16(AY);
\r
10374 FLAG_N = NFLAG_16(res);
\r
10376 FLAG_V = VFLAG_CLEAR;
\r
10377 FLAG_C = CFLAG_CLEAR;
\r
10380 m68ki_exception_illegal();
\r
10384 M68KMAKE_OP(tst, 16, ., .)
\r
10386 uint res = M68KMAKE_GET_OPER_AY_16;
\r
10388 FLAG_N = NFLAG_16(res);
\r
10390 FLAG_V = VFLAG_CLEAR;
\r
10391 FLAG_C = CFLAG_CLEAR;
\r
10395 M68KMAKE_OP(tst, 16, ., pcdi)
\r
10397 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10399 uint res = OPER_PCDI_16();
\r
10401 FLAG_N = NFLAG_16(res);
\r
10403 FLAG_V = VFLAG_CLEAR;
\r
10404 FLAG_C = CFLAG_CLEAR;
\r
10407 m68ki_exception_illegal();
\r
10411 M68KMAKE_OP(tst, 16, ., pcix)
\r
10413 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10415 uint res = OPER_PCIX_16();
\r
10417 FLAG_N = NFLAG_16(res);
\r
10419 FLAG_V = VFLAG_CLEAR;
\r
10420 FLAG_C = CFLAG_CLEAR;
\r
10423 m68ki_exception_illegal();
\r
10427 M68KMAKE_OP(tst, 16, ., i)
\r
10429 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10431 uint res = OPER_I_16();
\r
10433 FLAG_N = NFLAG_16(res);
\r
10435 FLAG_V = VFLAG_CLEAR;
\r
10436 FLAG_C = CFLAG_CLEAR;
\r
10439 m68ki_exception_illegal();
\r
10443 M68KMAKE_OP(tst, 32, ., d)
\r
10447 FLAG_N = NFLAG_32(res);
\r
10449 FLAG_V = VFLAG_CLEAR;
\r
10450 FLAG_C = CFLAG_CLEAR;
\r
10454 M68KMAKE_OP(tst, 32, ., a)
\r
10456 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10460 FLAG_N = NFLAG_32(res);
\r
10462 FLAG_V = VFLAG_CLEAR;
\r
10463 FLAG_C = CFLAG_CLEAR;
\r
10466 m68ki_exception_illegal();
\r
10470 M68KMAKE_OP(tst, 32, ., .)
\r
10472 uint res = M68KMAKE_GET_OPER_AY_32;
\r
10474 FLAG_N = NFLAG_32(res);
\r
10476 FLAG_V = VFLAG_CLEAR;
\r
10477 FLAG_C = CFLAG_CLEAR;
\r
10481 M68KMAKE_OP(tst, 32, ., pcdi)
\r
10483 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10485 uint res = OPER_PCDI_32();
\r
10487 FLAG_N = NFLAG_32(res);
\r
10489 FLAG_V = VFLAG_CLEAR;
\r
10490 FLAG_C = CFLAG_CLEAR;
\r
10493 m68ki_exception_illegal();
\r
10497 M68KMAKE_OP(tst, 32, ., pcix)
\r
10499 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10501 uint res = OPER_PCIX_32();
\r
10503 FLAG_N = NFLAG_32(res);
\r
10505 FLAG_V = VFLAG_CLEAR;
\r
10506 FLAG_C = CFLAG_CLEAR;
\r
10509 m68ki_exception_illegal();
\r
10513 M68KMAKE_OP(tst, 32, ., i)
\r
10515 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10517 uint res = OPER_I_32();
\r
10519 FLAG_N = NFLAG_32(res);
\r
10521 FLAG_V = VFLAG_CLEAR;
\r
10522 FLAG_C = CFLAG_CLEAR;
\r
10525 m68ki_exception_illegal();
\r
10529 M68KMAKE_OP(unlk, 32, ., a7)
\r
10531 REG_A[7] = m68ki_read_32(REG_A[7]);
\r
10535 M68KMAKE_OP(unlk, 32, ., .)
\r
10537 uint* r_dst = &AY;
\r
10539 REG_A[7] = *r_dst;
\r
10540 *r_dst = m68ki_pull_32();
\r
10544 M68KMAKE_OP(unpk, 16, rr, .)
\r
10546 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10548 /* Note: DX and DY are reversed in Motorola's docs */
\r
10550 uint* r_dst = &DX;
\r
10552 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
\r
10555 m68ki_exception_illegal();
\r
10559 M68KMAKE_OP(unpk, 16, mm, ax7)
\r
10561 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10563 /* Note: AX and AY are reversed in Motorola's docs */
\r
10564 uint src = OPER_AY_PD_8();
\r
10567 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10568 ea_dst = EA_A7_PD_8();
\r
10569 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10570 ea_dst = EA_A7_PD_8();
\r
10571 m68ki_write_8(ea_dst, src & 0xff);
\r
10574 m68ki_exception_illegal();
\r
10578 M68KMAKE_OP(unpk, 16, mm, ay7)
\r
10580 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10582 /* Note: AX and AY are reversed in Motorola's docs */
\r
10583 uint src = OPER_A7_PD_8();
\r
10586 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10587 ea_dst = EA_AX_PD_8();
\r
10588 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10589 ea_dst = EA_AX_PD_8();
\r
10590 m68ki_write_8(ea_dst, src & 0xff);
\r
10593 m68ki_exception_illegal();
\r
10597 M68KMAKE_OP(unpk, 16, mm, axy7)
\r
10599 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10601 uint src = OPER_A7_PD_8();
\r
10604 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10605 ea_dst = EA_A7_PD_8();
\r
10606 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10607 ea_dst = EA_A7_PD_8();
\r
10608 m68ki_write_8(ea_dst, src & 0xff);
\r
10611 m68ki_exception_illegal();
\r
10615 M68KMAKE_OP(unpk, 16, mm, .)
\r
10617 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10619 /* Note: AX and AY are reversed in Motorola's docs */
\r
10620 uint src = OPER_AY_PD_8();
\r
10623 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10624 ea_dst = EA_AX_PD_8();
\r
10625 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10626 ea_dst = EA_AX_PD_8();
\r
10627 m68ki_write_8(ea_dst, src & 0xff);
\r
10630 m68ki_exception_illegal();
\r
10635 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
\r
notaz.gp2x.de / picodrive.git / blob