6 /* ======================================================================== */
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7 /* ========================= LICENSING & COPYRIGHT ======================== */
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8 /* ======================================================================== */
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13 * A portable Motorola M680x0 processor emulation engine.
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14 * Copyright 1998-2007 Karl Stenerud. All rights reserved.
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16 * This code may be freely used for non-commercial purposes as long as this
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17 * copyright notice remains unaltered in the source code and any binary files
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18 * containing this code in compiled form.
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20 * All other lisencing terms must be negotiated with the author
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23 * The latest version of this code can be obtained at:
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24 * http://kstenerud.cjb.net
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27 /* Special thanks to Bart Trzynadlowski for his insight into the
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28 * undocumented features of this chip:
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30 * http://dynarec.com/~bart/files/68knotes.txt
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34 /* Input file for m68kmake
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35 * -----------------------
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37 * All sections begin with 80 X's in a row followed by an end-of-line
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39 * After this, m68kmake will expect to find one of the following section
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41 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
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42 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
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43 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
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44 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
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45 * M68KMAKE_TABLE_BODY - the table itself
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46 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
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47 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
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48 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
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50 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
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51 * M68KMAKE_TABLE_BODY must be second last in the file.
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53 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
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54 * primitives themselves. Each opcode handler begins with:
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55 * M68KMAKE_OP(A, B, C, D)
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57 * where A is the opcode handler name, B is the size of the operation,
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58 * C denotes any special processing mode, and D denotes a specific
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60 * For C and D where nothing is specified, use "."
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63 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
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64 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
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65 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
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67 * All opcode handler primitives end with a closing curly brace "}" at column 1
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69 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
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70 * and do not put a closing curly brace at column 1 unless it is
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71 * marking the end of the handler!
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73 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
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74 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
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75 * opcode handlers to handle variations in the opcode handler.
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76 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
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77 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
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78 * be interpreted on instructions where the corresponding table entry
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79 * specifies multiple effective addressing modes.
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81 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
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83 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
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84 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
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85 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
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88 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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89 M68KMAKE_PROTOTYPE_HEADER
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91 #ifndef M68KOPS__HEADER
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92 #define M68KOPS__HEADER
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94 /* ======================================================================== */
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95 /* ============================ OPCODE HANDLERS =========================== */
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96 /* ======================================================================== */
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100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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101 M68KMAKE_PROTOTYPE_FOOTER
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104 /* Build the opcode handler table */
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105 void m68ki_build_opcode_table(void);
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107 extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
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108 extern unsigned char m68ki_cycles[][0x10000];
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111 /* ======================================================================== */
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112 /* ============================== END OF FILE ============================= */
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113 /* ======================================================================== */
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115 #endif /* M68KOPS__HEADER */
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119 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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120 M68KMAKE_TABLE_HEADER
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122 /* ======================================================================== */
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123 /* ========================= OPCODE TABLE BUILDER ========================= */
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124 /* ======================================================================== */
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126 #include "m68kops.h"
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128 #define NUM_CPU_TYPES 4
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130 void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
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131 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
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133 /* This is used to generate the opcode handler jump table */
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136 void (*opcode_handler)(void); /* handler function */
\r
137 unsigned int mask; /* mask on opcode */
\r
138 unsigned int match; /* what to match after masking */
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139 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
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140 } opcode_handler_struct;
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143 /* Opcode handler table */
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144 static opcode_handler_struct m68k_opcode_handler_table[] =
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146 /* function mask match 000 010 020 040 */
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150 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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151 M68KMAKE_TABLE_FOOTER
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153 {0, 0, 0, {0, 0, 0, 0}}
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157 /* Build the opcode handler jump table */
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158 void m68ki_build_opcode_table(void)
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160 opcode_handler_struct *ostruct;
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166 for(i = 0; i < 0x10000; i++)
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168 /* default to illegal */
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169 m68ki_instruction_jump_table[i] = m68k_op_illegal;
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170 for(k=0;k<NUM_CPU_TYPES;k++)
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171 m68ki_cycles[k][i] = 0;
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174 ostruct = m68k_opcode_handler_table;
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175 while(ostruct->mask != 0xff00)
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177 for(i = 0;i < 0x10000;i++)
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179 if((i & ostruct->mask) == ostruct->match)
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181 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
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182 for(k=0;k<NUM_CPU_TYPES;k++)
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183 m68ki_cycles[k][i] = ostruct->cycles[k];
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188 while(ostruct->mask == 0xff00)
\r
190 for(i = 0;i <= 0xff;i++)
\r
192 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
\r
193 for(k=0;k<NUM_CPU_TYPES;k++)
\r
194 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
\r
198 while(ostruct->mask == 0xf1f8)
\r
200 for(i = 0;i < 8;i++)
\r
202 for(j = 0;j < 8;j++)
\r
204 instr = ostruct->match | (i << 9) | j;
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205 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
\r
206 for(k=0;k<NUM_CPU_TYPES;k++)
\r
207 m68ki_cycles[k][instr] = ostruct->cycles[k];
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212 while(ostruct->mask == 0xfff0)
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214 for(i = 0;i <= 0x0f;i++)
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216 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
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217 for(k=0;k<NUM_CPU_TYPES;k++)
\r
218 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
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222 while(ostruct->mask == 0xf1ff)
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224 for(i = 0;i <= 0x07;i++)
\r
226 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
\r
227 for(k=0;k<NUM_CPU_TYPES;k++)
\r
228 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
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232 while(ostruct->mask == 0xfff8)
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234 for(i = 0;i <= 0x07;i++)
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236 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
\r
237 for(k=0;k<NUM_CPU_TYPES;k++)
\r
238 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
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242 while(ostruct->mask == 0xffff)
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244 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
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245 for(k=0;k<NUM_CPU_TYPES;k++)
\r
246 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
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252 /* ======================================================================== */
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253 /* ============================== END OF FILE ============================= */
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254 /* ======================================================================== */
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258 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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259 M68KMAKE_OPCODE_HANDLER_HEADER
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261 #include "m68kcpu.h"
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262 extern void m68040_fpu_op0(void);
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263 extern void m68040_fpu_op1(void);
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265 /* ======================================================================== */
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266 /* ========================= INSTRUCTION HANDLERS ========================= */
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267 /* ======================================================================== */
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271 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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272 M68KMAKE_OPCODE_HANDLER_FOOTER
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274 /* ======================================================================== */
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275 /* ============================== END OF FILE ============================= */
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276 /* ======================================================================== */
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280 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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281 M68KMAKE_TABLE_BODY
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283 The following table is arranged as follows:
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285 name: Opcode mnemonic
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287 size: Operation size
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289 spec proc: Special processing mode:
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292 r: register operand
\r
293 rr: register to register
\r
294 mm: memory to memory
\r
295 er: effective address to register
\r
296 re: register to effective address
\r
297 dd: data register to data register
\r
298 da: data register to address register
\r
299 aa: address register to address register
\r
300 cr: control register to register
\r
301 rc: register to control register
\r
302 toc: to condition code register
\r
303 tos: to status register
\r
304 tou: to user stack pointer
\r
305 frc: from condition code register
\r
306 frs: from status register
\r
307 fru: from user stack pointer
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308 * for move.x, the special processing mode is a specific
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309 destination effective addressing mode.
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311 spec ea: Specific effective addressing mode:
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315 a: address register
\r
316 ai: address register indirect
\r
317 pi: address register indirect with postincrement
\r
318 pd: address register indirect with predecrement
\r
319 di: address register indirect with displacement
\r
320 ix: address register indirect with index
\r
321 aw: absolute word address
\r
322 al: absolute long address
\r
323 pcdi: program counter relative with displacement
\r
324 pcix: program counter relative with index
\r
325 a7: register specified in instruction is A7
\r
326 ax7: register field X of instruction is A7
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327 ay7: register field Y of instruction is A7
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328 axy7: register fields X and Y of instruction are A7
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330 bit pattern: Pattern to recognize this opcode. "." means don't care.
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332 allowed ea: List of allowed addressing modes:
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334 A: address register indirect
\r
335 +: ARI (address register indirect) with postincrement
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336 -: ARI with predecrement
\r
337 D: ARI with displacement
\r
339 W: absolute word address
\r
340 L: absolute long address
\r
341 d: program counter indirect with displacement
\r
342 x: program counter indirect with index
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344 mode: CPU operating mode for each cpu type. U = user or supervisor,
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345 S = supervisor only, "." = opcode not present.
\r
347 cpu cycles: Base number of cycles required to execute this opcode on the
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348 specified CPU type.
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349 Use "." if CPU does not have this opcode.
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353 spec spec allowed ea mode cpu cycles
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354 name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments
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355 ====== ==== ==== ==== ================ ========== = = = = === === === === =============
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356 M68KMAKE_TABLE_START
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357 1010 0 . . 1010............ .......... U U U U 4 4 4 4
\r
358 1111 0 . . 1111............ .......... U U U U 4 4 4 4
\r
359 040fpu0 32 . . 11110010........ .......... . . . U . . . 0
\r
360 040fpu1 32 . . 11110011........ .......... . . . U . . . 0
\r
361 abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4
\r
362 abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16
\r
363 abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16
\r
364 abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16
\r
365 abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16
\r
366 add 8 er d 1101...000000... .......... U U U U 4 4 2 2
\r
367 add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
368 add 16 er d 1101...001000... .......... U U U U 4 4 2 2
\r
369 add 16 er a 1101...001001... .......... U U U U 4 4 2 2
\r
370 add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
371 add 32 er d 1101...010000... .......... U U U U 6 6 2 2
\r
372 add 32 er a 1101...010001... .......... U U U U 6 6 2 2
\r
373 add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
374 add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4
\r
375 add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4
\r
376 add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4
\r
377 adda 16 . d 1101...011000... .......... U U U U 8 8 2 2
\r
378 adda 16 . a 1101...011001... .......... U U U U 8 8 2 2
\r
379 adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2
\r
380 adda 32 . d 1101...111000... .......... U U U U 6 6 2 2
\r
381 adda 32 . a 1101...111001... .......... U U U U 6 6 2 2
\r
382 adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2
\r
383 addi 8 . d 0000011000000... .......... U U U U 8 8 2 2
\r
384 addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4
\r
385 addi 16 . d 0000011001000... .......... U U U U 8 8 2 2
\r
386 addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4
\r
387 addi 32 . d 0000011010000... .......... U U U U 16 14 2 2
\r
388 addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4
\r
389 addq 8 . d 0101...000000... .......... U U U U 4 4 2 2
\r
390 addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4
\r
391 addq 16 . d 0101...001000... .......... U U U U 4 4 2 2
\r
392 addq 16 . a 0101...001001... .......... U U U U 4 4 2 2
\r
393 addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4
\r
394 addq 32 . d 0101...010000... .......... U U U U 8 8 2 2
\r
395 addq 32 . a 0101...010001... .......... U U U U 8 8 2 2
\r
396 addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4
\r
397 addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2
\r
398 addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2
\r
399 addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2
\r
400 addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12
\r
401 addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12
\r
402 addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12
\r
403 addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12
\r
404 addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12
\r
405 addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12
\r
406 and 8 er d 1100...000000... .......... U U U U 4 4 2 2
\r
407 and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
408 and 16 er d 1100...001000... .......... U U U U 4 4 2 2
\r
409 and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
410 and 32 er d 1100...010000... .......... U U U U 6 6 2 2
\r
411 and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
412 and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4
\r
413 and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4
\r
414 and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4
\r
415 andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12
\r
416 andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12
\r
417 andi 8 . d 0000001000000... .......... U U U U 8 8 2 2
\r
418 andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4
\r
419 andi 16 . d 0000001001000... .......... U U U U 8 8 2 2
\r
420 andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4
\r
421 andi 32 . d 0000001010000... .......... U U U U 14 14 2 2
\r
422 andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4
\r
423 asr 8 s . 1110...000000... .......... U U U U 6 6 6 6
\r
424 asr 16 s . 1110...001000... .......... U U U U 6 6 6 6
\r
425 asr 32 s . 1110...010000... .......... U U U U 8 8 6 6
\r
426 asr 8 r . 1110...000100... .......... U U U U 6 6 6 6
\r
427 asr 16 r . 1110...001100... .......... U U U U 6 6 6 6
\r
428 asr 32 r . 1110...010100... .......... U U U U 8 8 6 6
\r
429 asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5
\r
430 asl 8 s . 1110...100000... .......... U U U U 6 6 8 8
\r
431 asl 16 s . 1110...101000... .......... U U U U 6 6 8 8
\r
432 asl 32 s . 1110...110000... .......... U U U U 8 8 8 8
\r
433 asl 8 r . 1110...100100... .......... U U U U 6 6 8 8
\r
434 asl 16 r . 1110...101100... .......... U U U U 6 6 8 8
\r
435 asl 32 r . 1110...110100... .......... U U U U 8 8 8 8
\r
436 asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6
\r
437 bcc 8 . . 0110............ .......... U U U U 10 10 6 6
\r
438 bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6
\r
439 bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6
\r
440 bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4
\r
441 bchg 32 r d 0000...101000... .......... U U U U 8 8 4 4
\r
442 bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4
\r
443 bchg 32 s d 0000100001000... .......... U U U U 12 12 4 4
\r
444 bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 10 4 4
\r
445 bclr 32 r d 0000...110000... .......... U U U U 10 10 4 4
\r
446 bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4
\r
447 bclr 32 s d 0000100010000... .......... U U U U 14 14 4 4
\r
448 bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct
\r
449 bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20
\r
450 bfclr 32 . d 1110110011000... .......... . . U U . . 12 12
\r
451 bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20
\r
452 bfexts 32 . d 1110101111000... .......... . . U U . . 8 8
\r
453 bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15
\r
454 bfextu 32 . d 1110100111000... .......... . . U U . . 8 8
\r
455 bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15
\r
456 bfffo 32 . d 1110110111000... .......... . . U U . . 18 18
\r
457 bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28
\r
458 bfins 32 . d 1110111111000... .......... . . U U . . 10 10
\r
459 bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17
\r
460 bfset 32 . d 1110111011000... .......... . . U U . . 12 12
\r
461 bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20
\r
462 bftst 32 . d 1110100011000... .......... . . U U . . 6 6
\r
463 bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13
\r
464 bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10
\r
465 bra 8 . . 01100000........ .......... U U U U 10 10 10 10
\r
466 bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10
\r
467 bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10
\r
468 bset 32 r d 0000...111000... .......... U U U U 8 8 4 4
\r
469 bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4
\r
470 bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4
\r
471 bset 32 s d 0000100011000... .......... U U U U 12 12 4 4
\r
472 bsr 8 . . 01100001........ .......... U U U U 18 18 7 7
\r
473 bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7
\r
474 bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7
\r
475 btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4
\r
476 btst 32 r d 0000...100000... .......... U U U U 6 6 4 4
\r
477 btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4
\r
478 btst 32 s d 0000100000000... .......... U U U U 10 10 4 4
\r
479 callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated
\r
480 cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12
\r
481 cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12
\r
482 cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12
\r
483 cas2 16 . . 0000110011111100 .......... . . U U . . 12 12
\r
484 cas2 32 . . 0000111011111100 .......... . . U U . . 12 12
\r
485 chk 16 . d 0100...110000... .......... U U U U 10 8 8 8
\r
486 chk 16 . . 0100...110...... A+-DXWLdxI U U U U 10 8 8 8
\r
487 chk 32 . d 0100...100000... .......... . . U U . . 8 8
\r
488 chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8
\r
489 chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23
\r
490 chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23
\r
491 chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18
\r
492 chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23
\r
493 chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23
\r
494 chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18
\r
495 chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23
\r
496 chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23
\r
497 chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18
\r
498 clr 8 . d 0100001000000... .......... U U U U 4 4 2 2
\r
499 clr 8 . . 0100001000...... A+-DXWL... U U U U 6 4 4 4 notaz hack: changed 000 cycles 8 -> 6 like in starscream for Fatal Rewind
\r
500 clr 16 . d 0100001001000... .......... U U U U 4 4 2 2
\r
501 clr 16 . . 0100001001...... A+-DXWL... U U U U 6 4 4 4 notaz hack: ditto
\r
502 clr 32 . d 0100001010000... .......... U U U U 6 6 2 2
\r
503 clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4
\r
504 cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2
\r
505 cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
506 cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2
\r
507 cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2
\r
508 cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
509 cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2
\r
510 cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2
\r
511 cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
512 cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4
\r
513 cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4
\r
514 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4
\r
515 cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4
\r
516 cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4
\r
517 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4
\r
518 cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2
\r
519 cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2
\r
520 cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7
\r
521 cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9
\r
522 cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2
\r
523 cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2
\r
524 cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7
\r
525 cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9
\r
526 cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2
\r
527 cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2
\r
528 cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7
\r
529 cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9
\r
530 cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9
\r
531 cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9
\r
532 cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9
\r
533 cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9
\r
534 cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9
\r
535 cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9
\r
536 cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated
\r
537 cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated
\r
538 cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated
\r
539 cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated
\r
540 cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated
\r
541 dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6
\r
542 dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6
\r
543 dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6
\r
544 divs 16 . d 1000...111000... .......... U U U U 158 122 56 56
\r
545 divs 16 . . 1000...111...... A+-DXWLdxI U U U U 158 122 56 56
\r
546 divu 16 . d 1000...011000... .......... U U U U 140 108 44 44
\r
547 divu 16 . . 1000...011...... A+-DXWLdxI U U U U 140 108 44 44
\r
548 divl 32 . d 0100110001000... .......... . . U U . . 84 84
\r
549 divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84
\r
550 eor 8 . d 1011...100000... .......... U U U U 4 4 2 2
\r
551 eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4
\r
552 eor 16 . d 1011...101000... .......... U U U U 4 4 2 2
\r
553 eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4
\r
554 eor 32 . d 1011...110000... .......... U U U U 8 6 2 2
\r
555 eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4
\r
556 eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12
\r
557 eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12
\r
558 eori 8 . d 0000101000000... .......... U U U U 8 8 2 2
\r
559 eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4
\r
560 eori 16 . d 0000101001000... .......... U U U U 8 8 2 2
\r
561 eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4
\r
562 eori 32 . d 0000101010000... .......... U U U U 16 14 2 2
\r
563 eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4
\r
564 exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2
\r
565 exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2
\r
566 exg 32 da . 1100...110001... .......... U U U U 6 6 2 2
\r
567 ext 16 . . 0100100010000... .......... U U U U 4 4 4 4
\r
568 ext 32 . . 0100100011000... .......... U U U U 4 4 4 4
\r
569 extb 32 . . 0100100111000... .......... . . U U . . 4 4
\r
570 illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4
\r
571 jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0
\r
572 jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0
\r
573 lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2
\r
574 link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5
\r
575 link 16 . . 0100111001010... .......... U U U U 16 16 5 5
\r
576 link 32 . a7 0100100000001111 .......... . . U U . . 6 6
\r
577 link 32 . . 0100100000001... .......... . . U U . . 6 6
\r
578 lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4
\r
579 lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4
\r
580 lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4
\r
581 lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6
\r
582 lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6
\r
583 lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6
\r
584 lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5
\r
585 lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4
\r
586 lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4
\r
587 lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4
\r
588 lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6
\r
589 lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6
\r
590 lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6
\r
591 lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5
\r
592 move 8 d d 0001...000000... .......... U U U U 4 4 2 2
\r
593 move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
594 move 8 ai d 0001...010000... .......... U U U U 8 8 4 4
\r
595 move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4
\r
596 move 8 pi d 0001...011000... .......... U U U U 8 8 4 4
\r
597 move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4
\r
598 move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4
\r
599 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4
\r
600 move 8 pd d 0001...100000... .......... U U U U 8 8 5 5
\r
601 move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5
\r
602 move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5
\r
603 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5
\r
604 move 8 di d 0001...101000... .......... U U U U 12 12 5 5
\r
605 move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5
\r
606 move 8 ix d 0001...110000... .......... U U U U 14 14 7 7
\r
607 move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7
\r
608 move 8 aw d 0001000111000... .......... U U U U 12 12 4 4
\r
609 move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4
\r
610 move 8 al d 0001001111000... .......... U U U U 16 16 6 6
\r
611 move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6
\r
612 move 16 d d 0011...000000... .......... U U U U 4 4 2 2
\r
613 move 16 d a 0011...000001... .......... U U U U 4 4 2 2
\r
614 move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
615 move 16 ai d 0011...010000... .......... U U U U 8 8 4 4
\r
616 move 16 ai a 0011...010001... .......... U U U U 8 8 4 4
\r
617 move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4
\r
618 move 16 pi d 0011...011000... .......... U U U U 8 8 4 4
\r
619 move 16 pi a 0011...011001... .......... U U U U 8 8 4 4
\r
620 move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4
\r
621 move 16 pd d 0011...100000... .......... U U U U 8 8 5 5
\r
622 move 16 pd a 0011...100001... .......... U U U U 8 8 5 5
\r
623 move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5
\r
624 move 16 di d 0011...101000... .......... U U U U 12 12 5 5
\r
625 move 16 di a 0011...101001... .......... U U U U 12 12 5 5
\r
626 move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5
\r
627 move 16 ix d 0011...110000... .......... U U U U 14 14 7 7
\r
628 move 16 ix a 0011...110001... .......... U U U U 14 14 7 7
\r
629 move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7
\r
630 move 16 aw d 0011000111000... .......... U U U U 12 12 4 4
\r
631 move 16 aw a 0011000111001... .......... U U U U 12 12 4 4
\r
632 move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4
\r
633 move 16 al d 0011001111000... .......... U U U U 16 16 6 6
\r
634 move 16 al a 0011001111001... .......... U U U U 16 16 6 6
\r
635 move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6
\r
636 move 32 d d 0010...000000... .......... U U U U 4 4 2 2
\r
637 move 32 d a 0010...000001... .......... U U U U 4 4 2 2
\r
638 move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
639 move 32 ai d 0010...010000... .......... U U U U 12 12 4 4
\r
640 move 32 ai a 0010...010001... .......... U U U U 12 12 4 4
\r
641 move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4
\r
642 move 32 pi d 0010...011000... .......... U U U U 12 12 4 4
\r
643 move 32 pi a 0010...011001... .......... U U U U 12 12 4 4
\r
644 move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4
\r
645 move 32 pd d 0010...100000... .......... U U U U 12 14 5 5
\r
646 move 32 pd a 0010...100001... .......... U U U U 12 14 5 5
\r
647 move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5
\r
648 move 32 di d 0010...101000... .......... U U U U 16 16 5 5
\r
649 move 32 di a 0010...101001... .......... U U U U 16 16 5 5
\r
650 move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5
\r
651 move 32 ix d 0010...110000... .......... U U U U 18 18 7 7
\r
652 move 32 ix a 0010...110001... .......... U U U U 18 18 7 7
\r
653 move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7
\r
654 move 32 aw d 0010000111000... .......... U U U U 16 16 4 4
\r
655 move 32 aw a 0010000111001... .......... U U U U 16 16 4 4
\r
656 move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4
\r
657 move 32 al d 0010001111000... .......... U U U U 20 20 6 6
\r
658 move 32 al a 0010001111001... .......... U U U U 20 20 6 6
\r
659 move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6
\r
660 movea 16 . d 0011...001000... .......... U U U U 4 4 2 2
\r
661 movea 16 . a 0011...001001... .......... U U U U 4 4 2 2
\r
662 movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
663 movea 32 . d 0010...001000... .......... U U U U 4 4 2 2
\r
664 movea 32 . a 0010...001001... .......... U U U U 4 4 2 2
\r
665 movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
666 move 16 frc d 0100001011000... .......... . U U U . 4 4 4
\r
667 move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4
\r
668 move 16 toc d 0100010011000... .......... U U U U 12 12 4 4
\r
669 move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4
\r
670 move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000
\r
671 move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000
\r
672 move 16 tos d 0100011011000... .......... S S S S 12 12 8 8
\r
673 move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8
\r
674 move 32 fru . 0100111001101... .......... S S S S 4 6 2 2
\r
675 move 32 tou . 0100111001100... .......... S S S S 4 6 2 2
\r
676 movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6
\r
677 movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12
\r
678 movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4
\r
679 movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4
\r
680 movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4
\r
681 movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4
\r
682 movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8
\r
683 movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9
\r
684 movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11
\r
685 movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8
\r
686 movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8
\r
687 movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9
\r
688 movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11
\r
689 movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8
\r
690 movep 16 er . 0000...100001... .......... U U U U 16 16 12 12
\r
691 movep 32 er . 0000...101001... .......... U U U U 24 24 18 18
\r
692 movep 16 re . 0000...110001... .......... U U U U 16 16 11 11
\r
693 movep 32 re . 0000...111001... .......... U U U U 24 24 17 17
\r
694 moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2
\r
695 moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5
\r
696 moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5
\r
697 moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5
\r
698 move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing
\r
699 muls 16 . d 1100...111000... .......... U U U U 54 32 27 27
\r
700 muls 16 . . 1100...111...... A+-DXWLdxI U U U U 54 32 27 27
\r
701 mulu 16 . d 1100...011000... .......... U U U U 54 30 27 27
\r
702 mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 54 30 27 27
\r
703 mull 32 . d 0100110000000... .......... . . U U . . 43 43
\r
704 mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43
\r
705 nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6
\r
706 nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6
\r
707 neg 8 . d 0100010000000... .......... U U U U 4 4 2 2
\r
708 neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4
\r
709 neg 16 . d 0100010001000... .......... U U U U 4 4 2 2
\r
710 neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4
\r
711 neg 32 . d 0100010010000... .......... U U U U 6 6 2 2
\r
712 neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4
\r
713 negx 8 . d 0100000000000... .......... U U U U 4 4 2 2
\r
714 negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4
\r
715 negx 16 . d 0100000001000... .......... U U U U 4 4 2 2
\r
716 negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4
\r
717 negx 32 . d 0100000010000... .......... U U U U 6 6 2 2
\r
718 negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4
\r
719 nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2
\r
720 not 8 . d 0100011000000... .......... U U U U 4 4 2 2
\r
721 not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4
\r
722 not 16 . d 0100011001000... .......... U U U U 4 4 2 2
\r
723 not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4
\r
724 not 32 . d 0100011010000... .......... U U U U 6 6 2 2
\r
725 not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4
\r
726 or 8 er d 1000...000000... .......... U U U U 4 4 2 2
\r
727 or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
728 or 16 er d 1000...001000... .......... U U U U 4 4 2 2
\r
729 or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
730 or 32 er d 1000...010000... .......... U U U U 6 6 2 2
\r
731 or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
732 or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4
\r
733 or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4
\r
734 or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4
\r
735 ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12
\r
736 ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12
\r
737 ori 8 . d 0000000000000... .......... U U U U 8 8 2 2
\r
738 ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4
\r
739 ori 16 . d 0000000001000... .......... U U U U 8 8 2 2
\r
740 ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4
\r
741 ori 32 . d 0000000010000... .......... U U U U 16 14 2 2
\r
742 ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4
\r
743 pack 16 rr . 1000...101000... .......... . . U U . . 6 6
\r
744 pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13
\r
745 pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13
\r
746 pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13
\r
747 pack 16 mm . 1000...101001... .......... . . U U . . 13 13
\r
748 pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5
\r
749 pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing
\r
750 reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0
\r
751 ror 8 s . 1110...000011... .......... U U U U 6 6 8 8
\r
752 ror 16 s . 1110...001011... .......... U U U U 6 6 8 8
\r
753 ror 32 s . 1110...010011... .......... U U U U 8 8 8 8
\r
754 ror 8 r . 1110...000111... .......... U U U U 6 6 8 8
\r
755 ror 16 r . 1110...001111... .......... U U U U 6 6 8 8
\r
756 ror 32 r . 1110...010111... .......... U U U U 8 8 8 8
\r
757 ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7
\r
758 rol 8 s . 1110...100011... .......... U U U U 6 6 8 8
\r
759 rol 16 s . 1110...101011... .......... U U U U 6 6 8 8
\r
760 rol 32 s . 1110...110011... .......... U U U U 8 8 8 8
\r
761 rol 8 r . 1110...100111... .......... U U U U 6 6 8 8
\r
762 rol 16 r . 1110...101111... .......... U U U U 6 6 8 8
\r
763 rol 32 r . 1110...110111... .......... U U U U 8 8 8 8
\r
764 rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7
\r
765 roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12
\r
766 roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12
\r
767 roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12
\r
768 roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12
\r
769 roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12
\r
770 roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12
\r
771 roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5
\r
772 roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12
\r
773 roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12
\r
774 roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12
\r
775 roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12
\r
776 roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12
\r
777 roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12
\r
778 roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5
\r
779 rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10
\r
780 rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated
\r
781 rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated
\r
782 rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14
\r
783 rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10
\r
784 sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4
\r
785 sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16
\r
786 sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16
\r
787 sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16
\r
788 sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16
\r
789 st 8 . d 0101000011000... .......... U U U U 6 4 4 4
\r
790 st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6
\r
791 sf 8 . d 0101000111000... .......... U U U U 4 4 4 4
\r
792 sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6
\r
793 scc 8 . d 0101....11000... .......... U U U U 4 4 4 4
\r
794 scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6
\r
795 stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8
\r
796 sub 8 er d 1001...000000... .......... U U U U 4 4 2 2
\r
797 sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2
\r
798 sub 16 er d 1001...001000... .......... U U U U 4 4 2 2
\r
799 sub 16 er a 1001...001001... .......... U U U U 4 4 2 2
\r
800 sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2
\r
801 sub 32 er d 1001...010000... .......... U U U U 6 6 2 2
\r
802 sub 32 er a 1001...010001... .......... U U U U 6 6 2 2
\r
803 sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2
\r
804 sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4
\r
805 sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4
\r
806 sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4
\r
807 suba 16 . d 1001...011000... .......... U U U U 8 8 2 2
\r
808 suba 16 . a 1001...011001... .......... U U U U 8 8 2 2
\r
809 suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2
\r
810 suba 32 . d 1001...111000... .......... U U U U 6 6 2 2
\r
811 suba 32 . a 1001...111001... .......... U U U U 6 6 2 2
\r
812 suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2
\r
813 subi 8 . d 0000010000000... .......... U U U U 8 8 2 2
\r
814 subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4
\r
815 subi 16 . d 0000010001000... .......... U U U U 8 8 2 2
\r
816 subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4
\r
817 subi 32 . d 0000010010000... .......... U U U U 16 14 2 2
\r
818 subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4
\r
819 subq 8 . d 0101...100000... .......... U U U U 4 4 2 2
\r
820 subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4
\r
821 subq 16 . d 0101...101000... .......... U U U U 4 4 2 2
\r
822 subq 16 . a 0101...101001... .......... U U U U 8 4 2 2
\r
823 subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4
\r
824 subq 32 . d 0101...110000... .......... U U U U 8 8 2 2
\r
825 subq 32 . a 0101...110001... .......... U U U U 8 8 2 2
\r
826 subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4
\r
827 subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2
\r
828 subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2
\r
829 subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2
\r
830 subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12
\r
831 subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12
\r
832 subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12
\r
833 subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12
\r
834 subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12
\r
835 subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12
\r
836 swap 32 . . 0100100001000... .......... U U U U 4 4 4 4
\r
837 tas 8 . d 0100101011000... .......... U U U U 4 4 4 4
\r
838 tas 8 . . 0100101011...... A+-DXWL... U U U U 14 14 12 12
\r
839 trap 0 . . 010011100100.... .......... U U U U 4 4 4 4
\r
840 trapt 0 . . 0101000011111100 .......... . . U U . . 4 4
\r
841 trapt 16 . . 0101000011111010 .......... . . U U . . 6 6
\r
842 trapt 32 . . 0101000011111011 .......... . . U U . . 8 8
\r
843 trapf 0 . . 0101000111111100 .......... . . U U . . 4 4
\r
844 trapf 16 . . 0101000111111010 .......... . . U U . . 6 6
\r
845 trapf 32 . . 0101000111111011 .......... . . U U . . 8 8
\r
846 trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4
\r
847 trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6
\r
848 trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8
\r
849 trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4
\r
850 tst 8 . d 0100101000000... .......... U U U U 4 4 2 2
\r
851 tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2
\r
852 tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7
\r
853 tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9
\r
854 tst 8 . i 0100101000111100 .......... . . U U . . 6 6
\r
855 tst 16 . d 0100101001000... .......... U U U U 4 4 2 2
\r
856 tst 16 . a 0100101001001... .......... . . U U . . 2 2
\r
857 tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2
\r
858 tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7
\r
859 tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9
\r
860 tst 16 . i 0100101001111100 .......... . . U U . . 6 6
\r
861 tst 32 . d 0100101010000... .......... U U U U 4 4 2 2
\r
862 tst 32 . a 0100101010001... .......... . . U U . . 2 2
\r
863 tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2
\r
864 tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7
\r
865 tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9
\r
866 tst 32 . i 0100101010111100 .......... . . U U . . 6 6
\r
867 unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6
\r
868 unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6
\r
869 unpk 16 rr . 1000...110000... .......... . . U U . . 8 8
\r
870 unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13
\r
871 unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13
\r
872 unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13
\r
873 unpk 16 mm . 1000...110001... .......... . . U U . . 13 13
\r
877 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
\r
878 M68KMAKE_OPCODE_HANDLER_BODY
\r
880 M68KMAKE_OP(1010, 0, ., .)
\r
882 m68ki_exception_1010();
\r
886 M68KMAKE_OP(1111, 0, ., .)
\r
888 m68ki_exception_1111();
\r
892 M68KMAKE_OP(040fpu0, 32, ., .)
\r
894 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
899 m68ki_exception_1111();
\r
903 M68KMAKE_OP(040fpu1, 32, ., .)
\r
905 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
910 m68ki_exception_1111();
\r
915 M68KMAKE_OP(abcd, 8, rr, .)
\r
920 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
922 FLAG_V = ~res; /* Undefined V behavior */
\r
926 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
927 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
931 FLAG_V &= res; /* Undefined V behavior part II */
\r
932 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
934 res = MASK_OUT_ABOVE_8(res);
\r
937 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
941 M68KMAKE_OP(abcd, 8, mm, ax7)
\r
943 uint src = OPER_AY_PD_8();
\r
944 uint ea = EA_A7_PD_8();
\r
945 uint dst = m68ki_read_8(ea);
\r
946 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
948 FLAG_V = ~res; /* Undefined V behavior */
\r
952 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
953 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
957 FLAG_V &= res; /* Undefined V behavior part II */
\r
958 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
960 res = MASK_OUT_ABOVE_8(res);
\r
963 m68ki_write_8(ea, res);
\r
967 M68KMAKE_OP(abcd, 8, mm, ay7)
\r
969 uint src = OPER_A7_PD_8();
\r
970 uint ea = EA_AX_PD_8();
\r
971 uint dst = m68ki_read_8(ea);
\r
972 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
974 FLAG_V = ~res; /* Undefined V behavior */
\r
978 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
979 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
983 FLAG_V &= res; /* Undefined V behavior part II */
\r
984 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
986 res = MASK_OUT_ABOVE_8(res);
\r
989 m68ki_write_8(ea, res);
\r
993 M68KMAKE_OP(abcd, 8, mm, axy7)
\r
995 uint src = OPER_A7_PD_8();
\r
996 uint ea = EA_A7_PD_8();
\r
997 uint dst = m68ki_read_8(ea);
\r
998 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
1000 FLAG_V = ~res; /* Undefined V behavior */
\r
1004 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
1005 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
1009 FLAG_V &= res; /* Undefined V behavior part II */
\r
1010 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
1012 res = MASK_OUT_ABOVE_8(res);
\r
1015 m68ki_write_8(ea, res);
\r
1019 M68KMAKE_OP(abcd, 8, mm, .)
\r
1021 uint src = OPER_AY_PD_8();
\r
1022 uint ea = EA_AX_PD_8();
\r
1023 uint dst = m68ki_read_8(ea);
\r
1024 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
1026 FLAG_V = ~res; /* Undefined V behavior */
\r
1030 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
1031 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
1035 FLAG_V &= res; /* Undefined V behavior part II */
\r
1036 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
1038 res = MASK_OUT_ABOVE_8(res);
\r
1041 m68ki_write_8(ea, res);
\r
1045 M68KMAKE_OP(add, 8, er, d)
\r
1047 uint* r_dst = &DX;
\r
1048 uint src = MASK_OUT_ABOVE_8(DY);
\r
1049 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1050 uint res = src + dst;
\r
1052 FLAG_N = NFLAG_8(res);
\r
1053 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1054 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1055 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1057 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1061 M68KMAKE_OP(add, 8, er, .)
\r
1063 uint* r_dst = &DX;
\r
1064 uint src = M68KMAKE_GET_OPER_AY_8;
\r
1065 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1066 uint res = src + dst;
\r
1068 FLAG_N = NFLAG_8(res);
\r
1069 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1070 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1071 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1073 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1077 M68KMAKE_OP(add, 16, er, d)
\r
1079 uint* r_dst = &DX;
\r
1080 uint src = MASK_OUT_ABOVE_16(DY);
\r
1081 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1082 uint res = src + dst;
\r
1084 FLAG_N = NFLAG_16(res);
\r
1085 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1086 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1087 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1089 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1093 M68KMAKE_OP(add, 16, er, a)
\r
1095 uint* r_dst = &DX;
\r
1096 uint src = MASK_OUT_ABOVE_16(AY);
\r
1097 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1098 uint res = src + dst;
\r
1100 FLAG_N = NFLAG_16(res);
\r
1101 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1102 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1103 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1105 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1109 M68KMAKE_OP(add, 16, er, .)
\r
1111 uint* r_dst = &DX;
\r
1112 uint src = M68KMAKE_GET_OPER_AY_16;
\r
1113 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1114 uint res = src + dst;
\r
1116 FLAG_N = NFLAG_16(res);
\r
1117 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1118 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1119 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1121 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1125 M68KMAKE_OP(add, 32, er, d)
\r
1127 uint* r_dst = &DX;
\r
1129 uint dst = *r_dst;
\r
1130 uint res = src + dst;
\r
1132 FLAG_N = NFLAG_32(res);
\r
1133 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1134 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1135 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1141 M68KMAKE_OP(add, 32, er, a)
\r
1143 uint* r_dst = &DX;
\r
1145 uint dst = *r_dst;
\r
1146 uint res = src + dst;
\r
1148 FLAG_N = NFLAG_32(res);
\r
1149 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1150 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1151 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1157 M68KMAKE_OP(add, 32, er, .)
\r
1159 uint* r_dst = &DX;
\r
1160 uint src = M68KMAKE_GET_OPER_AY_32;
\r
1161 uint dst = *r_dst;
\r
1162 uint res = src + dst;
\r
1164 FLAG_N = NFLAG_32(res);
\r
1165 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1166 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1167 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1173 M68KMAKE_OP(add, 8, re, .)
\r
1175 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1176 uint src = MASK_OUT_ABOVE_8(DX);
\r
1177 uint dst = m68ki_read_8(ea);
\r
1178 uint res = src + dst;
\r
1180 FLAG_N = NFLAG_8(res);
\r
1181 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1182 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1183 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1185 m68ki_write_8(ea, FLAG_Z);
\r
1189 M68KMAKE_OP(add, 16, re, .)
\r
1191 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1192 uint src = MASK_OUT_ABOVE_16(DX);
\r
1193 uint dst = m68ki_read_16(ea);
\r
1194 uint res = src + dst;
\r
1196 FLAG_N = NFLAG_16(res);
\r
1197 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1198 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1199 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1201 m68ki_write_16(ea, FLAG_Z);
\r
1205 M68KMAKE_OP(add, 32, re, .)
\r
1207 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1209 uint dst = m68ki_read_32(ea);
\r
1210 uint res = src + dst;
\r
1212 FLAG_N = NFLAG_32(res);
\r
1213 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1214 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1215 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1217 m68ki_write_32(ea, FLAG_Z);
\r
1221 M68KMAKE_OP(adda, 16, ., d)
\r
1223 uint* r_dst = &AX;
\r
1225 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
\r
1229 M68KMAKE_OP(adda, 16, ., a)
\r
1231 uint* r_dst = &AX;
\r
1233 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
\r
1237 M68KMAKE_OP(adda, 16, ., .)
\r
1239 uint* r_dst = &AX;
\r
1240 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
1242 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
\r
1246 M68KMAKE_OP(adda, 32, ., d)
\r
1248 uint* r_dst = &AX;
\r
1250 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
\r
1254 M68KMAKE_OP(adda, 32, ., a)
\r
1256 uint* r_dst = &AX;
\r
1258 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
\r
1262 M68KMAKE_OP(adda, 32, ., .)
\r
1264 uint* r_dst = &AX;
\r
1266 *r_dst = MASK_OUT_ABOVE_32(*r_dst + M68KMAKE_GET_OPER_AY_32);
\r
1270 M68KMAKE_OP(addi, 8, ., d)
\r
1272 uint* r_dst = &DY;
\r
1273 uint src = OPER_I_8();
\r
1274 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1275 uint res = src + dst;
\r
1277 FLAG_N = NFLAG_8(res);
\r
1278 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1279 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1280 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1282 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1286 M68KMAKE_OP(addi, 8, ., .)
\r
1288 uint src = OPER_I_8();
\r
1289 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1290 uint dst = m68ki_read_8(ea);
\r
1291 uint res = src + dst;
\r
1293 FLAG_N = NFLAG_8(res);
\r
1294 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1295 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1296 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1298 m68ki_write_8(ea, FLAG_Z);
\r
1302 M68KMAKE_OP(addi, 16, ., d)
\r
1304 uint* r_dst = &DY;
\r
1305 uint src = OPER_I_16();
\r
1306 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1307 uint res = src + dst;
\r
1309 FLAG_N = NFLAG_16(res);
\r
1310 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1311 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1312 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1314 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1318 M68KMAKE_OP(addi, 16, ., .)
\r
1320 uint src = OPER_I_16();
\r
1321 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1322 uint dst = m68ki_read_16(ea);
\r
1323 uint res = src + dst;
\r
1325 FLAG_N = NFLAG_16(res);
\r
1326 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1327 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1328 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1330 m68ki_write_16(ea, FLAG_Z);
\r
1334 M68KMAKE_OP(addi, 32, ., d)
\r
1336 uint* r_dst = &DY;
\r
1337 uint src = OPER_I_32();
\r
1338 uint dst = *r_dst;
\r
1339 uint res = src + dst;
\r
1341 FLAG_N = NFLAG_32(res);
\r
1342 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1343 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1344 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1350 M68KMAKE_OP(addi, 32, ., .)
\r
1352 uint src = OPER_I_32();
\r
1353 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1354 uint dst = m68ki_read_32(ea);
\r
1355 uint res = src + dst;
\r
1357 FLAG_N = NFLAG_32(res);
\r
1358 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1359 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1360 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1362 m68ki_write_32(ea, FLAG_Z);
\r
1366 M68KMAKE_OP(addq, 8, ., d)
\r
1368 uint* r_dst = &DY;
\r
1369 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1370 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1371 uint res = src + dst;
\r
1373 FLAG_N = NFLAG_8(res);
\r
1374 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1375 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1376 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1378 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1382 M68KMAKE_OP(addq, 8, ., .)
\r
1384 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1385 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1386 uint dst = m68ki_read_8(ea);
\r
1387 uint res = src + dst;
\r
1389 FLAG_N = NFLAG_8(res);
\r
1390 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1391 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1392 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1394 m68ki_write_8(ea, FLAG_Z);
\r
1398 M68KMAKE_OP(addq, 16, ., d)
\r
1400 uint* r_dst = &DY;
\r
1401 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1402 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1403 uint res = src + dst;
\r
1405 FLAG_N = NFLAG_16(res);
\r
1406 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1407 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1408 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1410 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1414 M68KMAKE_OP(addq, 16, ., a)
\r
1416 uint* r_dst = &AY;
\r
1418 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
\r
1422 M68KMAKE_OP(addq, 16, ., .)
\r
1424 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1425 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1426 uint dst = m68ki_read_16(ea);
\r
1427 uint res = src + dst;
\r
1429 FLAG_N = NFLAG_16(res);
\r
1430 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1431 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1432 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1434 m68ki_write_16(ea, FLAG_Z);
\r
1438 M68KMAKE_OP(addq, 32, ., d)
\r
1440 uint* r_dst = &DY;
\r
1441 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1442 uint dst = *r_dst;
\r
1443 uint res = src + dst;
\r
1445 FLAG_N = NFLAG_32(res);
\r
1446 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1447 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1448 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1454 M68KMAKE_OP(addq, 32, ., a)
\r
1456 uint* r_dst = &AY;
\r
1458 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
\r
1462 M68KMAKE_OP(addq, 32, ., .)
\r
1464 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1465 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1466 uint dst = m68ki_read_32(ea);
\r
1467 uint res = src + dst;
\r
1470 FLAG_N = NFLAG_32(res);
\r
1471 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1472 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1473 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1475 m68ki_write_32(ea, FLAG_Z);
\r
1479 M68KMAKE_OP(addx, 8, rr, .)
\r
1481 uint* r_dst = &DX;
\r
1482 uint src = MASK_OUT_ABOVE_8(DY);
\r
1483 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1484 uint res = src + dst + XFLAG_AS_1();
\r
1486 FLAG_N = NFLAG_8(res);
\r
1487 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1488 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1490 res = MASK_OUT_ABOVE_8(res);
\r
1493 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1497 M68KMAKE_OP(addx, 16, rr, .)
\r
1499 uint* r_dst = &DX;
\r
1500 uint src = MASK_OUT_ABOVE_16(DY);
\r
1501 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1502 uint res = src + dst + XFLAG_AS_1();
\r
1504 FLAG_N = NFLAG_16(res);
\r
1505 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1506 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1508 res = MASK_OUT_ABOVE_16(res);
\r
1511 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1515 M68KMAKE_OP(addx, 32, rr, .)
\r
1517 uint* r_dst = &DX;
\r
1519 uint dst = *r_dst;
\r
1520 uint res = src + dst + XFLAG_AS_1();
\r
1522 FLAG_N = NFLAG_32(res);
\r
1523 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1524 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1526 res = MASK_OUT_ABOVE_32(res);
\r
1533 M68KMAKE_OP(addx, 8, mm, ax7)
\r
1535 uint src = OPER_AY_PD_8();
\r
1536 uint ea = EA_A7_PD_8();
\r
1537 uint dst = m68ki_read_8(ea);
\r
1538 uint res = src + dst + XFLAG_AS_1();
\r
1540 FLAG_N = NFLAG_8(res);
\r
1541 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1542 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1544 res = MASK_OUT_ABOVE_8(res);
\r
1547 m68ki_write_8(ea, res);
\r
1551 M68KMAKE_OP(addx, 8, mm, ay7)
\r
1553 uint src = OPER_A7_PD_8();
\r
1554 uint ea = EA_AX_PD_8();
\r
1555 uint dst = m68ki_read_8(ea);
\r
1556 uint res = src + dst + XFLAG_AS_1();
\r
1558 FLAG_N = NFLAG_8(res);
\r
1559 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1560 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1562 res = MASK_OUT_ABOVE_8(res);
\r
1565 m68ki_write_8(ea, res);
\r
1569 M68KMAKE_OP(addx, 8, mm, axy7)
\r
1571 uint src = OPER_A7_PD_8();
\r
1572 uint ea = EA_A7_PD_8();
\r
1573 uint dst = m68ki_read_8(ea);
\r
1574 uint res = src + dst + XFLAG_AS_1();
\r
1576 FLAG_N = NFLAG_8(res);
\r
1577 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1578 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1580 res = MASK_OUT_ABOVE_8(res);
\r
1583 m68ki_write_8(ea, res);
\r
1587 M68KMAKE_OP(addx, 8, mm, .)
\r
1589 uint src = OPER_AY_PD_8();
\r
1590 uint ea = EA_AX_PD_8();
\r
1591 uint dst = m68ki_read_8(ea);
\r
1592 uint res = src + dst + XFLAG_AS_1();
\r
1594 FLAG_N = NFLAG_8(res);
\r
1595 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1596 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1598 res = MASK_OUT_ABOVE_8(res);
\r
1601 m68ki_write_8(ea, res);
\r
1605 M68KMAKE_OP(addx, 16, mm, .)
\r
1607 uint src = OPER_AY_PD_16();
\r
1608 uint ea = EA_AX_PD_16();
\r
1609 uint dst = m68ki_read_16(ea);
\r
1610 uint res = src + dst + XFLAG_AS_1();
\r
1612 FLAG_N = NFLAG_16(res);
\r
1613 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1614 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1616 res = MASK_OUT_ABOVE_16(res);
\r
1619 m68ki_write_16(ea, res);
\r
1623 M68KMAKE_OP(addx, 32, mm, .)
\r
1625 uint src = OPER_AY_PD_32();
\r
1626 uint ea = EA_AX_PD_32();
\r
1627 uint dst = m68ki_read_32(ea);
\r
1628 uint res = src + dst + XFLAG_AS_1();
\r
1630 FLAG_N = NFLAG_32(res);
\r
1631 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1632 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1634 res = MASK_OUT_ABOVE_32(res);
\r
1637 m68ki_write_32(ea, res);
\r
1641 M68KMAKE_OP(and, 8, er, d)
\r
1643 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
\r
1645 FLAG_N = NFLAG_8(FLAG_Z);
\r
1646 FLAG_C = CFLAG_CLEAR;
\r
1647 FLAG_V = VFLAG_CLEAR;
\r
1651 M68KMAKE_OP(and, 8, er, .)
\r
1653 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
\r
1655 FLAG_N = NFLAG_8(FLAG_Z);
\r
1656 FLAG_C = CFLAG_CLEAR;
\r
1657 FLAG_V = VFLAG_CLEAR;
\r
1661 M68KMAKE_OP(and, 16, er, d)
\r
1663 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
\r
1665 FLAG_N = NFLAG_16(FLAG_Z);
\r
1666 FLAG_C = CFLAG_CLEAR;
\r
1667 FLAG_V = VFLAG_CLEAR;
\r
1671 M68KMAKE_OP(and, 16, er, .)
\r
1673 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
\r
1675 FLAG_N = NFLAG_16(FLAG_Z);
\r
1676 FLAG_C = CFLAG_CLEAR;
\r
1677 FLAG_V = VFLAG_CLEAR;
\r
1681 M68KMAKE_OP(and, 32, er, d)
\r
1683 FLAG_Z = DX &= DY;
\r
1685 FLAG_N = NFLAG_32(FLAG_Z);
\r
1686 FLAG_C = CFLAG_CLEAR;
\r
1687 FLAG_V = VFLAG_CLEAR;
\r
1691 M68KMAKE_OP(and, 32, er, .)
\r
1693 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
\r
1695 FLAG_N = NFLAG_32(FLAG_Z);
\r
1696 FLAG_C = CFLAG_CLEAR;
\r
1697 FLAG_V = VFLAG_CLEAR;
\r
1701 M68KMAKE_OP(and, 8, re, .)
\r
1703 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1704 uint res = DX & m68ki_read_8(ea);
\r
1706 FLAG_N = NFLAG_8(res);
\r
1707 FLAG_C = CFLAG_CLEAR;
\r
1708 FLAG_V = VFLAG_CLEAR;
\r
1709 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1711 m68ki_write_8(ea, FLAG_Z);
\r
1715 M68KMAKE_OP(and, 16, re, .)
\r
1717 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1718 uint res = DX & m68ki_read_16(ea);
\r
1720 FLAG_N = NFLAG_16(res);
\r
1721 FLAG_C = CFLAG_CLEAR;
\r
1722 FLAG_V = VFLAG_CLEAR;
\r
1723 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1725 m68ki_write_16(ea, FLAG_Z);
\r
1729 M68KMAKE_OP(and, 32, re, .)
\r
1731 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1732 uint res = DX & m68ki_read_32(ea);
\r
1734 FLAG_N = NFLAG_32(res);
\r
1736 FLAG_C = CFLAG_CLEAR;
\r
1737 FLAG_V = VFLAG_CLEAR;
\r
1739 m68ki_write_32(ea, res);
\r
1743 M68KMAKE_OP(andi, 8, ., d)
\r
1745 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
\r
1747 FLAG_N = NFLAG_8(FLAG_Z);
\r
1748 FLAG_C = CFLAG_CLEAR;
\r
1749 FLAG_V = VFLAG_CLEAR;
\r
1753 M68KMAKE_OP(andi, 8, ., .)
\r
1755 uint src = OPER_I_8();
\r
1756 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1757 uint res = src & m68ki_read_8(ea);
\r
1759 FLAG_N = NFLAG_8(res);
\r
1761 FLAG_C = CFLAG_CLEAR;
\r
1762 FLAG_V = VFLAG_CLEAR;
\r
1764 m68ki_write_8(ea, res);
\r
1768 M68KMAKE_OP(andi, 16, ., d)
\r
1770 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
\r
1772 FLAG_N = NFLAG_16(FLAG_Z);
\r
1773 FLAG_C = CFLAG_CLEAR;
\r
1774 FLAG_V = VFLAG_CLEAR;
\r
1778 M68KMAKE_OP(andi, 16, ., .)
\r
1780 uint src = OPER_I_16();
\r
1781 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1782 uint res = src & m68ki_read_16(ea);
\r
1784 FLAG_N = NFLAG_16(res);
\r
1786 FLAG_C = CFLAG_CLEAR;
\r
1787 FLAG_V = VFLAG_CLEAR;
\r
1789 m68ki_write_16(ea, res);
\r
1793 M68KMAKE_OP(andi, 32, ., d)
\r
1795 FLAG_Z = DY &= (OPER_I_32());
\r
1797 FLAG_N = NFLAG_32(FLAG_Z);
\r
1798 FLAG_C = CFLAG_CLEAR;
\r
1799 FLAG_V = VFLAG_CLEAR;
\r
1803 M68KMAKE_OP(andi, 32, ., .)
\r
1805 uint src = OPER_I_32();
\r
1806 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1807 uint res = src & m68ki_read_32(ea);
\r
1809 FLAG_N = NFLAG_32(res);
\r
1811 FLAG_C = CFLAG_CLEAR;
\r
1812 FLAG_V = VFLAG_CLEAR;
\r
1814 m68ki_write_32(ea, res);
\r
1818 M68KMAKE_OP(andi, 16, toc, .)
\r
1820 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
\r
1824 M68KMAKE_OP(andi, 16, tos, .)
\r
1828 uint src = OPER_I_16();
\r
1829 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
1830 m68ki_set_sr(m68ki_get_sr() & src);
\r
1833 m68ki_exception_privilege_violation();
\r
1837 M68KMAKE_OP(asr, 8, s, .)
\r
1839 uint* r_dst = &DY;
\r
1840 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1841 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
1842 uint res = src >> shift;
\r
1845 USE_CYCLES(shift<<CYC_SHIFT);
\r
1847 if(GET_MSB_8(src))
\r
1848 res |= m68ki_shift_8_table[shift];
\r
1850 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1852 FLAG_N = NFLAG_8(res);
\r
1854 FLAG_V = VFLAG_CLEAR;
\r
1855 FLAG_X = FLAG_C = src << (9-shift);
\r
1859 M68KMAKE_OP(asr, 16, s, .)
\r
1861 uint* r_dst = &DY;
\r
1862 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1863 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
1864 uint res = src >> shift;
\r
1867 USE_CYCLES(shift<<CYC_SHIFT);
\r
1869 if(GET_MSB_16(src))
\r
1870 res |= m68ki_shift_16_table[shift];
\r
1872 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1874 FLAG_N = NFLAG_16(res);
\r
1876 FLAG_V = VFLAG_CLEAR;
\r
1877 FLAG_X = FLAG_C = src << (9-shift);
\r
1881 M68KMAKE_OP(asr, 32, s, .)
\r
1883 uint* r_dst = &DY;
\r
1884 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1885 uint src = *r_dst;
\r
1886 uint res = src >> shift;
\r
1889 USE_CYCLES(shift<<CYC_SHIFT);
\r
1891 if(GET_MSB_32(src))
\r
1892 res |= m68ki_shift_32_table[shift];
\r
1896 FLAG_N = NFLAG_32(res);
\r
1898 FLAG_V = VFLAG_CLEAR;
\r
1899 FLAG_X = FLAG_C = src << (9-shift);
\r
1903 M68KMAKE_OP(asr, 8, r, .)
\r
1905 uint* r_dst = &DY;
\r
1906 uint shift = DX & 0x3f;
\r
1907 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
1908 uint res = src >> shift;
\r
1912 USE_CYCLES(shift<<CYC_SHIFT);
\r
1916 if(GET_MSB_8(src))
\r
1917 res |= m68ki_shift_8_table[shift];
\r
1919 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1921 FLAG_X = FLAG_C = src << (9-shift);
\r
1922 FLAG_N = NFLAG_8(res);
\r
1924 FLAG_V = VFLAG_CLEAR;
\r
1928 if(GET_MSB_8(src))
\r
1931 FLAG_C = CFLAG_SET;
\r
1932 FLAG_X = XFLAG_SET;
\r
1933 FLAG_N = NFLAG_SET;
\r
1934 FLAG_Z = ZFLAG_CLEAR;
\r
1935 FLAG_V = VFLAG_CLEAR;
\r
1939 *r_dst &= 0xffffff00;
\r
1940 FLAG_C = CFLAG_CLEAR;
\r
1941 FLAG_X = XFLAG_CLEAR;
\r
1942 FLAG_N = NFLAG_CLEAR;
\r
1943 FLAG_Z = ZFLAG_SET;
\r
1944 FLAG_V = VFLAG_CLEAR;
\r
1948 FLAG_C = CFLAG_CLEAR;
\r
1949 FLAG_N = NFLAG_8(src);
\r
1951 FLAG_V = VFLAG_CLEAR;
\r
1955 M68KMAKE_OP(asr, 16, r, .)
\r
1957 uint* r_dst = &DY;
\r
1958 uint shift = DX & 0x3f;
\r
1959 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
1960 uint res = src >> shift;
\r
1964 USE_CYCLES(shift<<CYC_SHIFT);
\r
1968 if(GET_MSB_16(src))
\r
1969 res |= m68ki_shift_16_table[shift];
\r
1971 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1973 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
1974 FLAG_N = NFLAG_16(res);
\r
1976 FLAG_V = VFLAG_CLEAR;
\r
1980 if(GET_MSB_16(src))
\r
1983 FLAG_C = CFLAG_SET;
\r
1984 FLAG_X = XFLAG_SET;
\r
1985 FLAG_N = NFLAG_SET;
\r
1986 FLAG_Z = ZFLAG_CLEAR;
\r
1987 FLAG_V = VFLAG_CLEAR;
\r
1991 *r_dst &= 0xffff0000;
\r
1992 FLAG_C = CFLAG_CLEAR;
\r
1993 FLAG_X = XFLAG_CLEAR;
\r
1994 FLAG_N = NFLAG_CLEAR;
\r
1995 FLAG_Z = ZFLAG_SET;
\r
1996 FLAG_V = VFLAG_CLEAR;
\r
2000 FLAG_C = CFLAG_CLEAR;
\r
2001 FLAG_N = NFLAG_16(src);
\r
2003 FLAG_V = VFLAG_CLEAR;
\r
2007 M68KMAKE_OP(asr, 32, r, .)
\r
2009 uint* r_dst = &DY;
\r
2010 uint shift = DX & 0x3f;
\r
2011 uint src = *r_dst;
\r
2012 uint res = src >> shift;
\r
2016 USE_CYCLES(shift<<CYC_SHIFT);
\r
2020 if(GET_MSB_32(src))
\r
2021 res |= m68ki_shift_32_table[shift];
\r
2025 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
2026 FLAG_N = NFLAG_32(res);
\r
2028 FLAG_V = VFLAG_CLEAR;
\r
2032 if(GET_MSB_32(src))
\r
2034 *r_dst = 0xffffffff;
\r
2035 FLAG_C = CFLAG_SET;
\r
2036 FLAG_X = XFLAG_SET;
\r
2037 FLAG_N = NFLAG_SET;
\r
2038 FLAG_Z = ZFLAG_CLEAR;
\r
2039 FLAG_V = VFLAG_CLEAR;
\r
2044 FLAG_C = CFLAG_CLEAR;
\r
2045 FLAG_X = XFLAG_CLEAR;
\r
2046 FLAG_N = NFLAG_CLEAR;
\r
2047 FLAG_Z = ZFLAG_SET;
\r
2048 FLAG_V = VFLAG_CLEAR;
\r
2052 FLAG_C = CFLAG_CLEAR;
\r
2053 FLAG_N = NFLAG_32(src);
\r
2055 FLAG_V = VFLAG_CLEAR;
\r
2059 M68KMAKE_OP(asr, 16, ., .)
\r
2061 uint ea = M68KMAKE_GET_EA_AY_16;
\r
2062 uint src = m68ki_read_16(ea);
\r
2063 uint res = src >> 1;
\r
2065 if(GET_MSB_16(src))
\r
2068 m68ki_write_16(ea, res);
\r
2070 FLAG_N = NFLAG_16(res);
\r
2072 FLAG_V = VFLAG_CLEAR;
\r
2073 FLAG_C = FLAG_X = src << 8;
\r
2077 M68KMAKE_OP(asl, 8, s, .)
\r
2079 uint* r_dst = &DY;
\r
2080 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2081 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
2082 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
2085 USE_CYCLES(shift<<CYC_SHIFT);
\r
2087 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
2089 FLAG_X = FLAG_C = src << shift;
\r
2090 FLAG_N = NFLAG_8(res);
\r
2092 src &= m68ki_shift_8_table[shift + 1];
\r
2093 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
\r
2097 M68KMAKE_OP(asl, 16, s, .)
\r
2099 uint* r_dst = &DY;
\r
2100 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2101 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
2102 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
2105 USE_CYCLES(shift<<CYC_SHIFT);
\r
2107 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
2109 FLAG_N = NFLAG_16(res);
\r
2111 FLAG_X = FLAG_C = src >> (8-shift);
\r
2112 src &= m68ki_shift_16_table[shift + 1];
\r
2113 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
\r
2117 M68KMAKE_OP(asl, 32, s, .)
\r
2119 uint* r_dst = &DY;
\r
2120 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2121 uint src = *r_dst;
\r
2122 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
2125 USE_CYCLES(shift<<CYC_SHIFT);
\r
2129 FLAG_N = NFLAG_32(res);
\r
2131 FLAG_X = FLAG_C = src >> (24-shift);
\r
2132 src &= m68ki_shift_32_table[shift + 1];
\r
2133 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
\r
2137 M68KMAKE_OP(asl, 8, r, .)
\r
2139 uint* r_dst = &DY;
\r
2140 uint shift = DX & 0x3f;
\r
2141 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
2142 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
2146 USE_CYCLES(shift<<CYC_SHIFT);
\r
2150 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
2151 FLAG_X = FLAG_C = src << shift;
\r
2152 FLAG_N = NFLAG_8(res);
\r
2154 src &= m68ki_shift_8_table[shift + 1];
\r
2155 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
\r
2159 *r_dst &= 0xffffff00;
\r
2160 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
\r
2161 FLAG_N = NFLAG_CLEAR;
\r
2162 FLAG_Z = ZFLAG_SET;
\r
2163 FLAG_V = (!(src == 0))<<7;
\r
2167 FLAG_C = CFLAG_CLEAR;
\r
2168 FLAG_N = NFLAG_8(src);
\r
2170 FLAG_V = VFLAG_CLEAR;
\r
2174 M68KMAKE_OP(asl, 16, r, .)
\r
2176 uint* r_dst = &DY;
\r
2177 uint shift = DX & 0x3f;
\r
2178 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
2179 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
2183 USE_CYCLES(shift<<CYC_SHIFT);
\r
2187 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
2188 FLAG_X = FLAG_C = (src << shift) >> 8;
\r
2189 FLAG_N = NFLAG_16(res);
\r
2191 src &= m68ki_shift_16_table[shift + 1];
\r
2192 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
\r
2196 *r_dst &= 0xffff0000;
\r
2197 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
\r
2198 FLAG_N = NFLAG_CLEAR;
\r
2199 FLAG_Z = ZFLAG_SET;
\r
2200 FLAG_V = (!(src == 0))<<7;
\r
2204 FLAG_C = CFLAG_CLEAR;
\r
2205 FLAG_N = NFLAG_16(src);
\r
2207 FLAG_V = VFLAG_CLEAR;
\r
2211 M68KMAKE_OP(asl, 32, r, .)
\r
2213 uint* r_dst = &DY;
\r
2214 uint shift = DX & 0x3f;
\r
2215 uint src = *r_dst;
\r
2216 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
2220 USE_CYCLES(shift<<CYC_SHIFT);
\r
2225 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
\r
2226 FLAG_N = NFLAG_32(res);
\r
2228 src &= m68ki_shift_32_table[shift + 1];
\r
2229 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
\r
2234 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
\r
2235 FLAG_N = NFLAG_CLEAR;
\r
2236 FLAG_Z = ZFLAG_SET;
\r
2237 FLAG_V = (!(src == 0))<<7;
\r
2241 FLAG_C = CFLAG_CLEAR;
\r
2242 FLAG_N = NFLAG_32(src);
\r
2244 FLAG_V = VFLAG_CLEAR;
\r
2248 M68KMAKE_OP(asl, 16, ., .)
\r
2250 uint ea = M68KMAKE_GET_EA_AY_16;
\r
2251 uint src = m68ki_read_16(ea);
\r
2252 uint res = MASK_OUT_ABOVE_16(src << 1);
\r
2254 m68ki_write_16(ea, res);
\r
2256 FLAG_N = NFLAG_16(res);
\r
2258 FLAG_X = FLAG_C = src >> 7;
\r
2260 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
\r
2264 M68KMAKE_OP(bcc, 8, ., .)
\r
2268 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2269 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
2272 USE_CYCLES(CYC_BCC_NOTAKE_B);
\r
2276 M68KMAKE_OP(bcc, 16, ., .)
\r
2280 uint offset = OPER_I_16();
\r
2282 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2283 m68ki_branch_16(offset);
\r
2287 USE_CYCLES(CYC_BCC_NOTAKE_W);
\r
2291 M68KMAKE_OP(bcc, 32, ., .)
\r
2293 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2297 uint offset = OPER_I_32();
\r
2299 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2300 m68ki_branch_32(offset);
\r
2310 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2311 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
2314 USE_CYCLES(CYC_BCC_NOTAKE_B);
\r
2319 M68KMAKE_OP(bchg, 32, r, d)
\r
2321 uint* r_dst = &DY;
\r
2322 uint mask = 1 << (DX & 0x1f);
\r
2324 FLAG_Z = *r_dst & mask;
\r
2329 M68KMAKE_OP(bchg, 8, r, .)
\r
2331 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2332 uint src = m68ki_read_8(ea);
\r
2333 uint mask = 1 << (DX & 7);
\r
2335 FLAG_Z = src & mask;
\r
2336 m68ki_write_8(ea, src ^ mask);
\r
2340 M68KMAKE_OP(bchg, 32, s, d)
\r
2342 uint* r_dst = &DY;
\r
2343 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
2345 FLAG_Z = *r_dst & mask;
\r
2350 M68KMAKE_OP(bchg, 8, s, .)
\r
2352 uint mask = 1 << (OPER_I_8() & 7);
\r
2353 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2354 uint src = m68ki_read_8(ea);
\r
2356 FLAG_Z = src & mask;
\r
2357 m68ki_write_8(ea, src ^ mask);
\r
2361 M68KMAKE_OP(bclr, 32, r, d)
\r
2363 uint* r_dst = &DY;
\r
2364 uint mask = 1 << (DX & 0x1f);
\r
2366 FLAG_Z = *r_dst & mask;
\r
2371 M68KMAKE_OP(bclr, 8, r, .)
\r
2373 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2374 uint src = m68ki_read_8(ea);
\r
2375 uint mask = 1 << (DX & 7);
\r
2377 FLAG_Z = src & mask;
\r
2378 m68ki_write_8(ea, src & ~mask);
\r
2382 M68KMAKE_OP(bclr, 32, s, d)
\r
2384 uint* r_dst = &DY;
\r
2385 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
2387 FLAG_Z = *r_dst & mask;
\r
2392 M68KMAKE_OP(bclr, 8, s, .)
\r
2394 uint mask = 1 << (OPER_I_8() & 7);
\r
2395 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2396 uint src = m68ki_read_8(ea);
\r
2398 FLAG_Z = src & mask;
\r
2399 m68ki_write_8(ea, src & ~mask);
\r
2403 M68KMAKE_OP(bfchg, 32, ., d)
\r
2405 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2407 uint word2 = OPER_I_16();
\r
2408 uint offset = (word2>>6)&31;
\r
2409 uint width = word2;
\r
2415 offset = REG_D[offset&7];
\r
2417 width = REG_D[width&7];
\r
2420 width = ((width-1) & 31) + 1;
\r
2422 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2423 mask = ROR_32(mask, offset);
\r
2425 FLAG_N = NFLAG_32(*data<<offset);
\r
2426 FLAG_Z = *data & mask;
\r
2427 FLAG_V = VFLAG_CLEAR;
\r
2428 FLAG_C = CFLAG_CLEAR;
\r
2434 m68ki_exception_illegal();
\r
2438 M68KMAKE_OP(bfchg, 32, ., .)
\r
2440 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2442 uint word2 = OPER_I_16();
\r
2443 sint offset = (word2>>6)&31;
\r
2444 uint width = word2;
\r
2448 uint data_byte = 0;
\r
2449 uint mask_byte = 0;
\r
2450 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2454 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2456 width = REG_D[width&7];
\r
2458 /* Offset is signed so we have to use ugly math =( */
\r
2466 width = ((width-1) & 31) + 1;
\r
2468 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2469 mask_long = mask_base >> offset;
\r
2471 data_long = m68ki_read_32(ea);
\r
2472 FLAG_N = NFLAG_32(data_long << offset);
\r
2473 FLAG_Z = data_long & mask_long;
\r
2474 FLAG_V = VFLAG_CLEAR;
\r
2475 FLAG_C = CFLAG_CLEAR;
\r
2477 m68ki_write_32(ea, data_long ^ mask_long);
\r
2479 if((width + offset) > 32)
\r
2481 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2482 data_byte = m68ki_read_8(ea+4);
\r
2483 FLAG_Z |= (data_byte & mask_byte);
\r
2484 m68ki_write_8(ea+4, data_byte ^ mask_byte);
\r
2488 m68ki_exception_illegal();
\r
2492 M68KMAKE_OP(bfclr, 32, ., d)
\r
2494 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2496 uint word2 = OPER_I_16();
\r
2497 uint offset = (word2>>6)&31;
\r
2498 uint width = word2;
\r
2504 offset = REG_D[offset&7];
\r
2506 width = REG_D[width&7];
\r
2510 width = ((width-1) & 31) + 1;
\r
2513 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2514 mask = ROR_32(mask, offset);
\r
2516 FLAG_N = NFLAG_32(*data<<offset);
\r
2517 FLAG_Z = *data & mask;
\r
2518 FLAG_V = VFLAG_CLEAR;
\r
2519 FLAG_C = CFLAG_CLEAR;
\r
2525 m68ki_exception_illegal();
\r
2529 M68KMAKE_OP(bfclr, 32, ., .)
\r
2531 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2533 uint word2 = OPER_I_16();
\r
2534 sint offset = (word2>>6)&31;
\r
2535 uint width = word2;
\r
2539 uint data_byte = 0;
\r
2540 uint mask_byte = 0;
\r
2541 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2545 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2547 width = REG_D[width&7];
\r
2549 /* Offset is signed so we have to use ugly math =( */
\r
2557 width = ((width-1) & 31) + 1;
\r
2559 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2560 mask_long = mask_base >> offset;
\r
2562 data_long = m68ki_read_32(ea);
\r
2563 FLAG_N = NFLAG_32(data_long << offset);
\r
2564 FLAG_Z = data_long & mask_long;
\r
2565 FLAG_V = VFLAG_CLEAR;
\r
2566 FLAG_C = CFLAG_CLEAR;
\r
2568 m68ki_write_32(ea, data_long & ~mask_long);
\r
2570 if((width + offset) > 32)
\r
2572 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2573 data_byte = m68ki_read_8(ea+4);
\r
2574 FLAG_Z |= (data_byte & mask_byte);
\r
2575 m68ki_write_8(ea+4, data_byte & ~mask_byte);
\r
2579 m68ki_exception_illegal();
\r
2583 M68KMAKE_OP(bfexts, 32, ., d)
\r
2585 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2587 uint word2 = OPER_I_16();
\r
2588 uint offset = (word2>>6)&31;
\r
2589 uint width = word2;
\r
2594 offset = REG_D[offset&7];
\r
2596 width = REG_D[width&7];
\r
2599 width = ((width-1) & 31) + 1;
\r
2601 data = ROL_32(data, offset);
\r
2602 FLAG_N = NFLAG_32(data);
\r
2603 data = MAKE_INT_32(data) >> (32 - width);
\r
2606 FLAG_V = VFLAG_CLEAR;
\r
2607 FLAG_C = CFLAG_CLEAR;
\r
2609 REG_D[(word2>>12)&7] = data;
\r
2613 m68ki_exception_illegal();
\r
2617 M68KMAKE_OP(bfexts, 32, ., .)
\r
2619 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2621 uint word2 = OPER_I_16();
\r
2622 sint offset = (word2>>6)&31;
\r
2623 uint width = word2;
\r
2625 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2629 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2631 width = REG_D[width&7];
\r
2633 /* Offset is signed so we have to use ugly math =( */
\r
2641 width = ((width-1) & 31) + 1;
\r
2643 data = m68ki_read_32(ea);
\r
2645 data = MASK_OUT_ABOVE_32(data<<offset);
\r
2647 if((offset+width) > 32)
\r
2648 data |= (m68ki_read_8(ea+4) << offset) >> 8;
\r
2650 FLAG_N = NFLAG_32(data);
\r
2651 data = MAKE_INT_32(data) >> (32 - width);
\r
2654 FLAG_V = VFLAG_CLEAR;
\r
2655 FLAG_C = CFLAG_CLEAR;
\r
2657 REG_D[(word2 >> 12) & 7] = data;
\r
2661 m68ki_exception_illegal();
\r
2665 M68KMAKE_OP(bfextu, 32, ., d)
\r
2667 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2669 uint word2 = OPER_I_16();
\r
2670 uint offset = (word2>>6)&31;
\r
2671 uint width = word2;
\r
2676 offset = REG_D[offset&7];
\r
2678 width = REG_D[width&7];
\r
2681 width = ((width-1) & 31) + 1;
\r
2683 data = ROL_32(data, offset);
\r
2684 FLAG_N = NFLAG_32(data);
\r
2685 data >>= 32 - width;
\r
2688 FLAG_V = VFLAG_CLEAR;
\r
2689 FLAG_C = CFLAG_CLEAR;
\r
2691 REG_D[(word2>>12)&7] = data;
\r
2695 m68ki_exception_illegal();
\r
2699 M68KMAKE_OP(bfextu, 32, ., .)
\r
2701 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2703 uint word2 = OPER_I_16();
\r
2704 sint offset = (word2>>6)&31;
\r
2705 uint width = word2;
\r
2707 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2711 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2713 width = REG_D[width&7];
\r
2715 /* Offset is signed so we have to use ugly math =( */
\r
2723 width = ((width-1) & 31) + 1;
\r
2725 data = m68ki_read_32(ea);
\r
2726 data = MASK_OUT_ABOVE_32(data<<offset);
\r
2728 if((offset+width) > 32)
\r
2729 data |= (m68ki_read_8(ea+4) << offset) >> 8;
\r
2731 FLAG_N = NFLAG_32(data);
\r
2732 data >>= (32 - width);
\r
2735 FLAG_V = VFLAG_CLEAR;
\r
2736 FLAG_C = CFLAG_CLEAR;
\r
2738 REG_D[(word2 >> 12) & 7] = data;
\r
2742 m68ki_exception_illegal();
\r
2746 M68KMAKE_OP(bfffo, 32, ., d)
\r
2748 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2750 uint word2 = OPER_I_16();
\r
2751 uint offset = (word2>>6)&31;
\r
2752 uint width = word2;
\r
2758 offset = REG_D[offset&7];
\r
2760 width = REG_D[width&7];
\r
2763 width = ((width-1) & 31) + 1;
\r
2765 data = ROL_32(data, offset);
\r
2766 FLAG_N = NFLAG_32(data);
\r
2767 data >>= 32 - width;
\r
2770 FLAG_V = VFLAG_CLEAR;
\r
2771 FLAG_C = CFLAG_CLEAR;
\r
2773 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
\r
2776 REG_D[(word2>>12)&7] = offset;
\r
2780 m68ki_exception_illegal();
\r
2784 M68KMAKE_OP(bfffo, 32, ., .)
\r
2786 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2788 uint word2 = OPER_I_16();
\r
2789 sint offset = (word2>>6)&31;
\r
2790 sint local_offset;
\r
2791 uint width = word2;
\r
2794 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2798 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2800 width = REG_D[width&7];
\r
2802 /* Offset is signed so we have to use ugly math =( */
\r
2804 local_offset = offset % 8;
\r
2805 if(local_offset < 0)
\r
2807 local_offset += 8;
\r
2810 width = ((width-1) & 31) + 1;
\r
2812 data = m68ki_read_32(ea);
\r
2813 data = MASK_OUT_ABOVE_32(data<<local_offset);
\r
2815 if((local_offset+width) > 32)
\r
2816 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
\r
2818 FLAG_N = NFLAG_32(data);
\r
2819 data >>= (32 - width);
\r
2822 FLAG_V = VFLAG_CLEAR;
\r
2823 FLAG_C = CFLAG_CLEAR;
\r
2825 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
\r
2828 REG_D[(word2>>12)&7] = offset;
\r
2832 m68ki_exception_illegal();
\r
2836 M68KMAKE_OP(bfins, 32, ., d)
\r
2838 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2840 uint word2 = OPER_I_16();
\r
2841 uint offset = (word2>>6)&31;
\r
2842 uint width = word2;
\r
2845 uint64 insert = REG_D[(word2>>12)&7];
\r
2849 offset = REG_D[offset&7];
\r
2851 width = REG_D[width&7];
\r
2855 width = ((width-1) & 31) + 1;
\r
2858 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2859 mask = ROR_32(mask, offset);
\r
2861 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
\r
2862 FLAG_N = NFLAG_32(insert);
\r
2864 insert = ROR_32(insert, offset);
\r
2866 FLAG_V = VFLAG_CLEAR;
\r
2867 FLAG_C = CFLAG_CLEAR;
\r
2874 m68ki_exception_illegal();
\r
2878 M68KMAKE_OP(bfins, 32, ., .)
\r
2880 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2882 uint word2 = OPER_I_16();
\r
2883 sint offset = (word2>>6)&31;
\r
2884 uint width = word2;
\r
2885 uint insert_base = REG_D[(word2>>12)&7];
\r
2891 uint data_byte = 0;
\r
2892 uint mask_byte = 0;
\r
2893 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2897 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2899 width = REG_D[width&7];
\r
2901 /* Offset is signed so we have to use ugly math =( */
\r
2909 width = ((width-1) & 31) + 1;
\r
2911 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2912 mask_long = mask_base >> offset;
\r
2914 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
\r
2915 FLAG_N = NFLAG_32(insert_base);
\r
2916 FLAG_Z = insert_base;
\r
2917 insert_long = insert_base >> offset;
\r
2919 data_long = m68ki_read_32(ea);
\r
2920 FLAG_V = VFLAG_CLEAR;
\r
2921 FLAG_C = CFLAG_CLEAR;
\r
2923 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
\r
2925 if((width + offset) > 32)
\r
2927 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2928 insert_byte = MASK_OUT_ABOVE_8(insert_base);
\r
2929 data_byte = m68ki_read_8(ea+4);
\r
2930 FLAG_Z |= (data_byte & mask_byte);
\r
2931 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
\r
2935 m68ki_exception_illegal();
\r
2939 M68KMAKE_OP(bfset, 32, ., d)
\r
2941 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2943 uint word2 = OPER_I_16();
\r
2944 uint offset = (word2>>6)&31;
\r
2945 uint width = word2;
\r
2951 offset = REG_D[offset&7];
\r
2953 width = REG_D[width&7];
\r
2957 width = ((width-1) & 31) + 1;
\r
2960 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2961 mask = ROR_32(mask, offset);
\r
2963 FLAG_N = NFLAG_32(*data<<offset);
\r
2964 FLAG_Z = *data & mask;
\r
2965 FLAG_V = VFLAG_CLEAR;
\r
2966 FLAG_C = CFLAG_CLEAR;
\r
2972 m68ki_exception_illegal();
\r
2976 M68KMAKE_OP(bfset, 32, ., .)
\r
2978 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2980 uint word2 = OPER_I_16();
\r
2981 sint offset = (word2>>6)&31;
\r
2982 uint width = word2;
\r
2986 uint data_byte = 0;
\r
2987 uint mask_byte = 0;
\r
2988 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2992 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2994 width = REG_D[width&7];
\r
2996 /* Offset is signed so we have to use ugly math =( */
\r
3004 width = ((width-1) & 31) + 1;
\r
3007 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3008 mask_long = mask_base >> offset;
\r
3010 data_long = m68ki_read_32(ea);
\r
3011 FLAG_N = NFLAG_32(data_long << offset);
\r
3012 FLAG_Z = data_long & mask_long;
\r
3013 FLAG_V = VFLAG_CLEAR;
\r
3014 FLAG_C = CFLAG_CLEAR;
\r
3016 m68ki_write_32(ea, data_long | mask_long);
\r
3018 if((width + offset) > 32)
\r
3020 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
3021 data_byte = m68ki_read_8(ea+4);
\r
3022 FLAG_Z |= (data_byte & mask_byte);
\r
3023 m68ki_write_8(ea+4, data_byte | mask_byte);
\r
3027 m68ki_exception_illegal();
\r
3031 M68KMAKE_OP(bftst, 32, ., d)
\r
3033 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3035 uint word2 = OPER_I_16();
\r
3036 uint offset = (word2>>6)&31;
\r
3037 uint width = word2;
\r
3043 offset = REG_D[offset&7];
\r
3045 width = REG_D[width&7];
\r
3049 width = ((width-1) & 31) + 1;
\r
3052 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3053 mask = ROR_32(mask, offset);
\r
3055 FLAG_N = NFLAG_32(*data<<offset);
\r
3056 FLAG_Z = *data & mask;
\r
3057 FLAG_V = VFLAG_CLEAR;
\r
3058 FLAG_C = CFLAG_CLEAR;
\r
3062 m68ki_exception_illegal();
\r
3066 M68KMAKE_OP(bftst, 32, ., .)
\r
3068 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3070 uint word2 = OPER_I_16();
\r
3071 sint offset = (word2>>6)&31;
\r
3072 uint width = word2;
\r
3076 uint data_byte = 0;
\r
3077 uint mask_byte = 0;
\r
3078 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3081 offset = MAKE_INT_32(REG_D[offset&7]);
\r
3083 width = REG_D[width&7];
\r
3085 /* Offset is signed so we have to use ugly math =( */
\r
3093 width = ((width-1) & 31) + 1;
\r
3096 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3097 mask_long = mask_base >> offset;
\r
3099 data_long = m68ki_read_32(ea);
\r
3100 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
\r
3101 FLAG_Z = data_long & mask_long;
\r
3102 FLAG_V = VFLAG_CLEAR;
\r
3103 FLAG_C = CFLAG_CLEAR;
\r
3105 if((width + offset) > 32)
\r
3107 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
3108 data_byte = m68ki_read_8(ea+4);
\r
3109 FLAG_Z |= (data_byte & mask_byte);
\r
3113 m68ki_exception_illegal();
\r
3117 M68KMAKE_OP(bkpt, 0, ., .)
\r
3119 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
3121 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
\r
3123 m68ki_exception_illegal();
\r
3127 M68KMAKE_OP(bra, 8, ., .)
\r
3129 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3130 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3131 if(REG_PC == REG_PPC)
\r
3136 M68KMAKE_OP(bra, 16, ., .)
\r
3138 uint offset = OPER_I_16();
\r
3140 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3141 m68ki_branch_16(offset);
\r
3142 if(REG_PC == REG_PPC)
\r
3147 M68KMAKE_OP(bra, 32, ., .)
\r
3149 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3151 uint offset = OPER_I_32();
\r
3153 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3154 m68ki_branch_32(offset);
\r
3155 if(REG_PC == REG_PPC)
\r
3161 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3162 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3163 if(REG_PC == REG_PPC)
\r
3169 M68KMAKE_OP(bset, 32, r, d)
\r
3171 uint* r_dst = &DY;
\r
3172 uint mask = 1 << (DX & 0x1f);
\r
3174 FLAG_Z = *r_dst & mask;
\r
3179 M68KMAKE_OP(bset, 8, r, .)
\r
3181 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3182 uint src = m68ki_read_8(ea);
\r
3183 uint mask = 1 << (DX & 7);
\r
3185 FLAG_Z = src & mask;
\r
3186 m68ki_write_8(ea, src | mask);
\r
3190 M68KMAKE_OP(bset, 32, s, d)
\r
3192 uint* r_dst = &DY;
\r
3193 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
3195 FLAG_Z = *r_dst & mask;
\r
3200 M68KMAKE_OP(bset, 8, s, .)
\r
3202 uint mask = 1 << (OPER_I_8() & 7);
\r
3203 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3204 uint src = m68ki_read_8(ea);
\r
3206 FLAG_Z = src & mask;
\r
3207 m68ki_write_8(ea, src | mask);
\r
3211 M68KMAKE_OP(bsr, 8, ., .)
\r
3213 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3214 m68ki_push_32(REG_PC);
\r
3215 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3219 M68KMAKE_OP(bsr, 16, ., .)
\r
3221 uint offset = OPER_I_16();
\r
3222 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3223 m68ki_push_32(REG_PC);
\r
3225 m68ki_branch_16(offset);
\r
3229 M68KMAKE_OP(bsr, 32, ., .)
\r
3231 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3233 uint offset = OPER_I_32();
\r
3234 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3235 m68ki_push_32(REG_PC);
\r
3237 m68ki_branch_32(offset);
\r
3242 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3243 m68ki_push_32(REG_PC);
\r
3244 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3249 M68KMAKE_OP(btst, 32, r, d)
\r
3251 FLAG_Z = DY & (1 << (DX & 0x1f));
\r
3255 M68KMAKE_OP(btst, 8, r, .)
\r
3257 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
\r
3261 M68KMAKE_OP(btst, 32, s, d)
\r
3263 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
\r
3267 M68KMAKE_OP(btst, 8, s, .)
\r
3269 uint bit = OPER_I_8() & 7;
\r
3271 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
\r
3275 M68KMAKE_OP(callm, 32, ., .)
\r
3277 /* note: watch out for pcrelative modes */
\r
3278 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
3280 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3282 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3284 (void)ea; /* just to avoid an 'unused variable' warning */
\r
3285 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
3286 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
3287 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
3290 m68ki_exception_illegal();
\r
3294 M68KMAKE_OP(cas, 8, ., .)
\r
3296 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3298 uint word2 = OPER_I_16();
\r
3299 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3300 uint dest = m68ki_read_8(ea);
\r
3301 uint* compare = ®_D[word2 & 7];
\r
3302 uint res = dest - MASK_OUT_ABOVE_8(*compare);
\r
3304 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3305 FLAG_N = NFLAG_8(res);
\r
3306 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3307 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
\r
3308 FLAG_C = CFLAG_8(res);
\r
3311 *compare = MASK_OUT_BELOW_8(*compare) | dest;
\r
3315 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
\r
3319 m68ki_exception_illegal();
\r
3323 M68KMAKE_OP(cas, 16, ., .)
\r
3325 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3327 uint word2 = OPER_I_16();
\r
3328 uint ea = M68KMAKE_GET_EA_AY_16;
\r
3329 uint dest = m68ki_read_16(ea);
\r
3330 uint* compare = ®_D[word2 & 7];
\r
3331 uint res = dest - MASK_OUT_ABOVE_16(*compare);
\r
3333 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3334 FLAG_N = NFLAG_16(res);
\r
3335 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3336 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
\r
3337 FLAG_C = CFLAG_16(res);
\r
3340 *compare = MASK_OUT_BELOW_16(*compare) | dest;
\r
3344 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
\r
3348 m68ki_exception_illegal();
\r
3352 M68KMAKE_OP(cas, 32, ., .)
\r
3354 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3356 uint word2 = OPER_I_16();
\r
3357 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3358 uint dest = m68ki_read_32(ea);
\r
3359 uint* compare = ®_D[word2 & 7];
\r
3360 uint res = dest - *compare;
\r
3362 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3363 FLAG_N = NFLAG_32(res);
\r
3364 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3365 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
\r
3366 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
\r
3373 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
\r
3377 m68ki_exception_illegal();
\r
3381 M68KMAKE_OP(cas2, 16, ., .)
\r
3383 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3385 uint word2 = OPER_I_32();
\r
3386 uint* compare1 = ®_D[(word2 >> 16) & 7];
\r
3387 uint ea1 = REG_DA[(word2 >> 28) & 15];
\r
3388 uint dest1 = m68ki_read_16(ea1);
\r
3389 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
\r
3390 uint* compare2 = ®_D[word2 & 7];
\r
3391 uint ea2 = REG_DA[(word2 >> 12) & 15];
\r
3392 uint dest2 = m68ki_read_16(ea2);
\r
3395 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3396 FLAG_N = NFLAG_16(res1);
\r
3397 FLAG_Z = MASK_OUT_ABOVE_16(res1);
\r
3398 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
\r
3399 FLAG_C = CFLAG_16(res1);
\r
3403 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
\r
3405 FLAG_N = NFLAG_16(res2);
\r
3406 FLAG_Z = MASK_OUT_ABOVE_16(res2);
\r
3407 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
\r
3408 FLAG_C = CFLAG_16(res2);
\r
3413 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
\r
3414 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
\r
3418 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
\r
3419 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
\r
3422 m68ki_exception_illegal();
\r
3426 M68KMAKE_OP(cas2, 32, ., .)
\r
3428 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3430 uint word2 = OPER_I_32();
\r
3431 uint* compare1 = ®_D[(word2 >> 16) & 7];
\r
3432 uint ea1 = REG_DA[(word2 >> 28) & 15];
\r
3433 uint dest1 = m68ki_read_32(ea1);
\r
3434 uint res1 = dest1 - *compare1;
\r
3435 uint* compare2 = ®_D[word2 & 7];
\r
3436 uint ea2 = REG_DA[(word2 >> 12) & 15];
\r
3437 uint dest2 = m68ki_read_32(ea2);
\r
3440 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3441 FLAG_N = NFLAG_32(res1);
\r
3442 FLAG_Z = MASK_OUT_ABOVE_32(res1);
\r
3443 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
\r
3444 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
\r
3448 res2 = dest2 - *compare2;
\r
3450 FLAG_N = NFLAG_32(res2);
\r
3451 FLAG_Z = MASK_OUT_ABOVE_32(res2);
\r
3452 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
\r
3453 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
\r
3458 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
\r
3459 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
\r
3463 *compare1 = dest1;
\r
3464 *compare2 = dest2;
\r
3467 m68ki_exception_illegal();
\r
3471 M68KMAKE_OP(chk, 16, ., d)
\r
3473 sint src = MAKE_INT_16(DX);
\r
3474 sint bound = MAKE_INT_16(DY);
\r
3476 FLAG_Z = ZFLAG_16(src); /* Undocumented */
\r
3477 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3478 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3480 if(src >= 0 && src <= bound)
\r
3484 FLAG_N = (src < 0)<<7;
\r
3485 m68ki_exception_trap(EXCEPTION_CHK);
\r
3489 M68KMAKE_OP(chk, 16, ., .)
\r
3491 sint src = MAKE_INT_16(DX);
\r
3492 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
3494 FLAG_Z = ZFLAG_16(src); /* Undocumented */
\r
3495 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3496 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3498 if(src >= 0 && src <= bound)
\r
3502 FLAG_N = (src < 0)<<7;
\r
3503 m68ki_exception_trap(EXCEPTION_CHK);
\r
3507 M68KMAKE_OP(chk, 32, ., d)
\r
3509 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3511 sint src = MAKE_INT_32(DX);
\r
3512 sint bound = MAKE_INT_32(DY);
\r
3514 FLAG_Z = ZFLAG_32(src); /* Undocumented */
\r
3515 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3516 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3518 if(src >= 0 && src <= bound)
\r
3522 FLAG_N = (src < 0)<<7;
\r
3523 m68ki_exception_trap(EXCEPTION_CHK);
\r
3526 m68ki_exception_illegal();
\r
3530 M68KMAKE_OP(chk, 32, ., .)
\r
3532 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3534 sint src = MAKE_INT_32(DX);
\r
3535 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
\r
3537 FLAG_Z = ZFLAG_32(src); /* Undocumented */
\r
3538 FLAG_V = VFLAG_CLEAR; /* Undocumented */
\r
3539 FLAG_C = CFLAG_CLEAR; /* Undocumented */
\r
3541 if(src >= 0 && src <= bound)
\r
3545 FLAG_N = (src < 0)<<7;
\r
3546 m68ki_exception_trap(EXCEPTION_CHK);
\r
3549 m68ki_exception_illegal();
\r
3553 M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
\r
3555 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3557 uint word2 = OPER_I_16();
\r
3558 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3559 uint ea = EA_PCDI_8();
\r
3560 uint lower_bound = m68ki_read_pcrel_8(ea);
\r
3561 uint upper_bound = m68ki_read_pcrel_8(ea + 1);
\r
3564 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3566 FLAG_C = compare - lower_bound;
\r
3567 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3571 m68ki_exception_trap(EXCEPTION_CHK);
\r
3575 FLAG_C = upper_bound - compare;
\r
3576 if(COND_CS() && BIT_B(word2))
\r
3577 m68ki_exception_trap(EXCEPTION_CHK);
\r
3580 m68ki_exception_illegal();
\r
3584 M68KMAKE_OP(chk2cmp2, 8, ., pcix)
\r
3586 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3588 uint word2 = OPER_I_16();
\r
3589 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3590 uint ea = EA_PCIX_8();
\r
3591 uint lower_bound = m68ki_read_pcrel_8(ea);
\r
3592 uint upper_bound = m68ki_read_pcrel_8(ea + 1);
\r
3595 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3597 FLAG_C = compare - lower_bound;
\r
3598 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3602 m68ki_exception_trap(EXCEPTION_CHK);
\r
3606 FLAG_C = upper_bound - compare;
\r
3607 if(COND_CS() && BIT_B(word2))
\r
3608 m68ki_exception_trap(EXCEPTION_CHK);
\r
3611 m68ki_exception_illegal();
\r
3615 M68KMAKE_OP(chk2cmp2, 8, ., .)
\r
3617 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3619 uint word2 = OPER_I_16();
\r
3620 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
\r
3621 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3622 uint lower_bound = m68ki_read_8(ea);
\r
3623 uint upper_bound = m68ki_read_8(ea + 1);
\r
3626 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
\r
3628 FLAG_C = compare - lower_bound;
\r
3629 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3633 m68ki_exception_trap(EXCEPTION_CHK);
\r
3637 FLAG_C = upper_bound - compare;
\r
3638 if(COND_CS() && BIT_B(word2))
\r
3639 m68ki_exception_trap(EXCEPTION_CHK);
\r
3642 m68ki_exception_illegal();
\r
3646 M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
\r
3648 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3650 uint word2 = OPER_I_16();
\r
3651 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3652 uint ea = EA_PCDI_16();
\r
3653 uint lower_bound = m68ki_read_pcrel_16(ea);
\r
3654 uint upper_bound = m68ki_read_pcrel_16(ea + 2);
\r
3657 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3659 FLAG_C = compare - lower_bound;
\r
3660 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3661 FLAG_C = CFLAG_16(FLAG_C);
\r
3665 m68ki_exception_trap(EXCEPTION_CHK);
\r
3670 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3672 FLAG_C = upper_bound - compare;
\r
3673 FLAG_C = CFLAG_16(FLAG_C);
\r
3674 if(COND_CS() && BIT_B(word2))
\r
3675 m68ki_exception_trap(EXCEPTION_CHK);
\r
3678 m68ki_exception_illegal();
\r
3682 M68KMAKE_OP(chk2cmp2, 16, ., pcix)
\r
3684 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3686 uint word2 = OPER_I_16();
\r
3687 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3688 uint ea = EA_PCIX_16();
\r
3689 uint lower_bound = m68ki_read_pcrel_16(ea);
\r
3690 uint upper_bound = m68ki_read_pcrel_16(ea + 2);
\r
3693 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3695 FLAG_C = compare - lower_bound;
\r
3696 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3697 FLAG_C = CFLAG_16(FLAG_C);
\r
3701 m68ki_exception_trap(EXCEPTION_CHK);
\r
3706 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3708 FLAG_C = upper_bound - compare;
\r
3709 FLAG_C = CFLAG_16(FLAG_C);
\r
3710 if(COND_CS() && BIT_B(word2))
\r
3711 m68ki_exception_trap(EXCEPTION_CHK);
\r
3714 m68ki_exception_illegal();
\r
3718 M68KMAKE_OP(chk2cmp2, 16, ., .)
\r
3720 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3722 uint word2 = OPER_I_16();
\r
3723 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
\r
3724 uint ea = M68KMAKE_GET_EA_AY_16;
\r
3725 uint lower_bound = m68ki_read_16(ea);
\r
3726 uint upper_bound = m68ki_read_16(ea + 2);
\r
3729 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
\r
3731 FLAG_C = compare - lower_bound;
\r
3733 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3734 FLAG_C = CFLAG_16(FLAG_C);
\r
3738 m68ki_exception_trap(EXCEPTION_CHK);
\r
3742 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
\r
3744 FLAG_C = upper_bound - compare;
\r
3746 FLAG_C = CFLAG_16(FLAG_C);
\r
3747 if(COND_CS() && BIT_B(word2))
\r
3748 m68ki_exception_trap(EXCEPTION_CHK);
\r
3751 m68ki_exception_illegal();
\r
3755 M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
\r
3757 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3759 uint word2 = OPER_I_16();
\r
3760 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3761 uint ea = EA_PCDI_32();
\r
3762 uint lower_bound = m68ki_read_pcrel_32(ea);
\r
3763 uint upper_bound = m68ki_read_pcrel_32(ea + 4);
\r
3765 FLAG_C = compare - lower_bound;
\r
3766 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3767 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3771 m68ki_exception_trap(EXCEPTION_CHK);
\r
3775 FLAG_C = upper_bound - compare;
\r
3776 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3777 if(COND_CS() && BIT_B(word2))
\r
3778 m68ki_exception_trap(EXCEPTION_CHK);
\r
3781 m68ki_exception_illegal();
\r
3785 M68KMAKE_OP(chk2cmp2, 32, ., pcix)
\r
3787 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3789 uint word2 = OPER_I_16();
\r
3790 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3791 uint ea = EA_PCIX_32();
\r
3792 uint lower_bound = m68ki_read_pcrel_32(ea);
\r
3793 uint upper_bound = m68ki_read_pcrel_32(ea + 4);
\r
3795 FLAG_C = compare - lower_bound;
\r
3796 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3797 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3801 m68ki_exception_trap(EXCEPTION_CHK);
\r
3805 FLAG_C = upper_bound - compare;
\r
3806 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3807 if(COND_CS() && BIT_B(word2))
\r
3808 m68ki_exception_trap(EXCEPTION_CHK);
\r
3811 m68ki_exception_illegal();
\r
3815 M68KMAKE_OP(chk2cmp2, 32, ., .)
\r
3817 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3819 uint word2 = OPER_I_16();
\r
3820 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3821 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3822 uint lower_bound = m68ki_read_32(ea);
\r
3823 uint upper_bound = m68ki_read_32(ea + 4);
\r
3825 FLAG_C = compare - lower_bound;
\r
3826 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
\r
3827 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3831 m68ki_exception_trap(EXCEPTION_CHK);
\r
3835 FLAG_C = upper_bound - compare;
\r
3836 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3837 if(COND_CS() && BIT_B(word2))
\r
3838 m68ki_exception_trap(EXCEPTION_CHK);
\r
3841 m68ki_exception_illegal();
\r
3845 M68KMAKE_OP(clr, 8, ., d)
\r
3849 FLAG_N = NFLAG_CLEAR;
\r
3850 FLAG_V = VFLAG_CLEAR;
\r
3851 FLAG_C = CFLAG_CLEAR;
\r
3852 FLAG_Z = ZFLAG_SET;
\r
3856 M68KMAKE_OP(clr, 8, ., .)
\r
3858 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
\r
3860 FLAG_N = NFLAG_CLEAR;
\r
3861 FLAG_V = VFLAG_CLEAR;
\r
3862 FLAG_C = CFLAG_CLEAR;
\r
3863 FLAG_Z = ZFLAG_SET;
\r
3867 M68KMAKE_OP(clr, 16, ., d)
\r
3871 FLAG_N = NFLAG_CLEAR;
\r
3872 FLAG_V = VFLAG_CLEAR;
\r
3873 FLAG_C = CFLAG_CLEAR;
\r
3874 FLAG_Z = ZFLAG_SET;
\r
3878 M68KMAKE_OP(clr, 16, ., .)
\r
3880 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
\r
3882 FLAG_N = NFLAG_CLEAR;
\r
3883 FLAG_V = VFLAG_CLEAR;
\r
3884 FLAG_C = CFLAG_CLEAR;
\r
3885 FLAG_Z = ZFLAG_SET;
\r
3889 M68KMAKE_OP(clr, 32, ., d)
\r
3893 FLAG_N = NFLAG_CLEAR;
\r
3894 FLAG_V = VFLAG_CLEAR;
\r
3895 FLAG_C = CFLAG_CLEAR;
\r
3896 FLAG_Z = ZFLAG_SET;
\r
3900 M68KMAKE_OP(clr, 32, ., .)
\r
3902 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
\r
3904 FLAG_N = NFLAG_CLEAR;
\r
3905 FLAG_V = VFLAG_CLEAR;
\r
3906 FLAG_C = CFLAG_CLEAR;
\r
3907 FLAG_Z = ZFLAG_SET;
\r
3911 M68KMAKE_OP(cmp, 8, ., d)
\r
3913 uint src = MASK_OUT_ABOVE_8(DY);
\r
3914 uint dst = MASK_OUT_ABOVE_8(DX);
\r
3915 uint res = dst - src;
\r
3917 FLAG_N = NFLAG_8(res);
\r
3918 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3919 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3920 FLAG_C = CFLAG_8(res);
\r
3924 M68KMAKE_OP(cmp, 8, ., .)
\r
3926 uint src = M68KMAKE_GET_OPER_AY_8;
\r
3927 uint dst = MASK_OUT_ABOVE_8(DX);
\r
3928 uint res = dst - src;
\r
3930 FLAG_N = NFLAG_8(res);
\r
3931 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3932 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3933 FLAG_C = CFLAG_8(res);
\r
3937 M68KMAKE_OP(cmp, 16, ., d)
\r
3939 uint src = MASK_OUT_ABOVE_16(DY);
\r
3940 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3941 uint res = dst - src;
\r
3943 FLAG_N = NFLAG_16(res);
\r
3944 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3945 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3946 FLAG_C = CFLAG_16(res);
\r
3950 M68KMAKE_OP(cmp, 16, ., a)
\r
3952 uint src = MASK_OUT_ABOVE_16(AY);
\r
3953 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3954 uint res = dst - src;
\r
3956 FLAG_N = NFLAG_16(res);
\r
3957 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3958 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3959 FLAG_C = CFLAG_16(res);
\r
3963 M68KMAKE_OP(cmp, 16, ., .)
\r
3965 uint src = M68KMAKE_GET_OPER_AY_16;
\r
3966 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3967 uint res = dst - src;
\r
3969 FLAG_N = NFLAG_16(res);
\r
3970 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3971 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3972 FLAG_C = CFLAG_16(res);
\r
3976 M68KMAKE_OP(cmp, 32, ., d)
\r
3980 uint res = dst - src;
\r
3982 FLAG_N = NFLAG_32(res);
\r
3983 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3984 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3985 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3989 M68KMAKE_OP(cmp, 32, ., a)
\r
3993 uint res = dst - src;
\r
3995 FLAG_N = NFLAG_32(res);
\r
3996 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3997 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3998 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4002 M68KMAKE_OP(cmp, 32, ., .)
\r
4004 uint src = M68KMAKE_GET_OPER_AY_32;
\r
4006 uint res = dst - src;
\r
4008 FLAG_N = NFLAG_32(res);
\r
4009 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4010 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4011 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4015 M68KMAKE_OP(cmpa, 16, ., d)
\r
4017 uint src = MAKE_INT_16(DY);
\r
4019 uint res = dst - src;
\r
4021 FLAG_N = NFLAG_32(res);
\r
4022 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4023 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4024 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4028 M68KMAKE_OP(cmpa, 16, ., a)
\r
4030 uint src = MAKE_INT_16(AY);
\r
4032 uint res = dst - src;
\r
4034 FLAG_N = NFLAG_32(res);
\r
4035 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4036 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4037 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4041 M68KMAKE_OP(cmpa, 16, ., .)
\r
4043 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
4045 uint res = dst - src;
\r
4047 FLAG_N = NFLAG_32(res);
\r
4048 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4049 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4050 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4054 M68KMAKE_OP(cmpa, 32, ., d)
\r
4058 uint res = dst - src;
\r
4060 FLAG_N = NFLAG_32(res);
\r
4061 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4062 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4063 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4067 M68KMAKE_OP(cmpa, 32, ., a)
\r
4071 uint res = dst - src;
\r
4073 FLAG_N = NFLAG_32(res);
\r
4074 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4075 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4076 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4080 M68KMAKE_OP(cmpa, 32, ., .)
\r
4082 uint src = M68KMAKE_GET_OPER_AY_32;
\r
4084 uint res = dst - src;
\r
4086 FLAG_N = NFLAG_32(res);
\r
4087 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4088 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4089 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4093 M68KMAKE_OP(cmpi, 8, ., d)
\r
4095 uint src = OPER_I_8();
\r
4096 uint dst = MASK_OUT_ABOVE_8(DY);
\r
4097 uint res = dst - src;
\r
4099 FLAG_N = NFLAG_8(res);
\r
4100 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4101 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4102 FLAG_C = CFLAG_8(res);
\r
4106 M68KMAKE_OP(cmpi, 8, ., .)
\r
4108 uint src = OPER_I_8();
\r
4109 uint dst = M68KMAKE_GET_OPER_AY_8;
\r
4110 uint res = dst - src;
\r
4112 FLAG_N = NFLAG_8(res);
\r
4113 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4114 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4115 FLAG_C = CFLAG_8(res);
\r
4119 M68KMAKE_OP(cmpi, 8, ., pcdi)
\r
4121 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4123 uint src = OPER_I_8();
\r
4124 uint dst = OPER_PCDI_8();
\r
4125 uint res = dst - src;
\r
4127 FLAG_N = NFLAG_8(res);
\r
4128 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4129 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4130 FLAG_C = CFLAG_8(res);
\r
4133 m68ki_exception_illegal();
\r
4137 M68KMAKE_OP(cmpi, 8, ., pcix)
\r
4139 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4141 uint src = OPER_I_8();
\r
4142 uint dst = OPER_PCIX_8();
\r
4143 uint res = dst - src;
\r
4145 FLAG_N = NFLAG_8(res);
\r
4146 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4147 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4148 FLAG_C = CFLAG_8(res);
\r
4151 m68ki_exception_illegal();
\r
4155 M68KMAKE_OP(cmpi, 16, ., d)
\r
4157 uint src = OPER_I_16();
\r
4158 uint dst = MASK_OUT_ABOVE_16(DY);
\r
4159 uint res = dst - src;
\r
4161 FLAG_N = NFLAG_16(res);
\r
4162 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4163 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4164 FLAG_C = CFLAG_16(res);
\r
4168 M68KMAKE_OP(cmpi, 16, ., .)
\r
4170 uint src = OPER_I_16();
\r
4171 uint dst = M68KMAKE_GET_OPER_AY_16;
\r
4172 uint res = dst - src;
\r
4174 FLAG_N = NFLAG_16(res);
\r
4175 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4176 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4177 FLAG_C = CFLAG_16(res);
\r
4181 M68KMAKE_OP(cmpi, 16, ., pcdi)
\r
4183 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4185 uint src = OPER_I_16();
\r
4186 uint dst = OPER_PCDI_16();
\r
4187 uint res = dst - src;
\r
4189 FLAG_N = NFLAG_16(res);
\r
4190 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4191 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4192 FLAG_C = CFLAG_16(res);
\r
4195 m68ki_exception_illegal();
\r
4199 M68KMAKE_OP(cmpi, 16, ., pcix)
\r
4201 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4203 uint src = OPER_I_16();
\r
4204 uint dst = OPER_PCIX_16();
\r
4205 uint res = dst - src;
\r
4207 FLAG_N = NFLAG_16(res);
\r
4208 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4209 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4210 FLAG_C = CFLAG_16(res);
\r
4213 m68ki_exception_illegal();
\r
4217 M68KMAKE_OP(cmpi, 32, ., d)
\r
4219 uint src = OPER_I_32();
\r
4221 uint res = dst - src;
\r
4223 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */
\r
4225 FLAG_N = NFLAG_32(res);
\r
4226 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4227 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4228 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4232 M68KMAKE_OP(cmpi, 32, ., .)
\r
4234 uint src = OPER_I_32();
\r
4235 uint dst = M68KMAKE_GET_OPER_AY_32;
\r
4236 uint res = dst - src;
\r
4238 FLAG_N = NFLAG_32(res);
\r
4239 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4240 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4241 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4245 M68KMAKE_OP(cmpi, 32, ., pcdi)
\r
4247 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4249 uint src = OPER_I_32();
\r
4250 uint dst = OPER_PCDI_32();
\r
4251 uint res = dst - src;
\r
4253 FLAG_N = NFLAG_32(res);
\r
4254 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4255 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4256 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4259 m68ki_exception_illegal();
\r
4263 M68KMAKE_OP(cmpi, 32, ., pcix)
\r
4265 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4267 uint src = OPER_I_32();
\r
4268 uint dst = OPER_PCIX_32();
\r
4269 uint res = dst - src;
\r
4271 FLAG_N = NFLAG_32(res);
\r
4272 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4273 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4274 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4277 m68ki_exception_illegal();
\r
4281 M68KMAKE_OP(cmpm, 8, ., ax7)
\r
4283 uint src = OPER_AY_PI_8();
\r
4284 uint dst = OPER_A7_PI_8();
\r
4285 uint res = dst - src;
\r
4287 FLAG_N = NFLAG_8(res);
\r
4288 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4289 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4290 FLAG_C = CFLAG_8(res);
\r
4294 M68KMAKE_OP(cmpm, 8, ., ay7)
\r
4296 uint src = OPER_A7_PI_8();
\r
4297 uint dst = OPER_AX_PI_8();
\r
4298 uint res = dst - src;
\r
4300 FLAG_N = NFLAG_8(res);
\r
4301 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4302 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4303 FLAG_C = CFLAG_8(res);
\r
4307 M68KMAKE_OP(cmpm, 8, ., axy7)
\r
4309 uint src = OPER_A7_PI_8();
\r
4310 uint dst = OPER_A7_PI_8();
\r
4311 uint res = dst - src;
\r
4313 FLAG_N = NFLAG_8(res);
\r
4314 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4315 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4316 FLAG_C = CFLAG_8(res);
\r
4320 M68KMAKE_OP(cmpm, 8, ., .)
\r
4322 uint src = OPER_AY_PI_8();
\r
4323 uint dst = OPER_AX_PI_8();
\r
4324 uint res = dst - src;
\r
4326 FLAG_N = NFLAG_8(res);
\r
4327 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4328 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4329 FLAG_C = CFLAG_8(res);
\r
4333 M68KMAKE_OP(cmpm, 16, ., .)
\r
4335 uint src = OPER_AY_PI_16();
\r
4336 uint dst = OPER_AX_PI_16();
\r
4337 uint res = dst - src;
\r
4339 FLAG_N = NFLAG_16(res);
\r
4340 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4341 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4342 FLAG_C = CFLAG_16(res);
\r
4346 M68KMAKE_OP(cmpm, 32, ., .)
\r
4348 uint src = OPER_AY_PI_32();
\r
4349 uint dst = OPER_AX_PI_32();
\r
4350 uint res = dst - src;
\r
4352 FLAG_N = NFLAG_32(res);
\r
4353 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4354 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4355 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4359 M68KMAKE_OP(cpbcc, 32, ., .)
\r
4361 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4363 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4364 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4365 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4368 m68ki_exception_1111();
\r
4372 M68KMAKE_OP(cpdbcc, 32, ., .)
\r
4374 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4376 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4377 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4378 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4381 m68ki_exception_1111();
\r
4385 M68KMAKE_OP(cpgen, 32, ., .)
\r
4387 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4389 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4390 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4391 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4394 m68ki_exception_1111();
\r
4398 M68KMAKE_OP(cpscc, 32, ., .)
\r
4400 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4402 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4403 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4404 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4407 m68ki_exception_1111();
\r
4411 M68KMAKE_OP(cptrapcc, 32, ., .)
\r
4413 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4415 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4416 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4417 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4420 m68ki_exception_1111();
\r
4424 M68KMAKE_OP(dbt, 16, ., .)
\r
4430 M68KMAKE_OP(dbf, 16, ., .)
\r
4432 uint* r_dst = &DY;
\r
4433 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
\r
4435 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
4438 uint offset = OPER_I_16();
\r
4440 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4441 m68ki_branch_16(offset);
\r
4442 USE_CYCLES(CYC_DBCC_F_NOEXP);
\r
4446 USE_CYCLES(CYC_DBCC_F_EXP);
\r
4450 M68KMAKE_OP(dbcc, 16, ., .)
\r
4452 if(M68KMAKE_NOT_CC)
\r
4454 uint* r_dst = &DY;
\r
4455 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
\r
4457 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
4460 uint offset = OPER_I_16();
\r
4462 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4463 m68ki_branch_16(offset);
\r
4464 USE_CYCLES(CYC_DBCC_F_NOEXP);
\r
4468 USE_CYCLES(CYC_DBCC_F_EXP);
\r
4475 M68KMAKE_OP(divs, 16, ., d)
\r
4477 uint* r_dst = &DX;
\r
4478 sint src = MAKE_INT_16(DY);
\r
4484 if((uint32)*r_dst == 0x80000000 && src == -1)
\r
4487 FLAG_N = NFLAG_CLEAR;
\r
4488 FLAG_V = VFLAG_CLEAR;
\r
4489 FLAG_C = CFLAG_CLEAR;
\r
4494 quotient = MAKE_INT_32(*r_dst) / src;
\r
4495 remainder = MAKE_INT_32(*r_dst) % src;
\r
4497 if(quotient == MAKE_INT_16(quotient))
\r
4499 FLAG_Z = quotient;
\r
4500 FLAG_N = NFLAG_16(quotient);
\r
4501 FLAG_V = VFLAG_CLEAR;
\r
4502 FLAG_C = CFLAG_CLEAR;
\r
4503 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4506 FLAG_V = VFLAG_SET;
\r
4509 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4513 M68KMAKE_OP(divs, 16, ., .)
\r
4515 uint* r_dst = &DX;
\r
4516 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
4522 if((uint32)*r_dst == 0x80000000 && src == -1)
\r
4525 FLAG_N = NFLAG_CLEAR;
\r
4526 FLAG_V = VFLAG_CLEAR;
\r
4527 FLAG_C = CFLAG_CLEAR;
\r
4532 quotient = MAKE_INT_32(*r_dst) / src;
\r
4533 remainder = MAKE_INT_32(*r_dst) % src;
\r
4535 if(quotient == MAKE_INT_16(quotient))
\r
4537 FLAG_Z = quotient;
\r
4538 FLAG_N = NFLAG_16(quotient);
\r
4539 FLAG_V = VFLAG_CLEAR;
\r
4540 FLAG_C = CFLAG_CLEAR;
\r
4541 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4544 FLAG_V = VFLAG_SET;
\r
4547 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4551 M68KMAKE_OP(divu, 16, ., d)
\r
4553 uint* r_dst = &DX;
\r
4554 uint src = MASK_OUT_ABOVE_16(DY);
\r
4558 uint quotient = *r_dst / src;
\r
4559 uint remainder = *r_dst % src;
\r
4561 if(quotient < 0x10000)
\r
4563 FLAG_Z = quotient;
\r
4564 FLAG_N = NFLAG_16(quotient);
\r
4565 FLAG_V = VFLAG_CLEAR;
\r
4566 FLAG_C = CFLAG_CLEAR;
\r
4567 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4570 FLAG_V = VFLAG_SET;
\r
4573 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4577 M68KMAKE_OP(divu, 16, ., .)
\r
4579 uint* r_dst = &DX;
\r
4580 uint src = M68KMAKE_GET_OPER_AY_16;
\r
4584 uint quotient = *r_dst / src;
\r
4585 uint remainder = *r_dst % src;
\r
4587 if(quotient < 0x10000)
\r
4589 FLAG_Z = quotient;
\r
4590 FLAG_N = NFLAG_16(quotient);
\r
4591 FLAG_V = VFLAG_CLEAR;
\r
4592 FLAG_C = CFLAG_CLEAR;
\r
4593 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4596 FLAG_V = VFLAG_SET;
\r
4599 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4603 M68KMAKE_OP(divl, 32, ., d)
\r
4605 #if M68K_USE_64_BIT
\r
4607 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4609 uint word2 = OPER_I_16();
\r
4610 uint64 divisor = DY;
\r
4611 uint64 dividend = 0;
\r
4612 uint64 quotient = 0;
\r
4613 uint64 remainder = 0;
\r
4617 if(BIT_A(word2)) /* 64 bit */
\r
4619 dividend = REG_D[word2 & 7];
\r
4621 dividend |= REG_D[(word2 >> 12) & 7];
\r
4623 if(BIT_B(word2)) /* signed */
\r
4625 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
\r
4626 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
\r
4627 if((sint64)quotient != (sint64)((sint32)quotient))
\r
4629 FLAG_V = VFLAG_SET;
\r
4633 else /* unsigned */
\r
4635 quotient = dividend / divisor;
\r
4636 if(quotient > 0xffffffff)
\r
4638 FLAG_V = VFLAG_SET;
\r
4641 remainder = dividend % divisor;
\r
4646 dividend = REG_D[(word2 >> 12) & 7];
\r
4647 if(BIT_B(word2)) /* signed */
\r
4649 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
\r
4650 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
\r
4652 else /* unsigned */
\r
4654 quotient = dividend / divisor;
\r
4655 remainder = dividend % divisor;
\r
4659 REG_D[word2 & 7] = remainder;
\r
4660 REG_D[(word2 >> 12) & 7] = quotient;
\r
4662 FLAG_N = NFLAG_32(quotient);
\r
4663 FLAG_Z = quotient;
\r
4664 FLAG_V = VFLAG_CLEAR;
\r
4665 FLAG_C = CFLAG_CLEAR;
\r
4668 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4671 m68ki_exception_illegal();
\r
4675 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4677 uint word2 = OPER_I_16();
\r
4678 uint divisor = DY;
\r
4679 uint dividend_hi = REG_D[word2 & 7];
\r
4680 uint dividend_lo = REG_D[(word2 >> 12) & 7];
\r
4681 uint quotient = 0;
\r
4682 uint remainder = 0;
\r
4683 uint dividend_neg = 0;
\r
4684 uint divisor_neg = 0;
\r
4690 /* quad / long : long quotient, long remainder */
\r
4693 if(BIT_B(word2)) /* signed */
\r
4695 /* special case in signed divide */
\r
4696 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4698 REG_D[word2 & 7] = 0;
\r
4699 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4701 FLAG_N = NFLAG_SET;
\r
4702 FLAG_Z = ZFLAG_CLEAR;
\r
4703 FLAG_V = VFLAG_CLEAR;
\r
4704 FLAG_C = CFLAG_CLEAR;
\r
4707 if(GET_MSB_32(dividend_hi))
\r
4710 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
\r
4711 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
\r
4713 if(GET_MSB_32(divisor))
\r
4716 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
\r
4721 /* if the upper long is greater than the divisor, we're overflowing. */
\r
4722 if(dividend_hi >= divisor)
\r
4724 FLAG_V = VFLAG_SET;
\r
4728 for(i = 31; i >= 0; i--)
\r
4731 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
\r
4732 if(remainder >= divisor)
\r
4734 remainder -= divisor;
\r
4738 for(i = 31; i >= 0; i--)
\r
4741 overflow = GET_MSB_32(remainder);
\r
4742 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
\r
4743 if(remainder >= divisor || overflow)
\r
4745 remainder -= divisor;
\r
4750 if(BIT_B(word2)) /* signed */
\r
4752 if(quotient > 0x7fffffff)
\r
4754 FLAG_V = VFLAG_SET;
\r
4759 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
\r
4760 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4763 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4766 REG_D[word2 & 7] = remainder;
\r
4767 REG_D[(word2 >> 12) & 7] = quotient;
\r
4769 FLAG_N = NFLAG_32(quotient);
\r
4770 FLAG_Z = quotient;
\r
4771 FLAG_V = VFLAG_CLEAR;
\r
4772 FLAG_C = CFLAG_CLEAR;
\r
4776 /* long / long: long quotient, maybe long remainder */
\r
4777 if(BIT_B(word2)) /* signed */
\r
4779 /* Special case in divide */
\r
4780 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4782 FLAG_N = NFLAG_SET;
\r
4783 FLAG_Z = ZFLAG_CLEAR;
\r
4784 FLAG_V = VFLAG_CLEAR;
\r
4785 FLAG_C = CFLAG_CLEAR;
\r
4786 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4787 REG_D[word2 & 7] = 0;
\r
4790 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
\r
4791 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
\r
4795 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
\r
4796 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
\r
4799 FLAG_N = NFLAG_32(quotient);
\r
4800 FLAG_Z = quotient;
\r
4801 FLAG_V = VFLAG_CLEAR;
\r
4802 FLAG_C = CFLAG_CLEAR;
\r
4805 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4808 m68ki_exception_illegal();
\r
4814 M68KMAKE_OP(divl, 32, ., .)
\r
4816 #if M68K_USE_64_BIT
\r
4818 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4820 uint word2 = OPER_I_16();
\r
4821 uint64 divisor = M68KMAKE_GET_OPER_AY_32;
\r
4822 uint64 dividend = 0;
\r
4823 uint64 quotient = 0;
\r
4824 uint64 remainder = 0;
\r
4828 if(BIT_A(word2)) /* 64 bit */
\r
4830 dividend = REG_D[word2 & 7];
\r
4832 dividend |= REG_D[(word2 >> 12) & 7];
\r
4834 if(BIT_B(word2)) /* signed */
\r
4836 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
\r
4837 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
\r
4838 if((sint64)quotient != (sint64)((sint32)quotient))
\r
4840 FLAG_V = VFLAG_SET;
\r
4844 else /* unsigned */
\r
4846 quotient = dividend / divisor;
\r
4847 if(quotient > 0xffffffff)
\r
4849 FLAG_V = VFLAG_SET;
\r
4852 remainder = dividend % divisor;
\r
4857 dividend = REG_D[(word2 >> 12) & 7];
\r
4858 if(BIT_B(word2)) /* signed */
\r
4860 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
\r
4861 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
\r
4863 else /* unsigned */
\r
4865 quotient = dividend / divisor;
\r
4866 remainder = dividend % divisor;
\r
4870 REG_D[word2 & 7] = remainder;
\r
4871 REG_D[(word2 >> 12) & 7] = quotient;
\r
4873 FLAG_N = NFLAG_32(quotient);
\r
4874 FLAG_Z = quotient;
\r
4875 FLAG_V = VFLAG_CLEAR;
\r
4876 FLAG_C = CFLAG_CLEAR;
\r
4879 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4882 m68ki_exception_illegal();
\r
4886 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4888 uint word2 = OPER_I_16();
\r
4889 uint divisor = M68KMAKE_GET_OPER_AY_32;
\r
4890 uint dividend_hi = REG_D[word2 & 7];
\r
4891 uint dividend_lo = REG_D[(word2 >> 12) & 7];
\r
4892 uint quotient = 0;
\r
4893 uint remainder = 0;
\r
4894 uint dividend_neg = 0;
\r
4895 uint divisor_neg = 0;
\r
4901 /* quad / long : long quotient, long remainder */
\r
4904 if(BIT_B(word2)) /* signed */
\r
4906 /* special case in signed divide */
\r
4907 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4909 REG_D[word2 & 7] = 0;
\r
4910 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4912 FLAG_N = NFLAG_SET;
\r
4913 FLAG_Z = ZFLAG_CLEAR;
\r
4914 FLAG_V = VFLAG_CLEAR;
\r
4915 FLAG_C = CFLAG_CLEAR;
\r
4918 if(GET_MSB_32(dividend_hi))
\r
4921 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
\r
4922 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
\r
4924 if(GET_MSB_32(divisor))
\r
4927 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
\r
4932 /* if the upper long is greater than the divisor, we're overflowing. */
\r
4933 if(dividend_hi >= divisor)
\r
4935 FLAG_V = VFLAG_SET;
\r
4939 for(i = 31; i >= 0; i--)
\r
4942 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
\r
4943 if(remainder >= divisor)
\r
4945 remainder -= divisor;
\r
4949 for(i = 31; i >= 0; i--)
\r
4952 overflow = GET_MSB_32(remainder);
\r
4953 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
\r
4954 if(remainder >= divisor || overflow)
\r
4956 remainder -= divisor;
\r
4961 if(BIT_B(word2)) /* signed */
\r
4963 if(quotient > 0x7fffffff)
\r
4965 FLAG_V = VFLAG_SET;
\r
4970 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
\r
4971 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4974 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4977 REG_D[word2 & 7] = remainder;
\r
4978 REG_D[(word2 >> 12) & 7] = quotient;
\r
4980 FLAG_N = NFLAG_32(quotient);
\r
4981 FLAG_Z = quotient;
\r
4982 FLAG_V = VFLAG_CLEAR;
\r
4983 FLAG_C = CFLAG_CLEAR;
\r
4987 /* long / long: long quotient, maybe long remainder */
\r
4988 if(BIT_B(word2)) /* signed */
\r
4990 /* Special case in divide */
\r
4991 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4993 FLAG_N = NFLAG_SET;
\r
4994 FLAG_Z = ZFLAG_CLEAR;
\r
4995 FLAG_V = VFLAG_CLEAR;
\r
4996 FLAG_C = CFLAG_CLEAR;
\r
4997 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4998 REG_D[word2 & 7] = 0;
\r
5001 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
\r
5002 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
\r
5006 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
\r
5007 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
\r
5010 FLAG_N = NFLAG_32(quotient);
\r
5011 FLAG_Z = quotient;
\r
5012 FLAG_V = VFLAG_CLEAR;
\r
5013 FLAG_C = CFLAG_CLEAR;
\r
5016 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
5019 m68ki_exception_illegal();
\r
5025 M68KMAKE_OP(eor, 8, ., d)
\r
5027 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
\r
5029 FLAG_N = NFLAG_8(res);
\r
5031 FLAG_C = CFLAG_CLEAR;
\r
5032 FLAG_V = VFLAG_CLEAR;
\r
5036 M68KMAKE_OP(eor, 8, ., .)
\r
5038 uint ea = M68KMAKE_GET_EA_AY_8;
\r
5039 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
\r
5041 m68ki_write_8(ea, res);
\r
5043 FLAG_N = NFLAG_8(res);
\r
5045 FLAG_C = CFLAG_CLEAR;
\r
5046 FLAG_V = VFLAG_CLEAR;
\r
5050 M68KMAKE_OP(eor, 16, ., d)
\r
5052 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
\r
5054 FLAG_N = NFLAG_16(res);
\r
5056 FLAG_C = CFLAG_CLEAR;
\r
5057 FLAG_V = VFLAG_CLEAR;
\r
5061 M68KMAKE_OP(eor, 16, ., .)
\r
5063 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5064 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
\r
5066 m68ki_write_16(ea, res);
\r
5068 FLAG_N = NFLAG_16(res);
\r
5070 FLAG_C = CFLAG_CLEAR;
\r
5071 FLAG_V = VFLAG_CLEAR;
\r
5075 M68KMAKE_OP(eor, 32, ., d)
\r
5077 uint res = DY ^= DX;
\r
5079 FLAG_N = NFLAG_32(res);
\r
5081 FLAG_C = CFLAG_CLEAR;
\r
5082 FLAG_V = VFLAG_CLEAR;
\r
5086 M68KMAKE_OP(eor, 32, ., .)
\r
5088 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5089 uint res = DX ^ m68ki_read_32(ea);
\r
5091 m68ki_write_32(ea, res);
\r
5093 FLAG_N = NFLAG_32(res);
\r
5095 FLAG_C = CFLAG_CLEAR;
\r
5096 FLAG_V = VFLAG_CLEAR;
\r
5100 M68KMAKE_OP(eori, 8, ., d)
\r
5102 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
\r
5104 FLAG_N = NFLAG_8(res);
\r
5106 FLAG_C = CFLAG_CLEAR;
\r
5107 FLAG_V = VFLAG_CLEAR;
\r
5111 M68KMAKE_OP(eori, 8, ., .)
\r
5113 uint src = OPER_I_8();
\r
5114 uint ea = M68KMAKE_GET_EA_AY_8;
\r
5115 uint res = src ^ m68ki_read_8(ea);
\r
5117 m68ki_write_8(ea, res);
\r
5119 FLAG_N = NFLAG_8(res);
\r
5121 FLAG_C = CFLAG_CLEAR;
\r
5122 FLAG_V = VFLAG_CLEAR;
\r
5126 M68KMAKE_OP(eori, 16, ., d)
\r
5128 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
\r
5130 FLAG_N = NFLAG_16(res);
\r
5132 FLAG_C = CFLAG_CLEAR;
\r
5133 FLAG_V = VFLAG_CLEAR;
\r
5137 M68KMAKE_OP(eori, 16, ., .)
\r
5139 uint src = OPER_I_16();
\r
5140 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5141 uint res = src ^ m68ki_read_16(ea);
\r
5143 m68ki_write_16(ea, res);
\r
5145 FLAG_N = NFLAG_16(res);
\r
5147 FLAG_C = CFLAG_CLEAR;
\r
5148 FLAG_V = VFLAG_CLEAR;
\r
5152 M68KMAKE_OP(eori, 32, ., d)
\r
5154 uint res = DY ^= OPER_I_32();
\r
5156 FLAG_N = NFLAG_32(res);
\r
5158 FLAG_C = CFLAG_CLEAR;
\r
5159 FLAG_V = VFLAG_CLEAR;
\r
5163 M68KMAKE_OP(eori, 32, ., .)
\r
5165 uint src = OPER_I_32();
\r
5166 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5167 uint res = src ^ m68ki_read_32(ea);
\r
5169 m68ki_write_32(ea, res);
\r
5171 FLAG_N = NFLAG_32(res);
\r
5173 FLAG_C = CFLAG_CLEAR;
\r
5174 FLAG_V = VFLAG_CLEAR;
\r
5178 M68KMAKE_OP(eori, 16, toc, .)
\r
5180 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
\r
5184 M68KMAKE_OP(eori, 16, tos, .)
\r
5188 uint src = OPER_I_16();
\r
5189 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5190 m68ki_set_sr(m68ki_get_sr() ^ src);
\r
5193 m68ki_exception_privilege_violation();
\r
5197 M68KMAKE_OP(exg, 32, dd, .)
\r
5199 uint* reg_a = &DX;
\r
5200 uint* reg_b = &DY;
\r
5201 uint tmp = *reg_a;
\r
5207 M68KMAKE_OP(exg, 32, aa, .)
\r
5209 uint* reg_a = &AX;
\r
5210 uint* reg_b = &AY;
\r
5211 uint tmp = *reg_a;
\r
5217 M68KMAKE_OP(exg, 32, da, .)
\r
5219 uint* reg_a = &DX;
\r
5220 uint* reg_b = &AY;
\r
5221 uint tmp = *reg_a;
\r
5227 M68KMAKE_OP(ext, 16, ., .)
\r
5229 uint* r_dst = &DY;
\r
5231 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
\r
5233 FLAG_N = NFLAG_16(*r_dst);
\r
5234 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
5235 FLAG_V = VFLAG_CLEAR;
\r
5236 FLAG_C = CFLAG_CLEAR;
\r
5240 M68KMAKE_OP(ext, 32, ., .)
\r
5242 uint* r_dst = &DY;
\r
5244 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
\r
5246 FLAG_N = NFLAG_32(*r_dst);
\r
5248 FLAG_V = VFLAG_CLEAR;
\r
5249 FLAG_C = CFLAG_CLEAR;
\r
5253 M68KMAKE_OP(extb, 32, ., .)
\r
5255 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5257 uint* r_dst = &DY;
\r
5259 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
\r
5261 FLAG_N = NFLAG_32(*r_dst);
\r
5263 FLAG_V = VFLAG_CLEAR;
\r
5264 FLAG_C = CFLAG_CLEAR;
\r
5267 m68ki_exception_illegal();
\r
5271 M68KMAKE_OP(illegal, 0, ., .)
\r
5273 m68ki_exception_illegal();
\r
5276 M68KMAKE_OP(jmp, 32, ., .)
\r
5278 m68ki_jump(M68KMAKE_GET_EA_AY_32);
\r
5279 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5280 if(REG_PC == REG_PPC)
\r
5285 M68KMAKE_OP(jsr, 32, ., .)
\r
5287 uint ea = M68KMAKE_GET_EA_AY_32;
\r
5288 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
5289 m68ki_push_32(REG_PC);
\r
5294 M68KMAKE_OP(lea, 32, ., .)
\r
5296 AX = M68KMAKE_GET_EA_AY_32;
\r
5300 M68KMAKE_OP(link, 16, ., a7)
\r
5303 m68ki_write_32(REG_A[7], REG_A[7]);
\r
5304 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
5308 M68KMAKE_OP(link, 16, ., .)
\r
5310 uint* r_dst = &AY;
\r
5312 m68ki_push_32(*r_dst);
\r
5313 *r_dst = REG_A[7];
\r
5314 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
5318 M68KMAKE_OP(link, 32, ., a7)
\r
5320 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5323 m68ki_write_32(REG_A[7], REG_A[7]);
\r
5324 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
\r
5327 m68ki_exception_illegal();
\r
5331 M68KMAKE_OP(link, 32, ., .)
\r
5333 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5335 uint* r_dst = &AY;
\r
5337 m68ki_push_32(*r_dst);
\r
5338 *r_dst = REG_A[7];
\r
5339 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
\r
5342 m68ki_exception_illegal();
\r
5346 M68KMAKE_OP(lsr, 8, s, .)
\r
5348 uint* r_dst = &DY;
\r
5349 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5350 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5351 uint res = src >> shift;
\r
5354 USE_CYCLES(shift<<CYC_SHIFT);
\r
5356 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5358 FLAG_N = NFLAG_CLEAR;
\r
5360 FLAG_X = FLAG_C = src << (9-shift);
\r
5361 FLAG_V = VFLAG_CLEAR;
\r
5365 M68KMAKE_OP(lsr, 16, s, .)
\r
5367 uint* r_dst = &DY;
\r
5368 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5369 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5370 uint res = src >> shift;
\r
5373 USE_CYCLES(shift<<CYC_SHIFT);
\r
5375 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5377 FLAG_N = NFLAG_CLEAR;
\r
5379 FLAG_X = FLAG_C = src << (9-shift);
\r
5380 FLAG_V = VFLAG_CLEAR;
\r
5384 M68KMAKE_OP(lsr, 32, s, .)
\r
5386 uint* r_dst = &DY;
\r
5387 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5388 uint src = *r_dst;
\r
5389 uint res = src >> shift;
\r
5392 USE_CYCLES(shift<<CYC_SHIFT);
\r
5396 FLAG_N = NFLAG_CLEAR;
\r
5398 FLAG_X = FLAG_C = src << (9-shift);
\r
5399 FLAG_V = VFLAG_CLEAR;
\r
5403 M68KMAKE_OP(lsr, 8, r, .)
\r
5405 uint* r_dst = &DY;
\r
5406 uint shift = DX & 0x3f;
\r
5407 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5408 uint res = src >> shift;
\r
5412 USE_CYCLES(shift<<CYC_SHIFT);
\r
5416 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5417 FLAG_X = FLAG_C = src << (9-shift);
\r
5418 FLAG_N = NFLAG_CLEAR;
\r
5420 FLAG_V = VFLAG_CLEAR;
\r
5424 *r_dst &= 0xffffff00;
\r
5425 FLAG_X = XFLAG_CLEAR;
\r
5426 FLAG_C = CFLAG_CLEAR;
\r
5427 FLAG_N = NFLAG_CLEAR;
\r
5428 FLAG_Z = ZFLAG_SET;
\r
5429 FLAG_V = VFLAG_CLEAR;
\r
5433 FLAG_C = CFLAG_CLEAR;
\r
5434 FLAG_N = NFLAG_8(src);
\r
5436 FLAG_V = VFLAG_CLEAR;
\r
5440 M68KMAKE_OP(lsr, 16, r, .)
\r
5442 uint* r_dst = &DY;
\r
5443 uint shift = DX & 0x3f;
\r
5444 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5445 uint res = src >> shift;
\r
5449 USE_CYCLES(shift<<CYC_SHIFT);
\r
5453 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5454 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
5455 FLAG_N = NFLAG_CLEAR;
\r
5457 FLAG_V = VFLAG_CLEAR;
\r
5461 *r_dst &= 0xffff0000;
\r
5462 FLAG_X = XFLAG_CLEAR;
\r
5463 FLAG_C = CFLAG_CLEAR;
\r
5464 FLAG_N = NFLAG_CLEAR;
\r
5465 FLAG_Z = ZFLAG_SET;
\r
5466 FLAG_V = VFLAG_CLEAR;
\r
5470 FLAG_C = CFLAG_CLEAR;
\r
5471 FLAG_N = NFLAG_16(src);
\r
5473 FLAG_V = VFLAG_CLEAR;
\r
5477 M68KMAKE_OP(lsr, 32, r, .)
\r
5479 uint* r_dst = &DY;
\r
5480 uint shift = DX & 0x3f;
\r
5481 uint src = *r_dst;
\r
5482 uint res = src >> shift;
\r
5486 USE_CYCLES(shift<<CYC_SHIFT);
\r
5491 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
5492 FLAG_N = NFLAG_CLEAR;
\r
5494 FLAG_V = VFLAG_CLEAR;
\r
5499 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
\r
5500 FLAG_N = NFLAG_CLEAR;
\r
5501 FLAG_Z = ZFLAG_SET;
\r
5502 FLAG_V = VFLAG_CLEAR;
\r
5506 FLAG_C = CFLAG_CLEAR;
\r
5507 FLAG_N = NFLAG_32(src);
\r
5509 FLAG_V = VFLAG_CLEAR;
\r
5513 M68KMAKE_OP(lsr, 16, ., .)
\r
5515 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5516 uint src = m68ki_read_16(ea);
\r
5517 uint res = src >> 1;
\r
5519 m68ki_write_16(ea, res);
\r
5521 FLAG_N = NFLAG_CLEAR;
\r
5523 FLAG_C = FLAG_X = src << 8;
\r
5524 FLAG_V = VFLAG_CLEAR;
\r
5528 M68KMAKE_OP(lsl, 8, s, .)
\r
5530 uint* r_dst = &DY;
\r
5531 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5532 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5533 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
5536 USE_CYCLES(shift<<CYC_SHIFT);
\r
5538 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5540 FLAG_N = NFLAG_8(res);
\r
5542 FLAG_X = FLAG_C = src << shift;
\r
5543 FLAG_V = VFLAG_CLEAR;
\r
5547 M68KMAKE_OP(lsl, 16, s, .)
\r
5549 uint* r_dst = &DY;
\r
5550 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5551 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5552 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
5555 USE_CYCLES(shift<<CYC_SHIFT);
\r
5557 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5559 FLAG_N = NFLAG_16(res);
\r
5561 FLAG_X = FLAG_C = src >> (8-shift);
\r
5562 FLAG_V = VFLAG_CLEAR;
\r
5566 M68KMAKE_OP(lsl, 32, s, .)
\r
5568 uint* r_dst = &DY;
\r
5569 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5570 uint src = *r_dst;
\r
5571 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
5574 USE_CYCLES(shift<<CYC_SHIFT);
\r
5578 FLAG_N = NFLAG_32(res);
\r
5580 FLAG_X = FLAG_C = src >> (24-shift);
\r
5581 FLAG_V = VFLAG_CLEAR;
\r
5585 M68KMAKE_OP(lsl, 8, r, .)
\r
5587 uint* r_dst = &DY;
\r
5588 uint shift = DX & 0x3f;
\r
5589 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5590 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
5594 USE_CYCLES(shift<<CYC_SHIFT);
\r
5598 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5599 FLAG_X = FLAG_C = src << shift;
\r
5600 FLAG_N = NFLAG_8(res);
\r
5602 FLAG_V = VFLAG_CLEAR;
\r
5606 *r_dst &= 0xffffff00;
\r
5607 FLAG_X = XFLAG_CLEAR;
\r
5608 FLAG_C = CFLAG_CLEAR;
\r
5609 FLAG_N = NFLAG_CLEAR;
\r
5610 FLAG_Z = ZFLAG_SET;
\r
5611 FLAG_V = VFLAG_CLEAR;
\r
5615 FLAG_C = CFLAG_CLEAR;
\r
5616 FLAG_N = NFLAG_8(src);
\r
5618 FLAG_V = VFLAG_CLEAR;
\r
5622 M68KMAKE_OP(lsl, 16, r, .)
\r
5624 uint* r_dst = &DY;
\r
5625 uint shift = DX & 0x3f;
\r
5626 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5627 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
5631 USE_CYCLES(shift<<CYC_SHIFT);
\r
5635 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5636 FLAG_X = FLAG_C = (src << shift) >> 8;
\r
5637 FLAG_N = NFLAG_16(res);
\r
5639 FLAG_V = VFLAG_CLEAR;
\r
5643 *r_dst &= 0xffff0000;
\r
5644 FLAG_X = XFLAG_CLEAR;
\r
5645 FLAG_C = CFLAG_CLEAR;
\r
5646 FLAG_N = NFLAG_CLEAR;
\r
5647 FLAG_Z = ZFLAG_SET;
\r
5648 FLAG_V = VFLAG_CLEAR;
\r
5652 FLAG_C = CFLAG_CLEAR;
\r
5653 FLAG_N = NFLAG_16(src);
\r
5655 FLAG_V = VFLAG_CLEAR;
\r
5659 M68KMAKE_OP(lsl, 32, r, .)
\r
5661 uint* r_dst = &DY;
\r
5662 uint shift = DX & 0x3f;
\r
5663 uint src = *r_dst;
\r
5664 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
5668 USE_CYCLES(shift<<CYC_SHIFT);
\r
5673 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
\r
5674 FLAG_N = NFLAG_32(res);
\r
5676 FLAG_V = VFLAG_CLEAR;
\r
5681 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
\r
5682 FLAG_N = NFLAG_CLEAR;
\r
5683 FLAG_Z = ZFLAG_SET;
\r
5684 FLAG_V = VFLAG_CLEAR;
\r
5688 FLAG_C = CFLAG_CLEAR;
\r
5689 FLAG_N = NFLAG_32(src);
\r
5691 FLAG_V = VFLAG_CLEAR;
\r
5695 M68KMAKE_OP(lsl, 16, ., .)
\r
5697 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5698 uint src = m68ki_read_16(ea);
\r
5699 uint res = MASK_OUT_ABOVE_16(src << 1);
\r
5701 m68ki_write_16(ea, res);
\r
5703 FLAG_N = NFLAG_16(res);
\r
5705 FLAG_X = FLAG_C = src >> 7;
\r
5706 FLAG_V = VFLAG_CLEAR;
\r
5710 M68KMAKE_OP(move, 8, d, d)
\r
5712 uint res = MASK_OUT_ABOVE_8(DY);
\r
5713 uint* r_dst = &DX;
\r
5715 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5717 FLAG_N = NFLAG_8(res);
\r
5719 FLAG_V = VFLAG_CLEAR;
\r
5720 FLAG_C = CFLAG_CLEAR;
\r
5724 M68KMAKE_OP(move, 8, d, .)
\r
5726 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5727 uint* r_dst = &DX;
\r
5729 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5731 FLAG_N = NFLAG_8(res);
\r
5733 FLAG_V = VFLAG_CLEAR;
\r
5734 FLAG_C = CFLAG_CLEAR;
\r
5738 M68KMAKE_OP(move, 8, ai, d)
\r
5740 uint res = MASK_OUT_ABOVE_8(DY);
\r
5741 uint ea = EA_AX_AI_8();
\r
5743 m68ki_write_8(ea, res);
\r
5745 FLAG_N = NFLAG_8(res);
\r
5747 FLAG_V = VFLAG_CLEAR;
\r
5748 FLAG_C = CFLAG_CLEAR;
\r
5752 M68KMAKE_OP(move, 8, ai, .)
\r
5754 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5755 uint ea = EA_AX_AI_8();
\r
5757 m68ki_write_8(ea, res);
\r
5759 FLAG_N = NFLAG_8(res);
\r
5761 FLAG_V = VFLAG_CLEAR;
\r
5762 FLAG_C = CFLAG_CLEAR;
\r
5766 M68KMAKE_OP(move, 8, pi7, d)
\r
5768 uint res = MASK_OUT_ABOVE_8(DY);
\r
5769 uint ea = EA_A7_PI_8();
\r
5771 m68ki_write_8(ea, res);
\r
5773 FLAG_N = NFLAG_8(res);
\r
5775 FLAG_V = VFLAG_CLEAR;
\r
5776 FLAG_C = CFLAG_CLEAR;
\r
5780 M68KMAKE_OP(move, 8, pi, d)
\r
5782 uint res = MASK_OUT_ABOVE_8(DY);
\r
5783 uint ea = EA_AX_PI_8();
\r
5785 m68ki_write_8(ea, res);
\r
5787 FLAG_N = NFLAG_8(res);
\r
5789 FLAG_V = VFLAG_CLEAR;
\r
5790 FLAG_C = CFLAG_CLEAR;
\r
5794 M68KMAKE_OP(move, 8, pi7, .)
\r
5796 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5797 uint ea = EA_A7_PI_8();
\r
5799 m68ki_write_8(ea, res);
\r
5801 FLAG_N = NFLAG_8(res);
\r
5803 FLAG_V = VFLAG_CLEAR;
\r
5804 FLAG_C = CFLAG_CLEAR;
\r
5808 M68KMAKE_OP(move, 8, pi, .)
\r
5810 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5811 uint ea = EA_AX_PI_8();
\r
5813 m68ki_write_8(ea, res);
\r
5815 FLAG_N = NFLAG_8(res);
\r
5817 FLAG_V = VFLAG_CLEAR;
\r
5818 FLAG_C = CFLAG_CLEAR;
\r
5822 M68KMAKE_OP(move, 8, pd7, d)
\r
5824 uint res = MASK_OUT_ABOVE_8(DY);
\r
5825 uint ea = EA_A7_PD_8();
\r
5827 m68ki_write_8(ea, res);
\r
5829 FLAG_N = NFLAG_8(res);
\r
5831 FLAG_V = VFLAG_CLEAR;
\r
5832 FLAG_C = CFLAG_CLEAR;
\r
5836 M68KMAKE_OP(move, 8, pd, d)
\r
5838 uint res = MASK_OUT_ABOVE_8(DY);
\r
5839 uint ea = EA_AX_PD_8();
\r
5841 m68ki_write_8(ea, res);
\r
5843 FLAG_N = NFLAG_8(res);
\r
5845 FLAG_V = VFLAG_CLEAR;
\r
5846 FLAG_C = CFLAG_CLEAR;
\r
5850 M68KMAKE_OP(move, 8, pd7, .)
\r
5852 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5853 uint ea = EA_A7_PD_8();
\r
5855 m68ki_write_8(ea, res);
\r
5857 FLAG_N = NFLAG_8(res);
\r
5859 FLAG_V = VFLAG_CLEAR;
\r
5860 FLAG_C = CFLAG_CLEAR;
\r
5864 M68KMAKE_OP(move, 8, pd, .)
\r
5866 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5867 uint ea = EA_AX_PD_8();
\r
5869 m68ki_write_8(ea, res);
\r
5871 FLAG_N = NFLAG_8(res);
\r
5873 FLAG_V = VFLAG_CLEAR;
\r
5874 FLAG_C = CFLAG_CLEAR;
\r
5878 M68KMAKE_OP(move, 8, di, d)
\r
5880 uint res = MASK_OUT_ABOVE_8(DY);
\r
5881 uint ea = EA_AX_DI_8();
\r
5883 m68ki_write_8(ea, res);
\r
5885 FLAG_N = NFLAG_8(res);
\r
5887 FLAG_V = VFLAG_CLEAR;
\r
5888 FLAG_C = CFLAG_CLEAR;
\r
5892 M68KMAKE_OP(move, 8, di, .)
\r
5894 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5895 uint ea = EA_AX_DI_8();
\r
5897 m68ki_write_8(ea, res);
\r
5899 FLAG_N = NFLAG_8(res);
\r
5901 FLAG_V = VFLAG_CLEAR;
\r
5902 FLAG_C = CFLAG_CLEAR;
\r
5906 M68KMAKE_OP(move, 8, ix, d)
\r
5908 uint res = MASK_OUT_ABOVE_8(DY);
\r
5909 uint ea = EA_AX_IX_8();
\r
5911 m68ki_write_8(ea, res);
\r
5913 FLAG_N = NFLAG_8(res);
\r
5915 FLAG_V = VFLAG_CLEAR;
\r
5916 FLAG_C = CFLAG_CLEAR;
\r
5920 M68KMAKE_OP(move, 8, ix, .)
\r
5922 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5923 uint ea = EA_AX_IX_8();
\r
5925 m68ki_write_8(ea, res);
\r
5927 FLAG_N = NFLAG_8(res);
\r
5929 FLAG_V = VFLAG_CLEAR;
\r
5930 FLAG_C = CFLAG_CLEAR;
\r
5934 M68KMAKE_OP(move, 8, aw, d)
\r
5936 uint res = MASK_OUT_ABOVE_8(DY);
\r
5937 uint ea = EA_AW_8();
\r
5939 m68ki_write_8(ea, res);
\r
5941 FLAG_N = NFLAG_8(res);
\r
5943 FLAG_V = VFLAG_CLEAR;
\r
5944 FLAG_C = CFLAG_CLEAR;
\r
5948 M68KMAKE_OP(move, 8, aw, .)
\r
5950 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5951 uint ea = EA_AW_8();
\r
5953 m68ki_write_8(ea, res);
\r
5955 FLAG_N = NFLAG_8(res);
\r
5957 FLAG_V = VFLAG_CLEAR;
\r
5958 FLAG_C = CFLAG_CLEAR;
\r
5962 M68KMAKE_OP(move, 8, al, d)
\r
5964 uint res = MASK_OUT_ABOVE_8(DY);
\r
5965 uint ea = EA_AL_8();
\r
5967 m68ki_write_8(ea, res);
\r
5969 FLAG_N = NFLAG_8(res);
\r
5971 FLAG_V = VFLAG_CLEAR;
\r
5972 FLAG_C = CFLAG_CLEAR;
\r
5976 M68KMAKE_OP(move, 8, al, .)
\r
5978 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5979 uint ea = EA_AL_8();
\r
5981 m68ki_write_8(ea, res);
\r
5983 FLAG_N = NFLAG_8(res);
\r
5985 FLAG_V = VFLAG_CLEAR;
\r
5986 FLAG_C = CFLAG_CLEAR;
\r
5990 M68KMAKE_OP(move, 16, d, d)
\r
5992 uint res = MASK_OUT_ABOVE_16(DY);
\r
5993 uint* r_dst = &DX;
\r
5995 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5997 FLAG_N = NFLAG_16(res);
\r
5999 FLAG_V = VFLAG_CLEAR;
\r
6000 FLAG_C = CFLAG_CLEAR;
\r
6004 M68KMAKE_OP(move, 16, d, a)
\r
6006 uint res = MASK_OUT_ABOVE_16(AY);
\r
6007 uint* r_dst = &DX;
\r
6009 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
6011 FLAG_N = NFLAG_16(res);
\r
6013 FLAG_V = VFLAG_CLEAR;
\r
6014 FLAG_C = CFLAG_CLEAR;
\r
6018 M68KMAKE_OP(move, 16, d, .)
\r
6020 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6021 uint* r_dst = &DX;
\r
6023 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
6025 FLAG_N = NFLAG_16(res);
\r
6027 FLAG_V = VFLAG_CLEAR;
\r
6028 FLAG_C = CFLAG_CLEAR;
\r
6032 M68KMAKE_OP(move, 16, ai, d)
\r
6034 uint res = MASK_OUT_ABOVE_16(DY);
\r
6035 uint ea = EA_AX_AI_16();
\r
6037 m68ki_write_16(ea, res);
\r
6039 FLAG_N = NFLAG_16(res);
\r
6041 FLAG_V = VFLAG_CLEAR;
\r
6042 FLAG_C = CFLAG_CLEAR;
\r
6046 M68KMAKE_OP(move, 16, ai, a)
\r
6048 uint res = MASK_OUT_ABOVE_16(AY);
\r
6049 uint ea = EA_AX_AI_16();
\r
6051 m68ki_write_16(ea, res);
\r
6053 FLAG_N = NFLAG_16(res);
\r
6055 FLAG_V = VFLAG_CLEAR;
\r
6056 FLAG_C = CFLAG_CLEAR;
\r
6060 M68KMAKE_OP(move, 16, ai, .)
\r
6062 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6063 uint ea = EA_AX_AI_16();
\r
6065 m68ki_write_16(ea, res);
\r
6067 FLAG_N = NFLAG_16(res);
\r
6069 FLAG_V = VFLAG_CLEAR;
\r
6070 FLAG_C = CFLAG_CLEAR;
\r
6074 M68KMAKE_OP(move, 16, pi, d)
\r
6076 uint res = MASK_OUT_ABOVE_16(DY);
\r
6077 uint ea = EA_AX_PI_16();
\r
6079 m68ki_write_16(ea, res);
\r
6081 FLAG_N = NFLAG_16(res);
\r
6083 FLAG_V = VFLAG_CLEAR;
\r
6084 FLAG_C = CFLAG_CLEAR;
\r
6088 M68KMAKE_OP(move, 16, pi, a)
\r
6090 uint res = MASK_OUT_ABOVE_16(AY);
\r
6091 uint ea = EA_AX_PI_16();
\r
6093 m68ki_write_16(ea, res);
\r
6095 FLAG_N = NFLAG_16(res);
\r
6097 FLAG_V = VFLAG_CLEAR;
\r
6098 FLAG_C = CFLAG_CLEAR;
\r
6102 M68KMAKE_OP(move, 16, pi, .)
\r
6104 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6105 uint ea = EA_AX_PI_16();
\r
6107 m68ki_write_16(ea, res);
\r
6109 FLAG_N = NFLAG_16(res);
\r
6111 FLAG_V = VFLAG_CLEAR;
\r
6112 FLAG_C = CFLAG_CLEAR;
\r
6116 M68KMAKE_OP(move, 16, pd, d)
\r
6118 uint res = MASK_OUT_ABOVE_16(DY);
\r
6119 uint ea = EA_AX_PD_16();
\r
6121 m68ki_write_16(ea, res);
\r
6123 FLAG_N = NFLAG_16(res);
\r
6125 FLAG_V = VFLAG_CLEAR;
\r
6126 FLAG_C = CFLAG_CLEAR;
\r
6130 M68KMAKE_OP(move, 16, pd, a)
\r
6132 uint res = MASK_OUT_ABOVE_16(AY);
\r
6133 uint ea = EA_AX_PD_16();
\r
6135 m68ki_write_16(ea, res);
\r
6137 FLAG_N = NFLAG_16(res);
\r
6139 FLAG_V = VFLAG_CLEAR;
\r
6140 FLAG_C = CFLAG_CLEAR;
\r
6144 M68KMAKE_OP(move, 16, pd, .)
\r
6146 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6147 uint ea = EA_AX_PD_16();
\r
6149 m68ki_write_16(ea, res);
\r
6151 FLAG_N = NFLAG_16(res);
\r
6153 FLAG_V = VFLAG_CLEAR;
\r
6154 FLAG_C = CFLAG_CLEAR;
\r
6158 M68KMAKE_OP(move, 16, di, d)
\r
6160 uint res = MASK_OUT_ABOVE_16(DY);
\r
6161 uint ea = EA_AX_DI_16();
\r
6163 m68ki_write_16(ea, res);
\r
6165 FLAG_N = NFLAG_16(res);
\r
6167 FLAG_V = VFLAG_CLEAR;
\r
6168 FLAG_C = CFLAG_CLEAR;
\r
6172 M68KMAKE_OP(move, 16, di, a)
\r
6174 uint res = MASK_OUT_ABOVE_16(AY);
\r
6175 uint ea = EA_AX_DI_16();
\r
6177 m68ki_write_16(ea, res);
\r
6179 FLAG_N = NFLAG_16(res);
\r
6181 FLAG_V = VFLAG_CLEAR;
\r
6182 FLAG_C = CFLAG_CLEAR;
\r
6186 M68KMAKE_OP(move, 16, di, .)
\r
6188 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6189 uint ea = EA_AX_DI_16();
\r
6191 m68ki_write_16(ea, res);
\r
6193 FLAG_N = NFLAG_16(res);
\r
6195 FLAG_V = VFLAG_CLEAR;
\r
6196 FLAG_C = CFLAG_CLEAR;
\r
6200 M68KMAKE_OP(move, 16, ix, d)
\r
6202 uint res = MASK_OUT_ABOVE_16(DY);
\r
6203 uint ea = EA_AX_IX_16();
\r
6205 m68ki_write_16(ea, res);
\r
6207 FLAG_N = NFLAG_16(res);
\r
6209 FLAG_V = VFLAG_CLEAR;
\r
6210 FLAG_C = CFLAG_CLEAR;
\r
6214 M68KMAKE_OP(move, 16, ix, a)
\r
6216 uint res = MASK_OUT_ABOVE_16(AY);
\r
6217 uint ea = EA_AX_IX_16();
\r
6219 m68ki_write_16(ea, res);
\r
6221 FLAG_N = NFLAG_16(res);
\r
6223 FLAG_V = VFLAG_CLEAR;
\r
6224 FLAG_C = CFLAG_CLEAR;
\r
6228 M68KMAKE_OP(move, 16, ix, .)
\r
6230 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6231 uint ea = EA_AX_IX_16();
\r
6233 m68ki_write_16(ea, res);
\r
6235 FLAG_N = NFLAG_16(res);
\r
6237 FLAG_V = VFLAG_CLEAR;
\r
6238 FLAG_C = CFLAG_CLEAR;
\r
6242 M68KMAKE_OP(move, 16, aw, d)
\r
6244 uint res = MASK_OUT_ABOVE_16(DY);
\r
6245 uint ea = EA_AW_16();
\r
6247 m68ki_write_16(ea, res);
\r
6249 FLAG_N = NFLAG_16(res);
\r
6251 FLAG_V = VFLAG_CLEAR;
\r
6252 FLAG_C = CFLAG_CLEAR;
\r
6256 M68KMAKE_OP(move, 16, aw, a)
\r
6258 uint res = MASK_OUT_ABOVE_16(AY);
\r
6259 uint ea = EA_AW_16();
\r
6261 m68ki_write_16(ea, res);
\r
6263 FLAG_N = NFLAG_16(res);
\r
6265 FLAG_V = VFLAG_CLEAR;
\r
6266 FLAG_C = CFLAG_CLEAR;
\r
6270 M68KMAKE_OP(move, 16, aw, .)
\r
6272 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6273 uint ea = EA_AW_16();
\r
6275 m68ki_write_16(ea, res);
\r
6277 FLAG_N = NFLAG_16(res);
\r
6279 FLAG_V = VFLAG_CLEAR;
\r
6280 FLAG_C = CFLAG_CLEAR;
\r
6284 M68KMAKE_OP(move, 16, al, d)
\r
6286 uint res = MASK_OUT_ABOVE_16(DY);
\r
6287 uint ea = EA_AL_16();
\r
6289 m68ki_write_16(ea, res);
\r
6291 FLAG_N = NFLAG_16(res);
\r
6293 FLAG_V = VFLAG_CLEAR;
\r
6294 FLAG_C = CFLAG_CLEAR;
\r
6298 M68KMAKE_OP(move, 16, al, a)
\r
6300 uint res = MASK_OUT_ABOVE_16(AY);
\r
6301 uint ea = EA_AL_16();
\r
6303 m68ki_write_16(ea, res);
\r
6305 FLAG_N = NFLAG_16(res);
\r
6307 FLAG_V = VFLAG_CLEAR;
\r
6308 FLAG_C = CFLAG_CLEAR;
\r
6312 M68KMAKE_OP(move, 16, al, .)
\r
6314 uint res = M68KMAKE_GET_OPER_AY_16;
\r
6315 uint ea = EA_AL_16();
\r
6317 m68ki_write_16(ea, res);
\r
6319 FLAG_N = NFLAG_16(res);
\r
6321 FLAG_V = VFLAG_CLEAR;
\r
6322 FLAG_C = CFLAG_CLEAR;
\r
6326 M68KMAKE_OP(move, 32, d, d)
\r
6329 uint* r_dst = &DX;
\r
6333 FLAG_N = NFLAG_32(res);
\r
6335 FLAG_V = VFLAG_CLEAR;
\r
6336 FLAG_C = CFLAG_CLEAR;
\r
6340 M68KMAKE_OP(move, 32, d, a)
\r
6343 uint* r_dst = &DX;
\r
6347 FLAG_N = NFLAG_32(res);
\r
6349 FLAG_V = VFLAG_CLEAR;
\r
6350 FLAG_C = CFLAG_CLEAR;
\r
6354 M68KMAKE_OP(move, 32, d, .)
\r
6356 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6357 uint* r_dst = &DX;
\r
6361 FLAG_N = NFLAG_32(res);
\r
6363 FLAG_V = VFLAG_CLEAR;
\r
6364 FLAG_C = CFLAG_CLEAR;
\r
6368 M68KMAKE_OP(move, 32, ai, d)
\r
6371 uint ea = EA_AX_AI_32();
\r
6373 m68ki_write_32(ea, res);
\r
6375 FLAG_N = NFLAG_32(res);
\r
6377 FLAG_V = VFLAG_CLEAR;
\r
6378 FLAG_C = CFLAG_CLEAR;
\r
6382 M68KMAKE_OP(move, 32, ai, a)
\r
6385 uint ea = EA_AX_AI_32();
\r
6387 m68ki_write_32(ea, res);
\r
6389 FLAG_N = NFLAG_32(res);
\r
6391 FLAG_V = VFLAG_CLEAR;
\r
6392 FLAG_C = CFLAG_CLEAR;
\r
6396 M68KMAKE_OP(move, 32, ai, .)
\r
6398 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6399 uint ea = EA_AX_AI_32();
\r
6401 m68ki_write_32(ea, res);
\r
6403 FLAG_N = NFLAG_32(res);
\r
6405 FLAG_V = VFLAG_CLEAR;
\r
6406 FLAG_C = CFLAG_CLEAR;
\r
6410 M68KMAKE_OP(move, 32, pi, d)
\r
6413 uint ea = EA_AX_PI_32();
\r
6415 m68ki_write_32(ea, res);
\r
6417 FLAG_N = NFLAG_32(res);
\r
6419 FLAG_V = VFLAG_CLEAR;
\r
6420 FLAG_C = CFLAG_CLEAR;
\r
6424 M68KMAKE_OP(move, 32, pi, a)
\r
6427 uint ea = EA_AX_PI_32();
\r
6429 m68ki_write_32(ea, res);
\r
6431 FLAG_N = NFLAG_32(res);
\r
6433 FLAG_V = VFLAG_CLEAR;
\r
6434 FLAG_C = CFLAG_CLEAR;
\r
6438 M68KMAKE_OP(move, 32, pi, .)
\r
6440 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6441 uint ea = EA_AX_PI_32();
\r
6443 m68ki_write_32(ea, res);
\r
6445 FLAG_N = NFLAG_32(res);
\r
6447 FLAG_V = VFLAG_CLEAR;
\r
6448 FLAG_C = CFLAG_CLEAR;
\r
6452 M68KMAKE_OP(move, 32, pd, d)
\r
6455 uint ea = EA_AX_PD_32();
\r
6457 m68ki_write_16(ea+2, res & 0xFFFF );
\r
6458 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
\r
6460 FLAG_N = NFLAG_32(res);
\r
6462 FLAG_V = VFLAG_CLEAR;
\r
6463 FLAG_C = CFLAG_CLEAR;
\r
6467 M68KMAKE_OP(move, 32, pd, a)
\r
6470 uint ea = EA_AX_PD_32();
\r
6472 m68ki_write_16(ea+2, res & 0xFFFF );
\r
6473 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
\r
6475 FLAG_N = NFLAG_32(res);
\r
6477 FLAG_V = VFLAG_CLEAR;
\r
6478 FLAG_C = CFLAG_CLEAR;
\r
6482 M68KMAKE_OP(move, 32, pd, .)
\r
6484 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6485 uint ea = EA_AX_PD_32();
\r
6487 m68ki_write_16(ea+2, res & 0xFFFF );
\r
6488 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
\r
6490 FLAG_N = NFLAG_32(res);
\r
6492 FLAG_V = VFLAG_CLEAR;
\r
6493 FLAG_C = CFLAG_CLEAR;
\r
6497 M68KMAKE_OP(move, 32, di, d)
\r
6500 uint ea = EA_AX_DI_32();
\r
6502 m68ki_write_32(ea, res);
\r
6504 FLAG_N = NFLAG_32(res);
\r
6506 FLAG_V = VFLAG_CLEAR;
\r
6507 FLAG_C = CFLAG_CLEAR;
\r
6511 M68KMAKE_OP(move, 32, di, a)
\r
6514 uint ea = EA_AX_DI_32();
\r
6516 m68ki_write_32(ea, res);
\r
6518 FLAG_N = NFLAG_32(res);
\r
6520 FLAG_V = VFLAG_CLEAR;
\r
6521 FLAG_C = CFLAG_CLEAR;
\r
6525 M68KMAKE_OP(move, 32, di, .)
\r
6527 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6528 uint ea = EA_AX_DI_32();
\r
6530 m68ki_write_32(ea, res);
\r
6532 FLAG_N = NFLAG_32(res);
\r
6534 FLAG_V = VFLAG_CLEAR;
\r
6535 FLAG_C = CFLAG_CLEAR;
\r
6539 M68KMAKE_OP(move, 32, ix, d)
\r
6542 uint ea = EA_AX_IX_32();
\r
6544 m68ki_write_32(ea, res);
\r
6546 FLAG_N = NFLAG_32(res);
\r
6548 FLAG_V = VFLAG_CLEAR;
\r
6549 FLAG_C = CFLAG_CLEAR;
\r
6553 M68KMAKE_OP(move, 32, ix, a)
\r
6556 uint ea = EA_AX_IX_32();
\r
6558 m68ki_write_32(ea, res);
\r
6560 FLAG_N = NFLAG_32(res);
\r
6562 FLAG_V = VFLAG_CLEAR;
\r
6563 FLAG_C = CFLAG_CLEAR;
\r
6567 M68KMAKE_OP(move, 32, ix, .)
\r
6569 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6570 uint ea = EA_AX_IX_32();
\r
6572 m68ki_write_32(ea, res);
\r
6574 FLAG_N = NFLAG_32(res);
\r
6576 FLAG_V = VFLAG_CLEAR;
\r
6577 FLAG_C = CFLAG_CLEAR;
\r
6581 M68KMAKE_OP(move, 32, aw, d)
\r
6584 uint ea = EA_AW_32();
\r
6586 m68ki_write_32(ea, res);
\r
6588 FLAG_N = NFLAG_32(res);
\r
6590 FLAG_V = VFLAG_CLEAR;
\r
6591 FLAG_C = CFLAG_CLEAR;
\r
6595 M68KMAKE_OP(move, 32, aw, a)
\r
6598 uint ea = EA_AW_32();
\r
6600 m68ki_write_32(ea, res);
\r
6602 FLAG_N = NFLAG_32(res);
\r
6604 FLAG_V = VFLAG_CLEAR;
\r
6605 FLAG_C = CFLAG_CLEAR;
\r
6609 M68KMAKE_OP(move, 32, aw, .)
\r
6611 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6612 uint ea = EA_AW_32();
\r
6614 m68ki_write_32(ea, res);
\r
6616 FLAG_N = NFLAG_32(res);
\r
6618 FLAG_V = VFLAG_CLEAR;
\r
6619 FLAG_C = CFLAG_CLEAR;
\r
6623 M68KMAKE_OP(move, 32, al, d)
\r
6626 uint ea = EA_AL_32();
\r
6628 m68ki_write_32(ea, res);
\r
6630 FLAG_N = NFLAG_32(res);
\r
6632 FLAG_V = VFLAG_CLEAR;
\r
6633 FLAG_C = CFLAG_CLEAR;
\r
6637 M68KMAKE_OP(move, 32, al, a)
\r
6640 uint ea = EA_AL_32();
\r
6642 m68ki_write_32(ea, res);
\r
6644 FLAG_N = NFLAG_32(res);
\r
6646 FLAG_V = VFLAG_CLEAR;
\r
6647 FLAG_C = CFLAG_CLEAR;
\r
6651 M68KMAKE_OP(move, 32, al, .)
\r
6653 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6654 uint ea = EA_AL_32();
\r
6656 m68ki_write_32(ea, res);
\r
6658 FLAG_N = NFLAG_32(res);
\r
6660 FLAG_V = VFLAG_CLEAR;
\r
6661 FLAG_C = CFLAG_CLEAR;
\r
6665 M68KMAKE_OP(movea, 16, ., d)
\r
6667 AX = MAKE_INT_16(DY);
\r
6671 M68KMAKE_OP(movea, 16, ., a)
\r
6673 AX = MAKE_INT_16(AY);
\r
6677 M68KMAKE_OP(movea, 16, ., .)
\r
6679 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
6683 M68KMAKE_OP(movea, 32, ., d)
\r
6689 M68KMAKE_OP(movea, 32, ., a)
\r
6695 M68KMAKE_OP(movea, 32, ., .)
\r
6697 AX = M68KMAKE_GET_OPER_AY_32;
\r
6701 M68KMAKE_OP(move, 16, frc, d)
\r
6703 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6705 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
\r
6708 m68ki_exception_illegal();
\r
6712 M68KMAKE_OP(move, 16, frc, .)
\r
6714 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6716 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
\r
6719 m68ki_exception_illegal();
\r
6723 M68KMAKE_OP(move, 16, toc, d)
\r
6725 m68ki_set_ccr(DY);
\r
6729 M68KMAKE_OP(move, 16, toc, .)
\r
6731 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
\r
6735 M68KMAKE_OP(move, 16, frs, d)
\r
6737 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
\r
6739 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
\r
6742 m68ki_exception_privilege_violation();
\r
6746 M68KMAKE_OP(move, 16, frs, .)
\r
6748 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
\r
6750 uint ea = M68KMAKE_GET_EA_AY_16;
\r
6751 m68ki_write_16(ea, m68ki_get_sr());
\r
6754 m68ki_exception_privilege_violation();
\r
6758 M68KMAKE_OP(move, 16, tos, d)
\r
6765 m68ki_exception_privilege_violation();
\r
6769 M68KMAKE_OP(move, 16, tos, .)
\r
6773 uint new_sr = M68KMAKE_GET_OPER_AY_16;
\r
6774 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6775 m68ki_set_sr(new_sr);
\r
6778 m68ki_exception_privilege_violation();
\r
6782 M68KMAKE_OP(move, 32, fru, .)
\r
6789 m68ki_exception_privilege_violation();
\r
6793 M68KMAKE_OP(move, 32, tou, .)
\r
6797 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6801 m68ki_exception_privilege_violation();
\r
6805 M68KMAKE_OP(movec, 32, cr, .)
\r
6807 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6811 uint word2 = OPER_I_16();
\r
6813 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6814 switch (word2 & 0xfff)
\r
6816 case 0x000: /* SFC */
\r
6817 REG_DA[(word2 >> 12) & 15] = REG_SFC;
\r
6819 case 0x001: /* DFC */
\r
6820 REG_DA[(word2 >> 12) & 15] = REG_DFC;
\r
6822 case 0x002: /* CACR */
\r
6823 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6825 REG_DA[(word2 >> 12) & 15] = REG_CACR;
\r
6829 case 0x800: /* USP */
\r
6830 REG_DA[(word2 >> 12) & 15] = REG_USP;
\r
6832 case 0x801: /* VBR */
\r
6833 REG_DA[(word2 >> 12) & 15] = REG_VBR;
\r
6835 case 0x802: /* CAAR */
\r
6836 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6838 REG_DA[(word2 >> 12) & 15] = REG_CAAR;
\r
6841 m68ki_exception_illegal();
\r
6843 case 0x803: /* MSP */
\r
6844 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6846 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
\r
6849 m68ki_exception_illegal();
\r
6851 case 0x804: /* ISP */
\r
6852 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6854 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
\r
6857 m68ki_exception_illegal();
\r
6859 case 0x003: /* TC */
\r
6860 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6865 m68ki_exception_illegal();
\r
6867 case 0x004: /* ITT0 */
\r
6868 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6873 m68ki_exception_illegal();
\r
6875 case 0x005: /* ITT1 */
\r
6876 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6881 m68ki_exception_illegal();
\r
6883 case 0x006: /* DTT0 */
\r
6884 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6889 m68ki_exception_illegal();
\r
6891 case 0x007: /* DTT1 */
\r
6892 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6897 m68ki_exception_illegal();
\r
6899 case 0x805: /* MMUSR */
\r
6900 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6905 m68ki_exception_illegal();
\r
6907 case 0x806: /* URP */
\r
6908 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6913 m68ki_exception_illegal();
\r
6915 case 0x807: /* SRP */
\r
6916 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6921 m68ki_exception_illegal();
\r
6924 m68ki_exception_illegal();
\r
6928 m68ki_exception_privilege_violation();
\r
6931 m68ki_exception_illegal();
\r
6935 M68KMAKE_OP(movec, 32, rc, .)
\r
6937 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6941 uint word2 = OPER_I_16();
\r
6943 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6944 switch (word2 & 0xfff)
\r
6946 case 0x000: /* SFC */
\r
6947 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
\r
6949 case 0x001: /* DFC */
\r
6950 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
\r
6952 case 0x002: /* CACR */
\r
6953 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6955 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
6957 REG_CACR = REG_DA[(word2 >> 12) & 15];
\r
6961 /* non 68040 can only set the lower 4 bits (C,CE,F,E) */
\r
6962 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;
\r
6966 m68ki_exception_illegal();
\r
6968 case 0x800: /* USP */
\r
6969 REG_USP = REG_DA[(word2 >> 12) & 15];
\r
6971 case 0x801: /* VBR */
\r
6972 REG_VBR = REG_DA[(word2 >> 12) & 15];
\r
6974 case 0x802: /* CAAR */
\r
6975 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6977 REG_CAAR = REG_DA[(word2 >> 12) & 15];
\r
6980 m68ki_exception_illegal();
\r
6982 case 0x803: /* MSP */
\r
6983 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6985 /* we are in supervisor mode so just check for M flag */
\r
6988 REG_MSP = REG_DA[(word2 >> 12) & 15];
\r
6991 REG_SP = REG_DA[(word2 >> 12) & 15];
\r
6994 m68ki_exception_illegal();
\r
6996 case 0x804: /* ISP */
\r
6997 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7001 REG_SP = REG_DA[(word2 >> 12) & 15];
\r
7004 REG_ISP = REG_DA[(word2 >> 12) & 15];
\r
7007 m68ki_exception_illegal();
\r
7009 case 0x003: /* TC */
\r
7010 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7015 m68ki_exception_illegal();
\r
7017 case 0x004: /* ITT0 */
\r
7018 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7023 m68ki_exception_illegal();
\r
7025 case 0x005: /* ITT1 */
\r
7026 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7031 m68ki_exception_illegal();
\r
7033 case 0x006: /* DTT0 */
\r
7034 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7039 m68ki_exception_illegal();
\r
7041 case 0x007: /* DTT1 */
\r
7042 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7047 m68ki_exception_illegal();
\r
7049 case 0x805: /* MMUSR */
\r
7050 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7055 m68ki_exception_illegal();
\r
7057 case 0x806: /* URP */
\r
7058 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7063 m68ki_exception_illegal();
\r
7065 case 0x807: /* SRP */
\r
7066 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
7071 m68ki_exception_illegal();
\r
7074 m68ki_exception_illegal();
\r
7078 m68ki_exception_privilege_violation();
\r
7081 m68ki_exception_illegal();
\r
7085 M68KMAKE_OP(movem, 16, re, pd)
\r
7088 uint register_list = OPER_I_16();
\r
7092 for(; i < 16; i++)
\r
7093 if(register_list & (1 << i))
\r
7096 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
\r
7101 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7105 M68KMAKE_OP(movem, 16, re, .)
\r
7108 uint register_list = OPER_I_16();
\r
7109 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7112 for(; i < 16; i++)
\r
7113 if(register_list & (1 << i))
\r
7115 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
\r
7120 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7124 M68KMAKE_OP(movem, 32, re, pd)
\r
7127 uint register_list = OPER_I_16();
\r
7131 for(; i < 16; i++)
\r
7132 if(register_list & (1 << i))
\r
7135 m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
\r
7136 m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
\r
7141 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7145 M68KMAKE_OP(movem, 32, re, .)
\r
7148 uint register_list = OPER_I_16();
\r
7149 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7152 for(; i < 16; i++)
\r
7153 if(register_list & (1 << i))
\r
7155 m68ki_write_32(ea, REG_DA[i]);
\r
7160 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7164 M68KMAKE_OP(movem, 16, er, pi)
\r
7167 uint register_list = OPER_I_16();
\r
7171 for(; i < 16; i++)
\r
7172 if(register_list & (1 << i))
\r
7174 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
\r
7180 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7184 M68KMAKE_OP(movem, 16, er, pcdi)
\r
7187 uint register_list = OPER_I_16();
\r
7188 uint ea = EA_PCDI_16();
\r
7191 for(; i < 16; i++)
\r
7192 if(register_list & (1 << i))
\r
7194 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
\r
7199 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7203 M68KMAKE_OP(movem, 16, er, pcix)
\r
7206 uint register_list = OPER_I_16();
\r
7207 uint ea = EA_PCIX_16();
\r
7210 for(; i < 16; i++)
\r
7211 if(register_list & (1 << i))
\r
7213 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
\r
7218 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7222 M68KMAKE_OP(movem, 16, er, .)
\r
7225 uint register_list = OPER_I_16();
\r
7226 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7229 for(; i < 16; i++)
\r
7230 if(register_list & (1 << i))
\r
7232 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
\r
7237 USE_CYCLES(count<<CYC_MOVEM_W);
\r
7241 M68KMAKE_OP(movem, 32, er, pi)
\r
7244 uint register_list = OPER_I_16();
\r
7248 for(; i < 16; i++)
\r
7249 if(register_list & (1 << i))
\r
7251 REG_DA[i] = m68ki_read_32(ea);
\r
7257 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7261 M68KMAKE_OP(movem, 32, er, pcdi)
\r
7264 uint register_list = OPER_I_16();
\r
7265 uint ea = EA_PCDI_32();
\r
7268 for(; i < 16; i++)
\r
7269 if(register_list & (1 << i))
\r
7271 REG_DA[i] = m68ki_read_pcrel_32(ea);
\r
7276 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7280 M68KMAKE_OP(movem, 32, er, pcix)
\r
7283 uint register_list = OPER_I_16();
\r
7284 uint ea = EA_PCIX_32();
\r
7287 for(; i < 16; i++)
\r
7288 if(register_list & (1 << i))
\r
7290 REG_DA[i] = m68ki_read_pcrel_32(ea);
\r
7295 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7299 M68KMAKE_OP(movem, 32, er, .)
\r
7302 uint register_list = OPER_I_16();
\r
7303 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7306 for(; i < 16; i++)
\r
7307 if(register_list & (1 << i))
\r
7309 REG_DA[i] = m68ki_read_32(ea);
\r
7314 USE_CYCLES(count<<CYC_MOVEM_L);
\r
7318 M68KMAKE_OP(movep, 16, re, .)
\r
7320 uint ea = EA_AY_DI_16();
\r
7323 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
\r
7324 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
\r
7328 M68KMAKE_OP(movep, 32, re, .)
\r
7330 uint ea = EA_AY_DI_32();
\r
7333 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
\r
7334 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
\r
7335 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
\r
7336 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
\r
7340 M68KMAKE_OP(movep, 16, er, .)
\r
7342 uint ea = EA_AY_DI_16();
\r
7343 uint* r_dst = &DX;
\r
7345 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
\r
7349 M68KMAKE_OP(movep, 32, er, .)
\r
7351 uint ea = EA_AY_DI_32();
\r
7353 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
\r
7354 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
\r
7358 M68KMAKE_OP(moves, 8, ., .)
\r
7360 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7364 uint word2 = OPER_I_16();
\r
7365 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7367 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7368 if(BIT_B(word2)) /* Register to memory */
\r
7370 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
\r
7373 if(BIT_F(word2)) /* Memory to address register */
\r
7375 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
\r
7376 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7380 /* Memory to data register */
\r
7381 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
\r
7382 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7386 m68ki_exception_privilege_violation();
\r
7389 m68ki_exception_illegal();
\r
7393 M68KMAKE_OP(moves, 16, ., .)
\r
7395 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7399 uint word2 = OPER_I_16();
\r
7400 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7402 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7403 if(BIT_B(word2)) /* Register to memory */
\r
7405 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
\r
7408 if(BIT_F(word2)) /* Memory to address register */
\r
7410 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
\r
7411 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7415 /* Memory to data register */
\r
7416 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
\r
7417 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7421 m68ki_exception_privilege_violation();
\r
7424 m68ki_exception_illegal();
\r
7428 M68KMAKE_OP(moves, 32, ., .)
\r
7430 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
7434 uint word2 = OPER_I_16();
\r
7435 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7437 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7438 if(BIT_B(word2)) /* Register to memory */
\r
7440 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
\r
7441 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7445 /* Memory to register */
\r
7446 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
\r
7447 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
7451 m68ki_exception_privilege_violation();
\r
7454 m68ki_exception_illegal();
\r
7458 M68KMAKE_OP(moveq, 32, ., .)
\r
7460 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
\r
7462 FLAG_N = NFLAG_32(res);
\r
7464 FLAG_V = VFLAG_CLEAR;
\r
7465 FLAG_C = CFLAG_CLEAR;
\r
7469 M68KMAKE_OP(move16, 32, ., .)
\r
7471 UINT16 w2 = OPER_I_16();
\r
7472 int ax = REG_IR & 7;
\r
7473 int ay = (w2 >> 12) & 7;
\r
7475 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));
\r
7476 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));
\r
7477 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));
\r
7478 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));
\r
7485 M68KMAKE_OP(muls, 16, ., d)
\r
7487 uint* r_dst = &DX;
\r
7488 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
\r
7493 FLAG_N = NFLAG_32(res);
\r
7494 FLAG_V = VFLAG_CLEAR;
\r
7495 FLAG_C = CFLAG_CLEAR;
\r
7499 M68KMAKE_OP(muls, 16, ., .)
\r
7501 uint* r_dst = &DX;
\r
7502 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
\r
7507 FLAG_N = NFLAG_32(res);
\r
7508 FLAG_V = VFLAG_CLEAR;
\r
7509 FLAG_C = CFLAG_CLEAR;
\r
7513 M68KMAKE_OP(mulu, 16, ., d)
\r
7515 uint* r_dst = &DX;
\r
7516 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
\r
7521 FLAG_N = NFLAG_32(res);
\r
7522 FLAG_V = VFLAG_CLEAR;
\r
7523 FLAG_C = CFLAG_CLEAR;
\r
7527 M68KMAKE_OP(mulu, 16, ., .)
\r
7529 uint* r_dst = &DX;
\r
7530 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
\r
7535 FLAG_N = NFLAG_32(res);
\r
7536 FLAG_V = VFLAG_CLEAR;
\r
7537 FLAG_C = CFLAG_CLEAR;
\r
7541 M68KMAKE_OP(mull, 32, ., d)
\r
7543 #if M68K_USE_64_BIT
\r
7545 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7547 uint word2 = OPER_I_16();
\r
7549 uint64 dst = REG_D[(word2 >> 12) & 7];
\r
7552 FLAG_C = CFLAG_CLEAR;
\r
7554 if(BIT_B(word2)) /* signed */
\r
7556 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
\r
7559 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7560 FLAG_N = NFLAG_32(res);
\r
7561 FLAG_V = ((sint64)res != (sint32)res)<<7;
\r
7562 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7565 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7566 FLAG_N = NFLAG_64(res);
\r
7567 FLAG_V = VFLAG_CLEAR;
\r
7568 REG_D[word2 & 7] = (res >> 32);
\r
7569 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7576 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7577 FLAG_N = NFLAG_32(res);
\r
7578 FLAG_V = (res > 0xffffffff)<<7;
\r
7579 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7582 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7583 FLAG_N = NFLAG_64(res);
\r
7584 FLAG_V = VFLAG_CLEAR;
\r
7585 REG_D[word2 & 7] = (res >> 32);
\r
7586 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7589 m68ki_exception_illegal();
\r
7593 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7595 uint word2 = OPER_I_16();
\r
7597 uint dst = REG_D[(word2 >> 12) & 7];
\r
7598 uint neg = GET_MSB_32(src ^ dst);
\r
7610 FLAG_C = CFLAG_CLEAR;
\r
7612 if(BIT_B(word2)) /* signed */
\r
7614 if(GET_MSB_32(src))
\r
7615 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
\r
7616 if(GET_MSB_32(dst))
\r
7617 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
\r
7620 src1 = MASK_OUT_ABOVE_16(src);
\r
7622 dst1 = MASK_OUT_ABOVE_16(dst);
\r
7631 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
\r
7632 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
\r
7634 if(BIT_B(word2) && neg)
\r
7636 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
\r
7637 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
\r
7642 REG_D[word2 & 7] = hi;
\r
7643 REG_D[(word2 >> 12) & 7] = lo;
\r
7644 FLAG_N = NFLAG_32(hi);
\r
7646 FLAG_V = VFLAG_CLEAR;
\r
7650 REG_D[(word2 >> 12) & 7] = lo;
\r
7651 FLAG_N = NFLAG_32(lo);
\r
7654 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
\r
7656 FLAG_V = (hi != 0) << 7;
\r
7659 m68ki_exception_illegal();
\r
7665 M68KMAKE_OP(mull, 32, ., .)
\r
7667 #if M68K_USE_64_BIT
\r
7669 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7671 uint word2 = OPER_I_16();
\r
7672 uint64 src = M68KMAKE_GET_OPER_AY_32;
\r
7673 uint64 dst = REG_D[(word2 >> 12) & 7];
\r
7676 FLAG_C = CFLAG_CLEAR;
\r
7678 if(BIT_B(word2)) /* signed */
\r
7680 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
\r
7683 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7684 FLAG_N = NFLAG_32(res);
\r
7685 FLAG_V = ((sint64)res != (sint32)res)<<7;
\r
7686 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7689 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7690 FLAG_N = NFLAG_64(res);
\r
7691 FLAG_V = VFLAG_CLEAR;
\r
7692 REG_D[word2 & 7] = (res >> 32);
\r
7693 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7700 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7701 FLAG_N = NFLAG_32(res);
\r
7702 FLAG_V = (res > 0xffffffff)<<7;
\r
7703 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7706 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7707 FLAG_N = NFLAG_64(res);
\r
7708 FLAG_V = VFLAG_CLEAR;
\r
7709 REG_D[word2 & 7] = (res >> 32);
\r
7710 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7713 m68ki_exception_illegal();
\r
7717 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7719 uint word2 = OPER_I_16();
\r
7720 uint src = M68KMAKE_GET_OPER_AY_32;
\r
7721 uint dst = REG_D[(word2 >> 12) & 7];
\r
7722 uint neg = GET_MSB_32(src ^ dst);
\r
7734 FLAG_C = CFLAG_CLEAR;
\r
7736 if(BIT_B(word2)) /* signed */
\r
7738 if(GET_MSB_32(src))
\r
7739 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
\r
7740 if(GET_MSB_32(dst))
\r
7741 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
\r
7744 src1 = MASK_OUT_ABOVE_16(src);
\r
7746 dst1 = MASK_OUT_ABOVE_16(dst);
\r
7755 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
\r
7756 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
\r
7758 if(BIT_B(word2) && neg)
\r
7760 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
\r
7761 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
\r
7766 REG_D[word2 & 7] = hi;
\r
7767 REG_D[(word2 >> 12) & 7] = lo;
\r
7768 FLAG_N = NFLAG_32(hi);
\r
7770 FLAG_V = VFLAG_CLEAR;
\r
7774 REG_D[(word2 >> 12) & 7] = lo;
\r
7775 FLAG_N = NFLAG_32(lo);
\r
7778 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
\r
7780 FLAG_V = (hi != 0) << 7;
\r
7783 m68ki_exception_illegal();
\r
7789 M68KMAKE_OP(nbcd, 8, ., d)
\r
7791 uint* r_dst = &DY;
\r
7792 uint dst = *r_dst;
\r
7793 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
\r
7797 FLAG_V = ~res; /* Undefined V behavior */
\r
7799 if((res & 0x0f) == 0xa)
\r
7800 res = (res & 0xf0) + 0x10;
\r
7802 res = MASK_OUT_ABOVE_8(res);
\r
7804 FLAG_V &= res; /* Undefined V behavior part II */
\r
7806 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7809 FLAG_C = CFLAG_SET;
\r
7810 FLAG_X = XFLAG_SET;
\r
7814 FLAG_V = VFLAG_CLEAR;
\r
7815 FLAG_C = CFLAG_CLEAR;
\r
7816 FLAG_X = XFLAG_CLEAR;
\r
7818 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
7822 M68KMAKE_OP(nbcd, 8, ., .)
\r
7824 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7825 uint dst = m68ki_read_8(ea);
\r
7826 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
\r
7830 FLAG_V = ~res; /* Undefined V behavior */
\r
7832 if((res & 0x0f) == 0xa)
\r
7833 res = (res & 0xf0) + 0x10;
\r
7835 res = MASK_OUT_ABOVE_8(res);
\r
7837 FLAG_V &= res; /* Undefined V behavior part II */
\r
7839 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
\r
7842 FLAG_C = CFLAG_SET;
\r
7843 FLAG_X = XFLAG_SET;
\r
7847 FLAG_V = VFLAG_CLEAR;
\r
7848 FLAG_C = CFLAG_CLEAR;
\r
7849 FLAG_X = XFLAG_CLEAR;
\r
7851 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
7855 M68KMAKE_OP(neg, 8, ., d)
\r
7857 uint* r_dst = &DY;
\r
7858 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
\r
7860 FLAG_N = NFLAG_8(res);
\r
7861 FLAG_C = FLAG_X = CFLAG_8(res);
\r
7862 FLAG_V = *r_dst & res;
\r
7863 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
7865 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
7869 M68KMAKE_OP(neg, 8, ., .)
\r
7871 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7872 uint src = m68ki_read_8(ea);
\r
7873 uint res = 0 - src;
\r
7875 FLAG_N = NFLAG_8(res);
\r
7876 FLAG_C = FLAG_X = CFLAG_8(res);
\r
7877 FLAG_V = src & res;
\r
7878 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
7880 m68ki_write_8(ea, FLAG_Z);
\r
7884 M68KMAKE_OP(neg, 16, ., d)
\r
7886 uint* r_dst = &DY;
\r
7887 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
\r
7889 FLAG_N = NFLAG_16(res);
\r
7890 FLAG_C = FLAG_X = CFLAG_16(res);
\r
7891 FLAG_V = (*r_dst & res)>>8;
\r
7892 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
7894 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
7898 M68KMAKE_OP(neg, 16, ., .)
\r
7900 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7901 uint src = m68ki_read_16(ea);
\r
7902 uint res = 0 - src;
\r
7904 FLAG_N = NFLAG_16(res);
\r
7905 FLAG_C = FLAG_X = CFLAG_16(res);
\r
7906 FLAG_V = (src & res)>>8;
\r
7907 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
7909 m68ki_write_16(ea, FLAG_Z);
\r
7913 M68KMAKE_OP(neg, 32, ., d)
\r
7915 uint* r_dst = &DY;
\r
7916 uint res = 0 - *r_dst;
\r
7918 FLAG_N = NFLAG_32(res);
\r
7919 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
\r
7920 FLAG_V = (*r_dst & res)>>24;
\r
7921 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7927 M68KMAKE_OP(neg, 32, ., .)
\r
7929 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7930 uint src = m68ki_read_32(ea);
\r
7931 uint res = 0 - src;
\r
7933 FLAG_N = NFLAG_32(res);
\r
7934 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
\r
7935 FLAG_V = (src & res)>>24;
\r
7936 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7938 m68ki_write_32(ea, FLAG_Z);
\r
7942 M68KMAKE_OP(negx, 8, ., d)
\r
7944 uint* r_dst = &DY;
\r
7945 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
\r
7947 FLAG_N = NFLAG_8(res);
\r
7948 FLAG_X = FLAG_C = CFLAG_8(res);
\r
7949 FLAG_V = *r_dst & res;
\r
7951 res = MASK_OUT_ABOVE_8(res);
\r
7954 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7958 M68KMAKE_OP(negx, 8, ., .)
\r
7960 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7961 uint src = m68ki_read_8(ea);
\r
7962 uint res = 0 - src - XFLAG_AS_1();
\r
7964 FLAG_N = NFLAG_8(res);
\r
7965 FLAG_X = FLAG_C = CFLAG_8(res);
\r
7966 FLAG_V = src & res;
\r
7968 res = MASK_OUT_ABOVE_8(res);
\r
7971 m68ki_write_8(ea, res);
\r
7975 M68KMAKE_OP(negx, 16, ., d)
\r
7977 uint* r_dst = &DY;
\r
7978 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
\r
7980 FLAG_N = NFLAG_16(res);
\r
7981 FLAG_X = FLAG_C = CFLAG_16(res);
\r
7982 FLAG_V = (*r_dst & res)>>8;
\r
7984 res = MASK_OUT_ABOVE_16(res);
\r
7987 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
7991 M68KMAKE_OP(negx, 16, ., .)
\r
7993 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7994 uint src = m68ki_read_16(ea);
\r
7995 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
\r
7997 FLAG_N = NFLAG_16(res);
\r
7998 FLAG_X = FLAG_C = CFLAG_16(res);
\r
7999 FLAG_V = (src & res)>>8;
\r
8001 res = MASK_OUT_ABOVE_16(res);
\r
8004 m68ki_write_16(ea, res);
\r
8008 M68KMAKE_OP(negx, 32, ., d)
\r
8010 uint* r_dst = &DY;
\r
8011 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
\r
8013 FLAG_N = NFLAG_32(res);
\r
8014 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
\r
8015 FLAG_V = (*r_dst & res)>>24;
\r
8017 res = MASK_OUT_ABOVE_32(res);
\r
8024 M68KMAKE_OP(negx, 32, ., .)
\r
8026 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8027 uint src = m68ki_read_32(ea);
\r
8028 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
\r
8030 FLAG_N = NFLAG_32(res);
\r
8031 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
\r
8032 FLAG_V = (src & res)>>24;
\r
8034 res = MASK_OUT_ABOVE_32(res);
\r
8037 m68ki_write_32(ea, res);
\r
8041 M68KMAKE_OP(nop, 0, ., .)
\r
8043 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8047 M68KMAKE_OP(not, 8, ., d)
\r
8049 uint* r_dst = &DY;
\r
8050 uint res = MASK_OUT_ABOVE_8(~*r_dst);
\r
8052 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8054 FLAG_N = NFLAG_8(res);
\r
8056 FLAG_C = CFLAG_CLEAR;
\r
8057 FLAG_V = VFLAG_CLEAR;
\r
8061 M68KMAKE_OP(not, 8, ., .)
\r
8063 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8064 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
\r
8066 m68ki_write_8(ea, res);
\r
8068 FLAG_N = NFLAG_8(res);
\r
8070 FLAG_C = CFLAG_CLEAR;
\r
8071 FLAG_V = VFLAG_CLEAR;
\r
8075 M68KMAKE_OP(not, 16, ., d)
\r
8077 uint* r_dst = &DY;
\r
8078 uint res = MASK_OUT_ABOVE_16(~*r_dst);
\r
8080 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8082 FLAG_N = NFLAG_16(res);
\r
8084 FLAG_C = CFLAG_CLEAR;
\r
8085 FLAG_V = VFLAG_CLEAR;
\r
8089 M68KMAKE_OP(not, 16, ., .)
\r
8091 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8092 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
\r
8094 m68ki_write_16(ea, res);
\r
8096 FLAG_N = NFLAG_16(res);
\r
8098 FLAG_C = CFLAG_CLEAR;
\r
8099 FLAG_V = VFLAG_CLEAR;
\r
8103 M68KMAKE_OP(not, 32, ., d)
\r
8105 uint* r_dst = &DY;
\r
8106 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
\r
8108 FLAG_N = NFLAG_32(res);
\r
8110 FLAG_C = CFLAG_CLEAR;
\r
8111 FLAG_V = VFLAG_CLEAR;
\r
8115 M68KMAKE_OP(not, 32, ., .)
\r
8117 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8118 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
\r
8120 m68ki_write_32(ea, res);
\r
8122 FLAG_N = NFLAG_32(res);
\r
8124 FLAG_C = CFLAG_CLEAR;
\r
8125 FLAG_V = VFLAG_CLEAR;
\r
8129 M68KMAKE_OP(or, 8, er, d)
\r
8131 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
\r
8133 FLAG_N = NFLAG_8(res);
\r
8135 FLAG_C = CFLAG_CLEAR;
\r
8136 FLAG_V = VFLAG_CLEAR;
\r
8140 M68KMAKE_OP(or, 8, er, .)
\r
8142 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
\r
8144 FLAG_N = NFLAG_8(res);
\r
8146 FLAG_C = CFLAG_CLEAR;
\r
8147 FLAG_V = VFLAG_CLEAR;
\r
8151 M68KMAKE_OP(or, 16, er, d)
\r
8153 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
\r
8155 FLAG_N = NFLAG_16(res);
\r
8157 FLAG_C = CFLAG_CLEAR;
\r
8158 FLAG_V = VFLAG_CLEAR;
\r
8162 M68KMAKE_OP(or, 16, er, .)
\r
8164 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
\r
8166 FLAG_N = NFLAG_16(res);
\r
8168 FLAG_C = CFLAG_CLEAR;
\r
8169 FLAG_V = VFLAG_CLEAR;
\r
8173 M68KMAKE_OP(or, 32, er, d)
\r
8175 uint res = DX |= DY;
\r
8177 FLAG_N = NFLAG_32(res);
\r
8179 FLAG_C = CFLAG_CLEAR;
\r
8180 FLAG_V = VFLAG_CLEAR;
\r
8184 M68KMAKE_OP(or, 32, er, .)
\r
8186 uint res = DX |= M68KMAKE_GET_OPER_AY_32;
\r
8188 FLAG_N = NFLAG_32(res);
\r
8190 FLAG_C = CFLAG_CLEAR;
\r
8191 FLAG_V = VFLAG_CLEAR;
\r
8195 M68KMAKE_OP(or, 8, re, .)
\r
8197 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8198 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
\r
8200 m68ki_write_8(ea, res);
\r
8202 FLAG_N = NFLAG_8(res);
\r
8204 FLAG_C = CFLAG_CLEAR;
\r
8205 FLAG_V = VFLAG_CLEAR;
\r
8209 M68KMAKE_OP(or, 16, re, .)
\r
8211 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8212 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
\r
8214 m68ki_write_16(ea, res);
\r
8216 FLAG_N = NFLAG_16(res);
\r
8218 FLAG_C = CFLAG_CLEAR;
\r
8219 FLAG_V = VFLAG_CLEAR;
\r
8223 M68KMAKE_OP(or, 32, re, .)
\r
8225 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8226 uint res = DX | m68ki_read_32(ea);
\r
8228 m68ki_write_32(ea, res);
\r
8230 FLAG_N = NFLAG_32(res);
\r
8232 FLAG_C = CFLAG_CLEAR;
\r
8233 FLAG_V = VFLAG_CLEAR;
\r
8237 M68KMAKE_OP(ori, 8, ., d)
\r
8239 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
\r
8241 FLAG_N = NFLAG_8(res);
\r
8243 FLAG_C = CFLAG_CLEAR;
\r
8244 FLAG_V = VFLAG_CLEAR;
\r
8248 M68KMAKE_OP(ori, 8, ., .)
\r
8250 uint src = OPER_I_8();
\r
8251 uint ea = M68KMAKE_GET_EA_AY_8;
\r
8252 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
\r
8254 m68ki_write_8(ea, res);
\r
8256 FLAG_N = NFLAG_8(res);
\r
8258 FLAG_C = CFLAG_CLEAR;
\r
8259 FLAG_V = VFLAG_CLEAR;
\r
8263 M68KMAKE_OP(ori, 16, ., d)
\r
8265 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
\r
8267 FLAG_N = NFLAG_16(res);
\r
8269 FLAG_C = CFLAG_CLEAR;
\r
8270 FLAG_V = VFLAG_CLEAR;
\r
8274 M68KMAKE_OP(ori, 16, ., .)
\r
8276 uint src = OPER_I_16();
\r
8277 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8278 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
\r
8280 m68ki_write_16(ea, res);
\r
8282 FLAG_N = NFLAG_16(res);
\r
8284 FLAG_C = CFLAG_CLEAR;
\r
8285 FLAG_V = VFLAG_CLEAR;
\r
8289 M68KMAKE_OP(ori, 32, ., d)
\r
8291 uint res = DY |= OPER_I_32();
\r
8293 FLAG_N = NFLAG_32(res);
\r
8295 FLAG_C = CFLAG_CLEAR;
\r
8296 FLAG_V = VFLAG_CLEAR;
\r
8300 M68KMAKE_OP(ori, 32, ., .)
\r
8302 uint src = OPER_I_32();
\r
8303 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8304 uint res = src | m68ki_read_32(ea);
\r
8306 m68ki_write_32(ea, res);
\r
8308 FLAG_N = NFLAG_32(res);
\r
8310 FLAG_C = CFLAG_CLEAR;
\r
8311 FLAG_V = VFLAG_CLEAR;
\r
8315 M68KMAKE_OP(ori, 16, toc, .)
\r
8317 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
\r
8321 M68KMAKE_OP(ori, 16, tos, .)
\r
8325 uint src = OPER_I_16();
\r
8326 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8327 m68ki_set_sr(m68ki_get_sr() | src);
\r
8330 m68ki_exception_privilege_violation();
\r
8334 M68KMAKE_OP(pack, 16, rr, .)
\r
8336 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8338 /* Note: DX and DY are reversed in Motorola's docs */
\r
8339 uint src = DY + OPER_I_16();
\r
8340 uint* r_dst = &DX;
\r
8342 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
\r
8345 m68ki_exception_illegal();
\r
8349 M68KMAKE_OP(pack, 16, mm, ax7)
\r
8351 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8353 /* Note: AX and AY are reversed in Motorola's docs */
\r
8354 uint ea_src = EA_AY_PD_8();
\r
8355 uint src = m68ki_read_8(ea_src);
\r
8356 ea_src = EA_AY_PD_8();
\r
8357 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8359 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8362 m68ki_exception_illegal();
\r
8366 M68KMAKE_OP(pack, 16, mm, ay7)
\r
8368 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8370 /* Note: AX and AY are reversed in Motorola's docs */
\r
8371 uint ea_src = EA_A7_PD_8();
\r
8372 uint src = m68ki_read_8(ea_src);
\r
8373 ea_src = EA_A7_PD_8();
\r
8374 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8376 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8379 m68ki_exception_illegal();
\r
8383 M68KMAKE_OP(pack, 16, mm, axy7)
\r
8385 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8387 uint ea_src = EA_A7_PD_8();
\r
8388 uint src = m68ki_read_8(ea_src);
\r
8389 ea_src = EA_A7_PD_8();
\r
8390 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8392 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8395 m68ki_exception_illegal();
\r
8399 M68KMAKE_OP(pack, 16, mm, .)
\r
8401 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
8403 /* Note: AX and AY are reversed in Motorola's docs */
\r
8404 uint ea_src = EA_AY_PD_8();
\r
8405 uint src = m68ki_read_8(ea_src);
\r
8406 ea_src = EA_AY_PD_8();
\r
8407 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
8409 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
8412 m68ki_exception_illegal();
\r
8416 M68KMAKE_OP(pea, 32, ., .)
\r
8418 uint ea = M68KMAKE_GET_EA_AY_32;
\r
8420 m68ki_push_32(ea);
\r
8424 M68KMAKE_OP(pflush, 32, ., .)
\r
8426 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
\r
8428 // Nothing to do, unless address translation cache is emulated
\r
8431 m68ki_exception_illegal();
\r
8435 M68KMAKE_OP(reset, 0, ., .)
\r
8439 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
\r
8440 USE_CYCLES(CYC_RESET);
\r
8443 m68ki_exception_privilege_violation();
\r
8447 M68KMAKE_OP(ror, 8, s, .)
\r
8449 uint* r_dst = &DY;
\r
8450 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8451 uint shift = orig_shift & 7;
\r
8452 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8453 uint res = ROR_8(src, shift);
\r
8455 if(orig_shift != 0)
\r
8456 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8458 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8460 FLAG_N = NFLAG_8(res);
\r
8462 FLAG_C = src << (9-orig_shift);
\r
8463 FLAG_V = VFLAG_CLEAR;
\r
8467 M68KMAKE_OP(ror, 16, s, .)
\r
8469 uint* r_dst = &DY;
\r
8470 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8471 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8472 uint res = ROR_16(src, shift);
\r
8475 USE_CYCLES(shift<<CYC_SHIFT);
\r
8477 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8479 FLAG_N = NFLAG_16(res);
\r
8481 FLAG_C = src << (9-shift);
\r
8482 FLAG_V = VFLAG_CLEAR;
\r
8486 M68KMAKE_OP(ror, 32, s, .)
\r
8488 uint* r_dst = &DY;
\r
8489 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8490 uint64 src = *r_dst;
\r
8491 uint res = ROR_32(src, shift);
\r
8494 USE_CYCLES(shift<<CYC_SHIFT);
\r
8498 FLAG_N = NFLAG_32(res);
\r
8500 FLAG_C = src << (9-shift);
\r
8501 FLAG_V = VFLAG_CLEAR;
\r
8505 M68KMAKE_OP(ror, 8, r, .)
\r
8507 uint* r_dst = &DY;
\r
8508 uint orig_shift = DX & 0x3f;
\r
8509 uint shift = orig_shift & 7;
\r
8510 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8511 uint res = ROR_8(src, shift);
\r
8513 if(orig_shift != 0)
\r
8515 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8517 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8518 FLAG_C = src << (8-((shift-1)&7));
\r
8519 FLAG_N = NFLAG_8(res);
\r
8521 FLAG_V = VFLAG_CLEAR;
\r
8525 FLAG_C = CFLAG_CLEAR;
\r
8526 FLAG_N = NFLAG_8(src);
\r
8528 FLAG_V = VFLAG_CLEAR;
\r
8532 M68KMAKE_OP(ror, 16, r, .)
\r
8534 uint* r_dst = &DY;
\r
8535 uint orig_shift = DX & 0x3f;
\r
8536 uint shift = orig_shift & 15;
\r
8537 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8538 uint res = ROR_16(src, shift);
\r
8540 if(orig_shift != 0)
\r
8542 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8544 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8545 FLAG_C = (src >> ((shift - 1) & 15)) << 8;
\r
8546 FLAG_N = NFLAG_16(res);
\r
8548 FLAG_V = VFLAG_CLEAR;
\r
8552 FLAG_C = CFLAG_CLEAR;
\r
8553 FLAG_N = NFLAG_16(src);
\r
8555 FLAG_V = VFLAG_CLEAR;
\r
8559 M68KMAKE_OP(ror, 32, r, .)
\r
8561 uint* r_dst = &DY;
\r
8562 uint orig_shift = DX & 0x3f;
\r
8563 uint shift = orig_shift & 31;
\r
8564 uint64 src = *r_dst;
\r
8565 uint res = ROR_32(src, shift);
\r
8567 if(orig_shift != 0)
\r
8569 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8572 FLAG_C = (src >> ((shift - 1) & 31)) << 8;
\r
8573 FLAG_N = NFLAG_32(res);
\r
8575 FLAG_V = VFLAG_CLEAR;
\r
8579 FLAG_C = CFLAG_CLEAR;
\r
8580 FLAG_N = NFLAG_32(src);
\r
8582 FLAG_V = VFLAG_CLEAR;
\r
8586 M68KMAKE_OP(ror, 16, ., .)
\r
8588 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8589 uint src = m68ki_read_16(ea);
\r
8590 uint res = ROR_16(src, 1);
\r
8592 m68ki_write_16(ea, res);
\r
8594 FLAG_N = NFLAG_16(res);
\r
8596 FLAG_C = src << 8;
\r
8597 FLAG_V = VFLAG_CLEAR;
\r
8601 M68KMAKE_OP(rol, 8, s, .)
\r
8603 uint* r_dst = &DY;
\r
8604 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8605 uint shift = orig_shift & 7;
\r
8606 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8607 uint res = ROL_8(src, shift);
\r
8609 if(orig_shift != 0)
\r
8610 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8612 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8614 FLAG_N = NFLAG_8(res);
\r
8616 FLAG_C = src << orig_shift;
\r
8617 FLAG_V = VFLAG_CLEAR;
\r
8621 M68KMAKE_OP(rol, 16, s, .)
\r
8623 uint* r_dst = &DY;
\r
8624 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8625 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8626 uint res = ROL_16(src, shift);
\r
8629 USE_CYCLES(shift<<CYC_SHIFT);
\r
8631 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8633 FLAG_N = NFLAG_16(res);
\r
8635 FLAG_C = src >> (8-shift);
\r
8636 FLAG_V = VFLAG_CLEAR;
\r
8640 M68KMAKE_OP(rol, 32, s, .)
\r
8642 uint* r_dst = &DY;
\r
8643 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8644 uint64 src = *r_dst;
\r
8645 uint res = ROL_32(src, shift);
\r
8648 USE_CYCLES(shift<<CYC_SHIFT);
\r
8652 FLAG_N = NFLAG_32(res);
\r
8654 FLAG_C = src >> (24-shift);
\r
8655 FLAG_V = VFLAG_CLEAR;
\r
8659 M68KMAKE_OP(rol, 8, r, .)
\r
8661 uint* r_dst = &DY;
\r
8662 uint orig_shift = DX & 0x3f;
\r
8663 uint shift = orig_shift & 7;
\r
8664 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8665 uint res = ROL_8(src, shift);
\r
8667 if(orig_shift != 0)
\r
8669 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8673 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8674 FLAG_C = src << shift;
\r
8675 FLAG_N = NFLAG_8(res);
\r
8677 FLAG_V = VFLAG_CLEAR;
\r
8680 FLAG_C = (src & 1)<<8;
\r
8681 FLAG_N = NFLAG_8(src);
\r
8683 FLAG_V = VFLAG_CLEAR;
\r
8687 FLAG_C = CFLAG_CLEAR;
\r
8688 FLAG_N = NFLAG_8(src);
\r
8690 FLAG_V = VFLAG_CLEAR;
\r
8694 M68KMAKE_OP(rol, 16, r, .)
\r
8696 uint* r_dst = &DY;
\r
8697 uint orig_shift = DX & 0x3f;
\r
8698 uint shift = orig_shift & 15;
\r
8699 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8700 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
\r
8702 if(orig_shift != 0)
\r
8704 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8708 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8709 FLAG_C = (src << shift) >> 8;
\r
8710 FLAG_N = NFLAG_16(res);
\r
8712 FLAG_V = VFLAG_CLEAR;
\r
8715 FLAG_C = (src & 1)<<8;
\r
8716 FLAG_N = NFLAG_16(src);
\r
8718 FLAG_V = VFLAG_CLEAR;
\r
8722 FLAG_C = CFLAG_CLEAR;
\r
8723 FLAG_N = NFLAG_16(src);
\r
8725 FLAG_V = VFLAG_CLEAR;
\r
8729 M68KMAKE_OP(rol, 32, r, .)
\r
8731 uint* r_dst = &DY;
\r
8732 uint orig_shift = DX & 0x3f;
\r
8733 uint shift = orig_shift & 31;
\r
8734 uint64 src = *r_dst;
\r
8735 uint res = ROL_32(src, shift);
\r
8737 if(orig_shift != 0)
\r
8739 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8743 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
\r
8744 FLAG_N = NFLAG_32(res);
\r
8746 FLAG_V = VFLAG_CLEAR;
\r
8750 FLAG_C = CFLAG_CLEAR;
\r
8751 FLAG_N = NFLAG_32(src);
\r
8753 FLAG_V = VFLAG_CLEAR;
\r
8757 M68KMAKE_OP(rol, 16, ., .)
\r
8759 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8760 uint src = m68ki_read_16(ea);
\r
8761 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
\r
8763 m68ki_write_16(ea, res);
\r
8765 FLAG_N = NFLAG_16(res);
\r
8767 FLAG_C = src >> 7;
\r
8768 FLAG_V = VFLAG_CLEAR;
\r
8772 M68KMAKE_OP(roxr, 8, s, .)
\r
8774 uint* r_dst = &DY;
\r
8775 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8776 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8777 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
\r
8780 USE_CYCLES(shift<<CYC_SHIFT);
\r
8782 FLAG_C = FLAG_X = res;
\r
8783 res = MASK_OUT_ABOVE_8(res);
\r
8785 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8787 FLAG_N = NFLAG_8(res);
\r
8789 FLAG_V = VFLAG_CLEAR;
\r
8793 M68KMAKE_OP(roxr, 16, s, .)
\r
8795 uint* r_dst = &DY;
\r
8796 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8797 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8798 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
\r
8801 USE_CYCLES(shift<<CYC_SHIFT);
\r
8803 FLAG_C = FLAG_X = res >> 8;
\r
8804 res = MASK_OUT_ABOVE_16(res);
\r
8806 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8808 FLAG_N = NFLAG_16(res);
\r
8810 FLAG_V = VFLAG_CLEAR;
\r
8814 M68KMAKE_OP(roxr, 32, s, .)
\r
8816 #if M68K_USE_64_BIT
\r
8818 uint* r_dst = &DY;
\r
8819 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8820 uint64 src = *r_dst;
\r
8821 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
8824 USE_CYCLES(shift<<CYC_SHIFT);
\r
8826 res = ROR_33_64(res, shift);
\r
8828 FLAG_C = FLAG_X = res >> 24;
\r
8829 res = MASK_OUT_ABOVE_32(res);
\r
8833 FLAG_N = NFLAG_32(res);
\r
8835 FLAG_V = VFLAG_CLEAR;
\r
8839 uint* r_dst = &DY;
\r
8840 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8841 uint src = *r_dst;
\r
8842 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
\r
8843 uint new_x_flag = src & (1 << (shift - 1));
\r
8846 USE_CYCLES(shift<<CYC_SHIFT);
\r
8850 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
\r
8851 FLAG_N = NFLAG_32(res);
\r
8853 FLAG_V = VFLAG_CLEAR;
\r
8859 M68KMAKE_OP(roxr, 8, r, .)
\r
8861 uint* r_dst = &DY;
\r
8862 uint orig_shift = DX & 0x3f;
\r
8864 if(orig_shift != 0)
\r
8866 uint shift = orig_shift % 9;
\r
8867 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8868 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
\r
8870 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8872 FLAG_C = FLAG_X = res;
\r
8873 res = MASK_OUT_ABOVE_8(res);
\r
8875 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8876 FLAG_N = NFLAG_8(res);
\r
8878 FLAG_V = VFLAG_CLEAR;
\r
8883 FLAG_N = NFLAG_8(*r_dst);
\r
8884 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
8885 FLAG_V = VFLAG_CLEAR;
\r
8889 M68KMAKE_OP(roxr, 16, r, .)
\r
8891 uint* r_dst = &DY;
\r
8892 uint orig_shift = DX & 0x3f;
\r
8894 if(orig_shift != 0)
\r
8896 uint shift = orig_shift % 17;
\r
8897 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8898 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
\r
8900 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8902 FLAG_C = FLAG_X = res >> 8;
\r
8903 res = MASK_OUT_ABOVE_16(res);
\r
8905 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8906 FLAG_N = NFLAG_16(res);
\r
8908 FLAG_V = VFLAG_CLEAR;
\r
8913 FLAG_N = NFLAG_16(*r_dst);
\r
8914 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
8915 FLAG_V = VFLAG_CLEAR;
\r
8919 M68KMAKE_OP(roxr, 32, r, .)
\r
8921 #if M68K_USE_64_BIT
\r
8923 uint* r_dst = &DY;
\r
8924 uint orig_shift = DX & 0x3f;
\r
8926 if(orig_shift != 0)
\r
8928 uint shift = orig_shift % 33;
\r
8929 uint64 src = *r_dst;
\r
8930 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
8932 res = ROR_33_64(res, shift);
\r
8934 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8936 FLAG_C = FLAG_X = res >> 24;
\r
8937 res = MASK_OUT_ABOVE_32(res);
\r
8940 FLAG_N = NFLAG_32(res);
\r
8942 FLAG_V = VFLAG_CLEAR;
\r
8947 FLAG_N = NFLAG_32(*r_dst);
\r
8949 FLAG_V = VFLAG_CLEAR;
\r
8953 uint* r_dst = &DY;
\r
8954 uint orig_shift = DX & 0x3f;
\r
8955 uint shift = orig_shift % 33;
\r
8956 uint src = *r_dst;
\r
8957 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
\r
8958 uint new_x_flag = src & (1 << (shift - 1));
\r
8960 if(orig_shift != 0)
\r
8961 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8966 FLAG_X = (new_x_flag != 0)<<8;
\r
8971 FLAG_N = NFLAG_32(res);
\r
8973 FLAG_V = VFLAG_CLEAR;
\r
8979 M68KMAKE_OP(roxr, 16, ., .)
\r
8981 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8982 uint src = m68ki_read_16(ea);
\r
8983 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
\r
8985 FLAG_C = FLAG_X = res >> 8;
\r
8986 res = MASK_OUT_ABOVE_16(res);
\r
8988 m68ki_write_16(ea, res);
\r
8990 FLAG_N = NFLAG_16(res);
\r
8992 FLAG_V = VFLAG_CLEAR;
\r
8996 M68KMAKE_OP(roxl, 8, s, .)
\r
8998 uint* r_dst = &DY;
\r
8999 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9000 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
9001 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
\r
9004 USE_CYCLES(shift<<CYC_SHIFT);
\r
9006 FLAG_C = FLAG_X = res;
\r
9007 res = MASK_OUT_ABOVE_8(res);
\r
9009 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9011 FLAG_N = NFLAG_8(res);
\r
9013 FLAG_V = VFLAG_CLEAR;
\r
9017 M68KMAKE_OP(roxl, 16, s, .)
\r
9019 uint* r_dst = &DY;
\r
9020 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9021 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
9022 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
\r
9025 USE_CYCLES(shift<<CYC_SHIFT);
\r
9027 FLAG_C = FLAG_X = res >> 8;
\r
9028 res = MASK_OUT_ABOVE_16(res);
\r
9030 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
9032 FLAG_N = NFLAG_16(res);
\r
9034 FLAG_V = VFLAG_CLEAR;
\r
9038 M68KMAKE_OP(roxl, 32, s, .)
\r
9040 #if M68K_USE_64_BIT
\r
9042 uint* r_dst = &DY;
\r
9043 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9044 uint64 src = *r_dst;
\r
9045 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
9048 USE_CYCLES(shift<<CYC_SHIFT);
\r
9050 res = ROL_33_64(res, shift);
\r
9052 FLAG_C = FLAG_X = res >> 24;
\r
9053 res = MASK_OUT_ABOVE_32(res);
\r
9057 FLAG_N = NFLAG_32(res);
\r
9059 FLAG_V = VFLAG_CLEAR;
\r
9063 uint* r_dst = &DY;
\r
9064 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9065 uint src = *r_dst;
\r
9066 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
\r
9067 uint new_x_flag = src & (1 << (32 - shift));
\r
9070 USE_CYCLES(shift<<CYC_SHIFT);
\r
9074 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
\r
9075 FLAG_N = NFLAG_32(res);
\r
9077 FLAG_V = VFLAG_CLEAR;
\r
9083 M68KMAKE_OP(roxl, 8, r, .)
\r
9085 uint* r_dst = &DY;
\r
9086 uint orig_shift = DX & 0x3f;
\r
9089 if(orig_shift != 0)
\r
9091 uint shift = orig_shift % 9;
\r
9092 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
9093 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
\r
9095 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9097 FLAG_C = FLAG_X = res;
\r
9098 res = MASK_OUT_ABOVE_8(res);
\r
9100 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9101 FLAG_N = NFLAG_8(res);
\r
9103 FLAG_V = VFLAG_CLEAR;
\r
9108 FLAG_N = NFLAG_8(*r_dst);
\r
9109 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
9110 FLAG_V = VFLAG_CLEAR;
\r
9114 M68KMAKE_OP(roxl, 16, r, .)
\r
9116 uint* r_dst = &DY;
\r
9117 uint orig_shift = DX & 0x3f;
\r
9119 if(orig_shift != 0)
\r
9121 uint shift = orig_shift % 17;
\r
9122 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
9123 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
\r
9125 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9127 FLAG_C = FLAG_X = res >> 8;
\r
9128 res = MASK_OUT_ABOVE_16(res);
\r
9130 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
9131 FLAG_N = NFLAG_16(res);
\r
9133 FLAG_V = VFLAG_CLEAR;
\r
9138 FLAG_N = NFLAG_16(*r_dst);
\r
9139 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
9140 FLAG_V = VFLAG_CLEAR;
\r
9144 M68KMAKE_OP(roxl, 32, r, .)
\r
9146 #if M68K_USE_64_BIT
\r
9148 uint* r_dst = &DY;
\r
9149 uint orig_shift = DX & 0x3f;
\r
9151 if(orig_shift != 0)
\r
9153 uint shift = orig_shift % 33;
\r
9154 uint64 src = *r_dst;
\r
9155 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
9157 res = ROL_33_64(res, shift);
\r
9159 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9161 FLAG_C = FLAG_X = res >> 24;
\r
9162 res = MASK_OUT_ABOVE_32(res);
\r
9165 FLAG_N = NFLAG_32(res);
\r
9167 FLAG_V = VFLAG_CLEAR;
\r
9172 FLAG_N = NFLAG_32(*r_dst);
\r
9174 FLAG_V = VFLAG_CLEAR;
\r
9178 uint* r_dst = &DY;
\r
9179 uint orig_shift = DX & 0x3f;
\r
9180 uint shift = orig_shift % 33;
\r
9181 uint src = *r_dst;
\r
9182 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
\r
9183 uint new_x_flag = src & (1 << (32 - shift));
\r
9185 if(orig_shift != 0)
\r
9186 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
9191 FLAG_X = (new_x_flag != 0)<<8;
\r
9196 FLAG_N = NFLAG_32(res);
\r
9198 FLAG_V = VFLAG_CLEAR;
\r
9204 M68KMAKE_OP(roxl, 16, ., .)
\r
9206 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9207 uint src = m68ki_read_16(ea);
\r
9208 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
\r
9210 FLAG_C = FLAG_X = res >> 8;
\r
9211 res = MASK_OUT_ABOVE_16(res);
\r
9213 m68ki_write_16(ea, res);
\r
9215 FLAG_N = NFLAG_16(res);
\r
9217 FLAG_V = VFLAG_CLEAR;
\r
9221 M68KMAKE_OP(rtd, 32, ., .)
\r
9223 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
9225 uint new_pc = m68ki_pull_32();
\r
9227 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9228 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
9229 m68ki_jump(new_pc);
\r
9232 m68ki_exception_illegal();
\r
9236 M68KMAKE_OP(rte, 32, ., .)
\r
9244 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */
\r
9245 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9247 if(CPU_TYPE_IS_000(CPU_TYPE))
\r
9249 new_sr = m68ki_pull_16();
\r
9250 new_pc = m68ki_pull_32();
\r
9251 m68ki_jump(new_pc);
\r
9252 m68ki_set_sr(new_sr);
\r
9254 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9255 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9260 if(CPU_TYPE_IS_010(CPU_TYPE))
\r
9262 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
\r
9263 if(format_word == 0)
\r
9265 new_sr = m68ki_pull_16();
\r
9266 new_pc = m68ki_pull_32();
\r
9267 m68ki_fake_pull_16(); /* format word */
\r
9268 m68ki_jump(new_pc);
\r
9269 m68ki_set_sr(new_sr);
\r
9270 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9271 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9274 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9275 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9276 /* Not handling bus fault (9) */
\r
9277 m68ki_exception_format_error();
\r
9281 /* Otherwise it's 020 */
\r
9283 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
\r
9284 switch(format_word)
\r
9286 case 0: /* Normal */
\r
9287 new_sr = m68ki_pull_16();
\r
9288 new_pc = m68ki_pull_32();
\r
9289 m68ki_fake_pull_16(); /* format word */
\r
9290 m68ki_jump(new_pc);
\r
9291 m68ki_set_sr(new_sr);
\r
9292 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9293 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9295 case 1: /* Throwaway */
\r
9296 new_sr = m68ki_pull_16();
\r
9297 m68ki_fake_pull_32(); /* program counter */
\r
9298 m68ki_fake_pull_16(); /* format word */
\r
9299 m68ki_set_sr_noint(new_sr);
\r
9301 case 2: /* Trap */
\r
9302 new_sr = m68ki_pull_16();
\r
9303 new_pc = m68ki_pull_32();
\r
9304 m68ki_fake_pull_16(); /* format word */
\r
9305 m68ki_fake_pull_32(); /* address */
\r
9306 m68ki_jump(new_pc);
\r
9307 m68ki_set_sr(new_sr);
\r
9308 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9309 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9312 /* Not handling long or short bus fault */
\r
9313 CPU_INSTR_MODE = INSTRUCTION_YES;
\r
9314 CPU_RUN_MODE = RUN_MODE_NORMAL;
\r
9315 m68ki_exception_format_error();
\r
9318 m68ki_exception_privilege_violation();
\r
9322 M68KMAKE_OP(rtm, 32, ., .)
\r
9324 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
9326 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9327 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
9328 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
9329 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
9332 m68ki_exception_illegal();
\r
9336 M68KMAKE_OP(rtr, 32, ., .)
\r
9338 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9339 m68ki_set_ccr(m68ki_pull_16());
\r
9340 m68ki_jump(m68ki_pull_32());
\r
9344 M68KMAKE_OP(rts, 32, ., .)
\r
9346 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9347 m68ki_jump(m68ki_pull_32());
\r
9351 M68KMAKE_OP(sbcd, 8, rr, .)
\r
9353 uint* r_dst = &DX;
\r
9355 uint dst = *r_dst;
\r
9356 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9358 // FLAG_V = ~res; /* Undefined V behavior */
\r
9359 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to assume cleared. */
\r
9363 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9367 FLAG_X = FLAG_C = CFLAG_SET;
\r
9368 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9371 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9373 res = MASK_OUT_ABOVE_8(res);
\r
9375 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9376 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9379 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9383 M68KMAKE_OP(sbcd, 8, mm, ax7)
\r
9385 uint src = OPER_AY_PD_8();
\r
9386 uint ea = EA_A7_PD_8();
\r
9387 uint dst = m68ki_read_8(ea);
\r
9388 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9390 // FLAG_V = ~res; /* Undefined V behavior */
\r
9391 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
\r
9395 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9399 FLAG_X = FLAG_C = CFLAG_SET;
\r
9400 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9403 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9405 res = MASK_OUT_ABOVE_8(res);
\r
9407 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9408 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9411 m68ki_write_8(ea, res);
\r
9415 M68KMAKE_OP(sbcd, 8, mm, ay7)
\r
9417 uint src = OPER_A7_PD_8();
\r
9418 uint ea = EA_AX_PD_8();
\r
9419 uint dst = m68ki_read_8(ea);
\r
9420 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9422 // FLAG_V = ~res; /* Undefined V behavior */
\r
9423 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
\r
9427 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9431 FLAG_X = FLAG_C = CFLAG_SET;
\r
9432 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9435 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9437 res = MASK_OUT_ABOVE_8(res);
\r
9439 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9440 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9443 m68ki_write_8(ea, res);
\r
9447 M68KMAKE_OP(sbcd, 8, mm, axy7)
\r
9449 uint src = OPER_A7_PD_8();
\r
9450 uint ea = EA_A7_PD_8();
\r
9451 uint dst = m68ki_read_8(ea);
\r
9452 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9454 // FLAG_V = ~res; /* Undefined V behavior */
\r
9455 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
\r
9459 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9463 FLAG_X = FLAG_C = CFLAG_SET;
\r
9464 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9467 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9469 res = MASK_OUT_ABOVE_8(res);
\r
9471 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9472 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9475 m68ki_write_8(ea, res);
\r
9479 M68KMAKE_OP(sbcd, 8, mm, .)
\r
9481 uint src = OPER_AY_PD_8();
\r
9482 uint ea = EA_AX_PD_8();
\r
9483 uint dst = m68ki_read_8(ea);
\r
9484 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
9486 // FLAG_V = ~res; /* Undefined V behavior */
\r
9487 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */
\r
9491 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
9495 FLAG_X = FLAG_C = CFLAG_SET;
\r
9496 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */
\r
9499 FLAG_N = FLAG_X = FLAG_C = 0;
\r
9501 res = MASK_OUT_ABOVE_8(res);
\r
9503 // FLAG_V &= res; /* Undefined V behavior part II */
\r
9504 // FLAG_N = NFLAG_8(res); /* Undefined N behavior */
\r
9507 m68ki_write_8(ea, res);
\r
9511 M68KMAKE_OP(st, 8, ., d)
\r
9517 M68KMAKE_OP(st, 8, ., .)
\r
9519 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
\r
9523 M68KMAKE_OP(sf, 8, ., d)
\r
9529 M68KMAKE_OP(sf, 8, ., .)
\r
9531 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
\r
9535 M68KMAKE_OP(scc, 8, ., d)
\r
9540 USE_CYCLES(CYC_SCC_R_TRUE);
\r
9547 M68KMAKE_OP(scc, 8, ., .)
\r
9549 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
\r
9553 M68KMAKE_OP(stop, 0, ., .)
\r
9557 uint new_sr = OPER_I_16();
\r
9558 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
9559 CPU_STOPPED |= STOP_LEVEL_STOP;
\r
9560 m68ki_set_sr(new_sr);
\r
9561 m68ki_remaining_cycles = 0;
\r
9564 m68ki_exception_privilege_violation();
\r
9568 M68KMAKE_OP(sub, 8, er, d)
\r
9570 uint* r_dst = &DX;
\r
9571 uint src = MASK_OUT_ABOVE_8(DY);
\r
9572 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9573 uint res = dst - src;
\r
9575 FLAG_N = NFLAG_8(res);
\r
9576 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9577 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9578 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9580 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9584 M68KMAKE_OP(sub, 8, er, .)
\r
9586 uint* r_dst = &DX;
\r
9587 uint src = M68KMAKE_GET_OPER_AY_8;
\r
9588 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9589 uint res = dst - src;
\r
9591 FLAG_N = NFLAG_8(res);
\r
9592 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9593 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9594 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9596 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9600 M68KMAKE_OP(sub, 16, er, d)
\r
9602 uint* r_dst = &DX;
\r
9603 uint src = MASK_OUT_ABOVE_16(DY);
\r
9604 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9605 uint res = dst - src;
\r
9607 FLAG_N = NFLAG_16(res);
\r
9608 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9609 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9610 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9612 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9616 M68KMAKE_OP(sub, 16, er, a)
\r
9618 uint* r_dst = &DX;
\r
9619 uint src = MASK_OUT_ABOVE_16(AY);
\r
9620 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9621 uint res = dst - src;
\r
9623 FLAG_N = NFLAG_16(res);
\r
9624 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9625 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9626 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9628 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9632 M68KMAKE_OP(sub, 16, er, .)
\r
9634 uint* r_dst = &DX;
\r
9635 uint src = M68KMAKE_GET_OPER_AY_16;
\r
9636 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9637 uint res = dst - src;
\r
9639 FLAG_N = NFLAG_16(res);
\r
9640 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9641 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9642 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9644 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9648 M68KMAKE_OP(sub, 32, er, d)
\r
9650 uint* r_dst = &DX;
\r
9652 uint dst = *r_dst;
\r
9653 uint res = dst - src;
\r
9655 FLAG_N = NFLAG_32(res);
\r
9656 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9657 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9658 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9664 M68KMAKE_OP(sub, 32, er, a)
\r
9666 uint* r_dst = &DX;
\r
9668 uint dst = *r_dst;
\r
9669 uint res = dst - src;
\r
9671 FLAG_N = NFLAG_32(res);
\r
9672 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9673 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9674 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9680 M68KMAKE_OP(sub, 32, er, .)
\r
9682 uint* r_dst = &DX;
\r
9683 uint src = M68KMAKE_GET_OPER_AY_32;
\r
9684 uint dst = *r_dst;
\r
9685 uint res = dst - src;
\r
9687 FLAG_N = NFLAG_32(res);
\r
9688 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9689 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9690 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9696 M68KMAKE_OP(sub, 8, re, .)
\r
9698 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9699 uint src = MASK_OUT_ABOVE_8(DX);
\r
9700 uint dst = m68ki_read_8(ea);
\r
9701 uint res = dst - src;
\r
9703 FLAG_N = NFLAG_8(res);
\r
9704 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9705 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9706 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9708 m68ki_write_8(ea, FLAG_Z);
\r
9712 M68KMAKE_OP(sub, 16, re, .)
\r
9714 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9715 uint src = MASK_OUT_ABOVE_16(DX);
\r
9716 uint dst = m68ki_read_16(ea);
\r
9717 uint res = dst - src;
\r
9719 FLAG_N = NFLAG_16(res);
\r
9720 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9721 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9722 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9724 m68ki_write_16(ea, FLAG_Z);
\r
9728 M68KMAKE_OP(sub, 32, re, .)
\r
9730 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9732 uint dst = m68ki_read_32(ea);
\r
9733 uint res = dst - src;
\r
9735 FLAG_N = NFLAG_32(res);
\r
9736 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9737 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9738 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9740 m68ki_write_32(ea, FLAG_Z);
\r
9744 M68KMAKE_OP(suba, 16, ., d)
\r
9746 uint* r_dst = &AX;
\r
9748 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
\r
9752 M68KMAKE_OP(suba, 16, ., a)
\r
9754 uint* r_dst = &AX;
\r
9756 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
\r
9760 M68KMAKE_OP(suba, 16, ., .)
\r
9762 uint* r_dst = &AX;
\r
9763 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
9765 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
\r
9769 M68KMAKE_OP(suba, 32, ., d)
\r
9771 uint* r_dst = &AX;
\r
9773 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
\r
9777 M68KMAKE_OP(suba, 32, ., a)
\r
9779 uint* r_dst = &AX;
\r
9781 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
\r
9785 M68KMAKE_OP(suba, 32, ., .)
\r
9787 uint* r_dst = &AX;
\r
9789 *r_dst = MASK_OUT_ABOVE_32(*r_dst - M68KMAKE_GET_OPER_AY_32);
\r
9793 M68KMAKE_OP(subi, 8, ., d)
\r
9795 uint* r_dst = &DY;
\r
9796 uint src = OPER_I_8();
\r
9797 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9798 uint res = dst - src;
\r
9800 FLAG_N = NFLAG_8(res);
\r
9801 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9802 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9803 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9805 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9809 M68KMAKE_OP(subi, 8, ., .)
\r
9811 uint src = OPER_I_8();
\r
9812 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9813 uint dst = m68ki_read_8(ea);
\r
9814 uint res = dst - src;
\r
9816 FLAG_N = NFLAG_8(res);
\r
9817 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9818 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9819 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9821 m68ki_write_8(ea, FLAG_Z);
\r
9825 M68KMAKE_OP(subi, 16, ., d)
\r
9827 uint* r_dst = &DY;
\r
9828 uint src = OPER_I_16();
\r
9829 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9830 uint res = dst - src;
\r
9832 FLAG_N = NFLAG_16(res);
\r
9833 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9834 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9835 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9837 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9841 M68KMAKE_OP(subi, 16, ., .)
\r
9843 uint src = OPER_I_16();
\r
9844 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9845 uint dst = m68ki_read_16(ea);
\r
9846 uint res = dst - src;
\r
9848 FLAG_N = NFLAG_16(res);
\r
9849 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9850 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9851 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9853 m68ki_write_16(ea, FLAG_Z);
\r
9857 M68KMAKE_OP(subi, 32, ., d)
\r
9859 uint* r_dst = &DY;
\r
9860 uint src = OPER_I_32();
\r
9861 uint dst = *r_dst;
\r
9862 uint res = dst - src;
\r
9864 FLAG_N = NFLAG_32(res);
\r
9865 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9866 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9867 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9873 M68KMAKE_OP(subi, 32, ., .)
\r
9875 uint src = OPER_I_32();
\r
9876 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9877 uint dst = m68ki_read_32(ea);
\r
9878 uint res = dst - src;
\r
9880 FLAG_N = NFLAG_32(res);
\r
9881 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9882 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9883 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9885 m68ki_write_32(ea, FLAG_Z);
\r
9889 M68KMAKE_OP(subq, 8, ., d)
\r
9891 uint* r_dst = &DY;
\r
9892 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9893 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9894 uint res = dst - src;
\r
9896 FLAG_N = NFLAG_8(res);
\r
9897 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9898 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9899 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9901 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9905 M68KMAKE_OP(subq, 8, ., .)
\r
9907 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9908 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9909 uint dst = m68ki_read_8(ea);
\r
9910 uint res = dst - src;
\r
9912 FLAG_N = NFLAG_8(res);
\r
9913 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9914 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9915 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9917 m68ki_write_8(ea, FLAG_Z);
\r
9921 M68KMAKE_OP(subq, 16, ., d)
\r
9923 uint* r_dst = &DY;
\r
9924 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9925 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9926 uint res = dst - src;
\r
9928 FLAG_N = NFLAG_16(res);
\r
9929 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9930 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9931 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9933 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9937 M68KMAKE_OP(subq, 16, ., a)
\r
9939 uint* r_dst = &AY;
\r
9941 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
\r
9945 M68KMAKE_OP(subq, 16, ., .)
\r
9947 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9948 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9949 uint dst = m68ki_read_16(ea);
\r
9950 uint res = dst - src;
\r
9952 FLAG_N = NFLAG_16(res);
\r
9953 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9954 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9955 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9957 m68ki_write_16(ea, FLAG_Z);
\r
9961 M68KMAKE_OP(subq, 32, ., d)
\r
9963 uint* r_dst = &DY;
\r
9964 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9965 uint dst = *r_dst;
\r
9966 uint res = dst - src;
\r
9968 FLAG_N = NFLAG_32(res);
\r
9969 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9970 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9971 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9977 M68KMAKE_OP(subq, 32, ., a)
\r
9979 uint* r_dst = &AY;
\r
9981 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
\r
9985 M68KMAKE_OP(subq, 32, ., .)
\r
9987 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9988 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9989 uint dst = m68ki_read_32(ea);
\r
9990 uint res = dst - src;
\r
9992 FLAG_N = NFLAG_32(res);
\r
9993 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9994 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9995 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9997 m68ki_write_32(ea, FLAG_Z);
\r
10001 M68KMAKE_OP(subx, 8, rr, .)
\r
10003 uint* r_dst = &DX;
\r
10004 uint src = MASK_OUT_ABOVE_8(DY);
\r
10005 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
10006 uint res = dst - src - XFLAG_AS_1();
\r
10008 FLAG_N = NFLAG_8(res);
\r
10009 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10010 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10012 res = MASK_OUT_ABOVE_8(res);
\r
10015 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
10019 M68KMAKE_OP(subx, 16, rr, .)
\r
10021 uint* r_dst = &DX;
\r
10022 uint src = MASK_OUT_ABOVE_16(DY);
\r
10023 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
10024 uint res = dst - src - XFLAG_AS_1();
\r
10026 FLAG_N = NFLAG_16(res);
\r
10027 FLAG_X = FLAG_C = CFLAG_16(res);
\r
10028 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
10030 res = MASK_OUT_ABOVE_16(res);
\r
10033 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
10037 M68KMAKE_OP(subx, 32, rr, .)
\r
10039 uint* r_dst = &DX;
\r
10041 uint dst = *r_dst;
\r
10042 uint res = dst - src - XFLAG_AS_1();
\r
10044 FLAG_N = NFLAG_32(res);
\r
10045 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10046 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10048 res = MASK_OUT_ABOVE_32(res);
\r
10055 M68KMAKE_OP(subx, 8, mm, ax7)
\r
10057 uint src = OPER_AY_PD_8();
\r
10058 uint ea = EA_A7_PD_8();
\r
10059 uint dst = m68ki_read_8(ea);
\r
10060 uint res = dst - src - XFLAG_AS_1();
\r
10062 FLAG_N = NFLAG_8(res);
\r
10063 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10064 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10066 res = MASK_OUT_ABOVE_8(res);
\r
10069 m68ki_write_8(ea, res);
\r
10073 M68KMAKE_OP(subx, 8, mm, ay7)
\r
10075 uint src = OPER_A7_PD_8();
\r
10076 uint ea = EA_AX_PD_8();
\r
10077 uint dst = m68ki_read_8(ea);
\r
10078 uint res = dst - src - XFLAG_AS_1();
\r
10080 FLAG_N = NFLAG_8(res);
\r
10081 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10082 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10084 res = MASK_OUT_ABOVE_8(res);
\r
10087 m68ki_write_8(ea, res);
\r
10091 M68KMAKE_OP(subx, 8, mm, axy7)
\r
10093 uint src = OPER_A7_PD_8();
\r
10094 uint ea = EA_A7_PD_8();
\r
10095 uint dst = m68ki_read_8(ea);
\r
10096 uint res = dst - src - XFLAG_AS_1();
\r
10098 FLAG_N = NFLAG_8(res);
\r
10099 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10100 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10102 res = MASK_OUT_ABOVE_8(res);
\r
10105 m68ki_write_8(ea, res);
\r
10109 M68KMAKE_OP(subx, 8, mm, .)
\r
10111 uint src = OPER_AY_PD_8();
\r
10112 uint ea = EA_AX_PD_8();
\r
10113 uint dst = m68ki_read_8(ea);
\r
10114 uint res = dst - src - XFLAG_AS_1();
\r
10116 FLAG_N = NFLAG_8(res);
\r
10117 FLAG_X = FLAG_C = CFLAG_8(res);
\r
10118 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
10120 res = MASK_OUT_ABOVE_8(res);
\r
10123 m68ki_write_8(ea, res);
\r
10127 M68KMAKE_OP(subx, 16, mm, .)
\r
10129 uint src = OPER_AY_PD_16();
\r
10130 uint ea = EA_AX_PD_16();
\r
10131 uint dst = m68ki_read_16(ea);
\r
10132 uint res = dst - src - XFLAG_AS_1();
\r
10134 FLAG_N = NFLAG_16(res);
\r
10135 FLAG_X = FLAG_C = CFLAG_16(res);
\r
10136 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
10138 res = MASK_OUT_ABOVE_16(res);
\r
10141 m68ki_write_16(ea, res);
\r
10145 M68KMAKE_OP(subx, 32, mm, .)
\r
10147 uint src = OPER_AY_PD_32();
\r
10148 uint ea = EA_AX_PD_32();
\r
10149 uint dst = m68ki_read_32(ea);
\r
10150 uint res = dst - src - XFLAG_AS_1();
\r
10152 FLAG_N = NFLAG_32(res);
\r
10153 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
10154 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
10156 res = MASK_OUT_ABOVE_32(res);
\r
10159 m68ki_write_32(ea, res);
\r
10163 M68KMAKE_OP(swap, 32, ., .)
\r
10165 uint* r_dst = &DY;
\r
10167 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
\r
10168 *r_dst = (*r_dst>>16) | FLAG_Z;
\r
10171 FLAG_N = NFLAG_32(*r_dst);
\r
10172 FLAG_C = CFLAG_CLEAR;
\r
10173 FLAG_V = VFLAG_CLEAR;
\r
10177 M68KMAKE_OP(tas, 8, ., d)
\r
10179 uint* r_dst = &DY;
\r
10181 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
10182 FLAG_N = NFLAG_8(*r_dst);
\r
10183 FLAG_V = VFLAG_CLEAR;
\r
10184 FLAG_C = CFLAG_CLEAR;
\r
10189 M68KMAKE_OP(tas, 8, ., .)
\r
10191 uint ea = M68KMAKE_GET_EA_AY_8;
\r
10192 uint dst = m68ki_read_8(ea);
\r
10193 uint allow_writeback;
\r
10196 FLAG_N = NFLAG_8(dst);
\r
10197 FLAG_V = VFLAG_CLEAR;
\r
10198 FLAG_C = CFLAG_CLEAR;
\r
10200 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
\r
10201 disabled in order to function properly. Some Amiga software may also rely
\r
10202 on this, but only when accessing specific addresses so additional functionality
\r
10203 will be needed. */
\r
10204 allow_writeback = m68ki_tas_callback();
\r
10206 if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);
\r
10210 M68KMAKE_OP(trap, 0, ., .)
\r
10212 /* Trap#n stacks exception frame type 0 */
\r
10213 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
\r
10217 M68KMAKE_OP(trapt, 0, ., .)
\r
10219 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10221 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10224 m68ki_exception_illegal();
\r
10228 M68KMAKE_OP(trapt, 16, ., .)
\r
10230 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10232 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10235 m68ki_exception_illegal();
\r
10239 M68KMAKE_OP(trapt, 32, ., .)
\r
10241 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10243 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10246 m68ki_exception_illegal();
\r
10250 M68KMAKE_OP(trapf, 0, ., .)
\r
10252 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10256 m68ki_exception_illegal();
\r
10260 M68KMAKE_OP(trapf, 16, ., .)
\r
10262 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10267 m68ki_exception_illegal();
\r
10271 M68KMAKE_OP(trapf, 32, ., .)
\r
10273 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10278 m68ki_exception_illegal();
\r
10282 M68KMAKE_OP(trapcc, 0, ., .)
\r
10284 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10287 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10290 m68ki_exception_illegal();
\r
10294 M68KMAKE_OP(trapcc, 16, ., .)
\r
10296 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10300 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10306 m68ki_exception_illegal();
\r
10310 M68KMAKE_OP(trapcc, 32, ., .)
\r
10312 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10316 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10322 m68ki_exception_illegal();
\r
10326 M68KMAKE_OP(trapv, 0, ., .)
\r
10332 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
10336 M68KMAKE_OP(tst, 8, ., d)
\r
10338 uint res = MASK_OUT_ABOVE_8(DY);
\r
10340 FLAG_N = NFLAG_8(res);
\r
10342 FLAG_V = VFLAG_CLEAR;
\r
10343 FLAG_C = CFLAG_CLEAR;
\r
10347 M68KMAKE_OP(tst, 8, ., .)
\r
10349 uint res = M68KMAKE_GET_OPER_AY_8;
\r
10351 FLAG_N = NFLAG_8(res);
\r
10353 FLAG_V = VFLAG_CLEAR;
\r
10354 FLAG_C = CFLAG_CLEAR;
\r
10358 M68KMAKE_OP(tst, 8, ., pcdi)
\r
10360 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10362 uint res = OPER_PCDI_8();
\r
10364 FLAG_N = NFLAG_8(res);
\r
10366 FLAG_V = VFLAG_CLEAR;
\r
10367 FLAG_C = CFLAG_CLEAR;
\r
10370 m68ki_exception_illegal();
\r
10374 M68KMAKE_OP(tst, 8, ., pcix)
\r
10376 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10378 uint res = OPER_PCIX_8();
\r
10380 FLAG_N = NFLAG_8(res);
\r
10382 FLAG_V = VFLAG_CLEAR;
\r
10383 FLAG_C = CFLAG_CLEAR;
\r
10386 m68ki_exception_illegal();
\r
10390 M68KMAKE_OP(tst, 8, ., i)
\r
10392 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10394 uint res = OPER_I_8();
\r
10396 FLAG_N = NFLAG_8(res);
\r
10398 FLAG_V = VFLAG_CLEAR;
\r
10399 FLAG_C = CFLAG_CLEAR;
\r
10402 m68ki_exception_illegal();
\r
10406 M68KMAKE_OP(tst, 16, ., d)
\r
10408 uint res = MASK_OUT_ABOVE_16(DY);
\r
10410 FLAG_N = NFLAG_16(res);
\r
10412 FLAG_V = VFLAG_CLEAR;
\r
10413 FLAG_C = CFLAG_CLEAR;
\r
10417 M68KMAKE_OP(tst, 16, ., a)
\r
10419 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10421 uint res = MAKE_INT_16(AY);
\r
10423 FLAG_N = NFLAG_16(res);
\r
10425 FLAG_V = VFLAG_CLEAR;
\r
10426 FLAG_C = CFLAG_CLEAR;
\r
10429 m68ki_exception_illegal();
\r
10433 M68KMAKE_OP(tst, 16, ., .)
\r
10435 uint res = M68KMAKE_GET_OPER_AY_16;
\r
10437 FLAG_N = NFLAG_16(res);
\r
10439 FLAG_V = VFLAG_CLEAR;
\r
10440 FLAG_C = CFLAG_CLEAR;
\r
10444 M68KMAKE_OP(tst, 16, ., pcdi)
\r
10446 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10448 uint res = OPER_PCDI_16();
\r
10450 FLAG_N = NFLAG_16(res);
\r
10452 FLAG_V = VFLAG_CLEAR;
\r
10453 FLAG_C = CFLAG_CLEAR;
\r
10456 m68ki_exception_illegal();
\r
10460 M68KMAKE_OP(tst, 16, ., pcix)
\r
10462 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10464 uint res = OPER_PCIX_16();
\r
10466 FLAG_N = NFLAG_16(res);
\r
10468 FLAG_V = VFLAG_CLEAR;
\r
10469 FLAG_C = CFLAG_CLEAR;
\r
10472 m68ki_exception_illegal();
\r
10476 M68KMAKE_OP(tst, 16, ., i)
\r
10478 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10480 uint res = OPER_I_16();
\r
10482 FLAG_N = NFLAG_16(res);
\r
10484 FLAG_V = VFLAG_CLEAR;
\r
10485 FLAG_C = CFLAG_CLEAR;
\r
10488 m68ki_exception_illegal();
\r
10492 M68KMAKE_OP(tst, 32, ., d)
\r
10496 FLAG_N = NFLAG_32(res);
\r
10498 FLAG_V = VFLAG_CLEAR;
\r
10499 FLAG_C = CFLAG_CLEAR;
\r
10503 M68KMAKE_OP(tst, 32, ., a)
\r
10505 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10509 FLAG_N = NFLAG_32(res);
\r
10511 FLAG_V = VFLAG_CLEAR;
\r
10512 FLAG_C = CFLAG_CLEAR;
\r
10515 m68ki_exception_illegal();
\r
10519 M68KMAKE_OP(tst, 32, ., .)
\r
10521 uint res = M68KMAKE_GET_OPER_AY_32;
\r
10523 FLAG_N = NFLAG_32(res);
\r
10525 FLAG_V = VFLAG_CLEAR;
\r
10526 FLAG_C = CFLAG_CLEAR;
\r
10530 M68KMAKE_OP(tst, 32, ., pcdi)
\r
10532 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10534 uint res = OPER_PCDI_32();
\r
10536 FLAG_N = NFLAG_32(res);
\r
10538 FLAG_V = VFLAG_CLEAR;
\r
10539 FLAG_C = CFLAG_CLEAR;
\r
10542 m68ki_exception_illegal();
\r
10546 M68KMAKE_OP(tst, 32, ., pcix)
\r
10548 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10550 uint res = OPER_PCIX_32();
\r
10552 FLAG_N = NFLAG_32(res);
\r
10554 FLAG_V = VFLAG_CLEAR;
\r
10555 FLAG_C = CFLAG_CLEAR;
\r
10558 m68ki_exception_illegal();
\r
10562 M68KMAKE_OP(tst, 32, ., i)
\r
10564 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10566 uint res = OPER_I_32();
\r
10568 FLAG_N = NFLAG_32(res);
\r
10570 FLAG_V = VFLAG_CLEAR;
\r
10571 FLAG_C = CFLAG_CLEAR;
\r
10574 m68ki_exception_illegal();
\r
10578 M68KMAKE_OP(unlk, 32, ., a7)
\r
10580 REG_A[7] = m68ki_read_32(REG_A[7]);
\r
10584 M68KMAKE_OP(unlk, 32, ., .)
\r
10586 uint* r_dst = &AY;
\r
10588 REG_A[7] = *r_dst;
\r
10589 *r_dst = m68ki_pull_32();
\r
10593 M68KMAKE_OP(unpk, 16, rr, .)
\r
10595 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10597 /* Note: DX and DY are reversed in Motorola's docs */
\r
10599 uint* r_dst = &DX;
\r
10601 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
\r
10604 m68ki_exception_illegal();
\r
10608 M68KMAKE_OP(unpk, 16, mm, ax7)
\r
10610 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10612 /* Note: AX and AY are reversed in Motorola's docs */
\r
10613 uint src = OPER_AY_PD_8();
\r
10616 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10617 ea_dst = EA_A7_PD_8();
\r
10618 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10619 ea_dst = EA_A7_PD_8();
\r
10620 m68ki_write_8(ea_dst, src & 0xff);
\r
10623 m68ki_exception_illegal();
\r
10627 M68KMAKE_OP(unpk, 16, mm, ay7)
\r
10629 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10631 /* Note: AX and AY are reversed in Motorola's docs */
\r
10632 uint src = OPER_A7_PD_8();
\r
10635 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10636 ea_dst = EA_AX_PD_8();
\r
10637 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10638 ea_dst = EA_AX_PD_8();
\r
10639 m68ki_write_8(ea_dst, src & 0xff);
\r
10642 m68ki_exception_illegal();
\r
10646 M68KMAKE_OP(unpk, 16, mm, axy7)
\r
10648 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10650 uint src = OPER_A7_PD_8();
\r
10653 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10654 ea_dst = EA_A7_PD_8();
\r
10655 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10656 ea_dst = EA_A7_PD_8();
\r
10657 m68ki_write_8(ea_dst, src & 0xff);
\r
10660 m68ki_exception_illegal();
\r
10664 M68KMAKE_OP(unpk, 16, mm, .)
\r
10666 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
10668 /* Note: AX and AY are reversed in Motorola's docs */
\r
10669 uint src = OPER_AY_PD_8();
\r
10672 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
10673 ea_dst = EA_AX_PD_8();
\r
10674 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
10675 ea_dst = EA_AX_PD_8();
\r
10676 m68ki_write_8(ea_dst, src & 0xff);
\r
10679 m68ki_exception_illegal();
\r
10684 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
\r
notaz.gp2x.de / picodrive.git / blob