3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * - tcache, block descriptor, link buffer overflows result in sh2_translate()
10 * failure, followed by full tcache invalidation for that region
11 * - jumps between blocks are tracked for SMC handling (in block_entry->links),
12 * except jumps between different tcaches
15 * - static register allocation
16 * - remaining register caching and tracking in temporaries
17 * - block-local branch linking
18 * - block linking (except between tcaches)
19 * - some constant propagation
22 * - better constant propagation
31 #include "../../pico/pico_int.h"
34 #include "../drc/cmn.h"
38 #define PROPAGATE_CONSTANTS 1
39 #define LINK_BRANCHES 1
42 #define MAX_BLOCK_SIZE (BLOCK_INSN_LIMIT * 6 * 6)
44 // max literal offset from the block end
45 #define MAX_LITERAL_OFFSET 32*2
46 #define MAX_LITERALS (BLOCK_INSN_LIMIT / 4)
47 #define MAX_LOCAL_BRANCHES 32
50 // 1 - warnings/errors
53 // 8 - runtime block entry log
60 #define dbg(l,...) { \
61 if ((l) & DRC_DEBUG) \
62 elprintf(EL_STATUS, ##__VA_ARGS__); \
64 #include "mame/sh2dasm.h"
65 #include <platform/libpicofe/linux/host_dasm.h>
66 static int insns_compiled, hash_collisions, host_insn_count;
75 #define FETCH_OP(pc) \
79 ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
81 #define CHECK_UNHANDLED_BITS(mask, label) { \
82 if ((op & (mask)) != 0) \
94 #define BITMASK1(v0) (1 << (v0))
95 #define BITMASK2(v0,v1) ((1 << (v0)) | (1 << (v1)))
96 #define BITMASK3(v0,v1,v2) (BITMASK2(v0,v1) | (1 << (v2)))
97 #define BITMASK4(v0,v1,v2,v3) (BITMASK3(v0,v1,v2) | (1 << (v3)))
98 #define BITMASK5(v0,v1,v2,v3,v4) (BITMASK4(v0,v1,v2,v3) | (1 << (v4)))
100 #define SHR_T SHR_SR // might make them separate someday
102 static struct op_data {
105 u8 size; // 0, 1, 2 - byte, word, long
106 s8 rm; // branch or load/store data reg
107 u32 source; // bitmask of src regs
108 u32 dest; // bitmask of dest regs
109 u32 imm; // immediate/io address/branch target
110 // (for literal - address, not value)
111 } ops[BLOCK_INSN_LIMIT];
116 OP_BRANCH_CT, // conditional, branch if T set
117 OP_BRANCH_CF, // conditional, branch if T clear
118 OP_BRANCH_R, // indirect
119 OP_BRANCH_RF, // indirect far (PC + Rm)
120 OP_SETCLRT, // T flag set/clear
121 OP_MOVE, // register move
122 OP_LOAD_POOL, // literal pool load, imm is address
130 static int literal_disabled_frames;
133 static u8 *tcache_dsm_ptrs[3];
134 static char sh2dasm_buff[64];
135 #define do_host_disasm(tcid) \
136 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
137 tcache_dsm_ptrs[tcid] = tcache_ptr
139 #define do_host_disasm(x)
142 #if (DRC_DEBUG & 8) || defined(PDB)
143 static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
146 dbg(8, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
147 sh2->pc, block, (signed int)sr >> 12);
148 pdb_step(sh2, sh2->pc);
155 #define TCACHE_BUFFERS 3
157 // we have 3 translation cache buffers, split from one drc/cmn buffer.
158 // BIOS shares tcache with data array because it's only used for init
159 // and can be discarded early
160 // XXX: need to tune sizes
161 static const int tcache_sizes[TCACHE_BUFFERS] = {
162 DRC_TCACHE_SIZE * 6 / 8, // ROM (rarely used), DRAM
163 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
164 DRC_TCACHE_SIZE / 8, // ... slave
167 static u8 *tcache_bases[TCACHE_BUFFERS];
168 static u8 *tcache_ptrs[TCACHE_BUFFERS];
170 // ptr for code emiters
171 static u8 *tcache_ptr;
173 #define MAX_BLOCK_ENTRIES (BLOCK_INSN_LIMIT / 8)
177 void *jump; // insn address
178 struct block_link *next; // either in block_entry->links or
183 void *tcache_ptr; // translated block for above PC
184 struct block_entry *next; // next block in hash_table with same pc hash
185 struct block_link *links; // links to this entry
187 struct block_desc *block;
192 u32 addr; // block start SH2 PC address
193 u16 size; // ..of recompiled insns+lit. pool
194 u16 size_nolit; // same without literals
199 struct block_entry entryp[MAX_BLOCK_ENTRIES];
202 static const int block_max_counts[TCACHE_BUFFERS] = {
207 static struct block_desc *block_tables[TCACHE_BUFFERS];
208 static int block_counts[TCACHE_BUFFERS];
210 // we have block_link_pool to avoid using mallocs
211 static const int block_link_pool_max_counts[TCACHE_BUFFERS] = {
216 static struct block_link *block_link_pool[TCACHE_BUFFERS];
217 static int block_link_pool_counts[TCACHE_BUFFERS];
218 static struct block_link *unresolved_links[TCACHE_BUFFERS];
220 // used for invalidation
221 static const int ram_sizes[TCACHE_BUFFERS] = {
226 #define INVAL_PAGE_SIZE 0x100
229 struct block_desc *block;
230 struct block_list *next;
233 // array of pointers to block_lists for RAM and 2 data arrays
234 // each array has len: sizeof(mem) / INVAL_PAGE_SIZE
235 static struct block_list **inval_lookup[TCACHE_BUFFERS];
237 static const int hash_table_sizes[TCACHE_BUFFERS] = {
242 static struct block_entry **hash_tables[TCACHE_BUFFERS];
244 #define HASH_FUNC(hash_tab, addr, mask) \
245 (hash_tab)[(((addr) >> 20) ^ ((addr) >> 2)) & (mask)]
247 // host register tracking
250 HR_CACHED, // 'val' has sh2_reg_e
251 // HR_CONST, // 'val' has a constant
252 HR_TEMP, // reg used for temp storage
256 HRF_DIRTY = 1 << 0, // reg has "dirty" value to be written to ctx
257 HRF_LOCKED = 1 << 1, // HR_CACHED can't be evicted
261 u32 hreg:5; // "host" reg
262 u32 greg:5; // "guest" reg
265 u32 stamp:16; // kind of a timestamp
268 // note: reg_temp[] must have at least the amount of
269 // registers used by handlers in worst case (currently 4)
271 #include "../drc/emit_arm.c"
275 static const int reg_map_g2h[] = {
279 -1, -1, -1, 9, // r12 .. sp
280 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
281 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
287 static const int reg_map_g2h[] = {
291 -1, -1, -1, 8, // r12 .. sp
292 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
293 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
298 static temp_reg_t reg_temp[] = {
307 #elif defined(__i386__)
308 #include "../drc/emit_x86.c"
310 static const int reg_map_g2h[] = {
319 // ax, cx, dx are usually temporaries by convention
320 static temp_reg_t reg_temp[] = {
328 #error unsupported arch
336 #define T_save 0x00000800
342 static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
343 static void (*sh2_drc_dispatcher)(void);
344 static void (*sh2_drc_exit)(void);
345 static void (*sh2_drc_test_irq)(void);
347 static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
348 static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
349 static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
350 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
351 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
352 static void REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
354 // address space stuff
355 static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
359 if ((a & ~0x7ff) == 0) {
361 poffs = offsetof(SH2, p_bios);
364 else if ((a & 0xfffff000) == 0xc0000000) {
366 // FIXME: access sh2->data_array instead
367 poffs = offsetof(SH2, p_da);
370 else if ((a & 0xc6000000) == 0x06000000) {
372 poffs = offsetof(SH2, p_sdram);
375 else if ((a & 0xc6000000) == 0x02000000) {
377 poffs = offsetof(SH2, p_rom);
384 static struct block_entry *dr_get_entry(u32 pc, int is_slave, int *tcache_id)
386 struct block_entry *be;
389 // data arrays have their own caches
390 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0)
395 mask = hash_table_sizes[tcid] - 1;
396 be = HASH_FUNC(hash_tables[tcid], pc, mask);
397 for (; be != NULL; be = be->next)
404 // ---------------------------------------------------------------
407 static void add_to_block_list(struct block_list **blist, struct block_desc *block)
409 struct block_list *added = malloc(sizeof(*added));
411 elprintf(EL_ANOMALY, "drc OOM (1)");
414 added->block = block;
415 added->next = *blist;
419 static void rm_from_block_list(struct block_list **blist, struct block_desc *block)
421 struct block_list *prev = NULL, *current = *blist;
422 for (; current != NULL; prev = current, current = current->next) {
423 if (current->block == block) {
425 *blist = current->next;
427 prev->next = current->next;
432 dbg(1, "can't rm block %p (%08x-%08x)",
433 block, block->addr, block->addr + block->size);
436 static void rm_block_list(struct block_list **blist)
438 struct block_list *tmp, *current = *blist;
439 while (current != NULL) {
441 current = current->next;
447 static void REGPARM(1) flush_tcache(int tcid)
451 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
452 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
453 block_counts[tcid], block_max_counts[tcid]);
455 block_counts[tcid] = 0;
456 block_link_pool_counts[tcid] = 0;
457 unresolved_links[tcid] = NULL;
458 memset(hash_tables[tcid], 0, sizeof(*hash_tables[0]) * hash_table_sizes[tcid]);
459 tcache_ptrs[tcid] = tcache_bases[tcid];
460 if (Pico32xMem != NULL) {
461 if (tcid == 0) // ROM, RAM
462 memset(Pico32xMem->drcblk_ram, 0,
463 sizeof(Pico32xMem->drcblk_ram));
465 memset(Pico32xMem->drcblk_da[tcid - 1], 0,
466 sizeof(Pico32xMem->drcblk_da[0]));
469 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
472 for (i = 0; i < ram_sizes[tcid] / INVAL_PAGE_SIZE; i++)
473 rm_block_list(&inval_lookup[tcid][i]);
476 static void add_to_hashlist(struct block_entry *be, int tcache_id)
478 u32 tcmask = hash_table_sizes[tcache_id] - 1;
480 be->next = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
481 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be;
484 if (be->next != NULL) {
485 printf(" %08x: hash collision with %08x\n",
486 be->pc, be->next->pc);
492 static void rm_from_hashlist(struct block_entry *be, int tcache_id)
494 u32 tcmask = hash_table_sizes[tcache_id] - 1;
495 struct block_entry *cur, *prev;
497 cur = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
501 if (be == cur) { // first
502 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be->next;
506 for (prev = cur, cur = cur->next; cur != NULL; cur = cur->next) {
508 prev->next = cur->next;
514 dbg(1, "rm_from_hashlist: be %p %08x missing?", be, be->pc);
517 static struct block_desc *dr_add_block(u32 addr, u16 size_lit,
518 u16 size_nolit, int is_slave, int *blk_id)
520 struct block_entry *be;
521 struct block_desc *bd;
525 // do a lookup to get tcache_id and override check
526 be = dr_get_entry(addr, is_slave, &tcache_id);
528 dbg(1, "block override for %08x", addr);
530 bcount = &block_counts[tcache_id];
531 if (*bcount >= block_max_counts[tcache_id]) {
532 dbg(1, "bd overflow for tcache %d", tcache_id);
536 bd = &block_tables[tcache_id][*bcount];
539 bd->size_nolit = size_nolit;
542 bd->entryp[0].pc = addr;
543 bd->entryp[0].tcache_ptr = tcache_ptr;
544 bd->entryp[0].links = NULL;
546 bd->entryp[0].block = bd;
549 add_to_hashlist(&bd->entryp[0], tcache_id);
557 static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id)
559 struct block_entry *be = NULL;
562 be = dr_get_entry(pc, is_slave, tcache_id);
564 block = be->tcache_ptr;
568 be->block->refcount++;
573 static void *dr_failure(void)
575 lprintf("recompilation failed\n");
579 static void *dr_prepare_ext_branch(u32 pc, int is_slave, int tcache_id)
582 struct block_link *bl = block_link_pool[tcache_id];
583 int cnt = block_link_pool_counts[tcache_id];
584 struct block_entry *be = NULL;
585 int target_tcache_id;
588 be = dr_get_entry(pc, is_slave, &target_tcache_id);
589 if (target_tcache_id != tcache_id)
590 return sh2_drc_dispatcher;
592 // if pool has been freed, reuse
593 for (i = cnt - 1; i >= 0; i--)
594 if (bl[i].target_pc != 0)
597 if (cnt >= block_link_pool_max_counts[tcache_id]) {
598 dbg(1, "bl overflow for tcache %d", tcache_id);
602 block_link_pool_counts[tcache_id]++;
605 bl->jump = tcache_ptr;
608 dbg(2, "- early link from %p to pc %08x", bl->jump, pc);
609 bl->next = be->links;
611 return be->tcache_ptr;
614 bl->next = unresolved_links[tcache_id];
615 unresolved_links[tcache_id] = bl;
616 return sh2_drc_dispatcher;
619 return sh2_drc_dispatcher;
623 static void dr_link_blocks(struct block_entry *be, int tcache_id)
626 struct block_link *first = unresolved_links[tcache_id];
627 struct block_link *bl, *prev, *tmp;
630 for (bl = prev = first; bl != NULL; ) {
631 if (bl->target_pc == pc) {
632 dbg(2, "- link from %p to pc %08x", bl->jump, pc);
633 emith_jump_patch(bl->jump, tcache_ptr);
635 // move bl from unresolved_links to block_entry
637 bl->next = be->links;
641 first = prev = bl = tmp;
643 prev->next = bl = tmp;
649 unresolved_links[tcache_id] = first;
651 // could sync arm caches here, but that's unnecessary
655 #define ADD_TO_ARRAY(array, count, item, failcode) \
656 if (count >= ARRAY_SIZE(array)) { \
657 dbg(1, "warning: " #array " overflow"); \
660 array[count++] = item;
662 static int find_in_array(u32 *array, size_t size, u32 what)
665 for (i = 0; i < size; i++)
666 if (what == array[i])
672 // ---------------------------------------------------------------
674 // register cache / constant propagation stuff
681 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking);
683 // guest regs with constants
684 static u32 dr_gcregs[24];
685 // a mask of constant/dirty regs
686 static u32 dr_gcregs_mask;
687 static u32 dr_gcregs_dirty;
689 #if PROPAGATE_CONSTANTS
690 static void gconst_new(sh2_reg_e r, u32 val)
694 dr_gcregs_mask |= 1 << r;
695 dr_gcregs_dirty |= 1 << r;
698 // throw away old r that we might have cached
699 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
700 if ((reg_temp[i].type == HR_CACHED) &&
701 reg_temp[i].greg == r) {
702 reg_temp[i].type = HR_FREE;
703 reg_temp[i].flags = 0;
709 static int gconst_get(sh2_reg_e r, u32 *val)
711 if (dr_gcregs_mask & (1 << r)) {
718 static int gconst_check(sh2_reg_e r)
720 if ((dr_gcregs_mask | dr_gcregs_dirty) & (1 << r))
725 // update hr if dirty, else do nothing
726 static int gconst_try_read(int hr, sh2_reg_e r)
728 if (dr_gcregs_dirty & (1 << r)) {
729 emith_move_r_imm(hr, dr_gcregs[r]);
730 dr_gcregs_dirty &= ~(1 << r);
736 static void gconst_check_evict(sh2_reg_e r)
738 if (dr_gcregs_mask & (1 << r))
739 // no longer cached in reg, make dirty again
740 dr_gcregs_dirty |= 1 << r;
743 static void gconst_kill(sh2_reg_e r)
745 dr_gcregs_mask &= ~(1 << r);
746 dr_gcregs_dirty &= ~(1 << r);
749 static void gconst_clean(void)
753 for (i = 0; i < ARRAY_SIZE(dr_gcregs); i++)
754 if (dr_gcregs_dirty & (1 << i)) {
755 // using RC_GR_READ here: it will call gconst_try_read,
756 // cache the reg and mark it dirty.
757 rcache_get_reg_(i, RC_GR_READ, 0);
761 static void gconst_invalidate(void)
763 dr_gcregs_mask = dr_gcregs_dirty = 0;
766 static u16 rcache_counter;
768 static temp_reg_t *rcache_evict(void)
770 // evict reg with oldest stamp
772 u16 min_stamp = (u16)-1;
774 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
775 if (reg_temp[i].type == HR_CACHED && !(reg_temp[i].flags & HRF_LOCKED) &&
776 reg_temp[i].stamp <= min_stamp) {
777 min_stamp = reg_temp[i].stamp;
783 printf("no registers to evict, aborting\n");
788 if (reg_temp[i].type == HR_CACHED) {
789 if (reg_temp[i].flags & HRF_DIRTY)
791 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
792 gconst_check_evict(reg_temp[i].greg);
795 reg_temp[i].type = HR_FREE;
796 reg_temp[i].flags = 0;
800 static int get_reg_static(sh2_reg_e r, rc_gr_mode mode)
802 int i = reg_map_g2h[r];
804 if (mode != RC_GR_WRITE)
805 gconst_try_read(i, r);
810 // note: must not be called when doing conditional code
811 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking)
816 // maybe statically mapped?
817 ret = get_reg_static(r, mode);
823 // maybe already cached?
824 // if so, prefer against gconst (they must be in sync)
825 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
826 if (reg_temp[i].type == HR_CACHED && reg_temp[i].greg == r) {
827 reg_temp[i].stamp = rcache_counter;
828 if (mode != RC_GR_READ)
829 reg_temp[i].flags |= HRF_DIRTY;
830 ret = reg_temp[i].hreg;
836 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
837 if (reg_temp[i].type == HR_FREE) {
846 tr->type = HR_CACHED;
848 tr->flags |= HRF_LOCKED;
849 if (mode != RC_GR_READ)
850 tr->flags |= HRF_DIRTY;
852 tr->stamp = rcache_counter;
855 if (mode != RC_GR_WRITE) {
856 if (gconst_check(r)) {
857 if (gconst_try_read(ret, r))
858 tr->flags |= HRF_DIRTY;
861 emith_ctx_read(tr->hreg, r * 4);
865 if (mode != RC_GR_READ)
871 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
873 return rcache_get_reg_(r, mode, 1);
876 static int rcache_get_tmp(void)
881 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
882 if (reg_temp[i].type == HR_FREE) {
894 static int rcache_get_arg_id(int arg)
897 host_arg2reg(r, arg);
899 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
900 if (reg_temp[i].hreg == r)
903 if (i == ARRAY_SIZE(reg_temp)) // can't happen
906 if (reg_temp[i].type == HR_CACHED) {
908 if (reg_temp[i].flags & HRF_DIRTY)
909 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
910 gconst_check_evict(reg_temp[i].greg);
912 else if (reg_temp[i].type == HR_TEMP) {
913 printf("arg %d reg %d already used, aborting\n", arg, r);
917 reg_temp[i].type = HR_FREE;
918 reg_temp[i].flags = 0;
923 // get a reg to be used as function arg
924 static int rcache_get_tmp_arg(int arg)
926 int id = rcache_get_arg_id(arg);
927 reg_temp[id].type = HR_TEMP;
929 return reg_temp[id].hreg;
932 // same but caches a reg. RC_GR_READ only.
933 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
935 int i, srcr, dstr, dstid;
936 int dirty = 0, src_dirty = 0;
938 dstid = rcache_get_arg_id(arg);
939 dstr = reg_temp[dstid].hreg;
941 // maybe already statically mapped?
942 srcr = get_reg_static(r, RC_GR_READ);
946 // maybe already cached?
947 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
948 if ((reg_temp[i].type == HR_CACHED) &&
949 reg_temp[i].greg == r)
951 srcr = reg_temp[i].hreg;
952 if (reg_temp[i].flags & HRF_DIRTY)
960 if (gconst_check(r)) {
961 if (gconst_try_read(srcr, r))
965 emith_ctx_read(srcr, r * 4);
969 emith_move_r_r(dstr, srcr);
975 // must clean, callers might want to modify the arg before call
976 emith_ctx_write(dstr, r * 4);
979 reg_temp[dstid].flags |= HRF_DIRTY;
982 reg_temp[dstid].stamp = ++rcache_counter;
983 reg_temp[dstid].type = HR_CACHED;
984 reg_temp[dstid].greg = r;
985 reg_temp[dstid].flags |= HRF_LOCKED;
989 static void rcache_free_tmp(int hr)
992 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
993 if (reg_temp[i].hreg == hr)
996 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
997 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
1001 reg_temp[i].type = HR_FREE;
1002 reg_temp[i].flags = 0;
1005 static void rcache_unlock(int hr)
1008 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1009 if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr)
1010 reg_temp[i].flags &= ~HRF_LOCKED;
1013 static void rcache_unlock_all(void)
1016 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1017 reg_temp[i].flags &= ~HRF_LOCKED;
1020 static inline u32 rcache_used_hreg_mask(void)
1025 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1026 if (reg_temp[i].type != HR_FREE)
1027 mask |= 1 << reg_temp[i].hreg;
1032 static void rcache_clean(void)
1037 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1038 if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) {
1040 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
1041 reg_temp[i].flags &= ~HRF_DIRTY;
1045 static void rcache_invalidate(void)
1048 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
1049 reg_temp[i].type = HR_FREE;
1050 reg_temp[i].flags = 0;
1054 gconst_invalidate();
1057 static void rcache_flush(void)
1060 rcache_invalidate();
1063 // ---------------------------------------------------------------
1065 static int emit_get_rbase_and_offs(u32 a, u32 *offs)
1071 poffs = dr_ctx_get_mem_ptr(a, &mask);
1075 // XXX: could use some related reg
1076 hr = rcache_get_tmp();
1077 emith_ctx_read(hr, poffs);
1078 emith_add_r_imm(hr, a & mask & ~0xff);
1079 *offs = a & 0xff; // XXX: ARM oriented..
1083 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
1085 #if PROPAGATE_CONSTANTS
1086 gconst_new(dst, imm);
1088 int hr = rcache_get_reg(dst, RC_GR_WRITE);
1089 emith_move_r_imm(hr, imm);
1093 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
1095 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
1096 int hr_s = rcache_get_reg(src, RC_GR_READ);
1098 emith_move_r_r(hr_d, hr_s);
1101 // T must be clear, and comparison done just before this
1102 static void emit_or_t_if_eq(int srr)
1104 EMITH_SJMP_START(DCOND_NE);
1105 emith_or_r_imm_c(DCOND_EQ, srr, T);
1106 EMITH_SJMP_END(DCOND_NE);
1109 // arguments must be ready
1110 // reg cache must be clean before call
1111 static int emit_memhandler_read_(int size, int ram_check)
1114 host_arg2reg(arg0, 0);
1118 // must writeback cycles for poll detection stuff
1120 if (reg_map_g2h[SHR_SR] != -1)
1121 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1123 arg1 = rcache_get_tmp_arg(1);
1124 emith_move_r_r(arg1, CONTEXT_REG);
1126 #if 0 // can't do this because of unmapped reads
1128 if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
1129 int tmp = rcache_get_tmp();
1130 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
1131 emith_cmp_r_imm(tmp, 0x02000000);
1134 EMITH_SJMP3_START(DCOND_NE);
1135 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
1136 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1137 EMITH_SJMP3_MID(DCOND_NE);
1138 emith_call_cond(DCOND_NE, sh2_drc_read8);
1142 EMITH_SJMP3_START(DCOND_NE);
1143 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1144 EMITH_SJMP3_MID(DCOND_NE);
1145 emith_call_cond(DCOND_NE, sh2_drc_read16);
1149 EMITH_SJMP3_START(DCOND_NE);
1150 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1151 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
1152 EMITH_SJMP3_MID(DCOND_NE);
1153 emith_call_cond(DCOND_NE, sh2_drc_read32);
1163 emith_call(sh2_drc_read8);
1166 emith_call(sh2_drc_read16);
1169 emith_call(sh2_drc_read32);
1173 rcache_invalidate();
1175 if (reg_map_g2h[SHR_SR] != -1)
1176 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1178 // assuming arg0 and retval reg matches
1179 return rcache_get_tmp_arg(0);
1182 static int emit_memhandler_read(int size)
1184 return emit_memhandler_read_(size, 1);
1187 static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size)
1189 int hr, hr2, ram_check = 1;
1192 if (gconst_get(rs, &val)) {
1193 hr = emit_get_rbase_and_offs(val + offs, &offs2);
1195 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1198 emith_read8_r_r_offs(hr2, hr, offs2 ^ 1);
1199 emith_sext(hr2, hr2, 8);
1202 emith_read16_r_r_offs(hr2, hr, offs2);
1203 emith_sext(hr2, hr2, 16);
1206 emith_read_r_r_offs(hr2, hr, offs2);
1207 emith_ror(hr2, hr2, 16);
1210 rcache_free_tmp(hr);
1217 hr = rcache_get_reg_arg(0, rs);
1219 emith_add_r_imm(hr, offs);
1220 hr = emit_memhandler_read_(size, ram_check);
1221 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1223 emith_sext(hr2, hr, (size == 1) ? 16 : 8);
1225 emith_move_r_r(hr2, hr);
1226 rcache_free_tmp(hr);
1231 static void emit_memhandler_write(int size)
1234 host_arg2reg(ctxr, 2);
1235 if (reg_map_g2h[SHR_SR] != -1)
1236 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1242 // XXX: consider inlining sh2_drc_write8
1243 emith_call(sh2_drc_write8);
1246 emith_call(sh2_drc_write16);
1249 emith_move_r_r(ctxr, CONTEXT_REG);
1250 emith_call(sh2_drc_write32);
1254 rcache_invalidate();
1255 if (reg_map_g2h[SHR_SR] != -1)
1256 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1260 static int emit_indirect_indexed_read(int rx, int ry, int size)
1263 a0 = rcache_get_reg_arg(0, rx);
1264 t = rcache_get_reg(ry, RC_GR_READ);
1265 emith_add_r_r(a0, t);
1266 return emit_memhandler_read(size);
1270 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
1274 rcache_get_reg_arg(0, rn);
1275 tmp = emit_memhandler_read(size);
1276 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
1277 rcache_free_tmp(tmp);
1278 tmp = rcache_get_reg(rn, RC_GR_RMW);
1279 emith_add_r_imm(tmp, 1 << size);
1282 rcache_get_reg_arg(0, rm);
1283 *rmr = emit_memhandler_read(size);
1284 *rnr = rcache_get_tmp();
1285 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
1286 tmp = rcache_get_reg(rm, RC_GR_RMW);
1287 emith_add_r_imm(tmp, 1 << size);
1291 static void emit_do_static_regs(int is_write, int tmpr)
1295 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
1300 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
1301 if (reg_map_g2h[i + 1] != r + 1)
1307 // i, r point to last item
1309 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1311 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1314 emith_ctx_write(r, i * 4);
1316 emith_ctx_read(r, i * 4);
1321 static void emit_block_entry(void)
1325 host_arg2reg(arg0, 0);
1327 #if (DRC_DEBUG & 8) || defined(PDB)
1329 host_arg2reg(arg1, 1);
1330 host_arg2reg(arg2, 2);
1332 emit_do_static_regs(1, arg2);
1333 emith_move_r_r(arg1, CONTEXT_REG);
1334 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
1335 emith_call(sh2_drc_log_entry);
1336 rcache_invalidate();
1338 emith_tst_r_r(arg0, arg0);
1339 EMITH_SJMP_START(DCOND_EQ);
1340 emith_jump_reg_c(DCOND_NE, arg0);
1341 EMITH_SJMP_END(DCOND_EQ);
1344 #define DELAY_SAVE_T(sr) { \
1345 emith_bic_r_imm(sr, T_save); \
1346 emith_tst_r_imm(sr, T); \
1347 EMITH_SJMP_START(DCOND_EQ); \
1348 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
1349 EMITH_SJMP_END(DCOND_EQ); \
1352 #define FLUSH_CYCLES(sr) \
1354 emith_sub_r_imm(sr, cycles << 12); \
1358 static void *dr_get_pc_base(u32 pc, int is_slave);
1360 static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
1362 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
1363 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
1364 int branch_target_count = 0;
1365 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
1366 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
1367 int branch_patch_count = 0;
1368 u32 literal_addr[MAX_LITERALS];
1369 int literal_addr_count = 0;
1370 u8 op_flags[BLOCK_INSN_LIMIT];
1373 u32 pending_branch_direct:1;
1374 u32 pending_branch_indirect:1;
1375 u32 literals_disabled:1;
1378 // PC of current, first, last SH2 insn
1379 u32 pc, base_pc, end_pc;
1381 void *block_entry_ptr;
1382 struct block_desc *block;
1384 struct op_data *opd;
1393 drcf.literals_disabled = literal_disabled_frames != 0;
1395 // get base/validate PC
1396 dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave);
1397 if (dr_pc_base == (void *)-1) {
1398 printf("invalid PC, aborting: %08x\n", base_pc);
1399 // FIXME: be less destructive
1403 tcache_ptr = tcache_ptrs[tcache_id];
1405 // predict tcache overflow
1406 tmp = tcache_ptr - tcache_bases[tcache_id];
1407 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
1408 dbg(1, "tcache %d overflow", tcache_id);
1412 // initial passes to disassemble and analyze the block
1413 scan_block(base_pc, sh2->is_slave, op_flags, &end_pc, &end_literals);
1415 if (drcf.literals_disabled)
1416 end_literals = end_pc;
1418 block = dr_add_block(base_pc, end_literals - base_pc,
1419 end_pc - base_pc, sh2->is_slave, &blkid_main);
1423 block_entry_ptr = tcache_ptr;
1424 dbg(2, "== %csh2 block #%d,%d %08x-%08x -> %p", sh2->is_slave ? 's' : 'm',
1425 tcache_id, blkid_main, base_pc, end_pc, block_entry_ptr);
1427 dr_link_blocks(&block->entryp[0], tcache_id);
1429 // collect branch_targets that don't land on delay slots
1430 for (pc = base_pc, i = 0; pc < end_pc; i++, pc += 2) {
1431 if (!(op_flags[i] & OF_BTARGET))
1433 if (op_flags[i] & OF_DELAY_OP) {
1434 op_flags[i] &= ~OF_BTARGET;
1437 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
1440 if (branch_target_count > 0) {
1441 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
1444 // clear stale state after compile errors
1445 rcache_invalidate();
1447 // -------------------------------------------------
1448 // 3rd pass: actual compilation
1451 for (i = 0; pc < end_pc; i++)
1453 u32 delay_dep_fw = 0, delay_dep_bk = 0;
1463 DasmSH2(sh2dasm_buff, pc, op);
1464 printf("%c%08x %04x %s\n", (op_flags[i] & OF_BTARGET) ? '*' : ' ',
1465 pc, op, sh2dasm_buff);
1468 if ((op_flags[i] & OF_BTARGET) || pc == base_pc)
1472 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1477 v = block->entry_count;
1478 if (v < ARRAY_SIZE(block->entryp)) {
1479 block->entryp[v].pc = pc;
1480 block->entryp[v].tcache_ptr = tcache_ptr;
1481 block->entryp[v].links = NULL;
1483 block->entryp[v].block = block;
1485 add_to_hashlist(&block->entryp[v], tcache_id);
1486 block->entry_count++;
1488 dbg(2, "-- %csh2 block #%d,%d entry %08x -> %p",
1489 sh2->is_slave ? 's' : 'm', tcache_id, blkid_main,
1492 // since we made a block entry, link any other blocks
1493 // that jump to current pc
1494 dr_link_blocks(&block->entryp[v], tcache_id);
1497 dbg(1, "too many entryp for block #%d,%d pc=%08x",
1498 tcache_id, blkid_main, pc);
1501 do_host_disasm(tcache_id);
1504 v = find_in_array(branch_target_pc, branch_target_count, pc);
1506 branch_target_ptr[v] = tcache_ptr;
1509 emit_move_r_imm32(SHR_PC, pc);
1513 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1514 emith_cmp_r_imm(sr, 0);
1515 emith_jump_cond(DCOND_LE, sh2_drc_exit);
1516 do_host_disasm(tcache_id);
1517 rcache_unlock_all();
1521 if (!(op_flags[i] & OF_DELAY_OP)) {
1522 emit_move_r_imm32(SHR_PC, pc);
1523 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1527 tmp = rcache_used_hreg_mask();
1528 emith_save_caller_regs(tmp);
1529 emit_do_static_regs(1, 0);
1530 emith_pass_arg_r(0, CONTEXT_REG);
1531 emith_call(do_sh2_cmp);
1532 emith_restore_caller_regs(tmp);
1543 if (op_flags[i] & OF_DELAY_OP)
1545 // handle delay slot dependencies
1546 delay_dep_fw = opd->dest & ops[i-1].source;
1547 delay_dep_bk = opd->source & ops[i-1].dest;
1548 if (delay_dep_fw & BITMASK1(SHR_T)) {
1549 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1552 if (delay_dep_bk & BITMASK1(SHR_PC)) {
1553 if (opd->op != OP_LOAD_POOL && opd->op != OP_MOVA) {
1554 // can only be those 2 really..
1555 elprintf_sh2(sh2, EL_ANOMALY,
1556 "drc: illegal slot insn %04x @ %08x?", op, pc - 2);
1559 ; // addr already resolved somehow
1561 switch (ops[i-1].op) {
1563 emit_move_r_imm32(SHR_PC, ops[i-1].imm);
1567 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1568 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1569 emith_move_r_imm(tmp, pc);
1570 emith_tst_r_imm(sr, T);
1571 tmp2 = ops[i-1].op == OP_BRANCH_CT ? DCOND_NE : DCOND_EQ;
1572 emith_move_r_imm_c(tmp2, tmp, ops[i-1].imm);
1574 // case OP_BRANCH_R OP_BRANCH_RF - PC already loaded
1578 //if (delay_dep_fw & ~BITMASK1(SHR_T))
1579 // dbg(1, "unhandled delay_dep_fw: %x", delay_dep_fw & ~BITMASK1(SHR_T));
1580 if (delay_dep_bk & ~BITMASK2(SHR_PC, SHR_PR))
1581 dbg(1, "unhandled delay_dep_bk: %x", delay_dep_bk);
1589 if (opd->dest & BITMASK1(SHR_PR))
1590 emit_move_r_imm32(SHR_PR, pc + 2);
1591 drcf.pending_branch_direct = 1;
1595 if (opd->dest & BITMASK1(SHR_PR))
1596 emit_move_r_imm32(SHR_PR, pc + 2);
1597 emit_move_r_r(SHR_PC, opd->rm);
1598 drcf.pending_branch_indirect = 1;
1602 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1603 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1604 if (opd->dest & BITMASK1(SHR_PR)) {
1605 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
1606 emith_move_r_imm(tmp3, pc + 2);
1607 emith_add_r_r_r(tmp, tmp2, tmp3);
1610 emith_move_r_r(tmp, tmp2);
1611 emith_add_r_imm(tmp, pc + 2);
1613 drcf.pending_branch_indirect = 1;
1617 printf("TODO sleep\n");
1622 emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2);
1624 tmp = rcache_get_reg_arg(0, SHR_SP);
1625 emith_add_r_imm(tmp, 4);
1626 tmp = emit_memhandler_read(2);
1627 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1628 emith_write_sr(sr, tmp);
1629 rcache_free_tmp(tmp);
1630 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1631 emith_add_r_imm(tmp, 4*2);
1633 drcf.pending_branch_indirect = 1;
1637 #if PROPAGATE_CONSTANTS
1638 if (opd->imm != 0 && opd->imm < end_literals
1639 && literal_addr_count < MAX_LITERALS)
1641 ADD_TO_ARRAY(literal_addr, literal_addr_count, opd->imm,);
1643 tmp = FETCH32(opd->imm);
1645 tmp = (u32)(int)(signed short)FETCH_OP(opd->imm);
1646 gconst_new(GET_Rn(), tmp);
1651 tmp = rcache_get_tmp_arg(0);
1653 emith_move_r_imm(tmp, opd->imm);
1655 // have to calculate read addr from PC
1656 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
1657 if (opd->size == 2) {
1658 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
1659 emith_bic_r_imm(tmp, 3);
1662 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 2);
1664 tmp2 = emit_memhandler_read(opd->size);
1665 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1667 emith_move_r_r(tmp3, tmp2);
1669 emith_sext(tmp3, tmp2, 16);
1670 rcache_free_tmp(tmp2);
1676 emit_move_r_imm32(SHR_R0, opd->imm);
1678 tmp = rcache_get_reg(SHR_R0, RC_GR_WRITE);
1679 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
1680 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
1681 emith_bic_r_imm(tmp, 3);
1686 switch ((op >> 12) & 0x0f)
1688 /////////////////////////////////////////////
1693 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1696 case 0: // STC SR,Rn 0000nnnn00000010
1699 case 1: // STC GBR,Rn 0000nnnn00010010
1702 case 2: // STC VBR,Rn 0000nnnn00100010
1708 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
1709 emith_move_r_r(tmp, tmp3);
1711 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
1713 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
1714 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
1715 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
1717 tmp = rcache_get_reg_arg(1, GET_Rm());
1718 tmp2 = rcache_get_reg_arg(0, SHR_R0);
1719 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1720 emith_add_r_r(tmp2, tmp3);
1721 emit_memhandler_write(op & 3);
1724 // MUL.L Rm,Rn 0000nnnnmmmm0111
1725 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1726 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1727 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1728 emith_mul(tmp3, tmp2, tmp);
1733 case 0: // CLRT 0000000000001000
1734 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1735 emith_bic_r_imm(sr, T);
1737 case 1: // SETT 0000000000011000
1738 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1739 emith_or_r_imm(sr, T);
1741 case 2: // CLRMAC 0000000000101000
1742 emit_move_r_imm32(SHR_MACL, 0);
1743 emit_move_r_imm32(SHR_MACH, 0);
1752 case 0: // NOP 0000000000001001
1754 case 1: // DIV0U 0000000000011001
1755 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1756 emith_bic_r_imm(sr, M|Q|T);
1758 case 2: // MOVT Rn 0000nnnn00101001
1759 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1760 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1761 emith_clear_msb(tmp2, sr, 31);
1768 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1771 case 0: // STS MACH,Rn 0000nnnn00001010
1774 case 1: // STS MACL,Rn 0000nnnn00011010
1777 case 2: // STS PR,Rn 0000nnnn00101010
1783 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1784 emith_move_r_r(tmp, tmp2);
1786 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1787 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1788 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1789 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1790 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1791 if ((op & 3) != 2) {
1792 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1794 emith_move_r_r(tmp2, tmp);
1795 rcache_free_tmp(tmp);
1797 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1798 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1799 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1800 /* MS 16 MAC bits unused if saturated */
1801 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1802 emith_tst_r_imm(sr, S);
1803 EMITH_SJMP_START(DCOND_EQ);
1804 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1805 EMITH_SJMP_END(DCOND_EQ);
1807 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1808 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1809 rcache_free_tmp(tmp2);
1810 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1811 emith_tst_r_imm(sr, S);
1813 EMITH_JMP_START(DCOND_EQ);
1814 emith_asr(tmp, tmp4, 15);
1815 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1816 EMITH_SJMP_START(DCOND_GE);
1817 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1818 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1819 EMITH_SJMP_END(DCOND_GE);
1820 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1821 EMITH_SJMP_START(DCOND_LE);
1822 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1823 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1824 EMITH_SJMP_END(DCOND_LE);
1825 EMITH_JMP_END(DCOND_EQ);
1827 rcache_free_tmp(tmp);
1832 /////////////////////////////////////////////
1834 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1836 tmp = rcache_get_reg_arg(0, GET_Rn());
1837 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1839 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1840 emit_memhandler_write(2);
1846 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1847 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1848 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1850 rcache_get_reg_arg(0, GET_Rn());
1851 rcache_get_reg_arg(1, GET_Rm());
1852 emit_memhandler_write(op & 3);
1854 case 0x04: // MOV.B Rm,@-Rn 0010nnnnmmmm0100
1855 case 0x05: // MOV.W Rm,@-Rn 0010nnnnmmmm0101
1856 case 0x06: // MOV.L Rm,@-Rn 0010nnnnmmmm0110
1857 rcache_get_reg_arg(1, GET_Rm()); // for Rm == Rn
1858 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1859 emith_sub_r_imm(tmp, (1 << (op & 3)));
1861 rcache_get_reg_arg(0, GET_Rn());
1862 emit_memhandler_write(op & 3);
1864 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1865 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1866 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1867 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1868 emith_bic_r_imm(sr, M|Q|T);
1869 emith_tst_r_imm(tmp2, (1<<31));
1870 EMITH_SJMP_START(DCOND_EQ);
1871 emith_or_r_imm_c(DCOND_NE, sr, Q);
1872 EMITH_SJMP_END(DCOND_EQ);
1873 emith_tst_r_imm(tmp3, (1<<31));
1874 EMITH_SJMP_START(DCOND_EQ);
1875 emith_or_r_imm_c(DCOND_NE, sr, M);
1876 EMITH_SJMP_END(DCOND_EQ);
1877 emith_teq_r_r(tmp2, tmp3);
1878 EMITH_SJMP_START(DCOND_PL);
1879 emith_or_r_imm_c(DCOND_MI, sr, T);
1880 EMITH_SJMP_END(DCOND_PL);
1882 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1883 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1884 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1885 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1886 emith_bic_r_imm(sr, T);
1887 emith_tst_r_r(tmp2, tmp3);
1888 emit_or_t_if_eq(sr);
1890 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1891 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1892 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1893 emith_and_r_r(tmp, tmp2);
1895 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1896 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1897 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1898 emith_eor_r_r(tmp, tmp2);
1900 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1901 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1902 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1903 emith_or_r_r(tmp, tmp2);
1905 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1906 tmp = rcache_get_tmp();
1907 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1908 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1909 emith_eor_r_r_r(tmp, tmp2, tmp3);
1910 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1911 emith_bic_r_imm(sr, T);
1912 emith_tst_r_imm(tmp, 0x000000ff);
1913 emit_or_t_if_eq(sr);
1914 emith_tst_r_imm(tmp, 0x0000ff00);
1915 emit_or_t_if_eq(sr);
1916 emith_tst_r_imm(tmp, 0x00ff0000);
1917 emit_or_t_if_eq(sr);
1918 emith_tst_r_imm(tmp, 0xff000000);
1919 emit_or_t_if_eq(sr);
1920 rcache_free_tmp(tmp);
1922 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1923 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1924 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1925 emith_lsr(tmp, tmp, 16);
1926 emith_or_r_r_lsl(tmp, tmp2, 16);
1928 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1929 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1930 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1931 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1933 emith_sext(tmp, tmp2, 16);
1935 emith_clear_msb(tmp, tmp2, 16);
1936 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1937 tmp2 = rcache_get_tmp();
1939 emith_sext(tmp2, tmp3, 16);
1941 emith_clear_msb(tmp2, tmp3, 16);
1942 emith_mul(tmp, tmp, tmp2);
1943 rcache_free_tmp(tmp2);
1948 /////////////////////////////////////////////
1952 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
1953 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
1954 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
1955 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
1956 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
1957 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1958 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1959 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1960 emith_bic_r_imm(sr, T);
1961 emith_cmp_r_r(tmp2, tmp3);
1964 case 0x00: // CMP/EQ
1965 emit_or_t_if_eq(sr);
1967 case 0x02: // CMP/HS
1968 EMITH_SJMP_START(DCOND_LO);
1969 emith_or_r_imm_c(DCOND_HS, sr, T);
1970 EMITH_SJMP_END(DCOND_LO);
1972 case 0x03: // CMP/GE
1973 EMITH_SJMP_START(DCOND_LT);
1974 emith_or_r_imm_c(DCOND_GE, sr, T);
1975 EMITH_SJMP_END(DCOND_LT);
1977 case 0x06: // CMP/HI
1978 EMITH_SJMP_START(DCOND_LS);
1979 emith_or_r_imm_c(DCOND_HI, sr, T);
1980 EMITH_SJMP_END(DCOND_LS);
1982 case 0x07: // CMP/GT
1983 EMITH_SJMP_START(DCOND_LE);
1984 emith_or_r_imm_c(DCOND_GT, sr, T);
1985 EMITH_SJMP_END(DCOND_LE);
1989 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
1990 // Q1 = carry(Rn = (Rn << 1) | T)
1992 // Q2 = carry(Rn += Rm)
1994 // Q2 = carry(Rn -= Rm)
1996 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
1997 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1998 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1999 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2000 emith_tpop_carry(sr, 0);
2001 emith_adcf_r_r(tmp2, tmp2);
2002 emith_tpush_carry(sr, 0); // keep Q1 in T for now
2003 tmp4 = rcache_get_tmp();
2004 emith_and_r_r_imm(tmp4, sr, M);
2005 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
2006 rcache_free_tmp(tmp4);
2007 // add or sub, invert T if carry to get Q1 ^ Q2
2008 // in: (Q ^ M) passed in Q, Q1 in T
2009 emith_sh2_div1_step(tmp2, tmp3, sr);
2010 emith_bic_r_imm(sr, Q);
2011 emith_tst_r_imm(sr, M);
2012 EMITH_SJMP_START(DCOND_EQ);
2013 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
2014 EMITH_SJMP_END(DCOND_EQ);
2015 emith_tst_r_imm(sr, T);
2016 EMITH_SJMP_START(DCOND_EQ);
2017 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
2018 EMITH_SJMP_END(DCOND_EQ);
2019 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
2021 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
2022 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2023 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2024 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
2025 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
2026 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
2028 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
2029 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
2030 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2031 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2033 emith_add_r_r(tmp, tmp2);
2035 emith_sub_r_r(tmp, tmp2);
2037 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
2038 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
2039 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2040 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2041 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2042 if (op & 4) { // adc
2043 emith_tpop_carry(sr, 0);
2044 emith_adcf_r_r(tmp, tmp2);
2045 emith_tpush_carry(sr, 0);
2047 emith_tpop_carry(sr, 1);
2048 emith_sbcf_r_r(tmp, tmp2);
2049 emith_tpush_carry(sr, 1);
2052 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
2053 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
2054 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2055 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2056 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2057 emith_bic_r_imm(sr, T);
2059 emith_addf_r_r(tmp, tmp2);
2061 emith_subf_r_r(tmp, tmp2);
2062 EMITH_SJMP_START(DCOND_VC);
2063 emith_or_r_imm_c(DCOND_VS, sr, T);
2064 EMITH_SJMP_END(DCOND_VC);
2066 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
2067 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2068 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2069 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
2070 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
2071 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
2076 /////////////////////////////////////////////
2083 case 0: // SHLL Rn 0100nnnn00000000
2084 case 2: // SHAL Rn 0100nnnn00100000
2085 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2086 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2087 emith_tpop_carry(sr, 0); // dummy
2088 emith_lslf(tmp, tmp, 1);
2089 emith_tpush_carry(sr, 0);
2091 case 1: // DT Rn 0100nnnn00010000
2092 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2093 #if 0 // scheduling needs tuning
2094 if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
2095 if (gconst_get(GET_Rn(), &tmp)) {
2096 // XXX: limit burned cycles
2097 emit_move_r_imm32(GET_Rn(), 0);
2098 emith_or_r_imm(sr, T);
2099 cycles += tmp * 4 + 1; // +1 syncs with noconst version, not sure why
2103 emith_sh2_dtbf_loop();
2107 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2108 emith_bic_r_imm(sr, T);
2109 emith_subf_r_imm(tmp, 1);
2110 emit_or_t_if_eq(sr);
2117 case 0: // SHLR Rn 0100nnnn00000001
2118 case 2: // SHAR Rn 0100nnnn00100001
2119 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2120 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2121 emith_tpop_carry(sr, 0); // dummy
2123 emith_asrf(tmp, tmp, 1);
2125 emith_lsrf(tmp, tmp, 1);
2126 emith_tpush_carry(sr, 0);
2128 case 1: // CMP/PZ Rn 0100nnnn00010001
2129 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2130 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2131 emith_bic_r_imm(sr, T);
2132 emith_cmp_r_imm(tmp, 0);
2133 EMITH_SJMP_START(DCOND_LT);
2134 emith_or_r_imm_c(DCOND_GE, sr, T);
2135 EMITH_SJMP_END(DCOND_LT);
2143 case 0x02: // STS.L MACH,@-Rn 0100nnnn00000010
2146 case 0x12: // STS.L MACL,@-Rn 0100nnnn00010010
2149 case 0x22: // STS.L PR,@-Rn 0100nnnn00100010
2152 case 0x03: // STC.L SR,@-Rn 0100nnnn00000011
2155 case 0x13: // STC.L GBR,@-Rn 0100nnnn00010011
2158 case 0x23: // STC.L VBR,@-Rn 0100nnnn00100011
2164 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2165 emith_sub_r_imm(tmp2, 4);
2167 rcache_get_reg_arg(0, GET_Rn());
2168 tmp3 = rcache_get_reg_arg(1, tmp);
2170 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
2171 emit_memhandler_write(2);
2177 case 0x04: // ROTL Rn 0100nnnn00000100
2178 case 0x05: // ROTR Rn 0100nnnn00000101
2179 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2180 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2181 emith_tpop_carry(sr, 0); // dummy
2183 emith_rorf(tmp, tmp, 1);
2185 emith_rolf(tmp, tmp, 1);
2186 emith_tpush_carry(sr, 0);
2188 case 0x24: // ROTCL Rn 0100nnnn00100100
2189 case 0x25: // ROTCR Rn 0100nnnn00100101
2190 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2191 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2192 emith_tpop_carry(sr, 0);
2197 emith_tpush_carry(sr, 0);
2199 case 0x15: // CMP/PL Rn 0100nnnn00010101
2200 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2201 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2202 emith_bic_r_imm(sr, T);
2203 emith_cmp_r_imm(tmp, 0);
2204 EMITH_SJMP_START(DCOND_LE);
2205 emith_or_r_imm_c(DCOND_GT, sr, T);
2206 EMITH_SJMP_END(DCOND_LE);
2214 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
2217 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
2220 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
2223 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
2226 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
2229 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
2235 rcache_get_reg_arg(0, GET_Rn());
2236 tmp2 = emit_memhandler_read(2);
2237 if (tmp == SHR_SR) {
2238 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2239 emith_write_sr(sr, tmp2);
2242 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
2243 emith_move_r_r(tmp, tmp2);
2245 rcache_free_tmp(tmp2);
2246 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2247 emith_add_r_imm(tmp, 4);
2254 // SHLL2 Rn 0100nnnn00001000
2255 // SHLR2 Rn 0100nnnn00001001
2259 // SHLL8 Rn 0100nnnn00011000
2260 // SHLR8 Rn 0100nnnn00011001
2264 // SHLL16 Rn 0100nnnn00101000
2265 // SHLR16 Rn 0100nnnn00101001
2271 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2273 emith_lsr(tmp2, tmp2, tmp);
2275 emith_lsl(tmp2, tmp2, tmp);
2280 case 0: // LDS Rm,MACH 0100mmmm00001010
2283 case 1: // LDS Rm,MACL 0100mmmm00011010
2286 case 2: // LDS Rm,PR 0100mmmm00101010
2292 emit_move_r_r(tmp2, GET_Rn());
2297 case 1: // TAS.B @Rn 0100nnnn00011011
2298 // XXX: is TAS working on 32X?
2299 rcache_get_reg_arg(0, GET_Rn());
2300 tmp = emit_memhandler_read(0);
2301 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2302 emith_bic_r_imm(sr, T);
2303 emith_cmp_r_imm(tmp, 0);
2304 emit_or_t_if_eq(sr);
2306 emith_or_r_imm(tmp, 0x80);
2307 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
2308 emith_move_r_r(tmp2, tmp);
2309 rcache_free_tmp(tmp);
2310 rcache_get_reg_arg(0, GET_Rn());
2311 emit_memhandler_write(0);
2318 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2321 case 0: // LDC Rm,SR 0100mmmm00001110
2324 case 1: // LDC Rm,GBR 0100mmmm00011110
2327 case 2: // LDC Rm,VBR 0100mmmm00101110
2333 if (tmp2 == SHR_SR) {
2334 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2335 emith_write_sr(sr, tmp);
2338 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
2339 emith_move_r_r(tmp2, tmp);
2343 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
2344 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
2345 emith_sext(tmp, tmp, 16);
2346 emith_sext(tmp2, tmp2, 16);
2347 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
2348 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
2349 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
2350 rcache_free_tmp(tmp2);
2351 // XXX: MACH should be untouched when S is set?
2352 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2353 emith_tst_r_imm(sr, S);
2354 EMITH_JMP_START(DCOND_EQ);
2356 emith_asr(tmp, tmp3, 31);
2357 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
2358 EMITH_JMP_START(DCOND_EQ);
2359 emith_move_r_imm(tmp3, 0x80000000);
2360 emith_tst_r_r(tmp4, tmp4);
2361 EMITH_SJMP_START(DCOND_MI);
2362 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
2363 EMITH_SJMP_END(DCOND_MI);
2364 EMITH_JMP_END(DCOND_EQ);
2366 EMITH_JMP_END(DCOND_EQ);
2367 rcache_free_tmp(tmp);
2372 /////////////////////////////////////////////
2374 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
2375 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2);
2378 /////////////////////////////////////////////
2382 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
2383 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
2384 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
2385 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
2386 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
2387 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
2388 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), 0, op & 3);
2389 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
2390 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
2391 emith_add_r_imm(tmp, (1 << (op & 3)));
2396 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
2397 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2400 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
2401 emith_move_r_r(tmp2, tmp);
2403 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
2404 emith_mvn_r_r(tmp2, tmp);
2406 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
2409 tmp3 = rcache_get_tmp();
2410 tmp4 = rcache_get_tmp();
2411 emith_lsr(tmp3, tmp, 16);
2412 emith_or_r_r_lsl(tmp3, tmp, 24);
2413 emith_and_r_r_imm(tmp4, tmp, 0xff00);
2414 emith_or_r_r_lsl(tmp3, tmp4, 8);
2415 emith_rol(tmp2, tmp3, 16);
2416 rcache_free_tmp(tmp4);
2418 rcache_free_tmp(tmp3);
2420 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
2421 emith_rol(tmp2, tmp, 16);
2423 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
2424 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2425 emith_tpop_carry(sr, 1);
2426 emith_negcf_r_r(tmp2, tmp);
2427 emith_tpush_carry(sr, 1);
2429 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
2430 emith_neg_r_r(tmp2, tmp);
2432 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
2433 emith_clear_msb(tmp2, tmp, 24);
2435 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
2436 emith_clear_msb(tmp2, tmp, 16);
2438 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
2439 emith_sext(tmp2, tmp, 8);
2441 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
2442 emith_sext(tmp2, tmp, 16);
2449 /////////////////////////////////////////////
2451 // ADD #imm,Rn 0111nnnniiiiiiii
2452 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2453 if (op & 0x80) { // adding negative
2454 emith_sub_r_imm(tmp, -op & 0xff);
2456 emith_add_r_imm(tmp, op & 0xff);
2459 /////////////////////////////////////////////
2461 switch (op & 0x0f00)
2463 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
2464 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
2466 tmp = rcache_get_reg_arg(0, GET_Rm());
2467 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2468 tmp3 = (op & 0x100) >> 8;
2470 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
2471 emit_memhandler_write(tmp3);
2473 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
2474 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
2475 tmp = (op & 0x100) >> 8;
2476 emit_memhandler_read_rr(SHR_R0, GET_Rm(), (op & 0x0f) << tmp, tmp);
2478 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
2479 // XXX: could use cmn
2480 tmp = rcache_get_tmp();
2481 tmp2 = rcache_get_reg(0, RC_GR_READ);
2482 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2483 emith_move_r_imm_s8(tmp, op & 0xff);
2484 emith_bic_r_imm(sr, T);
2485 emith_cmp_r_r(tmp2, tmp);
2486 emit_or_t_if_eq(sr);
2487 rcache_free_tmp(tmp);
2492 /////////////////////////////////////////////
2494 switch (op & 0x0f00)
2496 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
2497 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
2498 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
2500 tmp = rcache_get_reg_arg(0, SHR_GBR);
2501 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2502 tmp3 = (op & 0x300) >> 8;
2503 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
2504 emit_memhandler_write(tmp3);
2506 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
2507 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
2508 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
2509 tmp = (op & 0x300) >> 8;
2510 emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp);
2512 case 0x0300: // TRAPA #imm 11000011iiiiiiii
2513 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2514 emith_sub_r_imm(tmp, 4*2);
2516 tmp = rcache_get_reg_arg(0, SHR_SP);
2517 emith_add_r_imm(tmp, 4);
2518 tmp = rcache_get_reg_arg(1, SHR_SR);
2519 emith_clear_msb(tmp, tmp, 22);
2520 emit_memhandler_write(2);
2522 rcache_get_reg_arg(0, SHR_SP);
2523 tmp = rcache_get_tmp_arg(1);
2524 emith_move_r_imm(tmp, pc);
2525 emit_memhandler_write(2);
2527 emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
2528 // indirect jump -> back to dispatcher
2530 emith_jump(sh2_drc_dispatcher);
2532 case 0x0800: // TST #imm,R0 11001000iiiiiiii
2533 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
2534 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2535 emith_bic_r_imm(sr, T);
2536 emith_tst_r_imm(tmp, op & 0xff);
2537 emit_or_t_if_eq(sr);
2539 case 0x0900: // AND #imm,R0 11001001iiiiiiii
2540 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2541 emith_and_r_imm(tmp, op & 0xff);
2543 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
2544 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2545 emith_eor_r_imm(tmp, op & 0xff);
2547 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
2548 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2549 emith_or_r_imm(tmp, op & 0xff);
2551 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
2552 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2553 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2554 emith_bic_r_imm(sr, T);
2555 emith_tst_r_imm(tmp, op & 0xff);
2556 emit_or_t_if_eq(sr);
2557 rcache_free_tmp(tmp);
2559 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2560 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2561 emith_and_r_imm(tmp, op & 0xff);
2563 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2564 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2565 emith_eor_r_imm(tmp, op & 0xff);
2567 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2568 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2569 emith_or_r_imm(tmp, op & 0xff);
2571 tmp2 = rcache_get_tmp_arg(1);
2572 emith_move_r_r(tmp2, tmp);
2573 rcache_free_tmp(tmp);
2574 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2575 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2576 emith_add_r_r(tmp3, tmp4);
2577 emit_memhandler_write(0);
2582 /////////////////////////////////////////////
2584 // MOV #imm,Rn 1110nnnniiiiiiii
2585 emit_move_r_imm32(GET_Rn(), (u32)(signed int)(signed char)op);
2590 elprintf_sh2(sh2, EL_ANOMALY,
2591 "drc: illegal op %04x @ %08x", op, pc - 2);
2593 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2594 emith_sub_r_imm(tmp, 4*2);
2596 tmp = rcache_get_reg_arg(0, SHR_SP);
2597 emith_add_r_imm(tmp, 4);
2598 tmp = rcache_get_reg_arg(1, SHR_SR);
2599 emith_clear_msb(tmp, tmp, 22);
2600 emit_memhandler_write(2);
2602 rcache_get_reg_arg(0, SHR_SP);
2603 tmp = rcache_get_tmp_arg(1);
2604 emith_move_r_imm(tmp, pc - 2);
2605 emit_memhandler_write(2);
2607 emit_memhandler_read_rr(SHR_PC, SHR_VBR, 4 * 4, 2);
2608 // indirect jump -> back to dispatcher
2610 emith_jump(sh2_drc_dispatcher);
2615 rcache_unlock_all();
2617 cycles += opd->cycles;
2619 if (op_flags[i+1] & OF_DELAY_OP) {
2620 do_host_disasm(tcache_id);
2625 if (drcf.test_irq && !drcf.pending_branch_direct) {
2626 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2628 if (!drcf.pending_branch_indirect)
2629 emit_move_r_imm32(SHR_PC, pc);
2631 emith_call(sh2_drc_test_irq);
2635 // branch handling (with/without delay)
2636 if (drcf.pending_branch_direct)
2638 struct op_data *opd_b =
2639 (op_flags[i] & OF_DELAY_OP) ? &ops[i-1] : opd;
2640 u32 target_pc = opd_b->imm;
2642 void *target = NULL;
2644 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2647 if (opd_b->op != OP_BRANCH)
2648 cond = (opd_b->op == OP_BRANCH_CF) ? DCOND_EQ : DCOND_NE;
2650 int ctaken = (op_flags[i] & OF_DELAY_OP) ? 1 : 2;
2652 if (delay_dep_fw & BITMASK1(SHR_T))
2653 emith_tst_r_imm(sr, T_save);
2655 emith_tst_r_imm(sr, T);
2657 emith_sub_r_imm_c(cond, sr, ctaken<<12);
2662 if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0)
2665 // XXX: jumps back can be linked already
2666 if (branch_patch_count < MAX_LOCAL_BRANCHES) {
2667 target = tcache_ptr;
2668 branch_patch_pc[branch_patch_count] = target_pc;
2669 branch_patch_ptr[branch_patch_count] = target;
2670 branch_patch_count++;
2673 dbg(1, "warning: too many local branches");
2679 // can't resolve branch locally, make a block exit
2680 emit_move_r_imm32(SHR_PC, target_pc);
2683 target = dr_prepare_ext_branch(target_pc, sh2->is_slave, tcache_id);
2689 emith_jump_cond_patchable(cond, target);
2691 emith_jump_patchable(target);
2692 rcache_invalidate();
2695 drcf.pending_branch_direct = 0;
2697 else if (drcf.pending_branch_indirect) {
2698 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2701 emith_jump(sh2_drc_dispatcher);
2702 drcf.pending_branch_indirect = 0;
2705 do_host_disasm(tcache_id);
2708 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2712 // check the last op
2713 if (op_flags[i-1] & OF_DELAY_OP)
2718 if (opd->op != OP_BRANCH && opd->op != OP_BRANCH_R
2719 && opd->op != OP_BRANCH_RF && opd->op != OP_RTE)
2723 emit_move_r_imm32(SHR_PC, pc);
2726 target = dr_prepare_ext_branch(pc, sh2->is_slave, tcache_id);
2729 emith_jump_patchable(target);
2732 // link local branches
2733 for (i = 0; i < branch_patch_count; i++) {
2736 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2737 target = branch_target_ptr[t];
2738 if (target == NULL) {
2739 // flush pc and go back to dispatcher (this should no longer happen)
2740 dbg(1, "stray branch to %08x %p", branch_patch_pc[i], tcache_ptr);
2741 target = tcache_ptr;
2742 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2744 emith_jump(sh2_drc_dispatcher);
2746 emith_jump_patch(branch_patch_ptr[i], target);
2749 // mark memory blocks as containing compiled code
2750 // override any overlay blocks as they become unreachable anyway
2751 if ((block->addr & 0xc7fc0000) == 0x06000000
2752 || (block->addr & 0xfffff000) == 0xc0000000)
2754 u16 *drc_ram_blk = NULL;
2755 u32 addr, mask = 0, shift = 0;
2757 if (tcache_id != 0) {
2759 drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave];
2760 shift = SH2_DRCBLK_DA_SHIFT;
2765 drc_ram_blk = Pico32xMem->drcblk_ram;
2766 shift = SH2_DRCBLK_RAM_SHIFT;
2770 // mark recompiled insns
2771 drc_ram_blk[(base_pc & mask) >> shift] = 1;
2772 for (pc = base_pc; pc < end_pc; pc += 2)
2773 drc_ram_blk[(pc & mask) >> shift] = 1;
2776 for (i = 0; i < literal_addr_count; i++) {
2777 tmp = literal_addr[i];
2778 drc_ram_blk[(tmp & mask) >> shift] = 1;
2781 // add to invalidation lookup lists
2782 addr = base_pc & ~(INVAL_PAGE_SIZE - 1);
2783 for (; addr < end_literals; addr += INVAL_PAGE_SIZE) {
2784 i = (addr & mask) / INVAL_PAGE_SIZE;
2785 add_to_block_list(&inval_lookup[tcache_id][i], block);
2789 tcache_ptrs[tcache_id] = tcache_ptr;
2791 host_instructions_updated(block_entry_ptr, tcache_ptr);
2793 do_host_disasm(tcache_id);
2795 if (drcf.literals_disabled && literal_addr_count)
2796 dbg(1, "literals_disabled && literal_addr_count?");
2797 dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2798 tcache_id, blkid_main,
2799 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2800 insns_compiled, host_insn_count, (float)host_insn_count / insns_compiled);
2801 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2802 dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2805 tcache_dsm_ptrs[tcache_id] = block_entry_ptr;
2806 do_host_disasm(tcache_id);
2814 return block_entry_ptr;
2817 static void sh2_generate_utils(void)
2819 int arg0, arg1, arg2, sr, tmp;
2821 sh2_drc_write32 = p32x_sh2_write32;
2822 sh2_drc_read8 = p32x_sh2_read8;
2823 sh2_drc_read16 = p32x_sh2_read16;
2824 sh2_drc_read32 = p32x_sh2_read32;
2826 host_arg2reg(arg0, 0);
2827 host_arg2reg(arg1, 1);
2828 host_arg2reg(arg2, 2);
2829 emith_move_r_r(arg0, arg0); // nop
2831 // sh2_drc_exit(void)
2832 sh2_drc_exit = (void *)tcache_ptr;
2833 emit_do_static_regs(1, arg2);
2834 emith_sh2_drc_exit();
2836 // sh2_drc_dispatcher(void)
2837 sh2_drc_dispatcher = (void *)tcache_ptr;
2838 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2839 emith_cmp_r_imm(sr, 0);
2840 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2841 rcache_invalidate();
2842 emith_ctx_read(arg0, SHR_PC * 4);
2843 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2844 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2845 emith_call(dr_lookup_block);
2847 // lookup failed, call sh2_translate()
2848 emith_move_r_r(arg0, CONTEXT_REG);
2849 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2850 emith_call(sh2_translate);
2852 // sh2_translate() failed, flush cache and retry
2853 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2854 emith_call(flush_tcache);
2855 emith_move_r_r(arg0, CONTEXT_REG);
2856 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2857 emith_call(sh2_translate);
2859 // XXX: can't translate, fail
2860 emith_call(dr_failure);
2862 // sh2_drc_test_irq(void)
2863 // assumes it's called from main function (may jump to dispatcher)
2864 sh2_drc_test_irq = (void *)tcache_ptr;
2865 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2866 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2867 emith_lsr(arg0, sr, I_SHIFT);
2868 emith_and_r_imm(arg0, 0x0f);
2869 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2870 EMITH_SJMP_START(DCOND_GT);
2871 emith_ret_c(DCOND_LE); // nope, return
2872 EMITH_SJMP_END(DCOND_GT);
2874 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2875 emith_sub_r_imm(tmp, 4*2);
2878 tmp = rcache_get_reg_arg(0, SHR_SP);
2879 emith_add_r_imm(tmp, 4);
2880 tmp = rcache_get_reg_arg(1, SHR_SR);
2881 emith_clear_msb(tmp, tmp, 22);
2882 emith_move_r_r(arg2, CONTEXT_REG);
2883 emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
2884 rcache_invalidate();
2886 rcache_get_reg_arg(0, SHR_SP);
2887 emith_ctx_read(arg1, SHR_PC * 4);
2888 emith_move_r_r(arg2, CONTEXT_REG);
2889 emith_call(p32x_sh2_write32);
2890 rcache_invalidate();
2891 // update I, cycles, do callback
2892 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2893 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2894 emith_bic_r_imm(sr, I);
2895 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2896 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2898 emith_move_r_r(arg0, CONTEXT_REG);
2899 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2901 emith_lsl(arg0, arg0, 2);
2902 emith_ctx_read(arg1, SHR_VBR * 4);
2903 emith_add_r_r(arg0, arg1);
2904 emit_memhandler_read(2);
2905 emith_ctx_write(arg0, SHR_PC * 4);
2907 emith_add_r_imm(xSP, 4); // fix stack
2909 emith_jump(sh2_drc_dispatcher);
2910 rcache_invalidate();
2912 // sh2_drc_entry(SH2 *sh2)
2913 sh2_drc_entry = (void *)tcache_ptr;
2914 emith_sh2_drc_entry();
2915 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2916 emit_do_static_regs(0, arg2);
2917 emith_call(sh2_drc_test_irq);
2918 emith_jump(sh2_drc_dispatcher);
2920 // sh2_drc_write8(u32 a, u32 d)
2921 sh2_drc_write8 = (void *)tcache_ptr;
2922 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2923 emith_sh2_wcall(arg0, arg2);
2925 // sh2_drc_write16(u32 a, u32 d)
2926 sh2_drc_write16 = (void *)tcache_ptr;
2927 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2928 emith_sh2_wcall(arg0, arg2);
2932 #define MAKE_READ_WRAPPER(func) { \
2933 void *tmp = (void *)tcache_ptr; \
2936 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2937 emith_addf_r_r(arg2, arg0); \
2938 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2939 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2940 emith_adc_r_imm(arg2, 0x01000000); \
2941 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2942 emith_pop_and_ret(); \
2945 #define MAKE_WRITE_WRAPPER(func) { \
2946 void *tmp = (void *)tcache_ptr; \
2947 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2948 emith_addf_r_r(arg2, arg1); \
2949 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2950 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2951 emith_adc_r_imm(arg2, 0x01000000); \
2952 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2953 emith_move_r_r(arg2, CONTEXT_REG); \
2958 MAKE_READ_WRAPPER(sh2_drc_read8);
2959 MAKE_READ_WRAPPER(sh2_drc_read16);
2960 MAKE_READ_WRAPPER(sh2_drc_read32);
2961 MAKE_WRITE_WRAPPER(sh2_drc_write8);
2962 MAKE_WRITE_WRAPPER(sh2_drc_write16);
2963 MAKE_WRITE_WRAPPER(sh2_drc_write32);
2965 host_dasm_new_symbol(sh2_drc_read8);
2966 host_dasm_new_symbol(sh2_drc_read16);
2967 host_dasm_new_symbol(sh2_drc_read32);
2968 host_dasm_new_symbol(sh2_drc_write32);
2972 rcache_invalidate();
2974 host_dasm_new_symbol(sh2_drc_entry);
2975 host_dasm_new_symbol(sh2_drc_dispatcher);
2976 host_dasm_new_symbol(sh2_drc_exit);
2977 host_dasm_new_symbol(sh2_drc_test_irq);
2978 host_dasm_new_symbol(sh2_drc_write8);
2979 host_dasm_new_symbol(sh2_drc_write16);
2983 static void sh2_smc_rm_block_entry(struct block_desc *bd, int tcache_id, u32 ram_mask)
2985 struct block_link *bl, *bl_next, *bl_unresolved;
2986 u32 i, addr, end_addr;
2989 dbg(2, " killing entry %08x-%08x-%08x, blkid %d,%d",
2990 bd->addr, bd->addr + bd->size_nolit, bd->addr + bd->size,
2991 tcache_id, bd - block_tables[tcache_id]);
2992 if (bd->addr == 0 || bd->entry_count == 0) {
2993 dbg(1, " killing dead block!? %08x", bd->addr);
2997 // remove from inval_lookup
2998 addr = bd->addr & ~(INVAL_PAGE_SIZE - 1);
2999 end_addr = bd->addr + bd->size;
3000 for (; addr < end_addr; addr += INVAL_PAGE_SIZE) {
3001 i = (addr & ram_mask) / INVAL_PAGE_SIZE;
3002 rm_from_block_list(&inval_lookup[tcache_id][i], bd);
3006 bl_unresolved = unresolved_links[tcache_id];
3008 // remove from hash table, make incoming links unresolved
3009 // XXX: maybe patch branches w/flush instead?
3010 for (i = 0; i < bd->entry_count; i++) {
3011 rm_from_hashlist(&bd->entryp[i], tcache_id);
3013 // since we never reuse tcache space of dead blocks,
3014 // insert jump to dispatcher for blocks that are linked to this
3015 tcache_ptr = bd->entryp[i].tcache_ptr;
3016 emit_move_r_imm32(SHR_PC, bd->entryp[i].pc);
3018 emith_jump(sh2_drc_dispatcher);
3020 host_instructions_updated(bd->entryp[i].tcache_ptr, tcache_ptr);
3022 for (bl = bd->entryp[i].links; bl != NULL; ) {
3024 bl->next = bl_unresolved;
3031 unresolved_links[tcache_id] = bl_unresolved;
3033 bd->addr = bd->size = bd->size_nolit = 0;
3034 bd->entry_count = 0;
3037 static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask)
3039 struct block_list **blist = NULL, *entry;
3040 u32 from = ~0, to = 0, end_addr, taddr, i;
3041 struct block_desc *block;
3043 blist = &inval_lookup[tcache_id][(a & mask) / INVAL_PAGE_SIZE];
3045 while (entry != NULL) {
3046 block = entry->block;
3047 end_addr = block->addr + block->size;
3048 if (block->addr <= a && a < end_addr) {
3049 // get addr range that includes all removed blocks
3050 if (from > block->addr)
3055 sh2_smc_rm_block_entry(block, tcache_id, mask);
3056 if (a >= block->addr + block->size_nolit)
3057 literal_disabled_frames = 3;
3059 // entry lost, restart search
3063 entry = entry->next;
3069 // update range around a to match latest state
3070 from &= ~(INVAL_PAGE_SIZE - 1);
3071 to |= (INVAL_PAGE_SIZE - 1);
3072 for (taddr = from; taddr < to; taddr += INVAL_PAGE_SIZE) {
3073 i = (taddr & mask) / INVAL_PAGE_SIZE;
3074 entry = inval_lookup[tcache_id][i];
3076 for (; entry != NULL; entry = entry->next) {
3077 block = entry->block;
3079 if (block->addr > a) {
3080 if (to > block->addr)
3084 end_addr = block->addr + block->size;
3085 if (from < end_addr)
3093 u16 *p = drc_ram_blk + ((from & mask) >> shift);
3094 memset(p, 0, (to - from) >> (shift - 1));
3098 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
3100 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3101 sh2_smc_rm_block(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
3104 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
3106 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3107 sh2_smc_rm_block(a, Pico32xMem->drcblk_da[cpuid],
3108 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
3111 int sh2_execute(SH2 *sh2c, int cycles)
3115 sh2c->cycles_timeslice = cycles;
3117 // cycles are kept in SHR_SR unused bits (upper 20)
3118 // bit11 contains T saved for delay slot
3119 // others are usual SH2 flags
3121 sh2c->sr |= cycles << 12;
3122 sh2_drc_entry(sh2c);
3125 ret_cycles = (signed int)sh2c->sr >> 12;
3127 dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
3130 return sh2c->cycles_timeslice - ret_cycles;
3134 void block_stats(void)
3136 int c, b, i, total = 0;
3138 printf("block stats:\n");
3139 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3140 for (i = 0; i < block_counts[b]; i++)
3141 if (block_tables[b][i].addr != 0)
3142 total += block_tables[b][i].refcount;
3144 for (c = 0; c < 10; c++) {
3145 struct block_desc *blk, *maxb = NULL;
3147 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
3148 for (i = 0; i < block_counts[b]; i++) {
3149 blk = &block_tables[b][i];
3150 if (blk->addr != 0 && blk->refcount > max) {
3151 max = blk->refcount;
3158 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
3159 (double)maxb->refcount / total * 100.0);
3163 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3164 for (i = 0; i < block_counts[b]; i++)
3165 block_tables[b][i].refcount = 0;
3168 #define block_stats()
3171 void sh2_drc_flush_all(void)
3179 void sh2_drc_mem_setup(SH2 *sh2)
3181 // fill the convenience pointers
3182 sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3183 sh2->p_da = sh2->data_array;
3184 sh2->p_sdram = Pico32xMem->sdram;
3185 sh2->p_rom = Pico.rom;
3188 void sh2_drc_frame(void)
3190 if (literal_disabled_frames > 0)
3191 literal_disabled_frames--;
3194 int sh2_drc_init(SH2 *sh2)
3198 if (block_tables[0] == NULL)
3200 for (i = 0; i < TCACHE_BUFFERS; i++) {
3201 block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0]));
3202 if (block_tables[i] == NULL)
3204 // max 2 block links (exits) per block
3205 block_link_pool[i] = calloc(block_link_pool_max_counts[i],
3206 sizeof(*block_link_pool[0]));
3207 if (block_link_pool[i] == NULL)
3210 inval_lookup[i] = calloc(ram_sizes[i] / INVAL_PAGE_SIZE,
3211 sizeof(inval_lookup[0]));
3212 if (inval_lookup[i] == NULL)
3215 hash_tables[i] = calloc(hash_table_sizes[i], sizeof(*hash_tables[0]));
3216 if (hash_tables[i] == NULL)
3219 memset(block_counts, 0, sizeof(block_counts));
3220 memset(block_link_pool_counts, 0, sizeof(block_link_pool_counts));
3223 tcache_ptr = tcache;
3224 sh2_generate_utils();
3225 host_instructions_updated(tcache, tcache_ptr);
3227 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
3228 for (i = 1; i < ARRAY_SIZE(tcache_bases); i++)
3229 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
3232 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
3233 tcache_dsm_ptrs[i] = tcache_bases[i];
3235 tcache_dsm_ptrs[0] = tcache;
3239 hash_collisions = 0;
3246 sh2_drc_finish(sh2);
3250 void sh2_drc_finish(SH2 *sh2)
3254 if (block_tables[0] == NULL)
3257 sh2_drc_flush_all();
3259 for (i = 0; i < TCACHE_BUFFERS; i++) {
3261 printf("~~~ tcache %d\n", i);
3262 tcache_dsm_ptrs[i] = tcache_bases[i];
3263 tcache_ptr = tcache_ptrs[i];
3267 if (block_tables[i] != NULL)
3268 free(block_tables[i]);
3269 block_tables[i] = NULL;
3270 if (block_link_pool[i] == NULL)
3271 free(block_link_pool[i]);
3272 block_link_pool[i] = NULL;
3274 if (inval_lookup[i] == NULL)
3275 free(inval_lookup[i]);
3276 inval_lookup[i] = NULL;
3278 if (hash_tables[i] != NULL) {
3279 free(hash_tables[i]);
3280 hash_tables[i] = NULL;
3287 #endif /* DRC_SH2 */
3289 static void *dr_get_pc_base(u32 pc, int is_slave)
3294 if ((pc & ~0x7ff) == 0) {
3296 ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3299 else if ((pc & 0xfffff000) == 0xc0000000) {
3301 ret = sh2s[is_slave].data_array;
3304 else if ((pc & 0xc6000000) == 0x06000000) {
3306 ret = Pico32xMem->sdram;
3309 else if ((pc & 0xc6000000) == 0x02000000) {
3311 if ((pc & 0x3fffff) < Pico.romsize)
3317 return (void *)-1; // NULL is valid value
3319 return (char *)ret - (pc & ~mask);
3322 void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
3323 u32 *end_literals_out)
3327 u32 end_pc, end_literals = 0;
3328 u32 lowest_mova = 0;
3329 struct op_data *opd;
3330 int next_is_delay = 0;
3334 memset(op_flags, 0, BLOCK_INSN_LIMIT);
3336 dr_pc_base = dr_get_pc_base(base_pc, is_slave);
3338 // 1st pass: disassemble
3339 for (i = 0, pc = base_pc; ; i++, pc += 2) {
3340 // we need an ops[] entry after the last one initialized,
3341 // so do it before end_block checks
3343 opd->op = OP_UNHANDLED;
3345 opd->source = opd->dest = 0;
3349 if (next_is_delay) {
3350 op_flags[i] |= OF_DELAY_OP;
3353 else if (end_block || i >= BLOCK_INSN_LIMIT - 2)
3357 switch ((op & 0xf000) >> 12)
3359 /////////////////////////////////////////////
3366 case 0: // STC SR,Rn 0000nnnn00000010
3369 case 1: // STC GBR,Rn 0000nnnn00010010
3372 case 2: // STC VBR,Rn 0000nnnn00100010
3379 opd->source = BITMASK1(tmp);
3380 opd->dest = BITMASK1(GET_Rn());
3383 CHECK_UNHANDLED_BITS(0xd0, undefined);
3384 // BRAF Rm 0000mmmm00100011
3385 // BSRF Rm 0000mmmm00000011
3386 opd->op = OP_BRANCH_RF;
3388 opd->source = BITMASK1(opd->rm);
3389 opd->dest = BITMASK1(SHR_PC);
3391 opd->dest |= BITMASK1(SHR_PR);
3396 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
3397 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
3398 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
3399 opd->source = BITMASK3(GET_Rm(), SHR_R0, GET_Rn());
3402 // MUL.L Rm,Rn 0000nnnnmmmm0111
3403 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3404 opd->dest = BITMASK1(SHR_MACL);
3408 CHECK_UNHANDLED_BITS(0xf00, undefined);
3411 case 0: // CLRT 0000000000001000
3412 opd->op = OP_SETCLRT;
3413 opd->dest = BITMASK1(SHR_T);
3416 case 1: // SETT 0000000000011000
3417 opd->op = OP_SETCLRT;
3418 opd->dest = BITMASK1(SHR_T);
3421 case 2: // CLRMAC 0000000000101000
3422 opd->dest = BITMASK3(SHR_T, SHR_MACL, SHR_MACH);
3431 case 0: // NOP 0000000000001001
3432 CHECK_UNHANDLED_BITS(0xf00, undefined);
3434 case 1: // DIV0U 0000000000011001
3435 CHECK_UNHANDLED_BITS(0xf00, undefined);
3436 opd->dest = BITMASK2(SHR_SR, SHR_T);
3438 case 2: // MOVT Rn 0000nnnn00101001
3439 opd->source = BITMASK1(SHR_T);
3440 opd->dest = BITMASK1(GET_Rn());
3449 case 0: // STS MACH,Rn 0000nnnn00001010
3452 case 1: // STS MACL,Rn 0000nnnn00011010
3455 case 2: // STS PR,Rn 0000nnnn00101010
3462 opd->source = BITMASK1(tmp);
3463 opd->dest = BITMASK1(GET_Rn());
3466 CHECK_UNHANDLED_BITS(0xf00, undefined);
3469 case 0: // RTS 0000000000001011
3470 opd->op = OP_BRANCH_R;
3472 opd->source = BITMASK1(opd->rm);
3473 opd->dest = BITMASK1(SHR_PC);
3478 case 1: // SLEEP 0000000000011011
3482 case 2: // RTE 0000000000101011
3484 opd->source = BITMASK1(SHR_SP);
3485 opd->dest = BITMASK2(SHR_SR, SHR_PC);
3494 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
3495 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
3496 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
3497 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3498 opd->dest = BITMASK1(GET_Rn());
3500 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
3501 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3502 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3510 /////////////////////////////////////////////
3512 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
3513 opd->source = BITMASK1(GET_Rm());
3514 opd->source = BITMASK1(GET_Rn());
3515 opd->imm = (op & 0x0f) * 4;
3518 /////////////////////////////////////////////
3522 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
3523 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
3524 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
3525 opd->source = BITMASK1(GET_Rm());
3526 opd->source = BITMASK1(GET_Rn());
3528 case 0x04: // MOV.B Rm,@-Rn 0010nnnnmmmm0100
3529 case 0x05: // MOV.W Rm,@-Rn 0010nnnnmmmm0101
3530 case 0x06: // MOV.L Rm,@-Rn 0010nnnnmmmm0110
3531 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3532 opd->dest = BITMASK1(GET_Rn());
3534 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
3535 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3536 opd->dest = BITMASK1(SHR_SR);
3538 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
3539 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3540 opd->dest = BITMASK1(SHR_T);
3542 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
3543 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
3544 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
3545 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3546 opd->dest = BITMASK1(GET_Rn());
3548 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
3549 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3550 opd->dest = BITMASK1(SHR_T);
3552 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
3553 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3554 opd->dest = BITMASK1(GET_Rn());
3556 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
3557 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
3558 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3559 opd->dest = BITMASK1(SHR_MACL);
3566 /////////////////////////////////////////////
3570 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
3571 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
3572 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
3573 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
3574 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
3575 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3576 opd->dest = BITMASK1(SHR_T);
3578 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
3579 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_SR);
3580 opd->dest = BITMASK2(GET_Rn(), SHR_SR);
3582 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
3583 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
3584 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3585 opd->dest = BITMASK2(SHR_MACL, SHR_MACH);
3588 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
3589 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
3590 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3591 opd->dest = BITMASK1(GET_Rn());
3593 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
3594 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
3595 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_T);
3596 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3598 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
3599 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
3600 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3601 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3608 /////////////////////////////////////////////
3615 case 0: // SHLL Rn 0100nnnn00000000
3616 case 2: // SHAL Rn 0100nnnn00100000
3617 opd->source = BITMASK1(GET_Rn());
3618 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3620 case 1: // DT Rn 0100nnnn00010000
3621 opd->source = BITMASK1(GET_Rn());
3622 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3631 case 0: // SHLR Rn 0100nnnn00000001
3632 case 2: // SHAR Rn 0100nnnn00100001
3633 opd->source = BITMASK1(GET_Rn());
3634 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3636 case 1: // CMP/PZ Rn 0100nnnn00010001
3637 opd->source = BITMASK1(GET_Rn());
3638 opd->dest = BITMASK1(SHR_T);
3648 case 0x02: // STS.L MACH,@-Rn 0100nnnn00000010
3651 case 0x12: // STS.L MACL,@-Rn 0100nnnn00010010
3654 case 0x22: // STS.L PR,@-Rn 0100nnnn00100010
3657 case 0x03: // STC.L SR,@-Rn 0100nnnn00000011
3661 case 0x13: // STC.L GBR,@-Rn 0100nnnn00010011
3665 case 0x23: // STC.L VBR,@-Rn 0100nnnn00100011
3672 opd->source = BITMASK2(GET_Rn(), tmp);
3673 opd->dest = BITMASK1(GET_Rn());
3679 case 0x04: // ROTL Rn 0100nnnn00000100
3680 case 0x05: // ROTR Rn 0100nnnn00000101
3681 opd->source = BITMASK1(GET_Rn());
3682 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3684 case 0x24: // ROTCL Rn 0100nnnn00100100
3685 case 0x25: // ROTCR Rn 0100nnnn00100101
3686 opd->source = BITMASK2(GET_Rn(), SHR_T);
3687 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3689 case 0x15: // CMP/PL Rn 0100nnnn00010101
3690 opd->source = BITMASK1(GET_Rn());
3691 opd->dest = BITMASK1(SHR_T);
3701 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
3704 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
3707 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
3710 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
3714 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
3718 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
3725 opd->source = BITMASK1(GET_Rn());
3726 opd->dest = BITMASK2(GET_Rn(), tmp);
3733 // SHLL2 Rn 0100nnnn00001000
3734 // SHLR2 Rn 0100nnnn00001001
3737 // SHLL8 Rn 0100nnnn00011000
3738 // SHLR8 Rn 0100nnnn00011001
3741 // SHLL16 Rn 0100nnnn00101000
3742 // SHLR16 Rn 0100nnnn00101001
3747 opd->source = BITMASK1(GET_Rn());
3748 opd->dest = BITMASK1(GET_Rn());
3753 case 0: // LDS Rm,MACH 0100mmmm00001010
3756 case 1: // LDS Rm,MACL 0100mmmm00011010
3759 case 2: // LDS Rm,PR 0100mmmm00101010
3766 opd->source = BITMASK1(GET_Rn());
3767 opd->dest = BITMASK1(tmp);
3772 case 0: // JSR @Rm 0100mmmm00001011
3773 opd->dest = BITMASK1(SHR_PR);
3774 case 2: // JMP @Rm 0100mmmm00101011
3775 opd->op = OP_BRANCH_R;
3777 opd->source = BITMASK1(opd->rm);
3778 opd->dest |= BITMASK1(SHR_PC);
3783 case 1: // TAS.B @Rn 0100nnnn00011011
3784 opd->source = BITMASK1(GET_Rn());
3785 opd->dest = BITMASK1(SHR_T);
3795 case 0: // LDC Rm,SR 0100mmmm00001110
3798 case 1: // LDC Rm,GBR 0100mmmm00011110
3801 case 2: // LDC Rm,VBR 0100mmmm00101110
3808 opd->source = BITMASK1(GET_Rn());
3809 opd->dest = BITMASK1(tmp);
3812 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
3813 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3814 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3822 /////////////////////////////////////////////
3824 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
3825 opd->source = BITMASK1(GET_Rm());
3826 opd->dest = BITMASK1(GET_Rn());
3827 opd->imm = (op & 0x0f) * 4;
3830 /////////////////////////////////////////////
3834 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
3835 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
3836 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
3837 opd->dest = BITMASK1(GET_Rm());
3838 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
3839 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
3840 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
3841 opd->source = BITMASK1(GET_Rm());
3842 opd->dest |= BITMASK1(GET_Rn());
3844 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
3845 opd->source = BITMASK2(GET_Rm(), SHR_T);
3846 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3848 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
3851 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
3852 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
3853 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
3854 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
3855 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
3856 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
3857 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
3858 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
3860 opd->source = BITMASK1(GET_Rm());
3861 opd->dest = BITMASK1(GET_Rn());
3866 /////////////////////////////////////////////
3868 // ADD #imm,Rn 0111nnnniiiiiiii
3869 opd->source = opd->dest = BITMASK1(GET_Rn());
3870 opd->imm = (int)(signed char)op;
3873 /////////////////////////////////////////////
3875 switch (op & 0x0f00)
3877 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
3878 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3879 opd->imm = (op & 0x0f);
3881 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
3882 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3883 opd->imm = (op & 0x0f) * 2;
3885 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
3886 opd->source = BITMASK1(GET_Rm());
3887 opd->dest = BITMASK1(SHR_R0);
3888 opd->imm = (op & 0x0f);
3890 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
3891 opd->source = BITMASK1(GET_Rm());
3892 opd->dest = BITMASK1(SHR_R0);
3893 opd->imm = (op & 0x0f) * 2;
3895 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
3896 opd->source = BITMASK1(SHR_R0);
3897 opd->dest = BITMASK1(SHR_T);
3898 opd->imm = (int)(signed char)op;
3900 case 0x0d00: // BT/S label 10001101dddddddd
3901 case 0x0f00: // BF/S label 10001111dddddddd
3904 case 0x0900: // BT label 10001001dddddddd
3905 case 0x0b00: // BF label 10001011dddddddd
3906 opd->op = (op & 0x0200) ? OP_BRANCH_CF : OP_BRANCH_CT;
3907 opd->source = BITMASK1(SHR_T);
3908 opd->dest = BITMASK1(SHR_PC);
3909 opd->imm = ((signed int)(op << 24) >> 23);
3911 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
3912 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
3919 /////////////////////////////////////////////
3921 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
3922 opd->op = OP_LOAD_POOL;
3924 if (op_flags[i] & OF_DELAY_OP) {
3925 if (ops[i-1].op == OP_BRANCH)
3930 opd->source = BITMASK1(SHR_PC);
3931 opd->dest = BITMASK1(GET_Rn());
3933 opd->imm = tmp + 2 + (op & 0xff) * 2;
3937 /////////////////////////////////////////////
3939 // BSR label 1011dddddddddddd
3940 opd->dest = BITMASK1(SHR_PR);
3942 // BRA label 1010dddddddddddd
3943 opd->op = OP_BRANCH;
3944 opd->dest |= BITMASK1(SHR_PC);
3945 opd->imm = ((signed int)(op << 20) >> 19);
3950 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
3951 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
3954 /////////////////////////////////////////////
3956 switch (op & 0x0f00)
3958 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
3959 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
3960 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
3961 opd->source = BITMASK2(SHR_GBR, SHR_R0);
3962 opd->size = (op & 0x300) >> 8;
3963 opd->imm = (op & 0xff) << opd->size;
3965 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
3966 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
3967 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
3968 opd->source = BITMASK1(SHR_GBR);
3969 opd->dest = BITMASK1(SHR_R0);
3970 opd->size = (op & 0x300) >> 8;
3971 opd->imm = (op & 0xff) << opd->size;
3973 case 0x0300: // TRAPA #imm 11000011iiiiiiii
3974 opd->source = BITMASK2(SHR_PC, SHR_SR);
3975 opd->dest = BITMASK1(SHR_PC);
3976 opd->imm = (op & 0xff) * 4;
3978 end_block = 1; // FIXME
3980 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
3983 if (op_flags[i] & OF_DELAY_OP) {
3984 if (ops[i-1].op == OP_BRANCH)
3989 opd->dest = BITMASK1(SHR_R0);
3991 opd->imm = (tmp + 2 + (op & 0xff) * 4) & ~3;
3992 if (opd->imm >= base_pc) {
3993 if (lowest_mova == 0 || opd->imm < lowest_mova)
3994 lowest_mova = opd->imm;
3998 case 0x0800: // TST #imm,R0 11001000iiiiiiii
3999 opd->source = BITMASK1(SHR_R0);
4000 opd->dest = BITMASK1(SHR_T);
4001 opd->imm = op & 0xff;
4003 case 0x0900: // AND #imm,R0 11001001iiiiiiii
4004 opd->source = opd->dest = BITMASK1(SHR_R0);
4005 opd->imm = op & 0xff;
4007 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
4008 opd->source = opd->dest = BITMASK1(SHR_R0);
4009 opd->imm = op & 0xff;
4011 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
4012 opd->source = opd->dest = BITMASK1(SHR_R0);
4013 opd->imm = op & 0xff;
4015 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
4016 opd->source = BITMASK2(SHR_GBR, SHR_R0);
4017 opd->dest = BITMASK1(SHR_T);
4018 opd->imm = op & 0xff;
4021 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
4022 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
4023 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
4024 opd->source = BITMASK2(SHR_GBR, SHR_R0);
4025 opd->imm = op & 0xff;
4033 /////////////////////////////////////////////
4035 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
4036 opd->op = OP_LOAD_POOL;
4038 if (op_flags[i] & OF_DELAY_OP) {
4039 if (ops[i-1].op == OP_BRANCH)
4044 opd->source = BITMASK1(SHR_PC);
4045 opd->dest = BITMASK1(GET_Rn());
4047 opd->imm = (tmp + 2 + (op & 0xff) * 4) & ~3;
4051 /////////////////////////////////////////////
4053 // MOV #imm,Rn 1110nnnniiiiiiii
4054 opd->dest = BITMASK1(GET_Rn());
4055 opd->imm = (u32)(signed int)(signed char)op;
4060 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
4061 is_slave ? 's' : 'm', op, pc);
4068 // 2nd pass: some analysis
4069 for (i = 0; i < i_end; i++) {
4072 // propagate T (TODO: DIV0U)
4073 if ((opd->op == OP_SETCLRT && !opd->imm) || opd->op == OP_BRANCH_CT)
4074 op_flags[i + 1] |= OF_T_CLEAR;
4075 else if ((opd->op == OP_SETCLRT && opd->imm) || opd->op == OP_BRANCH_CF)
4076 op_flags[i + 1] |= OF_T_SET;
4078 if ((op_flags[i] & OF_BTARGET) || (opd->dest & BITMASK1(SHR_T)))
4079 op_flags[i] &= ~(OF_T_SET | OF_T_CLEAR);
4081 op_flags[i + 1] |= op_flags[i] & (OF_T_SET | OF_T_CLEAR);
4083 if ((opd->op == OP_BRANCH_CT && (op_flags[i] & OF_T_SET))
4084 || (opd->op == OP_BRANCH_CF && (op_flags[i] & OF_T_CLEAR)))
4086 opd->op = OP_BRANCH;
4089 if (op_flags[i + 1] & OF_DELAY_OP) {
4094 else if (opd->op == OP_LOAD_POOL)
4096 if (opd->imm < end_pc + MAX_LITERAL_OFFSET) {
4097 if (end_literals < opd->imm + opd->size * 2)
4098 end_literals = opd->imm + opd->size * 2;
4102 end_pc = base_pc + i_end * 2;
4103 if (end_literals < end_pc)
4104 end_literals = end_pc;
4106 // end_literals is used to decide to inline a literal or not
4107 // XXX: need better detection if this actually is used in write
4108 if (lowest_mova >= base_pc) {
4109 if (lowest_mova < end_literals) {
4110 dbg(1, "mova for %08x, block %08x", lowest_mova, base_pc);
4111 end_literals = end_pc;
4113 if (lowest_mova < end_pc) {
4114 dbg(1, "warning: mova inside of blk for %08x, block %08x",
4115 lowest_mova, base_pc);
4116 end_literals = end_pc;
4120 *end_pc_out = end_pc;
4121 if (end_literals_out != NULL)
4122 *end_literals_out = end_literals;
4125 // vim:shiftwidth=2:ts=2:expandtab