2 * vim:shiftwidth=2:expandtab
9 #include "../../pico/pico_int.h"
12 #include "../drc/cmn.h"
20 #define dbg(l,...) { \
21 if ((l) & DRC_DEBUG) \
22 elprintf(EL_STATUS, ##__VA_ARGS__); \
25 #include "mame/sh2dasm.h"
26 #include <platform/linux/host_dasm.h>
27 static int insns_compiled, hash_collisions, host_insn_count;
36 static u8 *tcache_dsm_ptrs[3];
37 static char sh2dasm_buff[64];
38 #define do_host_disasm(tcid) \
39 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
40 tcache_dsm_ptrs[tcid] = tcache_ptr
42 #define do_host_disasm(x)
46 static void REGPARM(3) *sh2_drc_announce_entry(void *block, SH2 *sh2, u32 sr)
49 dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
50 sh2->pc, block, (signed int)sr >> 12);
56 #define BLOCK_CYCLE_LIMIT 100
57 #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
59 // we have 3 translation cache buffers, split from one drc/cmn buffer.
60 // BIOS shares tcache with data array because it's only used for init
61 // and can be discarded early
62 // XXX: need to tune sizes
63 static const int tcache_sizes[3] = {
64 DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM
65 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
66 DRC_TCACHE_SIZE / 8, // ... slave
69 static u8 *tcache_bases[3];
70 static u8 *tcache_ptrs[3];
72 // ptr for code emiters
73 static u8 *tcache_ptr;
75 // host register tracking
78 HR_CACHED, // 'val' has sh2_reg_e
80 HR_CONST, // 'val' has constant
81 HR_TEMP, // reg used for temp storage
87 u16 stamp; // kind of a timestamp
91 // note: reg_temp[] must have at least the amount of
92 // registers used by handlers in worst case (currently 4)
94 #include "../drc/emit_arm.c"
96 static const int reg_map_g2h[] = {
105 static temp_reg_t reg_temp[] = {
114 #elif defined(__i386__)
115 #include "../drc/emit_x86.c"
117 static const int reg_map_g2h[] = {
126 // ax, cx, dx are usually temporaries by convention
127 static temp_reg_t reg_temp[] = {
135 #error unsupported arch
143 #define T_save 0x00000800
149 typedef struct block_desc_ {
150 u32 addr; // SH2 PC address
151 u32 end_addr; // TODO rm?
152 void *tcache_ptr; // translated block for above PC
153 struct block_desc_ *next; // next block with the same PC hash
159 static const int block_max_counts[3] = {
164 static block_desc *block_tables[3];
165 static int block_counts[3];
168 #define MAX_HASH_ENTRIES 1024
169 #define HASH_MASK (MAX_HASH_ENTRIES - 1)
170 static void **hash_table;
172 #define HASH_FUNC(hash_tab, addr) \
173 ((block_desc **)(hash_tab))[(addr) & HASH_MASK]
175 static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
176 static void (*sh2_drc_dispatcher)(void);
177 static void (*sh2_drc_exit)(void);
178 static void (*sh2_drc_test_irq)(void);
179 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
180 static void REGPARM(2) (*sh2_drc_write8_slot)(u32 a, u32 d);
181 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
182 static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d);
184 extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode);
186 static void flush_tcache(int tcid)
188 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
189 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
190 block_counts[tcid], block_max_counts[tcid]);
192 block_counts[tcid] = 0;
193 tcache_ptrs[tcid] = tcache_bases[tcid];
194 if (tcid == 0) { // ROM, RAM
195 memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES);
196 memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram));
199 memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0]));
201 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
205 static void *dr_find_block(block_desc *tab, u32 addr)
207 for (tab = tab->next; tab != NULL; tab = tab->next)
208 if (tab->addr == addr)
212 return tab->tcache_ptr;
214 printf("block miss for %08x\n", addr);
218 static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id)
220 int *bcount = &block_counts[tcache_id];
223 if (*bcount >= block_max_counts[tcache_id])
226 bd = &block_tables[tcache_id][*bcount];
228 bd->tcache_ptr = tcache_ptr;
232 if ((addr & 0xc6000000) == 0x02000000) { // ROM
233 bd->next = HASH_FUNC(hash_table, addr);
234 HASH_FUNC(hash_table, addr) = bd;
236 if (bd->next != NULL) {
237 printf(" hash collision with %08x\n", bd->next->addr);
246 int find_in_array(u32 *array, size_t size, u32 what)
249 for (i = 0; i < size; i++)
250 if (what == array[i])
256 // ---------------------------------------------------------------
259 static u16 rcache_counter;
261 static temp_reg_t *rcache_evict(void)
263 // evict reg with oldest stamp
265 u16 min_stamp = (u16)-1;
267 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
268 if (reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY)
269 if (reg_temp[i].stamp <= min_stamp) {
270 min_stamp = reg_temp[i].stamp;
276 printf("no registers to evict, aborting\n");
281 if (reg_temp[i].type == HR_CACHED_DIRTY) {
283 emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4);
295 // note: must not be called when doing conditional code
296 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
301 // maybe already statically mapped?
308 // maybe already cached?
309 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
310 if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) &&
311 reg_temp[i].val == r)
313 reg_temp[i].stamp = rcache_counter;
314 if (mode != RC_GR_READ)
315 reg_temp[i].type = HR_CACHED_DIRTY;
316 return reg_temp[i].reg;
321 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
322 if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) {
331 if (mode != RC_GR_WRITE)
332 emith_ctx_read(tr->reg, r * 4);
334 tr->type = mode != RC_GR_READ ? HR_CACHED_DIRTY : HR_CACHED;
336 tr->stamp = rcache_counter;
340 static int rcache_get_tmp(void)
345 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
346 if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) {
358 static int rcache_get_arg_id(int arg)
361 host_arg2reg(r, arg);
363 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
364 if (reg_temp[i].reg == r)
367 if (i == ARRAY_SIZE(reg_temp))
368 // let's just say it's untracked arg reg
371 if (reg_temp[i].type == HR_CACHED_DIRTY) {
373 emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4);
375 else if (reg_temp[i].type == HR_TEMP) {
376 printf("arg %d reg %d already used, aborting\n", arg, r);
383 // get a reg to be used as function arg
384 // it's assumed that regs are cleaned before call
385 static int rcache_get_tmp_arg(int arg)
387 int id = rcache_get_arg_id(arg);
388 reg_temp[id].type = HR_TEMP;
390 return reg_temp[id].reg;
393 // same but caches reg. RC_GR_READ only.
394 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
396 int i, srcr, dstr, dstid;
398 dstid = rcache_get_arg_id(arg);
399 dstr = reg_temp[dstid].reg;
401 // maybe already statically mapped?
402 srcr = reg_map_g2h[r];
406 // maybe already cached?
407 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
408 if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) &&
409 reg_temp[i].val == r)
411 srcr = reg_temp[i].reg;
418 emith_ctx_read(srcr, r * 4);
422 emith_move_r_r(dstr, srcr);
424 reg_temp[dstid].stamp = ++rcache_counter;
425 reg_temp[dstid].type = HR_CACHED;
426 reg_temp[dstid].val = r;
430 static void rcache_free_tmp(int hr)
433 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
434 if (reg_temp[i].reg == hr)
437 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
438 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
442 reg_temp[i].type = HR_FREE;
445 static void rcache_clean(void)
448 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
449 if (reg_temp[i].type == HR_CACHED_DIRTY) {
451 emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4);
452 reg_temp[i].type = HR_CACHED;
456 static void rcache_invalidate(void)
459 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
460 reg_temp[i].type = HR_FREE;
464 static void rcache_flush(void)
470 // ---------------------------------------------------------------
472 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
474 // TODO: propagate this constant
475 int hr = rcache_get_reg(dst, RC_GR_WRITE);
476 emith_move_r_imm(hr, imm);
479 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
481 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
482 int hr_s = rcache_get_reg(src, RC_GR_READ);
484 emith_move_r_r(hr_d, hr_s);
487 // T must be clear, and comparison done just before this
488 static void emit_or_t_if_eq(int srr)
490 EMITH_SJMP_START(DCOND_NE);
491 emith_or_r_imm_c(DCOND_EQ, srr, T);
492 EMITH_SJMP_END(DCOND_NE);
495 // arguments must be ready
496 // reg cache must be clean before call
497 static int emit_memhandler_read(int size)
500 host_arg2reg(arg0, 0);
502 // must writeback cycles for poll detection stuff
503 if (reg_map_g2h[SHR_SR] != -1)
504 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
505 arg1 = rcache_get_tmp_arg(1);
506 emith_move_r_r(arg1, CONTEXT_REG);
509 if (Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
510 int tmp = rcache_get_tmp();
511 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
512 emith_cmp_r_imm(tmp, 0x02000000);
515 EMITH_SJMP3_START(DCOND_NE);
516 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
517 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
518 EMITH_SJMP3_MID(DCOND_NE);
519 emith_call_cond(DCOND_NE, p32x_sh2_read8);
523 EMITH_SJMP3_START(DCOND_NE);
524 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
525 EMITH_SJMP3_MID(DCOND_NE);
526 emith_call_cond(DCOND_NE, p32x_sh2_read16);
530 EMITH_SJMP3_START(DCOND_NE);
531 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
532 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
533 EMITH_SJMP3_MID(DCOND_NE);
534 emith_call_cond(DCOND_NE, p32x_sh2_read32);
544 emith_call(p32x_sh2_read8);
547 emith_call(p32x_sh2_read16);
550 emith_call(p32x_sh2_read32);
555 // assuming arg0 and retval reg matches
556 return rcache_get_tmp_arg(0);
559 static void emit_memhandler_write(int size, u32 pc, int delay)
562 host_arg2reg(ctxr, 2);
565 // XXX: consider inlining sh2_drc_write8
567 emith_call(sh2_drc_write8_slot);
569 emit_move_r_imm32(SHR_PC, pc);
571 emith_call(sh2_drc_write8);
576 emith_call(sh2_drc_write16_slot);
578 emit_move_r_imm32(SHR_PC, pc);
580 emith_call(sh2_drc_write16);
584 emith_move_r_r(ctxr, CONTEXT_REG);
585 emith_call(p32x_sh2_write32);
592 static int emit_indirect_indexed_read(int rx, int ry, int size)
596 a0 = rcache_get_reg_arg(0, rx);
597 t = rcache_get_reg(ry, RC_GR_READ);
598 emith_add_r_r(a0, t);
599 return emit_memhandler_read(size);
603 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
608 rcache_get_reg_arg(0, rn);
609 tmp = emit_memhandler_read(size);
610 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
611 rcache_free_tmp(tmp);
612 tmp = rcache_get_reg(rn, RC_GR_RMW);
613 emith_add_r_imm(tmp, 1 << size);
616 rcache_get_reg_arg(0, rm);
617 *rmr = emit_memhandler_read(size);
618 *rnr = rcache_get_tmp();
619 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
620 tmp = rcache_get_reg(rm, RC_GR_RMW);
621 emith_add_r_imm(tmp, 1 << size);
624 static void emit_do_static_regs(int is_write, int tmpr)
628 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
633 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
634 if (reg_map_g2h[i + 1] != r + 1)
640 // i, r point to last item
642 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
644 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
647 emith_ctx_write(r, i * 4);
649 emith_ctx_read(r, i * 4);
654 static void emit_block_entry(void)
656 int arg0, arg1, arg2;
658 host_arg2reg(arg0, 0);
659 host_arg2reg(arg1, 1);
660 host_arg2reg(arg2, 2);
663 emith_move_r_r(arg1, CONTEXT_REG);
664 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
665 emith_call(sh2_drc_announce_entry);
668 emith_tst_r_r(arg0, arg0);
669 EMITH_SJMP_START(DCOND_EQ);
670 emith_jump_reg_c(DCOND_NE, arg0);
671 EMITH_SJMP_END(DCOND_EQ);
674 static void REGPARM(3) *lookup_block(u32 pc, int is_slave, int *tcache_id)
676 block_desc *bd = NULL;
680 // we have full block id tables for data_array and RAM
681 // BIOS goes to data_array table too
682 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0) {
683 int blkid = Pico32xMem->drcblk_da[is_slave][(pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
684 *tcache_id = 1 + is_slave;
686 bd = &block_tables[*tcache_id][blkid >> 1];
687 block = bd->tcache_ptr;
691 else if ((pc & 0xc6000000) == 0x06000000) {
692 int blkid = Pico32xMem->drcblk_ram[(pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
694 bd = &block_tables[0][blkid >> 1];
695 block = bd->tcache_ptr;
699 else if ((pc & 0xc6000000) == 0x02000000) {
700 bd = HASH_FUNC(hash_table, pc);
704 block = bd->tcache_ptr;
706 block = dr_find_block(bd, pc);
720 #define DELAY_SAVE_T(sr) { \
721 emith_bic_r_imm(sr, T_save); \
722 emith_tst_r_imm(sr, T); \
723 EMITH_SJMP_START(DCOND_EQ); \
724 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
725 EMITH_SJMP_END(DCOND_EQ); \
726 drcf.use_saved_t = 1; \
729 #define FLUSH_CYCLES(sr) \
731 emith_sub_r_imm(sr, cycles << 12); \
735 #define CHECK_UNHANDLED_BITS(mask) { \
736 if ((op & (mask)) != 0) \
743 #define GET_Rm GET_Fx
748 #define CHECK_FX_LT(n) \
752 #define MAX_LOCAL_BRANCHES 16
754 // op_flags: data from 1st pass
755 #define OP_FLAGS(pc) op_flags[((pc) - base_pc) / 2]
756 #define OF_DELAY_OP (1 << 0)
758 static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
760 // XXX: maybe use structs instead?
761 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
762 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
763 int branch_target_count = 0;
764 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
765 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
766 int branch_patch_count = 0;
767 int branch_patch_cond = -1;
768 u8 op_flags[BLOCK_CYCLE_LIMIT + 1];
772 u32 use_saved_t:1; // delayed op modifies T
776 block_desc *this_block;
777 u32 pc, base_pc, end_pc; // PC of current, first, last insn
788 if ((tmp != 0 && tmp != 1 && tmp != 6) || base_pc == 0) {
789 printf("invalid PC, aborting: %08x\n", base_pc);
790 // FIXME: be less destructive
794 tcache_ptr = tcache_ptrs[tcache_id];
795 this_block = dr_add_block(base_pc, tcache_id, &blkid_main);
797 // predict tcache overflow
798 tmp = tcache_ptr - tcache_bases[tcache_id];
799 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL)
802 block_entry = tcache_ptr;
803 dbg(1, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
804 tcache_id, blkid_main, base_pc, block_entry);
806 // 1st pass: scan forward for local branches
807 memset(op_flags, 0, sizeof(op_flags));
808 for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT; cycles++, pc += 2) {
809 op = p32x_sh2_read16(pc, sh2);
810 if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR
812 OP_FLAGS(pc) |= OF_DELAY_OP;
815 if ((op & 0xf000) == 0) {
817 if (op == 0x23 || op == 0x03 || op == 0x0b) { // BRAF, BSRF, RTS
819 OP_FLAGS(pc) |= OF_DELAY_OP;
824 if ((op & 0xf0df) == 0x400b) { // JMP, JSR
826 OP_FLAGS(pc) |= OF_DELAY_OP;
829 if ((op & 0xf900) == 0x8900) { // BT(S), BF(S)
830 signed int offs = ((signed int)(op << 24) >> 23);
832 OP_FLAGS(pc + 2) |= OF_DELAY_OP;
833 branch_target_pc[branch_target_count++] = pc + offs + 4;
834 if (branch_target_count == MAX_LOCAL_BRANCHES) {
835 printf("warning: branch target overflow\n");
836 // will only spawn additional blocks
844 // clean branch_targets that are not really local,
845 // and that land on delay slots
846 for (i = 0, tmp = 0; i < branch_target_count; i++) {
847 pc = branch_target_pc[i];
848 if (base_pc <= pc && pc <= end_pc && !(OP_FLAGS(pc) & OF_DELAY_OP))
849 branch_target_pc[tmp++] = branch_target_pc[i];
851 branch_target_count = tmp;
852 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
854 // -------------------------------------------------
855 // 2nd pass: actual compilation
857 for (cycles = 0; pc <= end_pc || drcf.delayed_op; )
861 if (drcf.delayed_op > 0)
864 i = find_in_array(branch_target_pc, branch_target_count, pc);
869 /* make "subblock" - just a mid-block entry */
870 block_desc *subblock;
874 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
877 do_host_disasm(tcache_id);
879 subblock = dr_add_block(pc, tcache_id, &blkid);
880 if (subblock == NULL)
882 subblock->end_addr = pc;
884 if (tcache_id != 0) { // data array, BIOS
885 drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
886 drcblk += (pc & 0x00fff) >> SH2_DRCBLK_DA_SHIFT;
887 *drcblk = (blkid << 1) | 1;
888 } else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
889 drcblk = Pico32xMem->drcblk_ram;
890 drcblk += (pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
891 *drcblk = (blkid << 1) | 1;
894 dbg(1, "=== %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
895 tcache_id, blkid, pc, tcache_ptr);
897 branch_target_ptr[i] = tcache_ptr;
900 emit_move_r_imm32(SHR_PC, pc);
904 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
905 emith_cmp_r_imm(sr, 0);
906 emith_jump_cond(DCOND_LE, sh2_drc_exit);
909 op = p32x_sh2_read16(pc, sh2);
914 DasmSH2(sh2dasm_buff, pc, op);
915 printf("%08x %04x %s\n", pc, op, sh2dasm_buff);
922 switch ((op >> 12) & 0x0f)
924 /////////////////////////////////////////////
929 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
932 case 0: // STC SR,Rn 0000nnnn00000010
935 case 1: // STC GBR,Rn 0000nnnn00010010
938 case 2: // STC VBR,Rn 0000nnnn00100010
944 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
945 emith_move_r_r(tmp, tmp3);
947 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
950 CHECK_UNHANDLED_BITS(0xd0);
951 // BRAF Rm 0000mmmm00100011
952 // BSRF Rm 0000mmmm00000011
954 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
955 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
956 emith_move_r_r(tmp, tmp2);
958 emith_add_r_imm(tmp, pc + 2);
960 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
961 emith_move_r_imm(tmp3, pc + 2);
962 emith_add_r_r(tmp, tmp3);
966 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
967 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
968 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
970 tmp = rcache_get_reg_arg(1, GET_Rm());
971 tmp2 = rcache_get_reg_arg(0, SHR_R0);
972 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
973 emith_add_r_r(tmp2, tmp3);
974 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
977 // MUL.L Rm,Rn 0000nnnnmmmm0111
978 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
979 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
980 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
981 emith_mul(tmp3, tmp2, tmp);
985 CHECK_UNHANDLED_BITS(0xf00);
988 case 0: // CLRT 0000000000001000
989 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
992 emith_bic_r_imm(sr, T);
994 case 1: // SETT 0000000000011000
995 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
998 emith_or_r_imm(sr, T);
1000 case 2: // CLRMAC 0000000000101000
1001 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1002 emith_move_r_imm(tmp, 0);
1003 tmp = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1004 emith_move_r_imm(tmp, 0);
1013 case 0: // NOP 0000000000001001
1014 CHECK_UNHANDLED_BITS(0xf00);
1016 case 1: // DIV0U 0000000000011001
1017 CHECK_UNHANDLED_BITS(0xf00);
1018 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1019 if (drcf.delayed_op)
1021 emith_bic_r_imm(sr, M|Q|T);
1023 case 2: // MOVT Rn 0000nnnn00101001
1024 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1025 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1026 emith_clear_msb(tmp2, sr, 31);
1033 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1036 case 0: // STS MACH,Rn 0000nnnn00001010
1039 case 1: // STS MACL,Rn 0000nnnn00011010
1042 case 2: // STS PR,Rn 0000nnnn00101010
1048 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1049 emith_move_r_r(tmp, tmp2);
1052 CHECK_UNHANDLED_BITS(0xf00);
1055 case 0: // RTS 0000000000001011
1057 emit_move_r_r(SHR_PC, SHR_PR);
1060 case 1: // SLEEP 0000000000011011
1061 emit_move_r_imm32(SHR_PC, pc - 2);
1062 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
1063 emith_clear_msb(tmp, tmp, 20); // clear cycles
1066 case 2: // RTE 0000000000101011
1070 rcache_get_reg_arg(0, SHR_SP);
1071 tmp = emit_memhandler_read(2);
1072 tmp2 = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1073 emith_move_r_r(tmp2, tmp);
1074 rcache_free_tmp(tmp);
1077 tmp = rcache_get_reg_arg(0, SHR_SP);
1078 emith_add_r_imm(tmp, 4);
1079 tmp = emit_memhandler_read(2);
1080 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1081 emith_write_sr(sr, tmp);
1082 rcache_free_tmp(tmp);
1083 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1084 emith_add_r_imm(tmp, 4*2);
1092 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1093 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1094 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1095 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1096 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1097 if ((op & 3) != 2) {
1098 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1100 emith_move_r_r(tmp2, tmp);
1101 rcache_free_tmp(tmp);
1103 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1104 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1105 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1106 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1107 /* MS 16 MAC bits unused if saturated */
1108 emith_tst_r_imm(sr, S);
1109 EMITH_SJMP_START(DCOND_EQ);
1110 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1111 EMITH_SJMP_END(DCOND_EQ);
1112 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1113 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1114 rcache_free_tmp(tmp2);
1115 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1116 emith_tst_r_imm(sr, S);
1118 EMITH_JMP_START(DCOND_EQ);
1119 emith_asr(tmp, tmp4, 15);
1120 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1121 EMITH_SJMP_START(DCOND_GE);
1122 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1123 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1124 EMITH_SJMP_END(DCOND_GE);
1125 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1126 EMITH_SJMP_START(DCOND_LE);
1127 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1128 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1129 EMITH_SJMP_END(DCOND_LE);
1130 EMITH_JMP_END(DCOND_EQ);
1132 rcache_free_tmp(tmp);
1138 /////////////////////////////////////////////
1140 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1142 tmp = rcache_get_reg_arg(0, GET_Rn());
1143 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1144 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1145 emit_memhandler_write(2, pc, drcf.delayed_op);
1151 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1152 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1153 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1155 rcache_get_reg_arg(0, GET_Rn());
1156 rcache_get_reg_arg(1, GET_Rm());
1157 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1159 case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
1160 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
1161 case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110
1162 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1163 emith_sub_r_imm(tmp, (1 << (op & 3)));
1165 rcache_get_reg_arg(0, GET_Rn());
1166 rcache_get_reg_arg(1, GET_Rm());
1167 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1169 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1170 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1171 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1172 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1173 if (drcf.delayed_op)
1175 emith_bic_r_imm(sr, M|Q|T);
1176 emith_tst_r_imm(tmp2, (1<<31));
1177 EMITH_SJMP_START(DCOND_EQ);
1178 emith_or_r_imm_c(DCOND_NE, sr, Q);
1179 EMITH_SJMP_END(DCOND_EQ);
1180 emith_tst_r_imm(tmp3, (1<<31));
1181 EMITH_SJMP_START(DCOND_EQ);
1182 emith_or_r_imm_c(DCOND_NE, sr, M);
1183 EMITH_SJMP_END(DCOND_EQ);
1184 emith_teq_r_r(tmp2, tmp3);
1185 EMITH_SJMP_START(DCOND_PL);
1186 emith_or_r_imm_c(DCOND_MI, sr, T);
1187 EMITH_SJMP_END(DCOND_PL);
1189 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1190 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1191 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1192 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1193 if (drcf.delayed_op)
1195 emith_bic_r_imm(sr, T);
1196 emith_tst_r_r(tmp2, tmp3);
1197 emit_or_t_if_eq(sr);
1199 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1200 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1201 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1202 emith_and_r_r(tmp, tmp2);
1204 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1205 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1206 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1207 emith_eor_r_r(tmp, tmp2);
1209 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1210 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1211 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1212 emith_or_r_r(tmp, tmp2);
1214 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1215 tmp = rcache_get_tmp();
1216 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1217 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1218 emith_eor_r_r_r(tmp, tmp2, tmp3);
1219 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1220 if (drcf.delayed_op)
1222 emith_bic_r_imm(sr, T);
1223 emith_tst_r_imm(tmp, 0x000000ff);
1224 emit_or_t_if_eq(tmp);
1225 emith_tst_r_imm(tmp, 0x0000ff00);
1226 emit_or_t_if_eq(tmp);
1227 emith_tst_r_imm(tmp, 0x00ff0000);
1228 emit_or_t_if_eq(tmp);
1229 emith_tst_r_imm(tmp, 0xff000000);
1230 emit_or_t_if_eq(tmp);
1231 rcache_free_tmp(tmp);
1233 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1234 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1235 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1236 emith_lsr(tmp, tmp, 16);
1237 emith_or_r_r_lsl(tmp, tmp2, 16);
1239 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1240 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1241 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1242 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1244 emith_sext(tmp, tmp2, 16);
1246 emith_clear_msb(tmp, tmp2, 16);
1247 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1248 tmp2 = rcache_get_tmp();
1250 emith_sext(tmp2, tmp3, 16);
1252 emith_clear_msb(tmp2, tmp3, 16);
1253 emith_mul(tmp, tmp, tmp2);
1254 rcache_free_tmp(tmp2);
1255 // FIXME: causes timing issues in Doom?
1261 /////////////////////////////////////////////
1265 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
1266 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
1267 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
1268 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
1269 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
1270 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1271 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1272 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1273 if (drcf.delayed_op)
1275 emith_bic_r_imm(sr, T);
1276 emith_cmp_r_r(tmp2, tmp3);
1279 case 0x00: // CMP/EQ
1280 emit_or_t_if_eq(sr);
1282 case 0x02: // CMP/HS
1283 EMITH_SJMP_START(DCOND_LO);
1284 emith_or_r_imm_c(DCOND_HS, sr, T);
1285 EMITH_SJMP_END(DCOND_LO);
1287 case 0x03: // CMP/GE
1288 EMITH_SJMP_START(DCOND_LT);
1289 emith_or_r_imm_c(DCOND_GE, sr, T);
1290 EMITH_SJMP_END(DCOND_LT);
1292 case 0x06: // CMP/HI
1293 EMITH_SJMP_START(DCOND_LS);
1294 emith_or_r_imm_c(DCOND_HI, sr, T);
1295 EMITH_SJMP_END(DCOND_LS);
1297 case 0x07: // CMP/GT
1298 EMITH_SJMP_START(DCOND_LE);
1299 emith_or_r_imm_c(DCOND_GT, sr, T);
1300 EMITH_SJMP_END(DCOND_LE);
1304 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
1305 // Q1 = carry(Rn = (Rn << 1) | T)
1307 // Q2 = carry(Rn += Rm)
1309 // Q2 = carry(Rn -= Rm)
1311 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
1312 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1313 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1314 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1315 if (drcf.delayed_op)
1317 emith_tpop_carry(sr, 0);
1318 emith_adcf_r_r(tmp2, tmp2);
1319 emith_tpush_carry(sr, 0); // keep Q1 in T for now
1320 tmp4 = rcache_get_tmp();
1321 emith_and_r_r_imm(tmp4, sr, M);
1322 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
1323 rcache_free_tmp(tmp4);
1324 // add or sub, invert T if carry to get Q1 ^ Q2
1325 // in: (Q ^ M) passed in Q, Q1 in T
1326 emith_sh2_div1_step(tmp2, tmp3, sr);
1327 emith_bic_r_imm(sr, Q);
1328 emith_tst_r_imm(sr, M);
1329 EMITH_SJMP_START(DCOND_EQ);
1330 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
1331 EMITH_SJMP_END(DCOND_EQ);
1332 emith_tst_r_imm(sr, T);
1333 EMITH_SJMP_START(DCOND_EQ);
1334 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
1335 EMITH_SJMP_END(DCOND_EQ);
1336 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
1338 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
1339 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1340 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1341 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1342 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1343 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
1345 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
1346 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
1347 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1348 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1350 emith_add_r_r(tmp, tmp2);
1352 emith_sub_r_r(tmp, tmp2);
1354 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
1355 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
1356 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1357 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1358 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1359 if (drcf.delayed_op)
1361 if (op & 4) { // adc
1362 emith_tpop_carry(sr, 0);
1363 emith_adcf_r_r(tmp, tmp2);
1364 emith_tpush_carry(sr, 0);
1366 emith_tpop_carry(sr, 1);
1367 emith_sbcf_r_r(tmp, tmp2);
1368 emith_tpush_carry(sr, 1);
1371 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
1372 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
1373 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1374 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1375 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1376 if (drcf.delayed_op)
1378 emith_bic_r_imm(sr, T);
1380 emith_addf_r_r(tmp, tmp2);
1382 emith_subf_r_r(tmp, tmp2);
1383 EMITH_SJMP_START(DCOND_VC);
1384 emith_or_r_imm_c(DCOND_VS, sr, T);
1385 EMITH_SJMP_END(DCOND_VC);
1387 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
1388 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1389 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1390 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1391 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1392 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
1397 /////////////////////////////////////////////
1404 case 0: // SHLL Rn 0100nnnn00000000
1405 case 2: // SHAL Rn 0100nnnn00100000
1406 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1407 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1408 if (drcf.delayed_op)
1410 emith_tpop_carry(sr, 0); // dummy
1411 emith_lslf(tmp, tmp, 1);
1412 emith_tpush_carry(sr, 0);
1414 case 1: // DT Rn 0100nnnn00010000
1415 if (p32x_sh2_read16(pc, sh2) == 0x8bfd) { // BF #-2
1416 emith_sh2_dtbf_loop();
1419 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1420 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1421 if (drcf.delayed_op)
1423 emith_bic_r_imm(sr, T);
1424 emith_subf_r_imm(tmp, 1);
1425 emit_or_t_if_eq(sr);
1432 case 0: // SHLR Rn 0100nnnn00000001
1433 case 2: // SHAR Rn 0100nnnn00100001
1434 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1435 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1436 if (drcf.delayed_op)
1438 emith_tpop_carry(sr, 0); // dummy
1440 emith_asrf(tmp, tmp, 1);
1442 emith_lsrf(tmp, tmp, 1);
1443 emith_tpush_carry(sr, 0);
1445 case 1: // CMP/PZ Rn 0100nnnn00010001
1446 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1447 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1448 if (drcf.delayed_op)
1450 emith_bic_r_imm(sr, T);
1451 emith_cmp_r_imm(tmp, 0);
1452 EMITH_SJMP_START(DCOND_LT);
1453 emith_or_r_imm_c(DCOND_GE, sr, T);
1454 EMITH_SJMP_END(DCOND_LT);
1462 case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
1465 case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
1468 case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
1471 case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
1474 case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
1477 case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
1483 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1484 emith_sub_r_imm(tmp2, 4);
1486 rcache_get_reg_arg(0, GET_Rn());
1487 tmp3 = rcache_get_reg_arg(1, tmp);
1489 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
1490 emit_memhandler_write(2, pc, drcf.delayed_op);
1496 case 0x04: // ROTL Rn 0100nnnn00000100
1497 case 0x05: // ROTR Rn 0100nnnn00000101
1498 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1499 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1500 if (drcf.delayed_op)
1502 emith_tpop_carry(sr, 0); // dummy
1504 emith_rorf(tmp, tmp, 1);
1506 emith_rolf(tmp, tmp, 1);
1507 emith_tpush_carry(sr, 0);
1509 case 0x24: // ROTCL Rn 0100nnnn00100100
1510 case 0x25: // ROTCR Rn 0100nnnn00100101
1511 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1512 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1513 if (drcf.delayed_op)
1515 emith_tpop_carry(sr, 0);
1520 emith_tpush_carry(sr, 0);
1522 case 0x15: // CMP/PL Rn 0100nnnn00010101
1523 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1524 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1525 if (drcf.delayed_op)
1527 emith_bic_r_imm(sr, T);
1528 emith_cmp_r_imm(tmp, 0);
1529 EMITH_SJMP_START(DCOND_LE);
1530 emith_or_r_imm_c(DCOND_GT, sr, T);
1531 EMITH_SJMP_END(DCOND_LE);
1539 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
1542 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
1545 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
1548 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
1551 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
1554 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
1561 rcache_get_reg_arg(0, GET_Rn());
1562 tmp2 = emit_memhandler_read(2);
1563 if (tmp == SHR_SR) {
1564 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1565 if (drcf.delayed_op)
1567 emith_write_sr(sr, tmp2);
1570 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
1571 emith_move_r_r(tmp, tmp2);
1573 rcache_free_tmp(tmp2);
1574 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1575 emith_add_r_imm(tmp, 4);
1582 // SHLL2 Rn 0100nnnn00001000
1583 // SHLR2 Rn 0100nnnn00001001
1587 // SHLL8 Rn 0100nnnn00011000
1588 // SHLR8 Rn 0100nnnn00011001
1592 // SHLL16 Rn 0100nnnn00101000
1593 // SHLR16 Rn 0100nnnn00101001
1599 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1601 emith_lsr(tmp2, tmp2, tmp);
1603 emith_lsl(tmp2, tmp2, tmp);
1608 case 0: // LDS Rm,MACH 0100mmmm00001010
1611 case 1: // LDS Rm,MACL 0100mmmm00011010
1614 case 2: // LDS Rm,PR 0100mmmm00101010
1620 emit_move_r_r(tmp2, GET_Rn());
1625 case 0: // JSR @Rm 0100mmmm00001011
1626 case 2: // JMP @Rm 0100mmmm00101011
1629 emit_move_r_imm32(SHR_PR, pc + 2);
1630 emit_move_r_r(SHR_PC, (op >> 8) & 0x0f);
1633 case 1: // TAS.B @Rn 0100nnnn00011011
1634 // XXX: is TAS working on 32X?
1636 rcache_get_reg_arg(0, GET_Rn());
1637 tmp = emit_memhandler_read(0);
1638 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1639 if (drcf.delayed_op)
1641 emith_bic_r_imm(sr, T);
1642 emith_cmp_r_imm(tmp, 0);
1643 emit_or_t_if_eq(sr);
1645 emith_or_r_imm(tmp, 0x80);
1646 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
1647 emith_move_r_r(tmp2, tmp);
1648 rcache_free_tmp(tmp);
1649 rcache_get_reg_arg(0, GET_Rn());
1650 emit_memhandler_write(0, pc, drcf.delayed_op);
1658 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1661 case 0: // LDC Rm,SR 0100mmmm00001110
1664 case 1: // LDC Rm,GBR 0100mmmm00011110
1667 case 2: // LDC Rm,VBR 0100mmmm00101110
1673 if (tmp2 == SHR_SR) {
1674 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1675 if (drcf.delayed_op)
1677 emith_write_sr(sr, tmp);
1680 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
1681 emith_move_r_r(tmp2, tmp);
1685 // MAC @Rm+,@Rn+ 0100nnnnmmmm1111
1686 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
1687 emith_sext(tmp, tmp, 16);
1688 emith_sext(tmp2, tmp2, 16);
1689 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
1690 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1691 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1692 rcache_free_tmp(tmp2);
1693 // XXX: MACH should be untouched when S is set?
1694 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1695 emith_tst_r_imm(sr, S);
1696 EMITH_JMP_START(DCOND_EQ);
1698 emith_asr(tmp, tmp3, 31);
1699 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
1700 EMITH_JMP_START(DCOND_EQ);
1701 emith_move_r_imm(tmp3, 0x80000000);
1702 emith_tst_r_r(tmp4, tmp4);
1703 EMITH_SJMP_START(DCOND_MI);
1704 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
1705 EMITH_SJMP_END(DCOND_MI);
1706 EMITH_JMP_END(DCOND_EQ);
1708 EMITH_JMP_END(DCOND_EQ);
1709 rcache_free_tmp(tmp);
1715 /////////////////////////////////////////////
1717 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
1719 tmp = rcache_get_reg_arg(0, GET_Rm());
1720 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1721 tmp = emit_memhandler_read(2);
1722 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1723 emith_move_r_r(tmp2, tmp);
1724 rcache_free_tmp(tmp);
1727 /////////////////////////////////////////////
1731 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
1732 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
1733 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
1734 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
1735 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
1736 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
1738 rcache_get_reg_arg(0, GET_Rm());
1739 tmp = emit_memhandler_read(op & 3);
1740 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1741 if ((op & 3) != 2) {
1742 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1744 emith_move_r_r(tmp2, tmp);
1745 rcache_free_tmp(tmp);
1746 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
1747 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
1748 emith_add_r_imm(tmp, (1 << (op & 3)));
1753 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
1754 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1757 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
1758 emith_move_r_r(tmp2, tmp);
1760 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
1761 emith_mvn_r_r(tmp2, tmp);
1763 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
1766 tmp3 = rcache_get_tmp();
1767 tmp4 = rcache_get_tmp();
1768 emith_lsr(tmp3, tmp, 16);
1769 emith_or_r_r_lsl(tmp3, tmp, 24);
1770 emith_and_r_r_imm(tmp4, tmp, 0xff00);
1771 emith_or_r_r_lsl(tmp3, tmp4, 8);
1772 emith_rol(tmp2, tmp3, 16);
1773 rcache_free_tmp(tmp4);
1775 rcache_free_tmp(tmp3);
1777 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
1778 emith_rol(tmp2, tmp, 16);
1780 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
1781 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1782 if (drcf.delayed_op)
1784 emith_tpop_carry(sr, 1);
1785 emith_negcf_r_r(tmp2, tmp);
1786 emith_tpush_carry(sr, 1);
1788 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
1789 emith_neg_r_r(tmp2, tmp);
1791 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
1792 emith_clear_msb(tmp2, tmp, 24);
1794 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
1795 emith_clear_msb(tmp2, tmp, 16);
1797 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
1798 emith_sext(tmp2, tmp, 8);
1800 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
1801 emith_sext(tmp2, tmp, 16);
1808 /////////////////////////////////////////////
1810 // ADD #imm,Rn 0111nnnniiiiiiii
1811 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1812 if (op & 0x80) { // adding negative
1813 emith_sub_r_imm(tmp, -op & 0xff);
1815 emith_add_r_imm(tmp, op & 0xff);
1818 /////////////////////////////////////////////
1820 switch (op & 0x0f00)
1822 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
1823 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
1825 tmp = rcache_get_reg_arg(0, GET_Rm());
1826 tmp2 = rcache_get_reg_arg(1, SHR_R0);
1827 tmp3 = (op & 0x100) >> 8;
1828 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
1829 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
1831 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
1832 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
1834 tmp = rcache_get_reg_arg(0, GET_Rm());
1835 tmp3 = (op & 0x100) >> 8;
1836 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
1837 tmp = emit_memhandler_read(tmp3);
1838 tmp2 = rcache_get_reg(0, RC_GR_WRITE);
1839 emith_sext(tmp2, tmp, 8 << tmp3);
1840 rcache_free_tmp(tmp);
1842 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
1843 // XXX: could use cmn
1844 tmp = rcache_get_tmp();
1845 tmp2 = rcache_get_reg(0, RC_GR_READ);
1846 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1847 if (drcf.delayed_op)
1849 emith_move_r_imm_s8(tmp, op & 0xff);
1850 emith_bic_r_imm(sr, T);
1851 emith_cmp_r_r(tmp2, tmp);
1852 emit_or_t_if_eq(sr);
1853 rcache_free_tmp(tmp);
1855 case 0x0d00: // BT/S label 10001101dddddddd
1856 case 0x0f00: // BF/S label 10001111dddddddd
1860 case 0x0900: // BT label 10001001dddddddd
1861 case 0x0b00: { // BF label 10001011dddddddd
1862 // jmp_cond ~ cond when guest doesn't jump
1863 int jmp_cond = (op & 0x0200) ? DCOND_NE : DCOND_EQ;
1864 int insn_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE;
1865 signed int offs = ((signed int)(op << 24) >> 23);
1866 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1867 if (find_in_array(branch_target_pc, branch_target_count, pc + offs + 2) >= 0) {
1868 branch_patch_pc[branch_patch_count] = pc + offs + 2;
1869 branch_patch_cond = insn_cond;
1873 // can't resolve branch, cause end of block
1874 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1875 emith_move_r_imm(tmp, pc + (drcf.delayed_op ? 2 : 0));
1876 emith_tst_r_imm(sr, T);
1877 EMITH_SJMP_START(jmp_cond);
1878 if (!drcf.delayed_op)
1881 emith_sub_r_imm_c(insn_cond, tmp, -offs);
1883 emith_add_r_imm_c(insn_cond, tmp, offs);
1884 EMITH_SJMP_END(jmp_cond);
1886 if (!drcf.delayed_op)
1892 /////////////////////////////////////////////
1894 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
1896 tmp = rcache_get_tmp_arg(0);
1897 emith_move_r_imm(tmp, pc + (op & 0xff) * 2 + 2);
1898 tmp = emit_memhandler_read(1);
1899 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1900 emith_sext(tmp2, tmp, 16);
1901 rcache_free_tmp(tmp);
1904 /////////////////////////////////////////////
1906 // BRA label 1010dddddddddddd
1909 tmp = ((signed int)(op << 20) >> 19);
1910 emit_move_r_imm32(SHR_PC, pc + tmp + 2);
1914 /////////////////////////////////////////////
1916 // BSR label 1011dddddddddddd
1918 emit_move_r_imm32(SHR_PR, pc + 2);
1921 /////////////////////////////////////////////
1923 switch (op & 0x0f00)
1925 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
1926 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
1927 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
1929 tmp = rcache_get_reg_arg(0, SHR_GBR);
1930 tmp2 = rcache_get_reg_arg(1, SHR_R0);
1931 tmp3 = (op & 0x300) >> 8;
1932 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
1933 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
1935 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
1936 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
1937 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
1939 tmp = rcache_get_reg_arg(0, SHR_GBR);
1940 tmp3 = (op & 0x300) >> 8;
1941 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
1942 tmp = emit_memhandler_read(tmp3);
1943 tmp2 = rcache_get_reg(0, RC_GR_WRITE);
1945 emith_sext(tmp2, tmp, 8 << tmp3);
1947 emith_move_r_r(tmp2, tmp);
1948 rcache_free_tmp(tmp);
1950 case 0x0300: // TRAPA #imm 11000011iiiiiiii
1951 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1952 emith_sub_r_imm(tmp, 4*2);
1955 tmp = rcache_get_reg_arg(0, SHR_SP);
1956 emith_add_r_imm(tmp, 4);
1957 tmp = rcache_get_reg_arg(1, SHR_SR);
1958 emith_clear_msb(tmp, tmp, 22);
1959 emit_memhandler_write(2, pc, drcf.delayed_op);
1961 rcache_get_reg_arg(0, SHR_SP);
1962 tmp = rcache_get_tmp_arg(1);
1963 emith_move_r_imm(tmp, pc);
1964 emit_memhandler_write(2, pc, drcf.delayed_op);
1966 tmp = rcache_get_reg_arg(0, SHR_VBR);
1967 emith_add_r_imm(tmp, (op & 0xff) * 4);
1968 tmp = emit_memhandler_read(2);
1969 tmp2 = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1970 emith_move_r_r(tmp2, tmp);
1971 rcache_free_tmp(tmp);
1974 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
1975 emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3);
1977 case 0x0800: // TST #imm,R0 11001000iiiiiiii
1978 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
1979 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1980 if (drcf.delayed_op)
1982 emith_bic_r_imm(sr, T);
1983 emith_tst_r_imm(tmp, op & 0xff);
1984 emit_or_t_if_eq(sr);
1986 case 0x0900: // AND #imm,R0 11001001iiiiiiii
1987 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
1988 emith_and_r_imm(tmp, op & 0xff);
1990 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
1991 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
1992 emith_eor_r_imm(tmp, op & 0xff);
1994 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
1995 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
1996 emith_or_r_imm(tmp, op & 0xff);
1998 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
1999 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2000 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2001 if (drcf.delayed_op)
2003 emith_bic_r_imm(sr, T);
2004 emith_tst_r_imm(tmp, op & 0xff);
2005 emit_or_t_if_eq(sr);
2006 rcache_free_tmp(tmp);
2009 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2010 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2011 emith_and_r_imm(tmp, op & 0xff);
2013 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2014 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2015 emith_eor_r_imm(tmp, op & 0xff);
2017 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2018 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2019 emith_or_r_imm(tmp, op & 0xff);
2021 tmp2 = rcache_get_tmp_arg(1);
2022 emith_move_r_r(tmp2, tmp);
2023 rcache_free_tmp(tmp);
2024 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2025 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2026 emith_add_r_r(tmp3, tmp4);
2027 emit_memhandler_write(0, pc, drcf.delayed_op);
2033 /////////////////////////////////////////////
2035 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
2037 tmp = rcache_get_tmp_arg(0);
2038 emith_move_r_imm(tmp, (pc + (op & 0xff) * 4 + 2) & ~3);
2039 tmp = emit_memhandler_read(2);
2040 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2041 emith_move_r_r(tmp2, tmp);
2042 rcache_free_tmp(tmp);
2045 /////////////////////////////////////////////
2047 // MOV #imm,Rn 1110nnnniiiiiiii
2048 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2049 emith_move_r_imm_s8(tmp, op & 0xff);
2054 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
2055 sh2->is_slave ? 's' : 'm', op, pc - 2);
2056 #ifdef DRC_DEBUG_INTERP
2057 emit_move_r_imm32(SHR_PC, pc - 2);
2059 emith_pass_arg_r(0, CONTEXT_REG);
2060 emith_pass_arg_imm(1, op);
2061 emith_call(sh2_do_op);
2067 // block-local conditional branch handling (with/without delay)
2068 if (branch_patch_cond != -1 && drcf.delayed_op != 2) {
2069 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2074 if (drcf.use_saved_t)
2075 emith_tst_r_imm(sr, T_save);
2077 emith_tst_r_imm(sr, T);
2078 branch_patch_ptr[branch_patch_count] = tcache_ptr;
2079 emith_jump_patchable(branch_patch_cond);
2081 drcf.use_saved_t = 0;
2082 branch_patch_cond = -1;
2083 branch_patch_count++;
2084 drcf.delayed_op = 0; // XXX: delayed_op ends block, so must override
2085 if (branch_patch_count == MAX_LOCAL_BRANCHES) {
2086 printf("too many local branches\n");
2091 // XXX: delay slots..
2092 if (drcf.test_irq && drcf.delayed_op != 2) {
2093 if (!drcf.delayed_op)
2094 emit_move_r_imm32(SHR_PC, pc);
2095 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2098 emith_call(sh2_drc_test_irq);
2101 if (drcf.delayed_op == 1)
2104 do_host_disasm(tcache_id);
2107 // delayed_op means some kind of branch - PC already handled
2108 if (!drcf.delayed_op)
2109 emit_move_r_imm32(SHR_PC, pc);
2112 this_block->end_addr = pc;
2114 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2117 emith_jump(sh2_drc_dispatcher);
2119 // link local branches
2120 for (i = 0; i < branch_patch_count; i++) {
2123 //printf("patch %08x %p\n", branch_patch_pc[i], branch_patch_ptr[i]);
2124 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2125 if (branch_target_ptr[t] != NULL)
2126 target = branch_target_ptr[t];
2128 // flush pc and go back to dispatcher (for now)
2129 printf("stray branch to %08x %p\n", branch_patch_pc[i], tcache_ptr);
2130 target = tcache_ptr;
2131 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2133 emith_jump(sh2_drc_dispatcher);
2135 emith_jump_patch(branch_patch_ptr[i], target);
2138 // mark memory blocks as containing compiled code
2139 if (tcache_id != 0) {
2141 u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
2142 tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
2143 tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
2144 drcblk[tmp] = (blkid_main << 1) | 1;
2145 for (++tmp; tmp < tmp2; tmp++) {
2147 continue; // dont overwrite overlay block(s)
2148 drcblk[tmp] = blkid_main << 1;
2151 else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
2152 tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
2153 tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
2154 Pico32xMem->drcblk_ram[tmp] = (blkid_main << 1) | 1;
2155 for (++tmp; tmp < tmp2; tmp++) {
2156 if (Pico32xMem->drcblk_ram[tmp])
2158 Pico32xMem->drcblk_ram[tmp] = blkid_main << 1;
2162 tcache_ptrs[tcache_id] = tcache_ptr;
2165 cache_flush_d_inval_i(block_entry, tcache_ptr);
2168 do_host_disasm(tcache_id);
2169 dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2170 tcache_id, block_counts[tcache_id],
2171 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2172 insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled);
2173 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2174 dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2177 tcache_dsm_ptrs[tcache_id] = block_entry;
2178 do_host_disasm(tcache_id);
2190 do_host_disasm(tcache_id);
2195 static void sh2_generate_utils(void)
2197 int arg0, arg1, arg2, sr, tmp;
2198 void *sh2_drc_write_end, *sh2_drc_write_slot_end;
2200 host_arg2reg(arg0, 0);
2201 host_arg2reg(arg1, 1);
2202 host_arg2reg(arg2, 2);
2203 emith_move_r_r(arg0, arg0); // nop
2205 // sh2_drc_exit(void)
2206 sh2_drc_exit = (void *)tcache_ptr;
2207 emit_do_static_regs(1, arg2);
2208 emith_sh2_drc_exit();
2210 // sh2_drc_dispatcher(void)
2211 sh2_drc_dispatcher = (void *)tcache_ptr;
2212 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2213 emith_cmp_r_imm(sr, 0);
2214 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2215 rcache_invalidate();
2216 emith_ctx_read(arg0, SHR_PC * 4);
2217 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2218 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2219 emith_call(lookup_block);
2221 // lookup failed, call sh2_translate()
2222 emith_move_r_r(arg0, CONTEXT_REG);
2223 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2224 emith_call(sh2_translate);
2226 // sh2_translate() failed, flush cache and retry
2227 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2228 emith_call(flush_tcache);
2229 emith_move_r_r(arg0, CONTEXT_REG);
2230 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2231 emith_call(sh2_translate);
2233 // XXX: can't translate, fail
2236 // sh2_drc_test_irq(void)
2237 // assumes it's called from main function (may jump to dispatcher)
2238 sh2_drc_test_irq = (void *)tcache_ptr;
2239 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2240 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2241 emith_lsr(arg0, sr, I_SHIFT);
2242 emith_and_r_imm(arg0, 0x0f);
2243 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2244 EMITH_SJMP_START(DCOND_GT);
2245 emith_ret_c(DCOND_LE); // nope, return
2246 EMITH_SJMP_END(DCOND_GT);
2248 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2249 emith_sub_r_imm(tmp, 4*2);
2252 tmp = rcache_get_reg_arg(0, SHR_SP);
2253 emith_add_r_imm(tmp, 4);
2254 tmp = rcache_get_reg_arg(1, SHR_SR);
2255 emith_clear_msb(tmp, tmp, 22);
2256 emith_move_r_r(arg2, CONTEXT_REG);
2257 emith_call(p32x_sh2_write32);
2258 rcache_invalidate();
2260 rcache_get_reg_arg(0, SHR_SP);
2261 emith_ctx_read(arg1, SHR_PC * 4);
2262 emith_move_r_r(arg2, CONTEXT_REG);
2263 emith_call(p32x_sh2_write32);
2264 rcache_invalidate();
2265 // update I, cycles, do callback
2266 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2267 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2268 emith_bic_r_imm(sr, I);
2269 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2270 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2272 emith_move_r_r(arg0, CONTEXT_REG);
2273 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2275 emith_lsl(arg0, arg0, 2);
2276 emith_ctx_read(arg1, SHR_VBR * 4);
2277 emith_add_r_r(arg0, arg1);
2278 emit_memhandler_read(2);
2279 emith_ctx_write(arg0, SHR_PC * 4);
2281 emith_add_r_imm(xSP, 4); // fix stack
2283 emith_jump(sh2_drc_dispatcher);
2284 rcache_invalidate();
2286 // sh2_drc_entry(SH2 *sh2)
2287 sh2_drc_entry = (void *)tcache_ptr;
2288 emith_sh2_drc_entry();
2289 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2290 emit_do_static_regs(0, arg2);
2291 emith_call(sh2_drc_test_irq);
2292 emith_jump(sh2_drc_dispatcher);
2294 // write-caused irq detection
2295 sh2_drc_write_end = tcache_ptr;
2296 emith_tst_r_r(arg0, arg0);
2297 EMITH_SJMP_START(DCOND_NE);
2298 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); // return
2299 EMITH_SJMP_END(DCOND_NE);
2300 // since PC is up to date, jump to it's block instead of returning
2301 emith_call(sh2_drc_test_irq);
2302 emith_jump_ctx(offsetof(SH2, drc_tmp));
2304 // write-caused irq detection for writes in delay slot
2305 sh2_drc_write_slot_end = tcache_ptr;
2306 emith_tst_r_r(arg0, arg0);
2307 EMITH_SJMP_START(DCOND_NE);
2308 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp));
2309 EMITH_SJMP_END(DCOND_NE);
2310 // just burn cycles to get back to dispatcher after branch is handled
2311 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2312 emith_ctx_write(sr, offsetof(SH2, irq_cycles));
2313 emith_clear_msb(sr, sr, 20); // clear cycles
2315 emith_jump_ctx(offsetof(SH2, drc_tmp));
2317 // sh2_drc_write8(u32 a, u32 d)
2318 sh2_drc_write8 = (void *)tcache_ptr;
2319 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2320 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2321 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2323 // sh2_drc_write16(u32 a, u32 d)
2324 sh2_drc_write16 = (void *)tcache_ptr;
2325 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2326 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2327 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2329 // sh2_drc_write8_slot(u32 a, u32 d)
2330 sh2_drc_write8_slot = (void *)tcache_ptr;
2331 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2332 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2333 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2335 // sh2_drc_write16_slot(u32 a, u32 d)
2336 sh2_drc_write16_slot = (void *)tcache_ptr;
2337 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2338 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2339 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2341 rcache_invalidate();
2343 host_dasm_new_symbol(sh2_drc_entry);
2344 host_dasm_new_symbol(sh2_drc_dispatcher);
2345 host_dasm_new_symbol(sh2_drc_exit);
2346 host_dasm_new_symbol(sh2_drc_test_irq);
2347 host_dasm_new_symbol(sh2_drc_write_end);
2348 host_dasm_new_symbol(sh2_drc_write_slot_end);
2349 host_dasm_new_symbol(sh2_drc_write8);
2350 host_dasm_new_symbol(sh2_drc_write8_slot);
2351 host_dasm_new_symbol(sh2_drc_write16);
2352 host_dasm_new_symbol(sh2_drc_write16_slot);
2356 static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a)
2359 block_desc *bd = btab + id;
2361 // FIXME: skip subblocks; do both directions
2362 dbg(1, " killing block %08x", bd->addr);
2363 bd->addr = bd->end_addr = 0;
2365 while (p > drcblk && (p[-1] >> 1) == id)
2368 // check for possible overlay block
2369 if (p > 0 && p[-1] != 0) {
2370 bd = btab + (p[-1] >> 1);
2371 if (bd->addr <= a && a < bd->end_addr)
2372 sh2_smc_rm_block(drcblk, p - 1, btab, a);
2378 while ((*p >> 1) == id);
2381 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
2383 u16 *drcblk = Pico32xMem->drcblk_ram;
2384 u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT);
2386 dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
2387 sh2_smc_rm_block(drcblk, p, block_tables[0], a);
2390 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
2392 u16 *drcblk = Pico32xMem->drcblk_da[cpuid];
2393 u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT);
2395 dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
2396 sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a);
2399 void sh2_execute(SH2 *sh2c, int cycles)
2404 sh2c->cycles_aim += cycles;
2405 cycles = sh2c->cycles_aim - sh2c->cycles_done;
2407 // cycles are kept in SHR_SR unused bits (upper 20)
2408 // bit19 contains T saved for delay slot
2409 // others are usual SH2 flags
2411 sh2c->sr |= cycles << 12;
2412 sh2_drc_entry(sh2c);
2415 ret_cycles = (signed int)sh2c->sr >> 12;
2417 printf("warning: drc returned with cycles: %d\n", ret_cycles);
2419 sh2c->cycles_done += cycles - ret_cycles;
2423 static void block_stats(void)
2425 int c, b, i, total = 0;
2427 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
2428 for (i = 0; i < block_counts[b]; i++)
2429 if (block_tables[b][i].addr != 0)
2430 total += block_tables[b][i].refcount;
2432 for (c = 0; c < 10; c++) {
2433 block_desc *blk, *maxb = NULL;
2435 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
2436 for (i = 0; i < block_counts[b]; i++) {
2437 blk = &block_tables[b][i];
2438 if (blk->addr != 0 && blk->refcount > max) {
2439 max = blk->refcount;
2446 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
2447 (double)maxb->refcount / total * 100.0);
2451 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
2452 for (i = 0; i < block_counts[b]; i++)
2453 block_tables[b][i].refcount = 0;
2456 #define block_stats()
2459 void sh2_drc_flush_all(void)
2467 int sh2_drc_init(SH2 *sh2)
2469 if (block_tables[0] == NULL) {
2474 cnt = block_max_counts[0] + block_max_counts[1] + block_max_counts[2];
2475 block_tables[0] = calloc(cnt, sizeof(*block_tables[0]));
2476 if (block_tables[0] == NULL)
2479 tcache_ptr = tcache;
2480 sh2_generate_utils();
2482 cache_flush_d_inval_i(tcache, tcache_ptr);
2485 memset(block_counts, 0, sizeof(block_counts));
2486 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
2488 for (i = 1; i < ARRAY_SIZE(block_tables); i++) {
2489 block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1];
2490 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
2494 PicoOpt |= POPT_DIS_VDP_FIFO;
2497 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
2498 tcache_dsm_ptrs[i] = tcache_bases[i];
2500 tcache_dsm_ptrs[0] = tcache;
2504 hash_collisions = 0;
2508 if (hash_table == NULL) {
2509 hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES);
2510 if (hash_table == NULL)
2517 void sh2_drc_finish(SH2 *sh2)
2519 if (block_tables[0] != NULL) {
2521 free(block_tables[0]);
2522 memset(block_tables, 0, sizeof(block_tables));
2527 if (hash_table != NULL) {