3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * - tcache, block descriptor, link buffer overflows result in sh2_translate()
10 * failure, followed by full tcache invalidation for that region
11 * - jumps between blocks are tracked for SMC handling (in block_entry->links),
12 * except jumps between different tcaches
15 * - static register allocation
16 * - remaining register caching and tracking in temporaries
17 * - block-local branch linking
18 * - block linking (except between tcaches)
19 * - some constant propagation
22 * - better constant propagation
31 #include "../../pico/pico_int.h"
34 #include "../drc/cmn.h"
38 #define PROPAGATE_CONSTANTS 1
39 #define LINK_BRANCHES 1
42 #define MAX_BLOCK_SIZE (BLOCK_INSN_LIMIT * 6 * 6)
44 // max literal offset from the block end
45 #define MAX_LITERAL_OFFSET 32*2
46 #define MAX_LITERALS (BLOCK_INSN_LIMIT / 4)
47 #define MAX_LOCAL_BRANCHES 32
50 // 1 - warnings/errors
53 // 8 - runtime block entry log
60 #define dbg(l,...) { \
61 if ((l) & DRC_DEBUG) \
62 elprintf(EL_STATUS, ##__VA_ARGS__); \
64 #include "mame/sh2dasm.h"
65 #include <platform/libpicofe/linux/host_dasm.h>
66 static int insns_compiled, hash_collisions, host_insn_count;
75 #define FETCH_OP(pc) \
79 ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
81 #define CHECK_UNHANDLED_BITS(mask, label) { \
82 if ((op & (mask)) != 0) \
94 #define BITMASK1(v0) (1 << (v0))
95 #define BITMASK2(v0,v1) ((1 << (v0)) | (1 << (v1)))
96 #define BITMASK3(v0,v1,v2) (BITMASK2(v0,v1) | (1 << (v2)))
97 #define BITMASK4(v0,v1,v2,v3) (BITMASK3(v0,v1,v2) | (1 << (v3)))
98 #define BITMASK5(v0,v1,v2,v3,v4) (BITMASK4(v0,v1,v2,v3) | (1 << (v4)))
100 #define SHR_T SHR_SR // might make them separate someday
102 static struct op_data {
105 u8 size; // 0, 1, 2 - byte, word, long
106 s8 rm; // branch or load/store data reg
107 u32 source; // bitmask of src regs
108 u32 dest; // bitmask of dest regs
109 u32 imm; // immediate/io address/branch target
110 // (for literal - address, not value)
111 } ops[BLOCK_INSN_LIMIT];
116 OP_BRANCH_CT, // conditional, branch if T set
117 OP_BRANCH_CF, // conditional, branch if T clear
118 OP_BRANCH_R, // indirect
119 OP_BRANCH_RF, // indirect far (PC + Rm)
120 OP_SETCLRT, // T flag set/clear
121 OP_MOVE, // register move
122 OP_LOAD_POOL, // literal pool load, imm is address
130 static int literal_disabled_frames;
133 static u8 *tcache_dsm_ptrs[3];
134 static char sh2dasm_buff[64];
135 #define do_host_disasm(tcid) \
136 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
137 tcache_dsm_ptrs[tcid] = tcache_ptr
139 #define do_host_disasm(x)
142 #if (DRC_DEBUG & 8) || defined(PDB)
143 static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
146 dbg(8, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
147 sh2->pc, block, (signed int)sr >> 12);
148 pdb_step(sh2, sh2->pc);
155 #define TCACHE_BUFFERS 3
157 // we have 3 translation cache buffers, split from one drc/cmn buffer.
158 // BIOS shares tcache with data array because it's only used for init
159 // and can be discarded early
160 // XXX: need to tune sizes
161 static const int tcache_sizes[TCACHE_BUFFERS] = {
162 DRC_TCACHE_SIZE * 6 / 8, // ROM (rarely used), DRAM
163 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
164 DRC_TCACHE_SIZE / 8, // ... slave
167 static u8 *tcache_bases[TCACHE_BUFFERS];
168 static u8 *tcache_ptrs[TCACHE_BUFFERS];
170 // ptr for code emiters
171 static u8 *tcache_ptr;
173 #define MAX_BLOCK_ENTRIES (BLOCK_INSN_LIMIT / 8)
177 void *jump; // insn address
178 struct block_link *next; // either in block_entry->links or
183 void *tcache_ptr; // translated block for above PC
184 struct block_entry *next; // next block in hash_table with same pc hash
185 struct block_link *links; // links to this entry
187 struct block_desc *block;
192 u32 addr; // block start SH2 PC address
193 u16 size; // ..of recompiled insns+lit. pool
194 u16 size_nolit; // same without literals
199 struct block_entry entryp[MAX_BLOCK_ENTRIES];
202 static const int block_max_counts[TCACHE_BUFFERS] = {
207 static struct block_desc *block_tables[TCACHE_BUFFERS];
208 static int block_counts[TCACHE_BUFFERS];
210 // we have block_link_pool to avoid using mallocs
211 static const int block_link_pool_max_counts[TCACHE_BUFFERS] = {
216 static struct block_link *block_link_pool[TCACHE_BUFFERS];
217 static int block_link_pool_counts[TCACHE_BUFFERS];
218 static struct block_link *unresolved_links[TCACHE_BUFFERS];
220 // used for invalidation
221 static const int ram_sizes[TCACHE_BUFFERS] = {
226 #define INVAL_PAGE_SIZE 0x100
229 struct block_desc *block;
230 struct block_list *next;
233 // array of pointers to block_lists for RAM and 2 data arrays
234 // each array has len: sizeof(mem) / INVAL_PAGE_SIZE
235 static struct block_list **inval_lookup[TCACHE_BUFFERS];
237 static const int hash_table_sizes[TCACHE_BUFFERS] = {
242 static struct block_entry **hash_tables[TCACHE_BUFFERS];
244 #define HASH_FUNC(hash_tab, addr, mask) \
245 (hash_tab)[(((addr) >> 20) ^ ((addr) >> 2)) & (mask)]
247 // host register tracking
250 HR_CACHED, // 'val' has sh2_reg_e
251 // HR_CONST, // 'val' has a constant
252 HR_TEMP, // reg used for temp storage
256 HRF_DIRTY = 1 << 0, // reg has "dirty" value to be written to ctx
257 HRF_LOCKED = 1 << 1, // HR_CACHED can't be evicted
261 u32 hreg:5; // "host" reg
262 u32 greg:5; // "guest" reg
265 u32 stamp:16; // kind of a timestamp
268 // note: reg_temp[] must have at least the amount of
269 // registers used by handlers in worst case (currently 4)
271 #include "../drc/emit_arm.c"
275 static const int reg_map_g2h[] = {
279 -1, -1, -1, 9, // r12 .. sp
280 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
281 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
287 static const int reg_map_g2h[] = {
291 -1, -1, -1, 8, // r12 .. sp
292 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
293 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
298 static temp_reg_t reg_temp[] = {
307 #elif defined(__i386__)
308 #include "../drc/emit_x86.c"
310 static const int reg_map_g2h[] = {
319 // ax, cx, dx are usually temporaries by convention
320 static temp_reg_t reg_temp[] = {
328 #error unsupported arch
336 #define T_save 0x00000800
342 static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
343 static void (*sh2_drc_dispatcher)(void);
344 static void (*sh2_drc_exit)(void);
345 static void (*sh2_drc_test_irq)(void);
347 static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
348 static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
349 static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
350 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
351 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
352 static void REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
354 // address space stuff
355 static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
359 if ((a & ~0x7ff) == 0) {
361 poffs = offsetof(SH2, p_bios);
364 else if ((a & 0xfffff000) == 0xc0000000) {
366 // FIXME: access sh2->data_array instead
367 poffs = offsetof(SH2, p_da);
370 else if ((a & 0xc6000000) == 0x06000000) {
372 poffs = offsetof(SH2, p_sdram);
375 else if ((a & 0xc6000000) == 0x02000000) {
377 poffs = offsetof(SH2, p_rom);
384 static struct block_entry *dr_get_entry(u32 pc, int is_slave, int *tcache_id)
386 struct block_entry *be;
389 // data arrays have their own caches
390 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0)
395 mask = hash_table_sizes[tcid] - 1;
396 be = HASH_FUNC(hash_tables[tcid], pc, mask);
397 for (; be != NULL; be = be->next)
404 // ---------------------------------------------------------------
407 static void add_to_block_list(struct block_list **blist, struct block_desc *block)
409 struct block_list *added = malloc(sizeof(*added));
411 elprintf(EL_ANOMALY, "drc OOM (1)");
414 added->block = block;
415 added->next = *blist;
419 static void rm_from_block_list(struct block_list **blist, struct block_desc *block)
421 struct block_list *prev = NULL, *current = *blist;
422 for (; current != NULL; prev = current, current = current->next) {
423 if (current->block == block) {
425 *blist = current->next;
427 prev->next = current->next;
432 dbg(1, "can't rm block %p (%08x-%08x)",
433 block, block->addr, block->addr + block->size);
436 static void rm_block_list(struct block_list **blist)
438 struct block_list *tmp, *current = *blist;
439 while (current != NULL) {
441 current = current->next;
447 static void REGPARM(1) flush_tcache(int tcid)
451 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
452 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
453 block_counts[tcid], block_max_counts[tcid]);
455 block_counts[tcid] = 0;
456 block_link_pool_counts[tcid] = 0;
457 unresolved_links[tcid] = NULL;
458 memset(hash_tables[tcid], 0, sizeof(*hash_tables[0]) * hash_table_sizes[tcid]);
459 tcache_ptrs[tcid] = tcache_bases[tcid];
460 if (Pico32xMem != NULL) {
461 if (tcid == 0) // ROM, RAM
462 memset(Pico32xMem->drcblk_ram, 0,
463 sizeof(Pico32xMem->drcblk_ram));
465 memset(Pico32xMem->drcblk_da[tcid - 1], 0,
466 sizeof(Pico32xMem->drcblk_da[0]));
469 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
472 for (i = 0; i < ram_sizes[tcid] / INVAL_PAGE_SIZE; i++)
473 rm_block_list(&inval_lookup[tcid][i]);
476 static void add_to_hashlist(struct block_entry *be, int tcache_id)
478 u32 tcmask = hash_table_sizes[tcache_id] - 1;
480 be->next = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
481 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be;
484 if (be->next != NULL) {
485 printf(" %08x: hash collision with %08x\n",
486 be->pc, be->next->pc);
492 static void rm_from_hashlist(struct block_entry *be, int tcache_id)
494 u32 tcmask = hash_table_sizes[tcache_id] - 1;
495 struct block_entry *cur, *prev;
497 cur = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
501 if (be == cur) { // first
502 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be->next;
506 for (prev = cur, cur = cur->next; cur != NULL; cur = cur->next) {
508 prev->next = cur->next;
514 dbg(1, "rm_from_hashlist: be %p %08x missing?", be, be->pc);
517 static struct block_desc *dr_add_block(u32 addr, u16 size_lit,
518 u16 size_nolit, int is_slave, int *blk_id)
520 struct block_entry *be;
521 struct block_desc *bd;
525 // do a lookup to get tcache_id and override check
526 be = dr_get_entry(addr, is_slave, &tcache_id);
528 dbg(1, "block override for %08x", addr);
530 bcount = &block_counts[tcache_id];
531 if (*bcount >= block_max_counts[tcache_id]) {
532 dbg(1, "bd overflow for tcache %d", tcache_id);
536 bd = &block_tables[tcache_id][*bcount];
539 bd->size_nolit = size_nolit;
542 bd->entryp[0].pc = addr;
543 bd->entryp[0].tcache_ptr = tcache_ptr;
544 bd->entryp[0].links = NULL;
546 bd->entryp[0].block = bd;
549 add_to_hashlist(&bd->entryp[0], tcache_id);
557 static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id)
559 struct block_entry *be = NULL;
562 be = dr_get_entry(pc, is_slave, tcache_id);
564 block = be->tcache_ptr;
568 be->block->refcount++;
573 static void *dr_failure(void)
575 lprintf("recompilation failed\n");
579 static void *dr_prepare_ext_branch(u32 pc, int is_slave, int tcache_id)
582 struct block_link *bl = block_link_pool[tcache_id];
583 int cnt = block_link_pool_counts[tcache_id];
584 struct block_entry *be = NULL;
585 int target_tcache_id;
588 be = dr_get_entry(pc, is_slave, &target_tcache_id);
589 if (target_tcache_id != tcache_id)
590 return sh2_drc_dispatcher;
592 // if pool has been freed, reuse
593 for (i = cnt - 1; i >= 0; i--)
594 if (bl[i].target_pc != 0)
597 if (cnt >= block_link_pool_max_counts[tcache_id]) {
598 dbg(1, "bl overflow for tcache %d", tcache_id);
602 block_link_pool_counts[tcache_id]++;
605 bl->jump = tcache_ptr;
608 dbg(2, "- early link from %p to pc %08x", bl->jump, pc);
609 bl->next = be->links;
611 return be->tcache_ptr;
614 bl->next = unresolved_links[tcache_id];
615 unresolved_links[tcache_id] = bl;
616 return sh2_drc_dispatcher;
619 return sh2_drc_dispatcher;
623 static void dr_link_blocks(struct block_entry *be, int tcache_id)
626 struct block_link *first = unresolved_links[tcache_id];
627 struct block_link *bl, *prev, *tmp;
630 for (bl = prev = first; bl != NULL; ) {
631 if (bl->target_pc == pc) {
632 dbg(2, "- link from %p to pc %08x", bl->jump, pc);
633 emith_jump_patch(bl->jump, tcache_ptr);
635 // move bl from unresolved_links to block_entry
637 bl->next = be->links;
641 first = prev = bl = tmp;
643 prev->next = bl = tmp;
649 unresolved_links[tcache_id] = first;
651 // could sync arm caches here, but that's unnecessary
655 #define ADD_TO_ARRAY(array, count, item, failcode) \
656 if (count >= ARRAY_SIZE(array)) { \
657 dbg(1, "warning: " #array " overflow"); \
660 array[count++] = item;
662 static int find_in_array(u32 *array, size_t size, u32 what)
665 for (i = 0; i < size; i++)
666 if (what == array[i])
672 // ---------------------------------------------------------------
674 // register cache / constant propagation stuff
681 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking);
683 // guest regs with constants
684 static u32 dr_gcregs[24];
685 // a mask of constant/dirty regs
686 static u32 dr_gcregs_mask;
687 static u32 dr_gcregs_dirty;
689 #if PROPAGATE_CONSTANTS
690 static void gconst_new(sh2_reg_e r, u32 val)
694 dr_gcregs_mask |= 1 << r;
695 dr_gcregs_dirty |= 1 << r;
698 // throw away old r that we might have cached
699 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
700 if ((reg_temp[i].type == HR_CACHED) &&
701 reg_temp[i].greg == r) {
702 reg_temp[i].type = HR_FREE;
703 reg_temp[i].flags = 0;
709 static int gconst_get(sh2_reg_e r, u32 *val)
711 if (dr_gcregs_mask & (1 << r)) {
718 static int gconst_check(sh2_reg_e r)
720 if ((dr_gcregs_mask | dr_gcregs_dirty) & (1 << r))
725 // update hr if dirty, else do nothing
726 static int gconst_try_read(int hr, sh2_reg_e r)
728 if (dr_gcregs_dirty & (1 << r)) {
729 emith_move_r_imm(hr, dr_gcregs[r]);
730 dr_gcregs_dirty &= ~(1 << r);
736 static void gconst_check_evict(sh2_reg_e r)
738 if (dr_gcregs_mask & (1 << r))
739 // no longer cached in reg, make dirty again
740 dr_gcregs_dirty |= 1 << r;
743 static void gconst_kill(sh2_reg_e r)
745 dr_gcregs_mask &= ~(1 << r);
746 dr_gcregs_dirty &= ~(1 << r);
749 static void gconst_clean(void)
753 for (i = 0; i < ARRAY_SIZE(dr_gcregs); i++)
754 if (dr_gcregs_dirty & (1 << i)) {
755 // using RC_GR_READ here: it will call gconst_try_read,
756 // cache the reg and mark it dirty.
757 rcache_get_reg_(i, RC_GR_READ, 0);
761 static void gconst_invalidate(void)
763 dr_gcregs_mask = dr_gcregs_dirty = 0;
766 static u16 rcache_counter;
768 static temp_reg_t *rcache_evict(void)
770 // evict reg with oldest stamp
772 u16 min_stamp = (u16)-1;
774 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
775 if (reg_temp[i].type == HR_CACHED && !(reg_temp[i].flags & HRF_LOCKED) &&
776 reg_temp[i].stamp <= min_stamp) {
777 min_stamp = reg_temp[i].stamp;
783 printf("no registers to evict, aborting\n");
788 if (reg_temp[i].type == HR_CACHED) {
789 if (reg_temp[i].flags & HRF_DIRTY)
791 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
792 gconst_check_evict(reg_temp[i].greg);
795 reg_temp[i].type = HR_FREE;
796 reg_temp[i].flags = 0;
800 static int get_reg_static(sh2_reg_e r, rc_gr_mode mode)
802 int i = reg_map_g2h[r];
804 if (mode != RC_GR_WRITE)
805 gconst_try_read(i, r);
810 // note: must not be called when doing conditional code
811 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking)
816 // maybe statically mapped?
817 ret = get_reg_static(r, mode);
823 // maybe already cached?
824 // if so, prefer against gconst (they must be in sync)
825 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
826 if (reg_temp[i].type == HR_CACHED && reg_temp[i].greg == r) {
827 reg_temp[i].stamp = rcache_counter;
828 if (mode != RC_GR_READ)
829 reg_temp[i].flags |= HRF_DIRTY;
830 ret = reg_temp[i].hreg;
836 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
837 if (reg_temp[i].type == HR_FREE) {
846 tr->type = HR_CACHED;
848 tr->flags |= HRF_LOCKED;
849 if (mode != RC_GR_READ)
850 tr->flags |= HRF_DIRTY;
852 tr->stamp = rcache_counter;
855 if (mode != RC_GR_WRITE) {
856 if (gconst_check(r)) {
857 if (gconst_try_read(ret, r))
858 tr->flags |= HRF_DIRTY;
861 emith_ctx_read(tr->hreg, r * 4);
865 if (mode != RC_GR_READ)
871 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
873 return rcache_get_reg_(r, mode, 1);
876 static int rcache_get_tmp(void)
881 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
882 if (reg_temp[i].type == HR_FREE) {
894 static int rcache_get_arg_id(int arg)
897 host_arg2reg(r, arg);
899 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
900 if (reg_temp[i].hreg == r)
903 if (i == ARRAY_SIZE(reg_temp)) // can't happen
906 if (reg_temp[i].type == HR_CACHED) {
908 if (reg_temp[i].flags & HRF_DIRTY)
909 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
910 gconst_check_evict(reg_temp[i].greg);
912 else if (reg_temp[i].type == HR_TEMP) {
913 printf("arg %d reg %d already used, aborting\n", arg, r);
917 reg_temp[i].type = HR_FREE;
918 reg_temp[i].flags = 0;
923 // get a reg to be used as function arg
924 static int rcache_get_tmp_arg(int arg)
926 int id = rcache_get_arg_id(arg);
927 reg_temp[id].type = HR_TEMP;
929 return reg_temp[id].hreg;
932 // same but caches a reg. RC_GR_READ only.
933 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
935 int i, srcr, dstr, dstid;
936 int dirty = 0, src_dirty = 0;
938 dstid = rcache_get_arg_id(arg);
939 dstr = reg_temp[dstid].hreg;
941 // maybe already statically mapped?
942 srcr = get_reg_static(r, RC_GR_READ);
946 // maybe already cached?
947 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
948 if ((reg_temp[i].type == HR_CACHED) &&
949 reg_temp[i].greg == r)
951 srcr = reg_temp[i].hreg;
952 if (reg_temp[i].flags & HRF_DIRTY)
960 if (gconst_check(r)) {
961 if (gconst_try_read(srcr, r))
965 emith_ctx_read(srcr, r * 4);
969 emith_move_r_r(dstr, srcr);
975 // must clean, callers might want to modify the arg before call
976 emith_ctx_write(dstr, r * 4);
979 reg_temp[dstid].flags |= HRF_DIRTY;
982 reg_temp[dstid].stamp = ++rcache_counter;
983 reg_temp[dstid].type = HR_CACHED;
984 reg_temp[dstid].greg = r;
985 reg_temp[dstid].flags |= HRF_LOCKED;
989 static void rcache_free_tmp(int hr)
992 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
993 if (reg_temp[i].hreg == hr)
996 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
997 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
1001 reg_temp[i].type = HR_FREE;
1002 reg_temp[i].flags = 0;
1005 static void rcache_unlock(int hr)
1008 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1009 if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr)
1010 reg_temp[i].flags &= ~HRF_LOCKED;
1013 static void rcache_unlock_all(void)
1016 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1017 reg_temp[i].flags &= ~HRF_LOCKED;
1020 static inline u32 rcache_used_hreg_mask(void)
1025 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1026 if (reg_temp[i].type != HR_FREE)
1027 mask |= 1 << reg_temp[i].hreg;
1032 static void rcache_clean(void)
1037 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1038 if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) {
1040 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
1041 reg_temp[i].flags &= ~HRF_DIRTY;
1045 static void rcache_invalidate(void)
1048 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
1049 reg_temp[i].type = HR_FREE;
1050 reg_temp[i].flags = 0;
1054 gconst_invalidate();
1057 static void rcache_flush(void)
1060 rcache_invalidate();
1063 // ---------------------------------------------------------------
1065 static int emit_get_rbase_and_offs(u32 a, u32 *offs)
1071 poffs = dr_ctx_get_mem_ptr(a, &mask);
1075 // XXX: could use some related reg
1076 hr = rcache_get_tmp();
1077 emith_ctx_read(hr, poffs);
1078 emith_add_r_imm(hr, a & mask & ~0xff);
1079 *offs = a & 0xff; // XXX: ARM oriented..
1083 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
1085 #if PROPAGATE_CONSTANTS
1086 gconst_new(dst, imm);
1088 int hr = rcache_get_reg(dst, RC_GR_WRITE);
1089 emith_move_r_imm(hr, imm);
1093 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
1095 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
1096 int hr_s = rcache_get_reg(src, RC_GR_READ);
1098 emith_move_r_r(hr_d, hr_s);
1101 // T must be clear, and comparison done just before this
1102 static void emit_or_t_if_eq(int srr)
1104 EMITH_SJMP_START(DCOND_NE);
1105 emith_or_r_imm_c(DCOND_EQ, srr, T);
1106 EMITH_SJMP_END(DCOND_NE);
1109 // arguments must be ready
1110 // reg cache must be clean before call
1111 static int emit_memhandler_read_(int size, int ram_check)
1116 host_arg2reg(arg0, 0);
1121 // must writeback cycles for poll detection stuff
1123 if (reg_map_g2h[SHR_SR] != -1)
1124 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1126 arg1 = rcache_get_tmp_arg(1);
1127 emith_move_r_r(arg1, CONTEXT_REG);
1129 #if 0 // can't do this because of unmapped reads
1131 if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
1132 int tmp = rcache_get_tmp();
1133 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
1134 emith_cmp_r_imm(tmp, 0x02000000);
1137 EMITH_SJMP3_START(DCOND_NE);
1138 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
1139 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1140 EMITH_SJMP3_MID(DCOND_NE);
1141 emith_call_cond(DCOND_NE, sh2_drc_read8);
1145 EMITH_SJMP3_START(DCOND_NE);
1146 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1147 EMITH_SJMP3_MID(DCOND_NE);
1148 emith_call_cond(DCOND_NE, sh2_drc_read16);
1152 EMITH_SJMP3_START(DCOND_NE);
1153 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1154 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
1155 EMITH_SJMP3_MID(DCOND_NE);
1156 emith_call_cond(DCOND_NE, sh2_drc_read32);
1166 emith_call(sh2_drc_read8);
1169 emith_call(sh2_drc_read16);
1172 emith_call(sh2_drc_read32);
1176 rcache_invalidate();
1178 if (reg_map_g2h[SHR_SR] != -1)
1179 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1181 // assuming arg0 and retval reg matches
1182 return rcache_get_tmp_arg(0);
1185 static int emit_memhandler_read(int size)
1187 return emit_memhandler_read_(size, 1);
1190 static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size)
1192 int hr, hr2, ram_check = 1;
1195 if (gconst_get(rs, &val)) {
1196 hr = emit_get_rbase_and_offs(val + offs, &offs2);
1198 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1201 emith_read8_r_r_offs(hr2, hr, offs2 ^ 1);
1202 emith_sext(hr2, hr2, 8);
1205 emith_read16_r_r_offs(hr2, hr, offs2);
1206 emith_sext(hr2, hr2, 16);
1209 emith_read_r_r_offs(hr2, hr, offs2);
1210 emith_ror(hr2, hr2, 16);
1213 rcache_free_tmp(hr);
1220 hr = rcache_get_reg_arg(0, rs);
1222 emith_add_r_imm(hr, offs);
1223 hr = emit_memhandler_read_(size, ram_check);
1224 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1226 emith_sext(hr2, hr, (size == 1) ? 16 : 8);
1228 emith_move_r_r(hr2, hr);
1229 rcache_free_tmp(hr);
1234 static void emit_memhandler_write(int size)
1237 host_arg2reg(ctxr, 2);
1238 if (reg_map_g2h[SHR_SR] != -1)
1239 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1245 // XXX: consider inlining sh2_drc_write8
1246 emith_call(sh2_drc_write8);
1249 emith_call(sh2_drc_write16);
1252 emith_move_r_r(ctxr, CONTEXT_REG);
1253 emith_call(sh2_drc_write32);
1257 rcache_invalidate();
1258 if (reg_map_g2h[SHR_SR] != -1)
1259 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1263 static int emit_indirect_indexed_read(int rx, int ry, int size)
1266 a0 = rcache_get_reg_arg(0, rx);
1267 t = rcache_get_reg(ry, RC_GR_READ);
1268 emith_add_r_r(a0, t);
1269 return emit_memhandler_read(size);
1273 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
1277 rcache_get_reg_arg(0, rn);
1278 tmp = emit_memhandler_read(size);
1279 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
1280 rcache_free_tmp(tmp);
1281 tmp = rcache_get_reg(rn, RC_GR_RMW);
1282 emith_add_r_imm(tmp, 1 << size);
1285 rcache_get_reg_arg(0, rm);
1286 *rmr = emit_memhandler_read(size);
1287 *rnr = rcache_get_tmp();
1288 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
1289 tmp = rcache_get_reg(rm, RC_GR_RMW);
1290 emith_add_r_imm(tmp, 1 << size);
1294 static void emit_do_static_regs(int is_write, int tmpr)
1298 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
1303 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
1304 if (reg_map_g2h[i + 1] != r + 1)
1310 // i, r point to last item
1312 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1314 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1317 emith_ctx_write(r, i * 4);
1319 emith_ctx_read(r, i * 4);
1324 static void emit_block_entry(void)
1328 host_arg2reg(arg0, 0);
1330 #if (DRC_DEBUG & 8) || defined(PDB)
1332 host_arg2reg(arg1, 1);
1333 host_arg2reg(arg2, 2);
1335 emit_do_static_regs(1, arg2);
1336 emith_move_r_r(arg1, CONTEXT_REG);
1337 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
1338 emith_call(sh2_drc_log_entry);
1339 rcache_invalidate();
1341 emith_tst_r_r(arg0, arg0);
1342 EMITH_SJMP_START(DCOND_EQ);
1343 emith_jump_reg_c(DCOND_NE, arg0);
1344 EMITH_SJMP_END(DCOND_EQ);
1347 #define DELAY_SAVE_T(sr) { \
1348 emith_bic_r_imm(sr, T_save); \
1349 emith_tst_r_imm(sr, T); \
1350 EMITH_SJMP_START(DCOND_EQ); \
1351 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
1352 EMITH_SJMP_END(DCOND_EQ); \
1355 #define FLUSH_CYCLES(sr) \
1357 emith_sub_r_imm(sr, cycles << 12); \
1361 static void *dr_get_pc_base(u32 pc, int is_slave);
1363 static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
1365 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
1366 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
1367 int branch_target_count = 0;
1368 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
1369 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
1370 int branch_patch_count = 0;
1371 u32 literal_addr[MAX_LITERALS];
1372 int literal_addr_count = 0;
1373 u8 op_flags[BLOCK_INSN_LIMIT];
1376 u32 pending_branch_direct:1;
1377 u32 pending_branch_indirect:1;
1378 u32 literals_disabled:1;
1381 // PC of current, first, last SH2 insn
1382 u32 pc, base_pc, end_pc;
1384 void *block_entry_ptr;
1385 struct block_desc *block;
1387 struct op_data *opd;
1396 drcf.literals_disabled = literal_disabled_frames != 0;
1398 // get base/validate PC
1399 dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave);
1400 if (dr_pc_base == (void *)-1) {
1401 printf("invalid PC, aborting: %08x\n", base_pc);
1402 // FIXME: be less destructive
1406 tcache_ptr = tcache_ptrs[tcache_id];
1408 // predict tcache overflow
1409 tmp = tcache_ptr - tcache_bases[tcache_id];
1410 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
1411 dbg(1, "tcache %d overflow", tcache_id);
1415 // initial passes to disassemble and analyze the block
1416 scan_block(base_pc, sh2->is_slave, op_flags, &end_pc, &end_literals);
1418 if (drcf.literals_disabled)
1419 end_literals = end_pc;
1421 block = dr_add_block(base_pc, end_literals - base_pc,
1422 end_pc - base_pc, sh2->is_slave, &blkid_main);
1426 block_entry_ptr = tcache_ptr;
1427 dbg(2, "== %csh2 block #%d,%d %08x-%08x -> %p", sh2->is_slave ? 's' : 'm',
1428 tcache_id, blkid_main, base_pc, end_pc, block_entry_ptr);
1430 dr_link_blocks(&block->entryp[0], tcache_id);
1432 // collect branch_targets that don't land on delay slots
1433 for (pc = base_pc, i = 0; pc < end_pc; i++, pc += 2) {
1434 if (!(op_flags[i] & OF_BTARGET))
1436 if (op_flags[i] & OF_DELAY_OP) {
1437 op_flags[i] &= ~OF_BTARGET;
1440 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
1443 if (branch_target_count > 0) {
1444 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
1447 // clear stale state after compile errors
1448 rcache_invalidate();
1450 // -------------------------------------------------
1451 // 3rd pass: actual compilation
1454 for (i = 0; pc < end_pc; i++)
1456 u32 delay_dep_fw = 0, delay_dep_bk = 0;
1466 DasmSH2(sh2dasm_buff, pc, op);
1467 printf("%c%08x %04x %s\n", (op_flags[i] & OF_BTARGET) ? '*' : ' ',
1468 pc, op, sh2dasm_buff);
1471 if ((op_flags[i] & OF_BTARGET) || pc == base_pc)
1475 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1480 v = block->entry_count;
1481 if (v < ARRAY_SIZE(block->entryp)) {
1482 block->entryp[v].pc = pc;
1483 block->entryp[v].tcache_ptr = tcache_ptr;
1484 block->entryp[v].links = NULL;
1486 block->entryp[v].block = block;
1488 add_to_hashlist(&block->entryp[v], tcache_id);
1489 block->entry_count++;
1491 dbg(2, "-- %csh2 block #%d,%d entry %08x -> %p",
1492 sh2->is_slave ? 's' : 'm', tcache_id, blkid_main,
1495 // since we made a block entry, link any other blocks
1496 // that jump to current pc
1497 dr_link_blocks(&block->entryp[v], tcache_id);
1500 dbg(1, "too many entryp for block #%d,%d pc=%08x",
1501 tcache_id, blkid_main, pc);
1504 do_host_disasm(tcache_id);
1507 v = find_in_array(branch_target_pc, branch_target_count, pc);
1509 branch_target_ptr[v] = tcache_ptr;
1512 emit_move_r_imm32(SHR_PC, pc);
1516 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1517 emith_cmp_r_imm(sr, 0);
1518 emith_jump_cond(DCOND_LE, sh2_drc_exit);
1519 do_host_disasm(tcache_id);
1520 rcache_unlock_all();
1524 if (!(op_flags[i] & OF_DELAY_OP)) {
1525 emit_move_r_imm32(SHR_PC, pc);
1526 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1530 tmp = rcache_used_hreg_mask();
1531 emith_save_caller_regs(tmp);
1532 emit_do_static_regs(1, 0);
1533 emith_pass_arg_r(0, CONTEXT_REG);
1534 emith_call(do_sh2_cmp);
1535 emith_restore_caller_regs(tmp);
1546 if (op_flags[i] & OF_DELAY_OP)
1548 // handle delay slot dependencies
1549 delay_dep_fw = opd->dest & ops[i-1].source;
1550 delay_dep_bk = opd->source & ops[i-1].dest;
1551 if (delay_dep_fw & BITMASK1(SHR_T)) {
1552 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1555 if (delay_dep_bk & BITMASK1(SHR_PC)) {
1556 if (opd->op != OP_LOAD_POOL && opd->op != OP_MOVA) {
1557 // can only be those 2 really..
1558 elprintf_sh2(sh2, EL_ANOMALY,
1559 "drc: illegal slot insn %04x @ %08x?", op, pc - 2);
1562 ; // addr already resolved somehow
1564 switch (ops[i-1].op) {
1566 emit_move_r_imm32(SHR_PC, ops[i-1].imm);
1570 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1571 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1572 emith_move_r_imm(tmp, pc);
1573 emith_tst_r_imm(sr, T);
1574 tmp2 = ops[i-1].op == OP_BRANCH_CT ? DCOND_NE : DCOND_EQ;
1575 emith_move_r_imm_c(tmp2, tmp, ops[i-1].imm);
1577 // case OP_BRANCH_R OP_BRANCH_RF - PC already loaded
1581 //if (delay_dep_fw & ~BITMASK1(SHR_T))
1582 // dbg(1, "unhandled delay_dep_fw: %x", delay_dep_fw & ~BITMASK1(SHR_T));
1583 if (delay_dep_bk & ~BITMASK2(SHR_PC, SHR_PR))
1584 dbg(1, "unhandled delay_dep_bk: %x", delay_dep_bk);
1592 if (opd->dest & BITMASK1(SHR_PR))
1593 emit_move_r_imm32(SHR_PR, pc + 2);
1594 drcf.pending_branch_direct = 1;
1598 if (opd->dest & BITMASK1(SHR_PR))
1599 emit_move_r_imm32(SHR_PR, pc + 2);
1600 emit_move_r_r(SHR_PC, opd->rm);
1601 drcf.pending_branch_indirect = 1;
1605 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1606 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1607 if (opd->dest & BITMASK1(SHR_PR)) {
1608 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
1609 emith_move_r_imm(tmp3, pc + 2);
1610 emith_add_r_r_r(tmp, tmp2, tmp3);
1613 emith_move_r_r(tmp, tmp2);
1614 emith_add_r_imm(tmp, pc + 2);
1616 drcf.pending_branch_indirect = 1;
1620 printf("TODO sleep\n");
1625 emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2);
1627 tmp = rcache_get_reg_arg(0, SHR_SP);
1628 emith_add_r_imm(tmp, 4);
1629 tmp = emit_memhandler_read(2);
1630 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1631 emith_write_sr(sr, tmp);
1632 rcache_free_tmp(tmp);
1633 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1634 emith_add_r_imm(tmp, 4*2);
1636 drcf.pending_branch_indirect = 1;
1640 #if PROPAGATE_CONSTANTS
1641 if (opd->imm != 0 && opd->imm < end_literals
1642 && literal_addr_count < MAX_LITERALS)
1644 ADD_TO_ARRAY(literal_addr, literal_addr_count, opd->imm,);
1646 tmp = FETCH32(opd->imm);
1648 tmp = (u32)(int)(signed short)FETCH_OP(opd->imm);
1649 gconst_new(GET_Rn(), tmp);
1654 tmp = rcache_get_tmp_arg(0);
1656 emith_move_r_imm(tmp, opd->imm);
1658 // have to calculate read addr from PC
1659 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
1660 if (opd->size == 2) {
1661 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
1662 emith_bic_r_imm(tmp, 3);
1665 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 2);
1667 tmp2 = emit_memhandler_read(opd->size);
1668 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1670 emith_move_r_r(tmp3, tmp2);
1672 emith_sext(tmp3, tmp2, 16);
1673 rcache_free_tmp(tmp2);
1679 emit_move_r_imm32(SHR_R0, opd->imm);
1681 tmp = rcache_get_reg(SHR_R0, RC_GR_WRITE);
1682 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
1683 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
1684 emith_bic_r_imm(tmp, 3);
1689 switch ((op >> 12) & 0x0f)
1691 /////////////////////////////////////////////
1696 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1699 case 0: // STC SR,Rn 0000nnnn00000010
1702 case 1: // STC GBR,Rn 0000nnnn00010010
1705 case 2: // STC VBR,Rn 0000nnnn00100010
1711 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
1712 emith_move_r_r(tmp, tmp3);
1714 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
1716 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
1717 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
1718 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
1720 tmp = rcache_get_reg_arg(1, GET_Rm());
1721 tmp2 = rcache_get_reg_arg(0, SHR_R0);
1722 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1723 emith_add_r_r(tmp2, tmp3);
1724 emit_memhandler_write(op & 3);
1727 // MUL.L Rm,Rn 0000nnnnmmmm0111
1728 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1729 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1730 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1731 emith_mul(tmp3, tmp2, tmp);
1736 case 0: // CLRT 0000000000001000
1737 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1738 emith_bic_r_imm(sr, T);
1740 case 1: // SETT 0000000000011000
1741 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1742 emith_or_r_imm(sr, T);
1744 case 2: // CLRMAC 0000000000101000
1745 emit_move_r_imm32(SHR_MACL, 0);
1746 emit_move_r_imm32(SHR_MACH, 0);
1755 case 0: // NOP 0000000000001001
1757 case 1: // DIV0U 0000000000011001
1758 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1759 emith_bic_r_imm(sr, M|Q|T);
1761 case 2: // MOVT Rn 0000nnnn00101001
1762 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1763 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1764 emith_clear_msb(tmp2, sr, 31);
1771 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1774 case 0: // STS MACH,Rn 0000nnnn00001010
1777 case 1: // STS MACL,Rn 0000nnnn00011010
1780 case 2: // STS PR,Rn 0000nnnn00101010
1786 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1787 emith_move_r_r(tmp, tmp2);
1789 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1790 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1791 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1792 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1793 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1794 if ((op & 3) != 2) {
1795 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1797 emith_move_r_r(tmp2, tmp);
1798 rcache_free_tmp(tmp);
1800 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1801 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1802 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1803 /* MS 16 MAC bits unused if saturated */
1804 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1805 emith_tst_r_imm(sr, S);
1806 EMITH_SJMP_START(DCOND_EQ);
1807 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1808 EMITH_SJMP_END(DCOND_EQ);
1810 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1811 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1812 rcache_free_tmp(tmp2);
1813 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1814 emith_tst_r_imm(sr, S);
1816 EMITH_JMP_START(DCOND_EQ);
1817 emith_asr(tmp, tmp4, 15);
1818 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1819 EMITH_SJMP_START(DCOND_GE);
1820 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1821 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1822 EMITH_SJMP_END(DCOND_GE);
1823 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1824 EMITH_SJMP_START(DCOND_LE);
1825 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1826 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1827 EMITH_SJMP_END(DCOND_LE);
1828 EMITH_JMP_END(DCOND_EQ);
1830 rcache_free_tmp(tmp);
1835 /////////////////////////////////////////////
1837 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1839 tmp = rcache_get_reg_arg(0, GET_Rn());
1840 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1842 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1843 emit_memhandler_write(2);
1849 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1850 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1851 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1853 rcache_get_reg_arg(0, GET_Rn());
1854 rcache_get_reg_arg(1, GET_Rm());
1855 emit_memhandler_write(op & 3);
1857 case 0x04: // MOV.B Rm,@-Rn 0010nnnnmmmm0100
1858 case 0x05: // MOV.W Rm,@-Rn 0010nnnnmmmm0101
1859 case 0x06: // MOV.L Rm,@-Rn 0010nnnnmmmm0110
1860 rcache_get_reg_arg(1, GET_Rm()); // for Rm == Rn
1861 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1862 emith_sub_r_imm(tmp, (1 << (op & 3)));
1864 rcache_get_reg_arg(0, GET_Rn());
1865 emit_memhandler_write(op & 3);
1867 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1868 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1869 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1870 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1871 emith_bic_r_imm(sr, M|Q|T);
1872 emith_tst_r_imm(tmp2, (1<<31));
1873 EMITH_SJMP_START(DCOND_EQ);
1874 emith_or_r_imm_c(DCOND_NE, sr, Q);
1875 EMITH_SJMP_END(DCOND_EQ);
1876 emith_tst_r_imm(tmp3, (1<<31));
1877 EMITH_SJMP_START(DCOND_EQ);
1878 emith_or_r_imm_c(DCOND_NE, sr, M);
1879 EMITH_SJMP_END(DCOND_EQ);
1880 emith_teq_r_r(tmp2, tmp3);
1881 EMITH_SJMP_START(DCOND_PL);
1882 emith_or_r_imm_c(DCOND_MI, sr, T);
1883 EMITH_SJMP_END(DCOND_PL);
1885 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1886 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1887 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1888 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1889 emith_bic_r_imm(sr, T);
1890 emith_tst_r_r(tmp2, tmp3);
1891 emit_or_t_if_eq(sr);
1893 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1894 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1895 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1896 emith_and_r_r(tmp, tmp2);
1898 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1899 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1900 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1901 emith_eor_r_r(tmp, tmp2);
1903 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1904 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1905 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1906 emith_or_r_r(tmp, tmp2);
1908 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1909 tmp = rcache_get_tmp();
1910 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1911 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1912 emith_eor_r_r_r(tmp, tmp2, tmp3);
1913 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1914 emith_bic_r_imm(sr, T);
1915 emith_tst_r_imm(tmp, 0x000000ff);
1916 emit_or_t_if_eq(sr);
1917 emith_tst_r_imm(tmp, 0x0000ff00);
1918 emit_or_t_if_eq(sr);
1919 emith_tst_r_imm(tmp, 0x00ff0000);
1920 emit_or_t_if_eq(sr);
1921 emith_tst_r_imm(tmp, 0xff000000);
1922 emit_or_t_if_eq(sr);
1923 rcache_free_tmp(tmp);
1925 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1926 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1927 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1928 emith_lsr(tmp, tmp, 16);
1929 emith_or_r_r_lsl(tmp, tmp2, 16);
1931 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1932 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1933 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1934 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1936 emith_sext(tmp, tmp2, 16);
1938 emith_clear_msb(tmp, tmp2, 16);
1939 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1940 tmp2 = rcache_get_tmp();
1942 emith_sext(tmp2, tmp3, 16);
1944 emith_clear_msb(tmp2, tmp3, 16);
1945 emith_mul(tmp, tmp, tmp2);
1946 rcache_free_tmp(tmp2);
1951 /////////////////////////////////////////////
1955 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
1956 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
1957 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
1958 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
1959 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
1960 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1961 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1962 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1963 emith_bic_r_imm(sr, T);
1964 emith_cmp_r_r(tmp2, tmp3);
1967 case 0x00: // CMP/EQ
1968 emit_or_t_if_eq(sr);
1970 case 0x02: // CMP/HS
1971 EMITH_SJMP_START(DCOND_LO);
1972 emith_or_r_imm_c(DCOND_HS, sr, T);
1973 EMITH_SJMP_END(DCOND_LO);
1975 case 0x03: // CMP/GE
1976 EMITH_SJMP_START(DCOND_LT);
1977 emith_or_r_imm_c(DCOND_GE, sr, T);
1978 EMITH_SJMP_END(DCOND_LT);
1980 case 0x06: // CMP/HI
1981 EMITH_SJMP_START(DCOND_LS);
1982 emith_or_r_imm_c(DCOND_HI, sr, T);
1983 EMITH_SJMP_END(DCOND_LS);
1985 case 0x07: // CMP/GT
1986 EMITH_SJMP_START(DCOND_LE);
1987 emith_or_r_imm_c(DCOND_GT, sr, T);
1988 EMITH_SJMP_END(DCOND_LE);
1992 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
1993 // Q1 = carry(Rn = (Rn << 1) | T)
1995 // Q2 = carry(Rn += Rm)
1997 // Q2 = carry(Rn -= Rm)
1999 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
2000 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2001 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2002 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2003 emith_tpop_carry(sr, 0);
2004 emith_adcf_r_r(tmp2, tmp2);
2005 emith_tpush_carry(sr, 0); // keep Q1 in T for now
2006 tmp4 = rcache_get_tmp();
2007 emith_and_r_r_imm(tmp4, sr, M);
2008 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
2009 rcache_free_tmp(tmp4);
2010 // add or sub, invert T if carry to get Q1 ^ Q2
2011 // in: (Q ^ M) passed in Q, Q1 in T
2012 emith_sh2_div1_step(tmp2, tmp3, sr);
2013 emith_bic_r_imm(sr, Q);
2014 emith_tst_r_imm(sr, M);
2015 EMITH_SJMP_START(DCOND_EQ);
2016 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
2017 EMITH_SJMP_END(DCOND_EQ);
2018 emith_tst_r_imm(sr, T);
2019 EMITH_SJMP_START(DCOND_EQ);
2020 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
2021 EMITH_SJMP_END(DCOND_EQ);
2022 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
2024 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
2025 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2026 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2027 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
2028 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
2029 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
2031 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
2032 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
2033 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2034 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2036 emith_add_r_r(tmp, tmp2);
2038 emith_sub_r_r(tmp, tmp2);
2040 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
2041 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
2042 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2043 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2044 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2045 if (op & 4) { // adc
2046 emith_tpop_carry(sr, 0);
2047 emith_adcf_r_r(tmp, tmp2);
2048 emith_tpush_carry(sr, 0);
2050 emith_tpop_carry(sr, 1);
2051 emith_sbcf_r_r(tmp, tmp2);
2052 emith_tpush_carry(sr, 1);
2055 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
2056 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
2057 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2058 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2059 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2060 emith_bic_r_imm(sr, T);
2062 emith_addf_r_r(tmp, tmp2);
2064 emith_subf_r_r(tmp, tmp2);
2065 EMITH_SJMP_START(DCOND_VC);
2066 emith_or_r_imm_c(DCOND_VS, sr, T);
2067 EMITH_SJMP_END(DCOND_VC);
2069 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
2070 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2071 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2072 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
2073 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
2074 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
2079 /////////////////////////////////////////////
2086 case 0: // SHLL Rn 0100nnnn00000000
2087 case 2: // SHAL Rn 0100nnnn00100000
2088 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2089 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2090 emith_tpop_carry(sr, 0); // dummy
2091 emith_lslf(tmp, tmp, 1);
2092 emith_tpush_carry(sr, 0);
2094 case 1: // DT Rn 0100nnnn00010000
2095 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2096 #if 0 // scheduling needs tuning
2097 if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
2098 if (gconst_get(GET_Rn(), &tmp)) {
2099 // XXX: limit burned cycles
2100 emit_move_r_imm32(GET_Rn(), 0);
2101 emith_or_r_imm(sr, T);
2102 cycles += tmp * 4 + 1; // +1 syncs with noconst version, not sure why
2106 emith_sh2_dtbf_loop();
2110 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2111 emith_bic_r_imm(sr, T);
2112 emith_subf_r_imm(tmp, 1);
2113 emit_or_t_if_eq(sr);
2120 case 0: // SHLR Rn 0100nnnn00000001
2121 case 2: // SHAR Rn 0100nnnn00100001
2122 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2123 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2124 emith_tpop_carry(sr, 0); // dummy
2126 emith_asrf(tmp, tmp, 1);
2128 emith_lsrf(tmp, tmp, 1);
2129 emith_tpush_carry(sr, 0);
2131 case 1: // CMP/PZ Rn 0100nnnn00010001
2132 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2133 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2134 emith_bic_r_imm(sr, T);
2135 emith_cmp_r_imm(tmp, 0);
2136 EMITH_SJMP_START(DCOND_LT);
2137 emith_or_r_imm_c(DCOND_GE, sr, T);
2138 EMITH_SJMP_END(DCOND_LT);
2146 case 0x02: // STS.L MACH,@-Rn 0100nnnn00000010
2149 case 0x12: // STS.L MACL,@-Rn 0100nnnn00010010
2152 case 0x22: // STS.L PR,@-Rn 0100nnnn00100010
2155 case 0x03: // STC.L SR,@-Rn 0100nnnn00000011
2158 case 0x13: // STC.L GBR,@-Rn 0100nnnn00010011
2161 case 0x23: // STC.L VBR,@-Rn 0100nnnn00100011
2167 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2168 emith_sub_r_imm(tmp2, 4);
2170 rcache_get_reg_arg(0, GET_Rn());
2171 tmp3 = rcache_get_reg_arg(1, tmp);
2173 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
2174 emit_memhandler_write(2);
2180 case 0x04: // ROTL Rn 0100nnnn00000100
2181 case 0x05: // ROTR Rn 0100nnnn00000101
2182 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2183 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2184 emith_tpop_carry(sr, 0); // dummy
2186 emith_rorf(tmp, tmp, 1);
2188 emith_rolf(tmp, tmp, 1);
2189 emith_tpush_carry(sr, 0);
2191 case 0x24: // ROTCL Rn 0100nnnn00100100
2192 case 0x25: // ROTCR Rn 0100nnnn00100101
2193 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2194 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2195 emith_tpop_carry(sr, 0);
2200 emith_tpush_carry(sr, 0);
2202 case 0x15: // CMP/PL Rn 0100nnnn00010101
2203 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2204 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2205 emith_bic_r_imm(sr, T);
2206 emith_cmp_r_imm(tmp, 0);
2207 EMITH_SJMP_START(DCOND_LE);
2208 emith_or_r_imm_c(DCOND_GT, sr, T);
2209 EMITH_SJMP_END(DCOND_LE);
2217 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
2220 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
2223 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
2226 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
2229 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
2232 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
2238 rcache_get_reg_arg(0, GET_Rn());
2239 tmp2 = emit_memhandler_read(2);
2240 if (tmp == SHR_SR) {
2241 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2242 emith_write_sr(sr, tmp2);
2245 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
2246 emith_move_r_r(tmp, tmp2);
2248 rcache_free_tmp(tmp2);
2249 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2250 emith_add_r_imm(tmp, 4);
2257 // SHLL2 Rn 0100nnnn00001000
2258 // SHLR2 Rn 0100nnnn00001001
2262 // SHLL8 Rn 0100nnnn00011000
2263 // SHLR8 Rn 0100nnnn00011001
2267 // SHLL16 Rn 0100nnnn00101000
2268 // SHLR16 Rn 0100nnnn00101001
2274 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2276 emith_lsr(tmp2, tmp2, tmp);
2278 emith_lsl(tmp2, tmp2, tmp);
2283 case 0: // LDS Rm,MACH 0100mmmm00001010
2286 case 1: // LDS Rm,MACL 0100mmmm00011010
2289 case 2: // LDS Rm,PR 0100mmmm00101010
2295 emit_move_r_r(tmp2, GET_Rn());
2300 case 1: // TAS.B @Rn 0100nnnn00011011
2301 // XXX: is TAS working on 32X?
2302 rcache_get_reg_arg(0, GET_Rn());
2303 tmp = emit_memhandler_read(0);
2304 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2305 emith_bic_r_imm(sr, T);
2306 emith_cmp_r_imm(tmp, 0);
2307 emit_or_t_if_eq(sr);
2309 emith_or_r_imm(tmp, 0x80);
2310 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
2311 emith_move_r_r(tmp2, tmp);
2312 rcache_free_tmp(tmp);
2313 rcache_get_reg_arg(0, GET_Rn());
2314 emit_memhandler_write(0);
2321 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2324 case 0: // LDC Rm,SR 0100mmmm00001110
2327 case 1: // LDC Rm,GBR 0100mmmm00011110
2330 case 2: // LDC Rm,VBR 0100mmmm00101110
2336 if (tmp2 == SHR_SR) {
2337 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2338 emith_write_sr(sr, tmp);
2341 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
2342 emith_move_r_r(tmp2, tmp);
2346 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
2347 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
2348 emith_sext(tmp, tmp, 16);
2349 emith_sext(tmp2, tmp2, 16);
2350 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
2351 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
2352 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
2353 rcache_free_tmp(tmp2);
2354 // XXX: MACH should be untouched when S is set?
2355 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2356 emith_tst_r_imm(sr, S);
2357 EMITH_JMP_START(DCOND_EQ);
2359 emith_asr(tmp, tmp3, 31);
2360 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
2361 EMITH_JMP_START(DCOND_EQ);
2362 emith_move_r_imm(tmp3, 0x80000000);
2363 emith_tst_r_r(tmp4, tmp4);
2364 EMITH_SJMP_START(DCOND_MI);
2365 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
2366 EMITH_SJMP_END(DCOND_MI);
2367 EMITH_JMP_END(DCOND_EQ);
2369 EMITH_JMP_END(DCOND_EQ);
2370 rcache_free_tmp(tmp);
2375 /////////////////////////////////////////////
2377 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
2378 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2);
2381 /////////////////////////////////////////////
2385 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
2386 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
2387 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
2388 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
2389 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
2390 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
2391 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), 0, op & 3);
2392 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
2393 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
2394 emith_add_r_imm(tmp, (1 << (op & 3)));
2399 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
2400 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2403 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
2404 emith_move_r_r(tmp2, tmp);
2406 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
2407 emith_mvn_r_r(tmp2, tmp);
2409 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
2412 tmp3 = rcache_get_tmp();
2413 tmp4 = rcache_get_tmp();
2414 emith_lsr(tmp3, tmp, 16);
2415 emith_or_r_r_lsl(tmp3, tmp, 24);
2416 emith_and_r_r_imm(tmp4, tmp, 0xff00);
2417 emith_or_r_r_lsl(tmp3, tmp4, 8);
2418 emith_rol(tmp2, tmp3, 16);
2419 rcache_free_tmp(tmp4);
2421 rcache_free_tmp(tmp3);
2423 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
2424 emith_rol(tmp2, tmp, 16);
2426 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
2427 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2428 emith_tpop_carry(sr, 1);
2429 emith_negcf_r_r(tmp2, tmp);
2430 emith_tpush_carry(sr, 1);
2432 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
2433 emith_neg_r_r(tmp2, tmp);
2435 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
2436 emith_clear_msb(tmp2, tmp, 24);
2438 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
2439 emith_clear_msb(tmp2, tmp, 16);
2441 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
2442 emith_sext(tmp2, tmp, 8);
2444 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
2445 emith_sext(tmp2, tmp, 16);
2452 /////////////////////////////////////////////
2454 // ADD #imm,Rn 0111nnnniiiiiiii
2455 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2456 if (op & 0x80) { // adding negative
2457 emith_sub_r_imm(tmp, -op & 0xff);
2459 emith_add_r_imm(tmp, op & 0xff);
2462 /////////////////////////////////////////////
2464 switch (op & 0x0f00)
2466 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
2467 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
2469 tmp = rcache_get_reg_arg(0, GET_Rm());
2470 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2471 tmp3 = (op & 0x100) >> 8;
2473 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
2474 emit_memhandler_write(tmp3);
2476 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
2477 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
2478 tmp = (op & 0x100) >> 8;
2479 emit_memhandler_read_rr(SHR_R0, GET_Rm(), (op & 0x0f) << tmp, tmp);
2481 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
2482 // XXX: could use cmn
2483 tmp = rcache_get_tmp();
2484 tmp2 = rcache_get_reg(0, RC_GR_READ);
2485 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2486 emith_move_r_imm_s8(tmp, op & 0xff);
2487 emith_bic_r_imm(sr, T);
2488 emith_cmp_r_r(tmp2, tmp);
2489 emit_or_t_if_eq(sr);
2490 rcache_free_tmp(tmp);
2495 /////////////////////////////////////////////
2497 switch (op & 0x0f00)
2499 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
2500 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
2501 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
2503 tmp = rcache_get_reg_arg(0, SHR_GBR);
2504 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2505 tmp3 = (op & 0x300) >> 8;
2506 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
2507 emit_memhandler_write(tmp3);
2509 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
2510 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
2511 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
2512 tmp = (op & 0x300) >> 8;
2513 emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp);
2515 case 0x0300: // TRAPA #imm 11000011iiiiiiii
2516 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2517 emith_sub_r_imm(tmp, 4*2);
2519 tmp = rcache_get_reg_arg(0, SHR_SP);
2520 emith_add_r_imm(tmp, 4);
2521 tmp = rcache_get_reg_arg(1, SHR_SR);
2522 emith_clear_msb(tmp, tmp, 22);
2523 emit_memhandler_write(2);
2525 rcache_get_reg_arg(0, SHR_SP);
2526 tmp = rcache_get_tmp_arg(1);
2527 emith_move_r_imm(tmp, pc);
2528 emit_memhandler_write(2);
2530 emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
2531 // indirect jump -> back to dispatcher
2533 emith_jump(sh2_drc_dispatcher);
2535 case 0x0800: // TST #imm,R0 11001000iiiiiiii
2536 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
2537 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2538 emith_bic_r_imm(sr, T);
2539 emith_tst_r_imm(tmp, op & 0xff);
2540 emit_or_t_if_eq(sr);
2542 case 0x0900: // AND #imm,R0 11001001iiiiiiii
2543 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2544 emith_and_r_imm(tmp, op & 0xff);
2546 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
2547 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2548 emith_eor_r_imm(tmp, op & 0xff);
2550 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
2551 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2552 emith_or_r_imm(tmp, op & 0xff);
2554 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
2555 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2556 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2557 emith_bic_r_imm(sr, T);
2558 emith_tst_r_imm(tmp, op & 0xff);
2559 emit_or_t_if_eq(sr);
2560 rcache_free_tmp(tmp);
2562 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2563 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2564 emith_and_r_imm(tmp, op & 0xff);
2566 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2567 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2568 emith_eor_r_imm(tmp, op & 0xff);
2570 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2571 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2572 emith_or_r_imm(tmp, op & 0xff);
2574 tmp2 = rcache_get_tmp_arg(1);
2575 emith_move_r_r(tmp2, tmp);
2576 rcache_free_tmp(tmp);
2577 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2578 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2579 emith_add_r_r(tmp3, tmp4);
2580 emit_memhandler_write(0);
2585 /////////////////////////////////////////////
2587 // MOV #imm,Rn 1110nnnniiiiiiii
2588 emit_move_r_imm32(GET_Rn(), (u32)(signed int)(signed char)op);
2593 if (!(op_flags[i] & OF_B_IN_DS))
2594 elprintf_sh2(sh2, EL_ANOMALY,
2595 "drc: illegal op %04x @ %08x", op, pc - 2);
2597 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2598 emith_sub_r_imm(tmp, 4*2);
2600 tmp = rcache_get_reg_arg(0, SHR_SP);
2601 emith_add_r_imm(tmp, 4);
2602 tmp = rcache_get_reg_arg(1, SHR_SR);
2603 emith_clear_msb(tmp, tmp, 22);
2604 emit_memhandler_write(2);
2606 rcache_get_reg_arg(0, SHR_SP);
2607 tmp = rcache_get_tmp_arg(1);
2608 if (drcf.pending_branch_indirect) {
2609 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
2610 emith_move_r_r(tmp, tmp2);
2613 emith_move_r_imm(tmp, pc - 2);
2614 emit_memhandler_write(2);
2616 v = (op_flags[i] & OF_B_IN_DS) ? 6 : 4;
2617 emit_memhandler_read_rr(SHR_PC, SHR_VBR, v * 4, 2);
2618 // indirect jump -> back to dispatcher
2620 emith_jump(sh2_drc_dispatcher);
2625 rcache_unlock_all();
2627 cycles += opd->cycles;
2629 if (op_flags[i+1] & OF_DELAY_OP) {
2630 do_host_disasm(tcache_id);
2635 if (drcf.test_irq && !drcf.pending_branch_direct) {
2636 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2638 if (!drcf.pending_branch_indirect)
2639 emit_move_r_imm32(SHR_PC, pc);
2641 emith_call(sh2_drc_test_irq);
2645 // branch handling (with/without delay)
2646 if (drcf.pending_branch_direct)
2648 struct op_data *opd_b =
2649 (op_flags[i] & OF_DELAY_OP) ? &ops[i-1] : opd;
2650 u32 target_pc = opd_b->imm;
2652 void *target = NULL;
2654 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2657 if (opd_b->op != OP_BRANCH)
2658 cond = (opd_b->op == OP_BRANCH_CF) ? DCOND_EQ : DCOND_NE;
2660 int ctaken = (op_flags[i] & OF_DELAY_OP) ? 1 : 2;
2662 if (delay_dep_fw & BITMASK1(SHR_T))
2663 emith_tst_r_imm(sr, T_save);
2665 emith_tst_r_imm(sr, T);
2667 emith_sub_r_imm_c(cond, sr, ctaken<<12);
2672 if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0)
2675 // XXX: jumps back can be linked already
2676 if (branch_patch_count < MAX_LOCAL_BRANCHES) {
2677 target = tcache_ptr;
2678 branch_patch_pc[branch_patch_count] = target_pc;
2679 branch_patch_ptr[branch_patch_count] = target;
2680 branch_patch_count++;
2683 dbg(1, "warning: too many local branches");
2689 // can't resolve branch locally, make a block exit
2690 emit_move_r_imm32(SHR_PC, target_pc);
2693 target = dr_prepare_ext_branch(target_pc, sh2->is_slave, tcache_id);
2699 emith_jump_cond_patchable(cond, target);
2701 emith_jump_patchable(target);
2702 rcache_invalidate();
2705 drcf.pending_branch_direct = 0;
2707 else if (drcf.pending_branch_indirect) {
2708 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2711 emith_jump(sh2_drc_dispatcher);
2712 drcf.pending_branch_indirect = 0;
2715 do_host_disasm(tcache_id);
2718 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2722 // check the last op
2723 if (op_flags[i-1] & OF_DELAY_OP)
2728 if (opd->op != OP_BRANCH && opd->op != OP_BRANCH_R
2729 && opd->op != OP_BRANCH_RF && opd->op != OP_RTE)
2733 emit_move_r_imm32(SHR_PC, pc);
2736 target = dr_prepare_ext_branch(pc, sh2->is_slave, tcache_id);
2739 emith_jump_patchable(target);
2742 // link local branches
2743 for (i = 0; i < branch_patch_count; i++) {
2746 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2747 target = branch_target_ptr[t];
2748 if (target == NULL) {
2749 // flush pc and go back to dispatcher (this should no longer happen)
2750 dbg(1, "stray branch to %08x %p", branch_patch_pc[i], tcache_ptr);
2751 target = tcache_ptr;
2752 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2754 emith_jump(sh2_drc_dispatcher);
2756 emith_jump_patch(branch_patch_ptr[i], target);
2759 // mark memory blocks as containing compiled code
2760 // override any overlay blocks as they become unreachable anyway
2761 if ((block->addr & 0xc7fc0000) == 0x06000000
2762 || (block->addr & 0xfffff000) == 0xc0000000)
2764 u16 *drc_ram_blk = NULL;
2765 u32 addr, mask = 0, shift = 0;
2767 if (tcache_id != 0) {
2769 drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave];
2770 shift = SH2_DRCBLK_DA_SHIFT;
2775 drc_ram_blk = Pico32xMem->drcblk_ram;
2776 shift = SH2_DRCBLK_RAM_SHIFT;
2780 // mark recompiled insns
2781 drc_ram_blk[(base_pc & mask) >> shift] = 1;
2782 for (pc = base_pc; pc < end_pc; pc += 2)
2783 drc_ram_blk[(pc & mask) >> shift] = 1;
2786 for (i = 0; i < literal_addr_count; i++) {
2787 tmp = literal_addr[i];
2788 drc_ram_blk[(tmp & mask) >> shift] = 1;
2791 // add to invalidation lookup lists
2792 addr = base_pc & ~(INVAL_PAGE_SIZE - 1);
2793 for (; addr < end_literals; addr += INVAL_PAGE_SIZE) {
2794 i = (addr & mask) / INVAL_PAGE_SIZE;
2795 add_to_block_list(&inval_lookup[tcache_id][i], block);
2799 tcache_ptrs[tcache_id] = tcache_ptr;
2801 host_instructions_updated(block_entry_ptr, tcache_ptr);
2803 do_host_disasm(tcache_id);
2805 if (drcf.literals_disabled && literal_addr_count)
2806 dbg(1, "literals_disabled && literal_addr_count?");
2807 dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2808 tcache_id, blkid_main,
2809 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2810 insns_compiled, host_insn_count, (float)host_insn_count / insns_compiled);
2811 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2812 dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2815 tcache_dsm_ptrs[tcache_id] = block_entry_ptr;
2816 do_host_disasm(tcache_id);
2824 return block_entry_ptr;
2827 static void sh2_generate_utils(void)
2829 int arg0, arg1, arg2, sr, tmp;
2831 sh2_drc_write32 = p32x_sh2_write32;
2832 sh2_drc_read8 = p32x_sh2_read8;
2833 sh2_drc_read16 = p32x_sh2_read16;
2834 sh2_drc_read32 = p32x_sh2_read32;
2836 host_arg2reg(arg0, 0);
2837 host_arg2reg(arg1, 1);
2838 host_arg2reg(arg2, 2);
2839 emith_move_r_r(arg0, arg0); // nop
2841 // sh2_drc_exit(void)
2842 sh2_drc_exit = (void *)tcache_ptr;
2843 emit_do_static_regs(1, arg2);
2844 emith_sh2_drc_exit();
2846 // sh2_drc_dispatcher(void)
2847 sh2_drc_dispatcher = (void *)tcache_ptr;
2848 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2849 emith_cmp_r_imm(sr, 0);
2850 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2851 rcache_invalidate();
2852 emith_ctx_read(arg0, SHR_PC * 4);
2853 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2854 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2855 emith_call(dr_lookup_block);
2857 // lookup failed, call sh2_translate()
2858 emith_move_r_r(arg0, CONTEXT_REG);
2859 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2860 emith_call(sh2_translate);
2862 // sh2_translate() failed, flush cache and retry
2863 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2864 emith_call(flush_tcache);
2865 emith_move_r_r(arg0, CONTEXT_REG);
2866 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2867 emith_call(sh2_translate);
2869 // XXX: can't translate, fail
2870 emith_call(dr_failure);
2872 // sh2_drc_test_irq(void)
2873 // assumes it's called from main function (may jump to dispatcher)
2874 sh2_drc_test_irq = (void *)tcache_ptr;
2875 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2876 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2877 emith_lsr(arg0, sr, I_SHIFT);
2878 emith_and_r_imm(arg0, 0x0f);
2879 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2880 EMITH_SJMP_START(DCOND_GT);
2881 emith_ret_c(DCOND_LE); // nope, return
2882 EMITH_SJMP_END(DCOND_GT);
2884 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2885 emith_sub_r_imm(tmp, 4*2);
2888 tmp = rcache_get_reg_arg(0, SHR_SP);
2889 emith_add_r_imm(tmp, 4);
2890 tmp = rcache_get_reg_arg(1, SHR_SR);
2891 emith_clear_msb(tmp, tmp, 22);
2892 emith_move_r_r(arg2, CONTEXT_REG);
2893 emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
2894 rcache_invalidate();
2896 rcache_get_reg_arg(0, SHR_SP);
2897 emith_ctx_read(arg1, SHR_PC * 4);
2898 emith_move_r_r(arg2, CONTEXT_REG);
2899 emith_call(p32x_sh2_write32);
2900 rcache_invalidate();
2901 // update I, cycles, do callback
2902 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2903 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2904 emith_bic_r_imm(sr, I);
2905 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2906 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2908 emith_move_r_r(arg0, CONTEXT_REG);
2909 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2911 emith_lsl(arg0, arg0, 2);
2912 emith_ctx_read(arg1, SHR_VBR * 4);
2913 emith_add_r_r(arg0, arg1);
2914 emit_memhandler_read(2);
2915 emith_ctx_write(arg0, SHR_PC * 4);
2917 emith_add_r_imm(xSP, 4); // fix stack
2919 emith_jump(sh2_drc_dispatcher);
2920 rcache_invalidate();
2922 // sh2_drc_entry(SH2 *sh2)
2923 sh2_drc_entry = (void *)tcache_ptr;
2924 emith_sh2_drc_entry();
2925 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2926 emit_do_static_regs(0, arg2);
2927 emith_call(sh2_drc_test_irq);
2928 emith_jump(sh2_drc_dispatcher);
2930 // sh2_drc_write8(u32 a, u32 d)
2931 sh2_drc_write8 = (void *)tcache_ptr;
2932 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2933 emith_sh2_wcall(arg0, arg2);
2935 // sh2_drc_write16(u32 a, u32 d)
2936 sh2_drc_write16 = (void *)tcache_ptr;
2937 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2938 emith_sh2_wcall(arg0, arg2);
2942 #define MAKE_READ_WRAPPER(func) { \
2943 void *tmp = (void *)tcache_ptr; \
2946 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2947 emith_addf_r_r(arg2, arg0); \
2948 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2949 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2950 emith_adc_r_imm(arg2, 0x01000000); \
2951 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2952 emith_pop_and_ret(); \
2955 #define MAKE_WRITE_WRAPPER(func) { \
2956 void *tmp = (void *)tcache_ptr; \
2957 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2958 emith_addf_r_r(arg2, arg1); \
2959 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2960 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2961 emith_adc_r_imm(arg2, 0x01000000); \
2962 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2963 emith_move_r_r(arg2, CONTEXT_REG); \
2968 MAKE_READ_WRAPPER(sh2_drc_read8);
2969 MAKE_READ_WRAPPER(sh2_drc_read16);
2970 MAKE_READ_WRAPPER(sh2_drc_read32);
2971 MAKE_WRITE_WRAPPER(sh2_drc_write8);
2972 MAKE_WRITE_WRAPPER(sh2_drc_write16);
2973 MAKE_WRITE_WRAPPER(sh2_drc_write32);
2975 host_dasm_new_symbol(sh2_drc_read8);
2976 host_dasm_new_symbol(sh2_drc_read16);
2977 host_dasm_new_symbol(sh2_drc_read32);
2978 host_dasm_new_symbol(sh2_drc_write32);
2982 rcache_invalidate();
2984 host_dasm_new_symbol(sh2_drc_entry);
2985 host_dasm_new_symbol(sh2_drc_dispatcher);
2986 host_dasm_new_symbol(sh2_drc_exit);
2987 host_dasm_new_symbol(sh2_drc_test_irq);
2988 host_dasm_new_symbol(sh2_drc_write8);
2989 host_dasm_new_symbol(sh2_drc_write16);
2993 static void sh2_smc_rm_block_entry(struct block_desc *bd, int tcache_id, u32 ram_mask)
2995 struct block_link *bl, *bl_next, *bl_unresolved;
2996 u32 i, addr, end_addr;
2999 dbg(2, " killing entry %08x-%08x-%08x, blkid %d,%d",
3000 bd->addr, bd->addr + bd->size_nolit, bd->addr + bd->size,
3001 tcache_id, bd - block_tables[tcache_id]);
3002 if (bd->addr == 0 || bd->entry_count == 0) {
3003 dbg(1, " killing dead block!? %08x", bd->addr);
3007 // remove from inval_lookup
3008 addr = bd->addr & ~(INVAL_PAGE_SIZE - 1);
3009 end_addr = bd->addr + bd->size;
3010 for (; addr < end_addr; addr += INVAL_PAGE_SIZE) {
3011 i = (addr & ram_mask) / INVAL_PAGE_SIZE;
3012 rm_from_block_list(&inval_lookup[tcache_id][i], bd);
3016 bl_unresolved = unresolved_links[tcache_id];
3018 // remove from hash table, make incoming links unresolved
3019 // XXX: maybe patch branches w/flush instead?
3020 for (i = 0; i < bd->entry_count; i++) {
3021 rm_from_hashlist(&bd->entryp[i], tcache_id);
3023 // since we never reuse tcache space of dead blocks,
3024 // insert jump to dispatcher for blocks that are linked to this
3025 tcache_ptr = bd->entryp[i].tcache_ptr;
3026 emit_move_r_imm32(SHR_PC, bd->entryp[i].pc);
3028 emith_jump(sh2_drc_dispatcher);
3030 host_instructions_updated(bd->entryp[i].tcache_ptr, tcache_ptr);
3032 for (bl = bd->entryp[i].links; bl != NULL; ) {
3034 bl->next = bl_unresolved;
3041 unresolved_links[tcache_id] = bl_unresolved;
3043 bd->addr = bd->size = bd->size_nolit = 0;
3044 bd->entry_count = 0;
3047 static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask)
3049 struct block_list **blist = NULL, *entry;
3050 u32 from = ~0, to = 0, end_addr, taddr, i;
3051 struct block_desc *block;
3053 blist = &inval_lookup[tcache_id][(a & mask) / INVAL_PAGE_SIZE];
3055 while (entry != NULL) {
3056 block = entry->block;
3057 end_addr = block->addr + block->size;
3058 if (block->addr <= a && a < end_addr) {
3059 // get addr range that includes all removed blocks
3060 if (from > block->addr)
3065 sh2_smc_rm_block_entry(block, tcache_id, mask);
3066 if (a >= block->addr + block->size_nolit)
3067 literal_disabled_frames = 3;
3069 // entry lost, restart search
3073 entry = entry->next;
3079 // update range around a to match latest state
3080 from &= ~(INVAL_PAGE_SIZE - 1);
3081 to |= (INVAL_PAGE_SIZE - 1);
3082 for (taddr = from; taddr < to; taddr += INVAL_PAGE_SIZE) {
3083 i = (taddr & mask) / INVAL_PAGE_SIZE;
3084 entry = inval_lookup[tcache_id][i];
3086 for (; entry != NULL; entry = entry->next) {
3087 block = entry->block;
3089 if (block->addr > a) {
3090 if (to > block->addr)
3094 end_addr = block->addr + block->size;
3095 if (from < end_addr)
3103 u16 *p = drc_ram_blk + ((from & mask) >> shift);
3104 memset(p, 0, (to - from) >> (shift - 1));
3108 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
3110 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3111 sh2_smc_rm_block(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
3114 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
3116 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3117 sh2_smc_rm_block(a, Pico32xMem->drcblk_da[cpuid],
3118 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
3121 int sh2_execute_drc(SH2 *sh2c, int cycles)
3125 // cycles are kept in SHR_SR unused bits (upper 20)
3126 // bit11 contains T saved for delay slot
3127 // others are usual SH2 flags
3129 sh2c->sr |= cycles << 12;
3130 sh2_drc_entry(sh2c);
3133 ret_cycles = (signed int)sh2c->sr >> 12;
3135 dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
3142 void block_stats(void)
3144 int c, b, i, total = 0;
3146 printf("block stats:\n");
3147 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3148 for (i = 0; i < block_counts[b]; i++)
3149 if (block_tables[b][i].addr != 0)
3150 total += block_tables[b][i].refcount;
3152 for (c = 0; c < 10; c++) {
3153 struct block_desc *blk, *maxb = NULL;
3155 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
3156 for (i = 0; i < block_counts[b]; i++) {
3157 blk = &block_tables[b][i];
3158 if (blk->addr != 0 && blk->refcount > max) {
3159 max = blk->refcount;
3166 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
3167 (double)maxb->refcount / total * 100.0);
3171 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3172 for (i = 0; i < block_counts[b]; i++)
3173 block_tables[b][i].refcount = 0;
3176 #define block_stats()
3179 void sh2_drc_flush_all(void)
3187 void sh2_drc_mem_setup(SH2 *sh2)
3189 // fill the convenience pointers
3190 sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w;
3191 sh2->p_da = sh2->data_array;
3192 sh2->p_sdram = Pico32xMem->sdram;
3193 sh2->p_rom = Pico.rom;
3196 void sh2_drc_frame(void)
3198 if (literal_disabled_frames > 0)
3199 literal_disabled_frames--;
3202 int sh2_drc_init(SH2 *sh2)
3206 if (block_tables[0] == NULL)
3208 for (i = 0; i < TCACHE_BUFFERS; i++) {
3209 block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0]));
3210 if (block_tables[i] == NULL)
3212 // max 2 block links (exits) per block
3213 block_link_pool[i] = calloc(block_link_pool_max_counts[i],
3214 sizeof(*block_link_pool[0]));
3215 if (block_link_pool[i] == NULL)
3218 inval_lookup[i] = calloc(ram_sizes[i] / INVAL_PAGE_SIZE,
3219 sizeof(inval_lookup[0]));
3220 if (inval_lookup[i] == NULL)
3223 hash_tables[i] = calloc(hash_table_sizes[i], sizeof(*hash_tables[0]));
3224 if (hash_tables[i] == NULL)
3227 memset(block_counts, 0, sizeof(block_counts));
3228 memset(block_link_pool_counts, 0, sizeof(block_link_pool_counts));
3231 tcache_ptr = tcache;
3232 sh2_generate_utils();
3233 host_instructions_updated(tcache, tcache_ptr);
3235 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
3236 for (i = 1; i < ARRAY_SIZE(tcache_bases); i++)
3237 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
3240 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
3241 tcache_dsm_ptrs[i] = tcache_bases[i];
3243 tcache_dsm_ptrs[0] = tcache;
3247 hash_collisions = 0;
3254 sh2_drc_finish(sh2);
3258 void sh2_drc_finish(SH2 *sh2)
3262 if (block_tables[0] == NULL)
3265 sh2_drc_flush_all();
3267 for (i = 0; i < TCACHE_BUFFERS; i++) {
3269 printf("~~~ tcache %d\n", i);
3270 tcache_dsm_ptrs[i] = tcache_bases[i];
3271 tcache_ptr = tcache_ptrs[i];
3275 if (block_tables[i] != NULL)
3276 free(block_tables[i]);
3277 block_tables[i] = NULL;
3278 if (block_link_pool[i] == NULL)
3279 free(block_link_pool[i]);
3280 block_link_pool[i] = NULL;
3282 if (inval_lookup[i] == NULL)
3283 free(inval_lookup[i]);
3284 inval_lookup[i] = NULL;
3286 if (hash_tables[i] != NULL) {
3287 free(hash_tables[i]);
3288 hash_tables[i] = NULL;
3295 #endif /* DRC_SH2 */
3297 static void *dr_get_pc_base(u32 pc, int is_slave)
3302 if ((pc & ~0x7ff) == 0) {
3304 ret = is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w;
3307 else if ((pc & 0xfffff000) == 0xc0000000) {
3309 ret = sh2s[is_slave].data_array;
3312 else if ((pc & 0xc6000000) == 0x06000000) {
3314 ret = Pico32xMem->sdram;
3317 else if ((pc & 0xc6000000) == 0x02000000) {
3319 if ((pc & 0x3fffff) < Pico.romsize)
3325 return (void *)-1; // NULL is valid value
3327 return (char *)ret - (pc & ~mask);
3330 void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
3331 u32 *end_literals_out)
3335 u32 end_pc, end_literals = 0;
3336 u32 lowest_mova = 0;
3337 struct op_data *opd;
3338 int next_is_delay = 0;
3342 memset(op_flags, 0, BLOCK_INSN_LIMIT);
3344 dr_pc_base = dr_get_pc_base(base_pc, is_slave);
3346 // 1st pass: disassemble
3347 for (i = 0, pc = base_pc; ; i++, pc += 2) {
3348 // we need an ops[] entry after the last one initialized,
3349 // so do it before end_block checks
3351 opd->op = OP_UNHANDLED;
3353 opd->source = opd->dest = 0;
3357 if (next_is_delay) {
3358 op_flags[i] |= OF_DELAY_OP;
3361 else if (end_block || i >= BLOCK_INSN_LIMIT - 2)
3365 switch ((op & 0xf000) >> 12)
3367 /////////////////////////////////////////////
3374 case 0: // STC SR,Rn 0000nnnn00000010
3377 case 1: // STC GBR,Rn 0000nnnn00010010
3380 case 2: // STC VBR,Rn 0000nnnn00100010
3387 opd->source = BITMASK1(tmp);
3388 opd->dest = BITMASK1(GET_Rn());
3391 CHECK_UNHANDLED_BITS(0xd0, undefined);
3392 // BRAF Rm 0000mmmm00100011
3393 // BSRF Rm 0000mmmm00000011
3394 opd->op = OP_BRANCH_RF;
3396 opd->source = BITMASK1(opd->rm);
3397 opd->dest = BITMASK1(SHR_PC);
3399 opd->dest |= BITMASK1(SHR_PR);
3404 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
3405 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
3406 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
3407 opd->source = BITMASK3(GET_Rm(), SHR_R0, GET_Rn());
3410 // MUL.L Rm,Rn 0000nnnnmmmm0111
3411 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3412 opd->dest = BITMASK1(SHR_MACL);
3416 CHECK_UNHANDLED_BITS(0xf00, undefined);
3419 case 0: // CLRT 0000000000001000
3420 opd->op = OP_SETCLRT;
3421 opd->dest = BITMASK1(SHR_T);
3424 case 1: // SETT 0000000000011000
3425 opd->op = OP_SETCLRT;
3426 opd->dest = BITMASK1(SHR_T);
3429 case 2: // CLRMAC 0000000000101000
3430 opd->dest = BITMASK3(SHR_T, SHR_MACL, SHR_MACH);
3439 case 0: // NOP 0000000000001001
3440 CHECK_UNHANDLED_BITS(0xf00, undefined);
3442 case 1: // DIV0U 0000000000011001
3443 CHECK_UNHANDLED_BITS(0xf00, undefined);
3444 opd->dest = BITMASK2(SHR_SR, SHR_T);
3446 case 2: // MOVT Rn 0000nnnn00101001
3447 opd->source = BITMASK1(SHR_T);
3448 opd->dest = BITMASK1(GET_Rn());
3457 case 0: // STS MACH,Rn 0000nnnn00001010
3460 case 1: // STS MACL,Rn 0000nnnn00011010
3463 case 2: // STS PR,Rn 0000nnnn00101010
3470 opd->source = BITMASK1(tmp);
3471 opd->dest = BITMASK1(GET_Rn());
3474 CHECK_UNHANDLED_BITS(0xf00, undefined);
3477 case 0: // RTS 0000000000001011
3478 opd->op = OP_BRANCH_R;
3480 opd->source = BITMASK1(opd->rm);
3481 opd->dest = BITMASK1(SHR_PC);
3486 case 1: // SLEEP 0000000000011011
3490 case 2: // RTE 0000000000101011
3492 opd->source = BITMASK1(SHR_SP);
3493 opd->dest = BITMASK2(SHR_SR, SHR_PC);
3502 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
3503 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
3504 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
3505 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3506 opd->dest = BITMASK1(GET_Rn());
3508 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
3509 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3510 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3518 /////////////////////////////////////////////
3520 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
3521 opd->source = BITMASK1(GET_Rm());
3522 opd->source = BITMASK1(GET_Rn());
3523 opd->imm = (op & 0x0f) * 4;
3526 /////////////////////////////////////////////
3530 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
3531 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
3532 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
3533 opd->source = BITMASK1(GET_Rm());
3534 opd->source = BITMASK1(GET_Rn());
3536 case 0x04: // MOV.B Rm,@-Rn 0010nnnnmmmm0100
3537 case 0x05: // MOV.W Rm,@-Rn 0010nnnnmmmm0101
3538 case 0x06: // MOV.L Rm,@-Rn 0010nnnnmmmm0110
3539 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3540 opd->dest = BITMASK1(GET_Rn());
3542 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
3543 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3544 opd->dest = BITMASK1(SHR_SR);
3546 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
3547 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3548 opd->dest = BITMASK1(SHR_T);
3550 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
3551 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
3552 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
3553 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3554 opd->dest = BITMASK1(GET_Rn());
3556 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
3557 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3558 opd->dest = BITMASK1(SHR_T);
3560 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
3561 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3562 opd->dest = BITMASK1(GET_Rn());
3564 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
3565 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
3566 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3567 opd->dest = BITMASK1(SHR_MACL);
3574 /////////////////////////////////////////////
3578 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
3579 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
3580 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
3581 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
3582 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
3583 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3584 opd->dest = BITMASK1(SHR_T);
3586 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
3587 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_SR);
3588 opd->dest = BITMASK2(GET_Rn(), SHR_SR);
3590 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
3591 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
3592 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3593 opd->dest = BITMASK2(SHR_MACL, SHR_MACH);
3596 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
3597 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
3598 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3599 opd->dest = BITMASK1(GET_Rn());
3601 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
3602 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
3603 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_T);
3604 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3606 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
3607 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
3608 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3609 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3616 /////////////////////////////////////////////
3623 case 0: // SHLL Rn 0100nnnn00000000
3624 case 2: // SHAL Rn 0100nnnn00100000
3625 opd->source = BITMASK1(GET_Rn());
3626 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3628 case 1: // DT Rn 0100nnnn00010000
3629 opd->source = BITMASK1(GET_Rn());
3630 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3639 case 0: // SHLR Rn 0100nnnn00000001
3640 case 2: // SHAR Rn 0100nnnn00100001
3641 opd->source = BITMASK1(GET_Rn());
3642 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3644 case 1: // CMP/PZ Rn 0100nnnn00010001
3645 opd->source = BITMASK1(GET_Rn());
3646 opd->dest = BITMASK1(SHR_T);
3656 case 0x02: // STS.L MACH,@-Rn 0100nnnn00000010
3659 case 0x12: // STS.L MACL,@-Rn 0100nnnn00010010
3662 case 0x22: // STS.L PR,@-Rn 0100nnnn00100010
3665 case 0x03: // STC.L SR,@-Rn 0100nnnn00000011
3669 case 0x13: // STC.L GBR,@-Rn 0100nnnn00010011
3673 case 0x23: // STC.L VBR,@-Rn 0100nnnn00100011
3680 opd->source = BITMASK2(GET_Rn(), tmp);
3681 opd->dest = BITMASK1(GET_Rn());
3687 case 0x04: // ROTL Rn 0100nnnn00000100
3688 case 0x05: // ROTR Rn 0100nnnn00000101
3689 opd->source = BITMASK1(GET_Rn());
3690 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3692 case 0x24: // ROTCL Rn 0100nnnn00100100
3693 case 0x25: // ROTCR Rn 0100nnnn00100101
3694 opd->source = BITMASK2(GET_Rn(), SHR_T);
3695 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3697 case 0x15: // CMP/PL Rn 0100nnnn00010101
3698 opd->source = BITMASK1(GET_Rn());
3699 opd->dest = BITMASK1(SHR_T);
3709 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
3712 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
3715 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
3718 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
3722 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
3726 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
3733 opd->source = BITMASK1(GET_Rn());
3734 opd->dest = BITMASK2(GET_Rn(), tmp);
3741 // SHLL2 Rn 0100nnnn00001000
3742 // SHLR2 Rn 0100nnnn00001001
3745 // SHLL8 Rn 0100nnnn00011000
3746 // SHLR8 Rn 0100nnnn00011001
3749 // SHLL16 Rn 0100nnnn00101000
3750 // SHLR16 Rn 0100nnnn00101001
3755 opd->source = BITMASK1(GET_Rn());
3756 opd->dest = BITMASK1(GET_Rn());
3761 case 0: // LDS Rm,MACH 0100mmmm00001010
3764 case 1: // LDS Rm,MACL 0100mmmm00011010
3767 case 2: // LDS Rm,PR 0100mmmm00101010
3774 opd->source = BITMASK1(GET_Rn());
3775 opd->dest = BITMASK1(tmp);
3780 case 0: // JSR @Rm 0100mmmm00001011
3781 opd->dest = BITMASK1(SHR_PR);
3782 case 2: // JMP @Rm 0100mmmm00101011
3783 opd->op = OP_BRANCH_R;
3785 opd->source = BITMASK1(opd->rm);
3786 opd->dest |= BITMASK1(SHR_PC);
3791 case 1: // TAS.B @Rn 0100nnnn00011011
3792 opd->source = BITMASK1(GET_Rn());
3793 opd->dest = BITMASK1(SHR_T);
3803 case 0: // LDC Rm,SR 0100mmmm00001110
3806 case 1: // LDC Rm,GBR 0100mmmm00011110
3809 case 2: // LDC Rm,VBR 0100mmmm00101110
3816 opd->source = BITMASK1(GET_Rn());
3817 opd->dest = BITMASK1(tmp);
3820 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
3821 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3822 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3830 /////////////////////////////////////////////
3832 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
3833 opd->source = BITMASK1(GET_Rm());
3834 opd->dest = BITMASK1(GET_Rn());
3835 opd->imm = (op & 0x0f) * 4;
3838 /////////////////////////////////////////////
3842 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
3843 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
3844 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
3845 opd->dest = BITMASK1(GET_Rm());
3846 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
3847 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
3848 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
3849 opd->source = BITMASK1(GET_Rm());
3850 opd->dest |= BITMASK1(GET_Rn());
3852 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
3853 opd->source = BITMASK2(GET_Rm(), SHR_T);
3854 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3856 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
3859 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
3860 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
3861 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
3862 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
3863 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
3864 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
3865 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
3866 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
3868 opd->source = BITMASK1(GET_Rm());
3869 opd->dest = BITMASK1(GET_Rn());
3874 /////////////////////////////////////////////
3876 // ADD #imm,Rn 0111nnnniiiiiiii
3877 opd->source = opd->dest = BITMASK1(GET_Rn());
3878 opd->imm = (int)(signed char)op;
3881 /////////////////////////////////////////////
3883 switch (op & 0x0f00)
3885 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
3886 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3887 opd->imm = (op & 0x0f);
3889 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
3890 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3891 opd->imm = (op & 0x0f) * 2;
3893 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
3894 opd->source = BITMASK1(GET_Rm());
3895 opd->dest = BITMASK1(SHR_R0);
3896 opd->imm = (op & 0x0f);
3898 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
3899 opd->source = BITMASK1(GET_Rm());
3900 opd->dest = BITMASK1(SHR_R0);
3901 opd->imm = (op & 0x0f) * 2;
3903 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
3904 opd->source = BITMASK1(SHR_R0);
3905 opd->dest = BITMASK1(SHR_T);
3906 opd->imm = (int)(signed char)op;
3908 case 0x0d00: // BT/S label 10001101dddddddd
3909 case 0x0f00: // BF/S label 10001111dddddddd
3912 case 0x0900: // BT label 10001001dddddddd
3913 case 0x0b00: // BF label 10001011dddddddd
3914 opd->op = (op & 0x0200) ? OP_BRANCH_CF : OP_BRANCH_CT;
3915 opd->source = BITMASK1(SHR_T);
3916 opd->dest = BITMASK1(SHR_PC);
3917 opd->imm = ((signed int)(op << 24) >> 23);
3919 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
3920 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
3927 /////////////////////////////////////////////
3929 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
3930 opd->op = OP_LOAD_POOL;
3932 if (op_flags[i] & OF_DELAY_OP) {
3933 if (ops[i-1].op == OP_BRANCH)
3938 opd->source = BITMASK1(SHR_PC);
3939 opd->dest = BITMASK1(GET_Rn());
3941 opd->imm = tmp + 2 + (op & 0xff) * 2;
3945 /////////////////////////////////////////////
3947 // BSR label 1011dddddddddddd
3948 opd->dest = BITMASK1(SHR_PR);
3950 // BRA label 1010dddddddddddd
3951 opd->op = OP_BRANCH;
3952 opd->dest |= BITMASK1(SHR_PC);
3953 opd->imm = ((signed int)(op << 20) >> 19);
3958 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
3959 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
3962 /////////////////////////////////////////////
3964 switch (op & 0x0f00)
3966 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
3967 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
3968 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
3969 opd->source = BITMASK2(SHR_GBR, SHR_R0);
3970 opd->size = (op & 0x300) >> 8;
3971 opd->imm = (op & 0xff) << opd->size;
3973 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
3974 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
3975 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
3976 opd->source = BITMASK1(SHR_GBR);
3977 opd->dest = BITMASK1(SHR_R0);
3978 opd->size = (op & 0x300) >> 8;
3979 opd->imm = (op & 0xff) << opd->size;
3981 case 0x0300: // TRAPA #imm 11000011iiiiiiii
3982 opd->source = BITMASK2(SHR_PC, SHR_SR);
3983 opd->dest = BITMASK1(SHR_PC);
3984 opd->imm = (op & 0xff) * 4;
3986 end_block = 1; // FIXME
3988 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
3991 if (op_flags[i] & OF_DELAY_OP) {
3992 if (ops[i-1].op == OP_BRANCH)
3997 opd->dest = BITMASK1(SHR_R0);
3999 opd->imm = (tmp + 2 + (op & 0xff) * 4) & ~3;
4000 if (opd->imm >= base_pc) {
4001 if (lowest_mova == 0 || opd->imm < lowest_mova)
4002 lowest_mova = opd->imm;
4006 case 0x0800: // TST #imm,R0 11001000iiiiiiii
4007 opd->source = BITMASK1(SHR_R0);
4008 opd->dest = BITMASK1(SHR_T);
4009 opd->imm = op & 0xff;
4011 case 0x0900: // AND #imm,R0 11001001iiiiiiii
4012 opd->source = opd->dest = BITMASK1(SHR_R0);
4013 opd->imm = op & 0xff;
4015 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
4016 opd->source = opd->dest = BITMASK1(SHR_R0);
4017 opd->imm = op & 0xff;
4019 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
4020 opd->source = opd->dest = BITMASK1(SHR_R0);
4021 opd->imm = op & 0xff;
4023 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
4024 opd->source = BITMASK2(SHR_GBR, SHR_R0);
4025 opd->dest = BITMASK1(SHR_T);
4026 opd->imm = op & 0xff;
4029 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
4030 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
4031 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
4032 opd->source = BITMASK2(SHR_GBR, SHR_R0);
4033 opd->imm = op & 0xff;
4041 /////////////////////////////////////////////
4043 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
4044 opd->op = OP_LOAD_POOL;
4046 if (op_flags[i] & OF_DELAY_OP) {
4047 if (ops[i-1].op == OP_BRANCH)
4052 opd->source = BITMASK1(SHR_PC);
4053 opd->dest = BITMASK1(GET_Rn());
4055 opd->imm = (tmp + 2 + (op & 0xff) * 4) & ~3;
4059 /////////////////////////////////////////////
4061 // MOV #imm,Rn 1110nnnniiiiiiii
4062 opd->dest = BITMASK1(GET_Rn());
4063 opd->imm = (u32)(signed int)(signed char)op;
4068 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
4069 is_slave ? 's' : 'm', op, pc);
4073 if (op_flags[i] & OF_DELAY_OP) {
4080 elprintf(EL_ANOMALY, "%csh2 drc: branch in DS @ %08x",
4081 is_slave ? 's' : 'm', pc);
4082 opd->op = OP_UNHANDLED;
4083 op_flags[i] |= OF_B_IN_DS;
4092 // 2nd pass: some analysis
4093 for (i = 0; i < i_end; i++) {
4096 // propagate T (TODO: DIV0U)
4097 if ((opd->op == OP_SETCLRT && !opd->imm) || opd->op == OP_BRANCH_CT)
4098 op_flags[i + 1] |= OF_T_CLEAR;
4099 else if ((opd->op == OP_SETCLRT && opd->imm) || opd->op == OP_BRANCH_CF)
4100 op_flags[i + 1] |= OF_T_SET;
4102 if ((op_flags[i] & OF_BTARGET) || (opd->dest & BITMASK1(SHR_T)))
4103 op_flags[i] &= ~(OF_T_SET | OF_T_CLEAR);
4105 op_flags[i + 1] |= op_flags[i] & (OF_T_SET | OF_T_CLEAR);
4107 if ((opd->op == OP_BRANCH_CT && (op_flags[i] & OF_T_SET))
4108 || (opd->op == OP_BRANCH_CF && (op_flags[i] & OF_T_CLEAR)))
4110 opd->op = OP_BRANCH;
4113 if (op_flags[i + 1] & OF_DELAY_OP) {
4118 else if (opd->op == OP_LOAD_POOL)
4120 if (opd->imm < end_pc + MAX_LITERAL_OFFSET) {
4121 if (end_literals < opd->imm + opd->size * 2)
4122 end_literals = opd->imm + opd->size * 2;
4126 end_pc = base_pc + i_end * 2;
4127 if (end_literals < end_pc)
4128 end_literals = end_pc;
4130 // end_literals is used to decide to inline a literal or not
4131 // XXX: need better detection if this actually is used in write
4132 if (lowest_mova >= base_pc) {
4133 if (lowest_mova < end_literals) {
4134 dbg(1, "mova for %08x, block %08x", lowest_mova, base_pc);
4135 end_literals = end_pc;
4137 if (lowest_mova < end_pc) {
4138 dbg(1, "warning: mova inside of blk for %08x, block %08x",
4139 lowest_mova, base_pc);
4140 end_literals = end_pc;
4144 *end_pc_out = end_pc;
4145 if (end_literals_out != NULL)
4146 *end_literals_out = end_literals;
4149 // vim:shiftwidth=2:ts=2:expandtab