3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * - tcache, block descriptor, link buffer overflows result in sh2_translate()
10 * failure, followed by full tcache invalidation for that region
11 * - jumps between blocks are tracked for SMC handling (in block_entry->links),
12 * except jumps between different tcaches
15 * - static register allocation
16 * - remaining register caching and tracking in temporaries
17 * - block-local branch linking
18 * - block linking (except between tcaches)
19 * - some constant propagation
22 * - better constant propagation
31 #include "../../pico/pico_int.h"
34 #include "../drc/cmn.h"
38 #define PROPAGATE_CONSTANTS 1
39 #define LINK_BRANCHES 1
42 #define MAX_BLOCK_SIZE (BLOCK_INSN_LIMIT * 6 * 6)
44 // max literal offset from the block end
45 #define MAX_LITERAL_OFFSET 32*2
46 #define MAX_LITERALS (BLOCK_INSN_LIMIT / 4)
47 #define MAX_LOCAL_BRANCHES 32
50 // 1 - warnings/errors
53 // 8 - runtime block entry log
60 #define dbg(l,...) { \
61 if ((l) & DRC_DEBUG) \
62 elprintf(EL_STATUS, ##__VA_ARGS__); \
64 #include "mame/sh2dasm.h"
65 #include <platform/libpicofe/linux/host_dasm.h>
66 static int insns_compiled, hash_collisions, host_insn_count;
75 #define FETCH_OP(pc) \
79 ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
81 #define CHECK_UNHANDLED_BITS(mask, label) { \
82 if ((op & (mask)) != 0) \
94 #define BITMASK1(v0) (1 << (v0))
95 #define BITMASK2(v0,v1) ((1 << (v0)) | (1 << (v1)))
96 #define BITMASK3(v0,v1,v2) (BITMASK2(v0,v1) | (1 << (v2)))
97 #define BITMASK4(v0,v1,v2,v3) (BITMASK3(v0,v1,v2) | (1 << (v3)))
98 #define BITMASK5(v0,v1,v2,v3,v4) (BITMASK4(v0,v1,v2,v3) | (1 << (v4)))
100 #define SHR_T SHR_SR // might make them separate someday
102 static struct op_data {
105 u8 size; // 0, 1, 2 - byte, word, long
106 s8 rm; // branch or load/store data reg
107 u32 source; // bitmask of src regs
108 u32 dest; // bitmask of dest regs
109 u32 imm; // immediate/io address/branch target
110 // (for literal - address, not value)
111 } ops[BLOCK_INSN_LIMIT];
116 OP_BRANCH_CT, // conditional, branch if T set
117 OP_BRANCH_CF, // conditional, branch if T clear
118 OP_BRANCH_R, // indirect
119 OP_BRANCH_RF, // indirect far (PC + Rm)
120 OP_SETCLRT, // T flag set/clear
121 OP_MOVE, // register move
122 OP_LOAD_POOL, // literal pool load
130 static u8 *tcache_dsm_ptrs[3];
131 static char sh2dasm_buff[64];
132 #define do_host_disasm(tcid) \
133 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
134 tcache_dsm_ptrs[tcid] = tcache_ptr
136 #define do_host_disasm(x)
139 #if (DRC_DEBUG & 8) || defined(PDB)
140 static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
143 dbg(8, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
144 sh2->pc, block, (signed int)sr >> 12);
145 pdb_step(sh2, sh2->pc);
152 #define TCACHE_BUFFERS 3
154 // we have 3 translation cache buffers, split from one drc/cmn buffer.
155 // BIOS shares tcache with data array because it's only used for init
156 // and can be discarded early
157 // XXX: need to tune sizes
158 static const int tcache_sizes[TCACHE_BUFFERS] = {
159 DRC_TCACHE_SIZE * 6 / 8, // ROM (rarely used), DRAM
160 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
161 DRC_TCACHE_SIZE / 8, // ... slave
164 static u8 *tcache_bases[TCACHE_BUFFERS];
165 static u8 *tcache_ptrs[TCACHE_BUFFERS];
167 // ptr for code emiters
168 static u8 *tcache_ptr;
170 #define MAX_BLOCK_ENTRIES (BLOCK_INSN_LIMIT / 8)
174 void *jump; // insn address
175 struct block_link *next; // either in block_entry->links or
180 void *tcache_ptr; // translated block for above PC
181 struct block_entry *next; // next block in hash_table with same pc hash
182 struct block_link *links; // links to this entry
184 struct block_desc *block;
189 u32 addr; // block start SH2 PC address
190 u32 end_addr; // address after last op or literal
195 struct block_entry entryp[MAX_BLOCK_ENTRIES];
198 static const int block_max_counts[TCACHE_BUFFERS] = {
203 static struct block_desc *block_tables[TCACHE_BUFFERS];
204 static int block_counts[TCACHE_BUFFERS];
206 // we have block_link_pool to avoid using mallocs
207 static const int block_link_pool_max_counts[TCACHE_BUFFERS] = {
212 static struct block_link *block_link_pool[TCACHE_BUFFERS];
213 static int block_link_pool_counts[TCACHE_BUFFERS];
214 static struct block_link *unresolved_links[TCACHE_BUFFERS];
216 // used for invalidation
217 static const int ram_sizes[TCACHE_BUFFERS] = {
222 #define ADDR_TO_BLOCK_PAGE 0x100
225 struct block_desc *block;
226 struct block_list *next;
229 // array of pointers to block_lists for RAM and 2 data arrays
230 // each array has len: sizeof(mem) / ADDR_TO_BLOCK_PAGE
231 static struct block_list **inval_lookup[TCACHE_BUFFERS];
233 static const int hash_table_sizes[TCACHE_BUFFERS] = {
238 static struct block_entry **hash_tables[TCACHE_BUFFERS];
240 #define HASH_FUNC(hash_tab, addr, mask) \
241 (hash_tab)[(((addr) >> 20) ^ ((addr) >> 2)) & (mask)]
243 // host register tracking
246 HR_CACHED, // 'val' has sh2_reg_e
247 // HR_CONST, // 'val' has a constant
248 HR_TEMP, // reg used for temp storage
252 HRF_DIRTY = 1 << 0, // reg has "dirty" value to be written to ctx
253 HRF_LOCKED = 1 << 1, // HR_CACHED can't be evicted
257 u32 hreg:5; // "host" reg
258 u32 greg:5; // "guest" reg
261 u32 stamp:16; // kind of a timestamp
264 // note: reg_temp[] must have at least the amount of
265 // registers used by handlers in worst case (currently 4)
267 #include "../drc/emit_arm.c"
269 static const int reg_map_g2h[] = {
273 -1, -1, -1, 9, // r12 .. sp
274 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
275 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
278 static temp_reg_t reg_temp[] = {
287 #elif defined(__i386__)
288 #include "../drc/emit_x86.c"
290 static const int reg_map_g2h[] = {
299 // ax, cx, dx are usually temporaries by convention
300 static temp_reg_t reg_temp[] = {
308 #error unsupported arch
316 #define T_save 0x00000800
322 static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
323 static void (*sh2_drc_dispatcher)(void);
324 static void (*sh2_drc_exit)(void);
325 static void (*sh2_drc_test_irq)(void);
327 static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
328 static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
329 static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
330 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
331 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
332 static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
334 // address space stuff
335 static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
339 if ((a & ~0x7ff) == 0) {
341 poffs = offsetof(SH2, p_bios);
344 else if ((a & 0xfffff000) == 0xc0000000) {
346 poffs = offsetof(SH2, p_da);
349 else if ((a & 0xc6000000) == 0x06000000) {
351 poffs = offsetof(SH2, p_sdram);
354 else if ((a & 0xc6000000) == 0x02000000) {
356 poffs = offsetof(SH2, p_rom);
363 static struct block_entry *dr_get_entry(u32 pc, int is_slave, int *tcache_id)
365 struct block_entry *be;
368 // data arrays have their own caches
369 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0)
374 mask = hash_table_sizes[tcid] - 1;
375 be = HASH_FUNC(hash_tables[tcid], pc, mask);
376 for (; be != NULL; be = be->next)
383 // ---------------------------------------------------------------
386 static void add_to_block_list(struct block_list **blist, struct block_desc *block)
388 struct block_list *added = malloc(sizeof(*added));
390 elprintf(EL_ANOMALY, "drc OOM (1)");
393 added->block = block;
394 added->next = *blist;
398 static void rm_from_block_list(struct block_list **blist, struct block_desc *block)
400 struct block_list *prev = NULL, *current = *blist;
401 for (; current != NULL; prev = current, current = current->next) {
402 if (current->block == block) {
404 *blist = current->next;
406 prev->next = current->next;
411 dbg(1, "can't rm block %p (%08x-%08x)",
412 block, block->addr, block->end_addr);
415 static void rm_block_list(struct block_list **blist)
417 struct block_list *tmp, *current = *blist;
418 while (current != NULL) {
420 current = current->next;
426 static void REGPARM(1) flush_tcache(int tcid)
430 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
431 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
432 block_counts[tcid], block_max_counts[tcid]);
434 block_counts[tcid] = 0;
435 block_link_pool_counts[tcid] = 0;
436 unresolved_links[tcid] = NULL;
437 memset(hash_tables[tcid], 0, sizeof(*hash_tables[0]) * hash_table_sizes[tcid]);
438 tcache_ptrs[tcid] = tcache_bases[tcid];
439 if (Pico32xMem != NULL) {
440 if (tcid == 0) // ROM, RAM
441 memset(Pico32xMem->drcblk_ram, 0,
442 sizeof(Pico32xMem->drcblk_ram));
444 memset(Pico32xMem->drcblk_da[tcid - 1], 0,
445 sizeof(Pico32xMem->drcblk_da[0]));
448 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
451 for (i = 0; i < ram_sizes[tcid] / ADDR_TO_BLOCK_PAGE; i++)
452 rm_block_list(&inval_lookup[tcid][i]);
455 static void add_to_hashlist(struct block_entry *be, int tcache_id)
457 u32 tcmask = hash_table_sizes[tcache_id] - 1;
459 be->next = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
460 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be;
463 if (be->next != NULL) {
464 printf(" %08x: hash collision with %08x\n",
465 be->pc, be->next->pc);
471 static void rm_from_hashlist(struct block_entry *be, int tcache_id)
473 u32 tcmask = hash_table_sizes[tcache_id] - 1;
474 struct block_entry *cur, *prev;
476 cur = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
480 if (be == cur) { // first
481 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be->next;
485 for (prev = cur, cur = cur->next; cur != NULL; cur = cur->next) {
487 prev->next = cur->next;
493 dbg(1, "rm_from_hashlist: be %p %08x missing?", be, be->pc);
496 static struct block_desc *dr_add_block(u32 addr, u32 end_addr, int is_slave, int *blk_id)
498 struct block_entry *be;
499 struct block_desc *bd;
503 // do a lookup to get tcache_id and override check
504 be = dr_get_entry(addr, is_slave, &tcache_id);
506 dbg(1, "block override for %08x", addr);
508 bcount = &block_counts[tcache_id];
509 if (*bcount >= block_max_counts[tcache_id]) {
510 dbg(1, "bd overflow for tcache %d", tcache_id);
514 bd = &block_tables[tcache_id][*bcount];
516 bd->end_addr = end_addr;
519 bd->entryp[0].pc = addr;
520 bd->entryp[0].tcache_ptr = tcache_ptr;
521 bd->entryp[0].links = NULL;
523 bd->entryp[0].block = bd;
526 add_to_hashlist(&bd->entryp[0], tcache_id);
534 static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id)
536 struct block_entry *be = NULL;
539 be = dr_get_entry(pc, is_slave, tcache_id);
541 block = be->tcache_ptr;
545 be->block->refcount++;
550 static void *dr_failure(void)
552 lprintf("recompilation failed\n");
556 static void *dr_prepare_ext_branch(u32 pc, int is_slave, int tcache_id)
559 struct block_link *bl = block_link_pool[tcache_id];
560 int cnt = block_link_pool_counts[tcache_id];
561 struct block_entry *be = NULL;
562 int target_tcache_id;
565 be = dr_get_entry(pc, is_slave, &target_tcache_id);
566 if (target_tcache_id != tcache_id)
567 return sh2_drc_dispatcher;
569 // if pool has been freed, reuse
570 for (i = cnt - 1; i >= 0; i--)
571 if (bl[i].target_pc != 0)
574 if (cnt >= block_link_pool_max_counts[tcache_id]) {
575 dbg(1, "bl overflow for tcache %d", tcache_id);
579 block_link_pool_counts[tcache_id]++;
582 bl->jump = tcache_ptr;
585 dbg(2, "- early link from %p to pc %08x", bl->jump, pc);
586 bl->next = be->links;
588 return be->tcache_ptr;
591 bl->next = unresolved_links[tcache_id];
592 unresolved_links[tcache_id] = bl;
593 return sh2_drc_dispatcher;
596 return sh2_drc_dispatcher;
600 static void dr_link_blocks(struct block_entry *be, int tcache_id)
603 struct block_link *first = unresolved_links[tcache_id];
604 struct block_link *bl, *prev, *tmp;
607 for (bl = prev = first; bl != NULL; ) {
608 if (bl->target_pc == pc) {
609 dbg(2, "- link from %p to pc %08x", bl->jump, pc);
610 emith_jump_patch(bl->jump, tcache_ptr);
612 // move bl from unresolved_links to block_entry
614 bl->next = be->links;
618 first = prev = bl = tmp;
620 prev->next = bl = tmp;
626 unresolved_links[tcache_id] = first;
628 // could sync arm caches here, but that's unnecessary
632 #define ADD_TO_ARRAY(array, count, item, failcode) \
633 array[count++] = item; \
634 if (count >= ARRAY_SIZE(array)) { \
635 dbg(1, "warning: " #array " overflow"); \
639 static int find_in_array(u32 *array, size_t size, u32 what)
642 for (i = 0; i < size; i++)
643 if (what == array[i])
649 // ---------------------------------------------------------------
651 // register cache / constant propagation stuff
658 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking);
660 // guest regs with constants
661 static u32 dr_gcregs[24];
662 // a mask of constant/dirty regs
663 static u32 dr_gcregs_mask;
664 static u32 dr_gcregs_dirty;
666 #if PROPAGATE_CONSTANTS
667 static void gconst_new(sh2_reg_e r, u32 val)
671 dr_gcregs_mask |= 1 << r;
672 dr_gcregs_dirty |= 1 << r;
675 // throw away old r that we might have cached
676 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
677 if ((reg_temp[i].type == HR_CACHED) &&
678 reg_temp[i].greg == r) {
679 reg_temp[i].type = HR_FREE;
680 reg_temp[i].flags = 0;
686 static int gconst_get(sh2_reg_e r, u32 *val)
688 if (dr_gcregs_mask & (1 << r)) {
695 static int gconst_check(sh2_reg_e r)
697 if ((dr_gcregs_mask | dr_gcregs_dirty) & (1 << r))
702 // update hr if dirty, else do nothing
703 static int gconst_try_read(int hr, sh2_reg_e r)
705 if (dr_gcregs_dirty & (1 << r)) {
706 emith_move_r_imm(hr, dr_gcregs[r]);
707 dr_gcregs_dirty &= ~(1 << r);
713 static void gconst_check_evict(sh2_reg_e r)
715 if (dr_gcregs_mask & (1 << r))
716 // no longer cached in reg, make dirty again
717 dr_gcregs_dirty |= 1 << r;
720 static void gconst_kill(sh2_reg_e r)
722 dr_gcregs_mask &= ~(1 << r);
723 dr_gcregs_dirty &= ~(1 << r);
726 static void gconst_clean(void)
730 for (i = 0; i < ARRAY_SIZE(dr_gcregs); i++)
731 if (dr_gcregs_dirty & (1 << i)) {
732 // using RC_GR_READ here: it will call gconst_try_read,
733 // cache the reg and mark it dirty.
734 rcache_get_reg_(i, RC_GR_READ, 0);
738 static void gconst_invalidate(void)
740 dr_gcregs_mask = dr_gcregs_dirty = 0;
743 static u16 rcache_counter;
745 static temp_reg_t *rcache_evict(void)
747 // evict reg with oldest stamp
749 u16 min_stamp = (u16)-1;
751 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
752 if (reg_temp[i].type == HR_CACHED && !(reg_temp[i].flags & HRF_LOCKED) &&
753 reg_temp[i].stamp <= min_stamp) {
754 min_stamp = reg_temp[i].stamp;
760 printf("no registers to evict, aborting\n");
765 if (reg_temp[i].type == HR_CACHED) {
766 if (reg_temp[i].flags & HRF_DIRTY)
768 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
769 gconst_check_evict(reg_temp[i].greg);
772 reg_temp[i].type = HR_FREE;
773 reg_temp[i].flags = 0;
777 static int get_reg_static(sh2_reg_e r, rc_gr_mode mode)
779 int i = reg_map_g2h[r];
781 if (mode != RC_GR_WRITE)
782 gconst_try_read(i, r);
787 // note: must not be called when doing conditional code
788 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking)
793 // maybe statically mapped?
794 ret = get_reg_static(r, mode);
800 // maybe already cached?
801 // if so, prefer against gconst (they must be in sync)
802 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
803 if (reg_temp[i].type == HR_CACHED && reg_temp[i].greg == r) {
804 reg_temp[i].stamp = rcache_counter;
805 if (mode != RC_GR_READ)
806 reg_temp[i].flags |= HRF_DIRTY;
807 ret = reg_temp[i].hreg;
813 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
814 if (reg_temp[i].type == HR_FREE) {
823 tr->type = HR_CACHED;
825 tr->flags |= HRF_LOCKED;
826 if (mode != RC_GR_READ)
827 tr->flags |= HRF_DIRTY;
829 tr->stamp = rcache_counter;
832 if (mode != RC_GR_WRITE) {
833 if (gconst_check(r)) {
834 if (gconst_try_read(ret, r))
835 tr->flags |= HRF_DIRTY;
838 emith_ctx_read(tr->hreg, r * 4);
842 if (mode != RC_GR_READ)
848 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
850 return rcache_get_reg_(r, mode, 1);
853 static int rcache_get_tmp(void)
858 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
859 if (reg_temp[i].type == HR_FREE) {
871 static int rcache_get_arg_id(int arg)
874 host_arg2reg(r, arg);
876 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
877 if (reg_temp[i].hreg == r)
880 if (i == ARRAY_SIZE(reg_temp)) // can't happen
883 if (reg_temp[i].type == HR_CACHED) {
885 if (reg_temp[i].flags & HRF_DIRTY)
886 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
887 gconst_check_evict(reg_temp[i].greg);
889 else if (reg_temp[i].type == HR_TEMP) {
890 printf("arg %d reg %d already used, aborting\n", arg, r);
894 reg_temp[i].type = HR_FREE;
895 reg_temp[i].flags = 0;
900 // get a reg to be used as function arg
901 static int rcache_get_tmp_arg(int arg)
903 int id = rcache_get_arg_id(arg);
904 reg_temp[id].type = HR_TEMP;
906 return reg_temp[id].hreg;
909 // same but caches a reg. RC_GR_READ only.
910 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
912 int i, srcr, dstr, dstid;
913 int dirty = 0, src_dirty = 0;
915 dstid = rcache_get_arg_id(arg);
916 dstr = reg_temp[dstid].hreg;
918 // maybe already statically mapped?
919 srcr = get_reg_static(r, RC_GR_READ);
923 // maybe already cached?
924 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
925 if ((reg_temp[i].type == HR_CACHED) &&
926 reg_temp[i].greg == r)
928 srcr = reg_temp[i].hreg;
929 if (reg_temp[i].flags & HRF_DIRTY)
937 if (gconst_check(r)) {
938 if (gconst_try_read(srcr, r))
942 emith_ctx_read(srcr, r * 4);
946 emith_move_r_r(dstr, srcr);
952 // must clean, callers might want to modify the arg before call
953 emith_ctx_write(dstr, r * 4);
956 reg_temp[dstid].flags |= HRF_DIRTY;
959 reg_temp[dstid].stamp = ++rcache_counter;
960 reg_temp[dstid].type = HR_CACHED;
961 reg_temp[dstid].greg = r;
962 reg_temp[dstid].flags |= HRF_LOCKED;
966 static void rcache_free_tmp(int hr)
969 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
970 if (reg_temp[i].hreg == hr)
973 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
974 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
978 reg_temp[i].type = HR_FREE;
979 reg_temp[i].flags = 0;
982 static void rcache_unlock(int hr)
985 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
986 if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr)
987 reg_temp[i].flags &= ~HRF_LOCKED;
990 static void rcache_unlock_all(void)
993 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
994 reg_temp[i].flags &= ~HRF_LOCKED;
997 static inline u32 rcache_used_hreg_mask(void)
1002 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1003 if (reg_temp[i].type != HR_FREE)
1004 mask |= 1 << reg_temp[i].hreg;
1009 static void rcache_clean(void)
1014 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1015 if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) {
1017 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
1018 reg_temp[i].flags &= ~HRF_DIRTY;
1022 static void rcache_invalidate(void)
1025 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
1026 reg_temp[i].type = HR_FREE;
1027 reg_temp[i].flags = 0;
1031 gconst_invalidate();
1034 static void rcache_flush(void)
1037 rcache_invalidate();
1040 // ---------------------------------------------------------------
1042 static int emit_get_rbase_and_offs(u32 a, u32 *offs)
1048 poffs = dr_ctx_get_mem_ptr(a, &mask);
1052 // XXX: could use some related reg
1053 hr = rcache_get_tmp();
1054 emith_ctx_read(hr, poffs);
1055 emith_add_r_imm(hr, a & mask & ~0xff);
1056 *offs = a & 0xff; // XXX: ARM oriented..
1060 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
1062 #if PROPAGATE_CONSTANTS
1063 gconst_new(dst, imm);
1065 int hr = rcache_get_reg(dst, RC_GR_WRITE);
1066 emith_move_r_imm(hr, imm);
1070 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
1072 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
1073 int hr_s = rcache_get_reg(src, RC_GR_READ);
1075 emith_move_r_r(hr_d, hr_s);
1078 // T must be clear, and comparison done just before this
1079 static void emit_or_t_if_eq(int srr)
1081 EMITH_SJMP_START(DCOND_NE);
1082 emith_or_r_imm_c(DCOND_EQ, srr, T);
1083 EMITH_SJMP_END(DCOND_NE);
1086 // arguments must be ready
1087 // reg cache must be clean before call
1088 static int emit_memhandler_read_(int size, int ram_check)
1091 host_arg2reg(arg0, 0);
1095 // must writeback cycles for poll detection stuff
1097 if (reg_map_g2h[SHR_SR] != -1)
1098 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1100 arg1 = rcache_get_tmp_arg(1);
1101 emith_move_r_r(arg1, CONTEXT_REG);
1104 if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
1105 int tmp = rcache_get_tmp();
1106 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
1107 emith_cmp_r_imm(tmp, 0x02000000);
1110 EMITH_SJMP3_START(DCOND_NE);
1111 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
1112 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1113 EMITH_SJMP3_MID(DCOND_NE);
1114 emith_call_cond(DCOND_NE, sh2_drc_read8);
1118 EMITH_SJMP3_START(DCOND_NE);
1119 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1120 EMITH_SJMP3_MID(DCOND_NE);
1121 emith_call_cond(DCOND_NE, sh2_drc_read16);
1125 EMITH_SJMP3_START(DCOND_NE);
1126 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1127 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
1128 EMITH_SJMP3_MID(DCOND_NE);
1129 emith_call_cond(DCOND_NE, sh2_drc_read32);
1139 emith_call(sh2_drc_read8);
1142 emith_call(sh2_drc_read16);
1145 emith_call(sh2_drc_read32);
1149 rcache_invalidate();
1151 if (reg_map_g2h[SHR_SR] != -1)
1152 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1154 // assuming arg0 and retval reg matches
1155 return rcache_get_tmp_arg(0);
1158 static int emit_memhandler_read(int size)
1160 return emit_memhandler_read_(size, 1);
1163 static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size)
1165 int hr, hr2, ram_check = 1;
1168 if (gconst_get(rs, &val)) {
1169 hr = emit_get_rbase_and_offs(val + offs, &offs2);
1171 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1174 emith_read8_r_r_offs(hr2, hr, offs2 ^ 1);
1175 emith_sext(hr2, hr2, 8);
1178 emith_read16_r_r_offs(hr2, hr, offs2);
1179 emith_sext(hr2, hr2, 16);
1182 emith_read_r_r_offs(hr2, hr, offs2);
1183 emith_ror(hr2, hr2, 16);
1186 rcache_free_tmp(hr);
1193 hr = rcache_get_reg_arg(0, rs);
1195 emith_add_r_imm(hr, offs);
1196 hr = emit_memhandler_read_(size, ram_check);
1197 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1199 emith_sext(hr2, hr, (size == 1) ? 16 : 8);
1201 emith_move_r_r(hr2, hr);
1202 rcache_free_tmp(hr);
1207 static void emit_memhandler_write(int size, u32 pc)
1210 host_arg2reg(ctxr, 2);
1211 if (reg_map_g2h[SHR_SR] != -1)
1212 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1218 // XXX: consider inlining sh2_drc_write8
1219 emith_call(sh2_drc_write8);
1222 emith_call(sh2_drc_write16);
1225 emith_move_r_r(ctxr, CONTEXT_REG);
1226 emith_call(sh2_drc_write32);
1230 rcache_invalidate();
1231 if (reg_map_g2h[SHR_SR] != -1)
1232 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1236 static int emit_indirect_indexed_read(int rx, int ry, int size)
1239 a0 = rcache_get_reg_arg(0, rx);
1240 t = rcache_get_reg(ry, RC_GR_READ);
1241 emith_add_r_r(a0, t);
1242 return emit_memhandler_read(size);
1246 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
1250 rcache_get_reg_arg(0, rn);
1251 tmp = emit_memhandler_read(size);
1252 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
1253 rcache_free_tmp(tmp);
1254 tmp = rcache_get_reg(rn, RC_GR_RMW);
1255 emith_add_r_imm(tmp, 1 << size);
1258 rcache_get_reg_arg(0, rm);
1259 *rmr = emit_memhandler_read(size);
1260 *rnr = rcache_get_tmp();
1261 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
1262 tmp = rcache_get_reg(rm, RC_GR_RMW);
1263 emith_add_r_imm(tmp, 1 << size);
1267 static void emit_do_static_regs(int is_write, int tmpr)
1271 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
1276 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
1277 if (reg_map_g2h[i + 1] != r + 1)
1283 // i, r point to last item
1285 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1287 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1290 emith_ctx_write(r, i * 4);
1292 emith_ctx_read(r, i * 4);
1297 static void emit_block_entry(void)
1301 host_arg2reg(arg0, 0);
1303 #if (DRC_DEBUG & 8) || defined(PDB)
1305 host_arg2reg(arg1, 1);
1306 host_arg2reg(arg2, 2);
1308 emit_do_static_regs(1, arg2);
1309 emith_move_r_r(arg1, CONTEXT_REG);
1310 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
1311 emith_call(sh2_drc_log_entry);
1312 rcache_invalidate();
1314 emith_tst_r_r(arg0, arg0);
1315 EMITH_SJMP_START(DCOND_EQ);
1316 emith_jump_reg_c(DCOND_NE, arg0);
1317 EMITH_SJMP_END(DCOND_EQ);
1320 #define DELAY_SAVE_T(sr) { \
1321 emith_bic_r_imm(sr, T_save); \
1322 emith_tst_r_imm(sr, T); \
1323 EMITH_SJMP_START(DCOND_EQ); \
1324 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
1325 EMITH_SJMP_END(DCOND_EQ); \
1328 #define FLUSH_CYCLES(sr) \
1330 emith_sub_r_imm(sr, cycles << 12); \
1334 static void *dr_get_pc_base(u32 pc, int is_slave);
1336 static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
1338 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
1339 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
1340 int branch_target_count = 0;
1341 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
1342 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
1343 int branch_patch_count = 0;
1344 u32 literal_addr[MAX_LITERALS];
1345 int literal_addr_count = 0;
1346 u8 op_flags[BLOCK_INSN_LIMIT];
1349 u32 pending_branch_direct:1;
1350 u32 pending_branch_indirect:1;
1353 // PC of current, first, last SH2 insn
1354 u32 pc, base_pc, end_pc;
1356 void *block_entry_ptr;
1357 struct block_desc *block;
1359 struct op_data *opd;
1369 // get base/validate PC
1370 dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave);
1371 if (dr_pc_base == (void *)-1) {
1372 printf("invalid PC, aborting: %08x\n", base_pc);
1373 // FIXME: be less destructive
1377 tcache_ptr = tcache_ptrs[tcache_id];
1379 // predict tcache overflow
1380 tmp = tcache_ptr - tcache_bases[tcache_id];
1381 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
1382 dbg(1, "tcache %d overflow", tcache_id);
1386 // initial passes to disassemble and analyze the block
1387 scan_block(base_pc, sh2->is_slave, op_flags, &end_pc, &end_literals);
1389 block = dr_add_block(base_pc, end_literals, sh2->is_slave, &blkid_main);
1393 block_entry_ptr = tcache_ptr;
1394 dbg(2, "== %csh2 block #%d,%d %08x-%08x -> %p", sh2->is_slave ? 's' : 'm',
1395 tcache_id, blkid_main, base_pc, end_pc, block_entry_ptr);
1397 dr_link_blocks(&block->entryp[0], tcache_id);
1399 // collect branch_targets that don't land on delay slots
1400 for (pc = base_pc, i = 0; pc < end_pc; i++, pc += 2) {
1401 if (!(op_flags[i] & OF_BTARGET))
1403 if (op_flags[i] & OF_DELAY_OP) {
1404 op_flags[i] &= ~OF_BTARGET;
1407 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
1410 if (branch_target_count > 0) {
1411 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
1414 // clear stale state after compile errors
1415 rcache_invalidate();
1417 // -------------------------------------------------
1418 // 3rd pass: actual compilation
1421 for (i = 0; pc < end_pc; i++)
1423 u32 delay_dep_fw = 0, delay_dep_bk = 0;
1433 DasmSH2(sh2dasm_buff, pc, op);
1434 printf("%c%08x %04x %s\n", (op_flags[i] & OF_BTARGET) ? '*' : ' ',
1435 pc, op, sh2dasm_buff);
1438 if ((op_flags[i] & OF_BTARGET) || pc == base_pc)
1442 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1447 v = block->entry_count;
1448 if (v < ARRAY_SIZE(block->entryp)) {
1449 block->entryp[v].pc = pc;
1450 block->entryp[v].tcache_ptr = tcache_ptr;
1451 block->entryp[v].links = NULL;
1453 block->entryp[v].block = block;
1455 add_to_hashlist(&block->entryp[v], tcache_id);
1456 block->entry_count++;
1458 dbg(2, "-- %csh2 block #%d,%d entry %08x -> %p",
1459 sh2->is_slave ? 's' : 'm', tcache_id, blkid_main,
1462 // since we made a block entry, link any other blocks
1463 // that jump to current pc
1464 dr_link_blocks(&block->entryp[v], tcache_id);
1467 dbg(1, "too many entryp for block #%d,%d pc=%08x",
1468 tcache_id, blkid_main, pc);
1471 do_host_disasm(tcache_id);
1474 v = find_in_array(branch_target_pc, branch_target_count, pc);
1476 branch_target_ptr[v] = tcache_ptr;
1479 emit_move_r_imm32(SHR_PC, pc);
1483 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1484 emith_cmp_r_imm(sr, 0);
1485 emith_jump_cond(DCOND_LE, sh2_drc_exit);
1486 do_host_disasm(tcache_id);
1487 rcache_unlock_all();
1491 if (!(op_flags[i] & OF_DELAY_OP)) {
1492 emit_move_r_imm32(SHR_PC, pc);
1493 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1497 tmp = rcache_used_hreg_mask();
1498 emith_save_caller_regs(tmp);
1499 emit_do_static_regs(1, 0);
1500 emith_pass_arg_r(0, CONTEXT_REG);
1501 emith_call(do_sh2_cmp);
1502 emith_restore_caller_regs(tmp);
1513 if (op_flags[i] & OF_DELAY_OP)
1515 // handle delay slot dependencies
1516 delay_dep_fw = opd->dest & ops[i-1].source;
1517 delay_dep_bk = opd->source & ops[i-1].dest;
1518 if (delay_dep_fw & BITMASK1(SHR_T)) {
1519 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1522 if (delay_dep_fw & ~BITMASK1(SHR_T))
1523 dbg(1, "unhandled delay_dep_fw: %x", delay_dep_fw & ~BITMASK1(SHR_T));
1525 dbg(1, "unhandled delay_dep_bk: %x", delay_dep_bk);
1533 if (opd->dest & BITMASK1(SHR_PR))
1534 emit_move_r_imm32(SHR_PR, pc + 2);
1535 drcf.pending_branch_direct = 1;
1539 if (opd->dest & BITMASK1(SHR_PR))
1540 emit_move_r_imm32(SHR_PR, pc + 2);
1541 emit_move_r_r(SHR_PC, opd->rm);
1542 drcf.pending_branch_indirect = 1;
1546 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1547 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1548 if (opd->dest & BITMASK1(SHR_PR)) {
1549 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
1550 emith_move_r_imm(tmp3, pc + 2);
1551 emith_add_r_r_r(tmp, tmp2, tmp3);
1554 emith_move_r_r(tmp, tmp2);
1555 emith_add_r_imm(tmp, pc + 2);
1557 drcf.pending_branch_indirect = 1;
1561 printf("TODO sleep\n");
1566 emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2);
1568 tmp = rcache_get_reg_arg(0, SHR_SP);
1569 emith_add_r_imm(tmp, 4);
1570 tmp = emit_memhandler_read(2);
1571 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1572 emith_write_sr(sr, tmp);
1573 rcache_free_tmp(tmp);
1574 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1575 emith_add_r_imm(tmp, 4*2);
1577 drcf.pending_branch_indirect = 1;
1581 switch ((op >> 12) & 0x0f)
1583 /////////////////////////////////////////////
1588 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1591 case 0: // STC SR,Rn 0000nnnn00000010
1594 case 1: // STC GBR,Rn 0000nnnn00010010
1597 case 2: // STC VBR,Rn 0000nnnn00100010
1603 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
1604 emith_move_r_r(tmp, tmp3);
1606 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
1608 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
1609 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
1610 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
1612 tmp = rcache_get_reg_arg(1, GET_Rm());
1613 tmp2 = rcache_get_reg_arg(0, SHR_R0);
1614 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1615 emith_add_r_r(tmp2, tmp3);
1616 emit_memhandler_write(op & 3, pc);
1619 // MUL.L Rm,Rn 0000nnnnmmmm0111
1620 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1621 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1622 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1623 emith_mul(tmp3, tmp2, tmp);
1628 case 0: // CLRT 0000000000001000
1629 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1630 emith_bic_r_imm(sr, T);
1632 case 1: // SETT 0000000000011000
1633 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1634 emith_or_r_imm(sr, T);
1636 case 2: // CLRMAC 0000000000101000
1637 emit_move_r_imm32(SHR_MACL, 0);
1638 emit_move_r_imm32(SHR_MACH, 0);
1647 case 0: // NOP 0000000000001001
1649 case 1: // DIV0U 0000000000011001
1650 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1651 emith_bic_r_imm(sr, M|Q|T);
1653 case 2: // MOVT Rn 0000nnnn00101001
1654 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1655 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1656 emith_clear_msb(tmp2, sr, 31);
1663 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1666 case 0: // STS MACH,Rn 0000nnnn00001010
1669 case 1: // STS MACL,Rn 0000nnnn00011010
1672 case 2: // STS PR,Rn 0000nnnn00101010
1678 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1679 emith_move_r_r(tmp, tmp2);
1681 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1682 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1683 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1684 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1685 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1686 if ((op & 3) != 2) {
1687 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1689 emith_move_r_r(tmp2, tmp);
1690 rcache_free_tmp(tmp);
1692 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1693 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1694 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1695 /* MS 16 MAC bits unused if saturated */
1696 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1697 emith_tst_r_imm(sr, S);
1698 EMITH_SJMP_START(DCOND_EQ);
1699 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1700 EMITH_SJMP_END(DCOND_EQ);
1702 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1703 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1704 rcache_free_tmp(tmp2);
1705 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1706 emith_tst_r_imm(sr, S);
1708 EMITH_JMP_START(DCOND_EQ);
1709 emith_asr(tmp, tmp4, 15);
1710 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1711 EMITH_SJMP_START(DCOND_GE);
1712 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1713 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1714 EMITH_SJMP_END(DCOND_GE);
1715 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1716 EMITH_SJMP_START(DCOND_LE);
1717 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1718 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1719 EMITH_SJMP_END(DCOND_LE);
1720 EMITH_JMP_END(DCOND_EQ);
1722 rcache_free_tmp(tmp);
1727 /////////////////////////////////////////////
1729 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1731 tmp = rcache_get_reg_arg(0, GET_Rn());
1732 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1734 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1735 emit_memhandler_write(2, pc);
1741 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1742 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1743 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1745 rcache_get_reg_arg(0, GET_Rn());
1746 rcache_get_reg_arg(1, GET_Rm());
1747 emit_memhandler_write(op & 3, pc);
1749 case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
1750 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
1751 case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110
1752 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1753 emith_sub_r_imm(tmp, (1 << (op & 3)));
1755 rcache_get_reg_arg(0, GET_Rn());
1756 rcache_get_reg_arg(1, GET_Rm());
1757 emit_memhandler_write(op & 3, pc);
1759 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1760 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1761 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1762 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1763 emith_bic_r_imm(sr, M|Q|T);
1764 emith_tst_r_imm(tmp2, (1<<31));
1765 EMITH_SJMP_START(DCOND_EQ);
1766 emith_or_r_imm_c(DCOND_NE, sr, Q);
1767 EMITH_SJMP_END(DCOND_EQ);
1768 emith_tst_r_imm(tmp3, (1<<31));
1769 EMITH_SJMP_START(DCOND_EQ);
1770 emith_or_r_imm_c(DCOND_NE, sr, M);
1771 EMITH_SJMP_END(DCOND_EQ);
1772 emith_teq_r_r(tmp2, tmp3);
1773 EMITH_SJMP_START(DCOND_PL);
1774 emith_or_r_imm_c(DCOND_MI, sr, T);
1775 EMITH_SJMP_END(DCOND_PL);
1777 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1778 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1779 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1780 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1781 emith_bic_r_imm(sr, T);
1782 emith_tst_r_r(tmp2, tmp3);
1783 emit_or_t_if_eq(sr);
1785 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1786 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1787 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1788 emith_and_r_r(tmp, tmp2);
1790 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1791 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1792 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1793 emith_eor_r_r(tmp, tmp2);
1795 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1796 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1797 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1798 emith_or_r_r(tmp, tmp2);
1800 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1801 tmp = rcache_get_tmp();
1802 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1803 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1804 emith_eor_r_r_r(tmp, tmp2, tmp3);
1805 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1806 emith_bic_r_imm(sr, T);
1807 emith_tst_r_imm(tmp, 0x000000ff);
1808 emit_or_t_if_eq(tmp);
1809 emith_tst_r_imm(tmp, 0x0000ff00);
1810 emit_or_t_if_eq(tmp);
1811 emith_tst_r_imm(tmp, 0x00ff0000);
1812 emit_or_t_if_eq(tmp);
1813 emith_tst_r_imm(tmp, 0xff000000);
1814 emit_or_t_if_eq(tmp);
1815 rcache_free_tmp(tmp);
1817 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1818 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1819 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1820 emith_lsr(tmp, tmp, 16);
1821 emith_or_r_r_lsl(tmp, tmp2, 16);
1823 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1824 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1825 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1826 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1828 emith_sext(tmp, tmp2, 16);
1830 emith_clear_msb(tmp, tmp2, 16);
1831 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1832 tmp2 = rcache_get_tmp();
1834 emith_sext(tmp2, tmp3, 16);
1836 emith_clear_msb(tmp2, tmp3, 16);
1837 emith_mul(tmp, tmp, tmp2);
1838 rcache_free_tmp(tmp2);
1843 /////////////////////////////////////////////
1847 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
1848 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
1849 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
1850 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
1851 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
1852 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1853 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1854 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1855 emith_bic_r_imm(sr, T);
1856 emith_cmp_r_r(tmp2, tmp3);
1859 case 0x00: // CMP/EQ
1860 emit_or_t_if_eq(sr);
1862 case 0x02: // CMP/HS
1863 EMITH_SJMP_START(DCOND_LO);
1864 emith_or_r_imm_c(DCOND_HS, sr, T);
1865 EMITH_SJMP_END(DCOND_LO);
1867 case 0x03: // CMP/GE
1868 EMITH_SJMP_START(DCOND_LT);
1869 emith_or_r_imm_c(DCOND_GE, sr, T);
1870 EMITH_SJMP_END(DCOND_LT);
1872 case 0x06: // CMP/HI
1873 EMITH_SJMP_START(DCOND_LS);
1874 emith_or_r_imm_c(DCOND_HI, sr, T);
1875 EMITH_SJMP_END(DCOND_LS);
1877 case 0x07: // CMP/GT
1878 EMITH_SJMP_START(DCOND_LE);
1879 emith_or_r_imm_c(DCOND_GT, sr, T);
1880 EMITH_SJMP_END(DCOND_LE);
1884 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
1885 // Q1 = carry(Rn = (Rn << 1) | T)
1887 // Q2 = carry(Rn += Rm)
1889 // Q2 = carry(Rn -= Rm)
1891 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
1892 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1893 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1894 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1895 emith_tpop_carry(sr, 0);
1896 emith_adcf_r_r(tmp2, tmp2);
1897 emith_tpush_carry(sr, 0); // keep Q1 in T for now
1898 tmp4 = rcache_get_tmp();
1899 emith_and_r_r_imm(tmp4, sr, M);
1900 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
1901 rcache_free_tmp(tmp4);
1902 // add or sub, invert T if carry to get Q1 ^ Q2
1903 // in: (Q ^ M) passed in Q, Q1 in T
1904 emith_sh2_div1_step(tmp2, tmp3, sr);
1905 emith_bic_r_imm(sr, Q);
1906 emith_tst_r_imm(sr, M);
1907 EMITH_SJMP_START(DCOND_EQ);
1908 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
1909 EMITH_SJMP_END(DCOND_EQ);
1910 emith_tst_r_imm(sr, T);
1911 EMITH_SJMP_START(DCOND_EQ);
1912 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
1913 EMITH_SJMP_END(DCOND_EQ);
1914 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
1916 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
1917 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1918 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1919 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1920 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1921 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
1923 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
1924 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
1925 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1926 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1928 emith_add_r_r(tmp, tmp2);
1930 emith_sub_r_r(tmp, tmp2);
1932 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
1933 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
1934 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1935 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1936 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1937 if (op & 4) { // adc
1938 emith_tpop_carry(sr, 0);
1939 emith_adcf_r_r(tmp, tmp2);
1940 emith_tpush_carry(sr, 0);
1942 emith_tpop_carry(sr, 1);
1943 emith_sbcf_r_r(tmp, tmp2);
1944 emith_tpush_carry(sr, 1);
1947 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
1948 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
1949 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1950 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1951 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1952 emith_bic_r_imm(sr, T);
1954 emith_addf_r_r(tmp, tmp2);
1956 emith_subf_r_r(tmp, tmp2);
1957 EMITH_SJMP_START(DCOND_VC);
1958 emith_or_r_imm_c(DCOND_VS, sr, T);
1959 EMITH_SJMP_END(DCOND_VC);
1961 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
1962 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1963 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1964 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1965 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1966 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
1971 /////////////////////////////////////////////
1978 case 0: // SHLL Rn 0100nnnn00000000
1979 case 2: // SHAL Rn 0100nnnn00100000
1980 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1981 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1982 emith_tpop_carry(sr, 0); // dummy
1983 emith_lslf(tmp, tmp, 1);
1984 emith_tpush_carry(sr, 0);
1986 case 1: // DT Rn 0100nnnn00010000
1987 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1989 if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
1990 if (gconst_get(GET_Rn(), &tmp)) {
1991 // XXX: limit burned cycles
1992 emit_move_r_imm32(GET_Rn(), 0);
1993 emith_or_r_imm(sr, T);
1994 cycles += tmp * 4 + 1; // +1 syncs with noconst version, not sure why
1998 emith_sh2_dtbf_loop();
2002 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2003 emith_bic_r_imm(sr, T);
2004 emith_subf_r_imm(tmp, 1);
2005 emit_or_t_if_eq(sr);
2012 case 0: // SHLR Rn 0100nnnn00000001
2013 case 2: // SHAR Rn 0100nnnn00100001
2014 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2015 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2016 emith_tpop_carry(sr, 0); // dummy
2018 emith_asrf(tmp, tmp, 1);
2020 emith_lsrf(tmp, tmp, 1);
2021 emith_tpush_carry(sr, 0);
2023 case 1: // CMP/PZ Rn 0100nnnn00010001
2024 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2025 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2026 emith_bic_r_imm(sr, T);
2027 emith_cmp_r_imm(tmp, 0);
2028 EMITH_SJMP_START(DCOND_LT);
2029 emith_or_r_imm_c(DCOND_GE, sr, T);
2030 EMITH_SJMP_END(DCOND_LT);
2038 case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
2041 case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
2044 case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
2047 case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
2050 case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
2053 case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
2059 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2060 emith_sub_r_imm(tmp2, 4);
2062 rcache_get_reg_arg(0, GET_Rn());
2063 tmp3 = rcache_get_reg_arg(1, tmp);
2065 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
2066 emit_memhandler_write(2, pc);
2072 case 0x04: // ROTL Rn 0100nnnn00000100
2073 case 0x05: // ROTR Rn 0100nnnn00000101
2074 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2075 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2076 emith_tpop_carry(sr, 0); // dummy
2078 emith_rorf(tmp, tmp, 1);
2080 emith_rolf(tmp, tmp, 1);
2081 emith_tpush_carry(sr, 0);
2083 case 0x24: // ROTCL Rn 0100nnnn00100100
2084 case 0x25: // ROTCR Rn 0100nnnn00100101
2085 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2086 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2087 emith_tpop_carry(sr, 0);
2092 emith_tpush_carry(sr, 0);
2094 case 0x15: // CMP/PL Rn 0100nnnn00010101
2095 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2096 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2097 emith_bic_r_imm(sr, T);
2098 emith_cmp_r_imm(tmp, 0);
2099 EMITH_SJMP_START(DCOND_LE);
2100 emith_or_r_imm_c(DCOND_GT, sr, T);
2101 EMITH_SJMP_END(DCOND_LE);
2109 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
2112 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
2115 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
2118 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
2121 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
2124 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
2130 rcache_get_reg_arg(0, GET_Rn());
2131 tmp2 = emit_memhandler_read(2);
2132 if (tmp == SHR_SR) {
2133 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2134 emith_write_sr(sr, tmp2);
2137 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
2138 emith_move_r_r(tmp, tmp2);
2140 rcache_free_tmp(tmp2);
2141 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2142 emith_add_r_imm(tmp, 4);
2149 // SHLL2 Rn 0100nnnn00001000
2150 // SHLR2 Rn 0100nnnn00001001
2154 // SHLL8 Rn 0100nnnn00011000
2155 // SHLR8 Rn 0100nnnn00011001
2159 // SHLL16 Rn 0100nnnn00101000
2160 // SHLR16 Rn 0100nnnn00101001
2166 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2168 emith_lsr(tmp2, tmp2, tmp);
2170 emith_lsl(tmp2, tmp2, tmp);
2175 case 0: // LDS Rm,MACH 0100mmmm00001010
2178 case 1: // LDS Rm,MACL 0100mmmm00011010
2181 case 2: // LDS Rm,PR 0100mmmm00101010
2187 emit_move_r_r(tmp2, GET_Rn());
2192 case 1: // TAS.B @Rn 0100nnnn00011011
2193 // XXX: is TAS working on 32X?
2194 rcache_get_reg_arg(0, GET_Rn());
2195 tmp = emit_memhandler_read(0);
2196 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2197 emith_bic_r_imm(sr, T);
2198 emith_cmp_r_imm(tmp, 0);
2199 emit_or_t_if_eq(sr);
2201 emith_or_r_imm(tmp, 0x80);
2202 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
2203 emith_move_r_r(tmp2, tmp);
2204 rcache_free_tmp(tmp);
2205 rcache_get_reg_arg(0, GET_Rn());
2206 emit_memhandler_write(0, pc);
2213 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2216 case 0: // LDC Rm,SR 0100mmmm00001110
2219 case 1: // LDC Rm,GBR 0100mmmm00011110
2222 case 2: // LDC Rm,VBR 0100mmmm00101110
2228 if (tmp2 == SHR_SR) {
2229 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2230 emith_write_sr(sr, tmp);
2233 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
2234 emith_move_r_r(tmp2, tmp);
2238 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
2239 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
2240 emith_sext(tmp, tmp, 16);
2241 emith_sext(tmp2, tmp2, 16);
2242 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
2243 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
2244 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
2245 rcache_free_tmp(tmp2);
2246 // XXX: MACH should be untouched when S is set?
2247 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2248 emith_tst_r_imm(sr, S);
2249 EMITH_JMP_START(DCOND_EQ);
2251 emith_asr(tmp, tmp3, 31);
2252 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
2253 EMITH_JMP_START(DCOND_EQ);
2254 emith_move_r_imm(tmp3, 0x80000000);
2255 emith_tst_r_r(tmp4, tmp4);
2256 EMITH_SJMP_START(DCOND_MI);
2257 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
2258 EMITH_SJMP_END(DCOND_MI);
2259 EMITH_JMP_END(DCOND_EQ);
2261 EMITH_JMP_END(DCOND_EQ);
2262 rcache_free_tmp(tmp);
2267 /////////////////////////////////////////////
2269 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
2270 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2);
2273 /////////////////////////////////////////////
2277 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
2278 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
2279 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
2280 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
2281 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
2282 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
2283 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), 0, op & 3);
2284 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
2285 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
2286 emith_add_r_imm(tmp, (1 << (op & 3)));
2291 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
2292 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2295 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
2296 emith_move_r_r(tmp2, tmp);
2298 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
2299 emith_mvn_r_r(tmp2, tmp);
2301 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
2304 tmp3 = rcache_get_tmp();
2305 tmp4 = rcache_get_tmp();
2306 emith_lsr(tmp3, tmp, 16);
2307 emith_or_r_r_lsl(tmp3, tmp, 24);
2308 emith_and_r_r_imm(tmp4, tmp, 0xff00);
2309 emith_or_r_r_lsl(tmp3, tmp4, 8);
2310 emith_rol(tmp2, tmp3, 16);
2311 rcache_free_tmp(tmp4);
2313 rcache_free_tmp(tmp3);
2315 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
2316 emith_rol(tmp2, tmp, 16);
2318 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
2319 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2320 emith_tpop_carry(sr, 1);
2321 emith_negcf_r_r(tmp2, tmp);
2322 emith_tpush_carry(sr, 1);
2324 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
2325 emith_neg_r_r(tmp2, tmp);
2327 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
2328 emith_clear_msb(tmp2, tmp, 24);
2330 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
2331 emith_clear_msb(tmp2, tmp, 16);
2333 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
2334 emith_sext(tmp2, tmp, 8);
2336 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
2337 emith_sext(tmp2, tmp, 16);
2344 /////////////////////////////////////////////
2346 // ADD #imm,Rn 0111nnnniiiiiiii
2347 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2348 if (op & 0x80) { // adding negative
2349 emith_sub_r_imm(tmp, -op & 0xff);
2351 emith_add_r_imm(tmp, op & 0xff);
2354 /////////////////////////////////////////////
2356 switch (op & 0x0f00)
2358 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
2359 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
2361 tmp = rcache_get_reg_arg(0, GET_Rm());
2362 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2363 tmp3 = (op & 0x100) >> 8;
2365 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
2366 emit_memhandler_write(tmp3, pc);
2368 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
2369 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
2370 tmp = (op & 0x100) >> 8;
2371 emit_memhandler_read_rr(SHR_R0, GET_Rm(), (op & 0x0f) << tmp, tmp);
2373 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
2374 // XXX: could use cmn
2375 tmp = rcache_get_tmp();
2376 tmp2 = rcache_get_reg(0, RC_GR_READ);
2377 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2378 emith_move_r_imm_s8(tmp, op & 0xff);
2379 emith_bic_r_imm(sr, T);
2380 emith_cmp_r_r(tmp2, tmp);
2381 emit_or_t_if_eq(sr);
2382 rcache_free_tmp(tmp);
2387 /////////////////////////////////////////////
2389 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
2390 tmp = pc + (op & 0xff) * 2 + 2;
2391 #if PROPAGATE_CONSTANTS
2392 if (tmp < end_pc + MAX_LITERAL_OFFSET && literal_addr_count < MAX_LITERALS) {
2393 ADD_TO_ARRAY(literal_addr, literal_addr_count, tmp,);
2394 gconst_new(GET_Rn(), (u32)(int)(signed short)FETCH_OP(tmp));
2399 tmp2 = rcache_get_tmp_arg(0);
2400 emith_move_r_imm(tmp2, tmp);
2401 tmp2 = emit_memhandler_read(1);
2402 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2403 emith_sext(tmp3, tmp2, 16);
2404 rcache_free_tmp(tmp2);
2408 /////////////////////////////////////////////
2410 switch (op & 0x0f00)
2412 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
2413 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
2414 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
2416 tmp = rcache_get_reg_arg(0, SHR_GBR);
2417 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2418 tmp3 = (op & 0x300) >> 8;
2419 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
2420 emit_memhandler_write(tmp3, pc);
2422 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
2423 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
2424 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
2425 tmp = (op & 0x300) >> 8;
2426 emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp);
2428 case 0x0300: // TRAPA #imm 11000011iiiiiiii
2429 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2430 emith_sub_r_imm(tmp, 4*2);
2432 tmp = rcache_get_reg_arg(0, SHR_SP);
2433 emith_add_r_imm(tmp, 4);
2434 tmp = rcache_get_reg_arg(1, SHR_SR);
2435 emith_clear_msb(tmp, tmp, 22);
2436 emit_memhandler_write(2, pc);
2438 rcache_get_reg_arg(0, SHR_SP);
2439 tmp = rcache_get_tmp_arg(1);
2440 emith_move_r_imm(tmp, pc);
2441 emit_memhandler_write(2, pc);
2443 emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
2444 // indirect jump -> back to dispatcher
2446 emith_jump(sh2_drc_dispatcher);
2448 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
2449 emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3);
2451 case 0x0800: // TST #imm,R0 11001000iiiiiiii
2452 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
2453 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2454 emith_bic_r_imm(sr, T);
2455 emith_tst_r_imm(tmp, op & 0xff);
2456 emit_or_t_if_eq(sr);
2458 case 0x0900: // AND #imm,R0 11001001iiiiiiii
2459 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2460 emith_and_r_imm(tmp, op & 0xff);
2462 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
2463 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2464 emith_eor_r_imm(tmp, op & 0xff);
2466 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
2467 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2468 emith_or_r_imm(tmp, op & 0xff);
2470 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
2471 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2472 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2473 emith_bic_r_imm(sr, T);
2474 emith_tst_r_imm(tmp, op & 0xff);
2475 emit_or_t_if_eq(sr);
2476 rcache_free_tmp(tmp);
2478 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2479 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2480 emith_and_r_imm(tmp, op & 0xff);
2482 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2483 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2484 emith_eor_r_imm(tmp, op & 0xff);
2486 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2487 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2488 emith_or_r_imm(tmp, op & 0xff);
2490 tmp2 = rcache_get_tmp_arg(1);
2491 emith_move_r_r(tmp2, tmp);
2492 rcache_free_tmp(tmp);
2493 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2494 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2495 emith_add_r_r(tmp3, tmp4);
2496 emit_memhandler_write(0, pc);
2501 /////////////////////////////////////////////
2503 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
2504 tmp = (pc + (op & 0xff) * 4 + 2) & ~3;
2505 #if PROPAGATE_CONSTANTS
2506 if (tmp < end_pc + MAX_LITERAL_OFFSET && literal_addr_count < MAX_LITERALS) {
2507 ADD_TO_ARRAY(literal_addr, literal_addr_count, tmp,);
2508 gconst_new(GET_Rn(), FETCH32(tmp));
2513 tmp2 = rcache_get_tmp_arg(0);
2514 emith_move_r_imm(tmp2, tmp);
2515 tmp2 = emit_memhandler_read(2);
2516 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2517 emith_move_r_r(tmp3, tmp2);
2518 rcache_free_tmp(tmp2);
2522 /////////////////////////////////////////////
2524 // MOV #imm,Rn 1110nnnniiiiiiii
2525 emit_move_r_imm32(GET_Rn(), (u32)(signed int)(signed char)op);
2530 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
2531 sh2->is_slave ? 's' : 'm', op, pc - 2);
2536 rcache_unlock_all();
2538 cycles += opd->cycles;
2540 if (op_flags[i+1] & OF_DELAY_OP) {
2541 do_host_disasm(tcache_id);
2546 if (drcf.test_irq && !drcf.pending_branch_direct) {
2547 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2550 emith_call(sh2_drc_test_irq);
2554 // branch handling (with/without delay)
2555 if (drcf.pending_branch_direct)
2557 struct op_data *opd_b =
2558 (op_flags[i] & OF_DELAY_OP) ? &ops[i-1] : opd;
2559 u32 target_pc = opd_b->imm;
2561 void *target = NULL;
2563 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2566 if (opd_b->op != OP_BRANCH)
2567 cond = (opd_b->op == OP_BRANCH_CF) ? DCOND_EQ : DCOND_NE;
2569 int ctaken = (op_flags[i] & OF_DELAY_OP) ? 1 : 2;
2571 if (delay_dep_fw & BITMASK1(SHR_T))
2572 emith_tst_r_imm(sr, T_save);
2574 emith_tst_r_imm(sr, T);
2576 emith_sub_r_imm_c(cond, sr, ctaken<<12);
2581 if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0)
2584 // XXX: jumps back can be linked already
2585 if (branch_patch_count < MAX_LOCAL_BRANCHES) {
2586 target = tcache_ptr;
2587 branch_patch_pc[branch_patch_count] = target_pc;
2588 branch_patch_ptr[branch_patch_count] = target;
2589 branch_patch_count++;
2592 dbg(1, "warning: too many local branches");
2598 // can't resolve branch locally, make a block exit
2599 emit_move_r_imm32(SHR_PC, target_pc);
2602 target = dr_prepare_ext_branch(target_pc, sh2->is_slave, tcache_id);
2608 emith_jump_cond_patchable(cond, target);
2610 emith_jump_patchable(target);
2611 rcache_invalidate();
2614 drcf.pending_branch_direct = 0;
2616 else if (drcf.pending_branch_indirect) {
2617 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2620 emith_jump(sh2_drc_dispatcher);
2621 drcf.pending_branch_indirect = 0;
2624 do_host_disasm(tcache_id);
2627 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2631 // check the last op
2632 if (op_flags[i-1] & OF_DELAY_OP)
2637 if (opd->op != OP_BRANCH && opd->op != OP_BRANCH_R
2638 && opd->op != OP_BRANCH_RF && opd->op != OP_RTE)
2642 emit_move_r_imm32(SHR_PC, pc);
2645 target = dr_prepare_ext_branch(pc, sh2->is_slave, tcache_id);
2648 emith_jump_patchable(target);
2651 // link local branches
2652 for (i = 0; i < branch_patch_count; i++) {
2655 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2656 target = branch_target_ptr[t];
2657 if (target == NULL) {
2658 // flush pc and go back to dispatcher (this should no longer happen)
2659 dbg(1, "stray branch to %08x %p", branch_patch_pc[i], tcache_ptr);
2660 target = tcache_ptr;
2661 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2663 emith_jump(sh2_drc_dispatcher);
2665 emith_jump_patch(branch_patch_ptr[i], target);
2668 // mark memory blocks as containing compiled code
2669 // override any overlay blocks as they become unreachable anyway
2670 if (tcache_id != 0 || (block->addr & 0xc7fc0000) == 0x06000000)
2672 u16 *drc_ram_blk = NULL;
2673 u32 addr, mask = 0, shift = 0;
2675 if (tcache_id != 0) {
2677 drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave];
2678 shift = SH2_DRCBLK_DA_SHIFT;
2681 else if ((block->addr & 0xc7fc0000) == 0x06000000) {
2683 drc_ram_blk = Pico32xMem->drcblk_ram;
2684 shift = SH2_DRCBLK_RAM_SHIFT;
2688 // mark recompiled insns
2689 drc_ram_blk[(base_pc & mask) >> shift] = 1;
2690 for (pc = base_pc; pc < end_pc; pc += 2)
2691 drc_ram_blk[(pc & mask) >> shift] = 1;
2694 for (i = 0; i < literal_addr_count; i++) {
2695 tmp = literal_addr[i];
2696 drc_ram_blk[(tmp & mask) >> shift] = 1;
2699 // add to invalidation lookup lists
2700 addr = base_pc & ~(ADDR_TO_BLOCK_PAGE - 1);
2701 for (; addr < end_literals; addr += ADDR_TO_BLOCK_PAGE) {
2702 i = (addr & mask) / ADDR_TO_BLOCK_PAGE;
2703 add_to_block_list(&inval_lookup[tcache_id][i], block);
2707 tcache_ptrs[tcache_id] = tcache_ptr;
2709 host_instructions_updated(block_entry_ptr, tcache_ptr);
2711 do_host_disasm(tcache_id);
2712 dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2713 tcache_id, blkid_main,
2714 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2715 insns_compiled, host_insn_count, (float)host_insn_count / insns_compiled);
2716 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2717 dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2720 tcache_dsm_ptrs[tcache_id] = block_entry_ptr;
2721 do_host_disasm(tcache_id);
2729 return block_entry_ptr;
2732 static void sh2_generate_utils(void)
2734 int arg0, arg1, arg2, sr, tmp;
2736 sh2_drc_write32 = p32x_sh2_write32;
2737 sh2_drc_read8 = p32x_sh2_read8;
2738 sh2_drc_read16 = p32x_sh2_read16;
2739 sh2_drc_read32 = p32x_sh2_read32;
2741 host_arg2reg(arg0, 0);
2742 host_arg2reg(arg1, 1);
2743 host_arg2reg(arg2, 2);
2744 emith_move_r_r(arg0, arg0); // nop
2746 // sh2_drc_exit(void)
2747 sh2_drc_exit = (void *)tcache_ptr;
2748 emit_do_static_regs(1, arg2);
2749 emith_sh2_drc_exit();
2751 // sh2_drc_dispatcher(void)
2752 sh2_drc_dispatcher = (void *)tcache_ptr;
2753 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2754 emith_cmp_r_imm(sr, 0);
2755 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2756 rcache_invalidate();
2757 emith_ctx_read(arg0, SHR_PC * 4);
2758 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2759 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2760 emith_call(dr_lookup_block);
2762 // lookup failed, call sh2_translate()
2763 emith_move_r_r(arg0, CONTEXT_REG);
2764 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2765 emith_call(sh2_translate);
2767 // sh2_translate() failed, flush cache and retry
2768 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2769 emith_call(flush_tcache);
2770 emith_move_r_r(arg0, CONTEXT_REG);
2771 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2772 emith_call(sh2_translate);
2774 // XXX: can't translate, fail
2775 emith_call(dr_failure);
2777 // sh2_drc_test_irq(void)
2778 // assumes it's called from main function (may jump to dispatcher)
2779 sh2_drc_test_irq = (void *)tcache_ptr;
2780 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2781 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2782 emith_lsr(arg0, sr, I_SHIFT);
2783 emith_and_r_imm(arg0, 0x0f);
2784 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2785 EMITH_SJMP_START(DCOND_GT);
2786 emith_ret_c(DCOND_LE); // nope, return
2787 EMITH_SJMP_END(DCOND_GT);
2789 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2790 emith_sub_r_imm(tmp, 4*2);
2793 tmp = rcache_get_reg_arg(0, SHR_SP);
2794 emith_add_r_imm(tmp, 4);
2795 tmp = rcache_get_reg_arg(1, SHR_SR);
2796 emith_clear_msb(tmp, tmp, 22);
2797 emith_move_r_r(arg2, CONTEXT_REG);
2798 emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
2799 rcache_invalidate();
2801 rcache_get_reg_arg(0, SHR_SP);
2802 emith_ctx_read(arg1, SHR_PC * 4);
2803 emith_move_r_r(arg2, CONTEXT_REG);
2804 emith_call(p32x_sh2_write32);
2805 rcache_invalidate();
2806 // update I, cycles, do callback
2807 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2808 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2809 emith_bic_r_imm(sr, I);
2810 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2811 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2813 emith_move_r_r(arg0, CONTEXT_REG);
2814 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2816 emith_lsl(arg0, arg0, 2);
2817 emith_ctx_read(arg1, SHR_VBR * 4);
2818 emith_add_r_r(arg0, arg1);
2819 emit_memhandler_read(2);
2820 emith_ctx_write(arg0, SHR_PC * 4);
2822 emith_add_r_imm(xSP, 4); // fix stack
2824 emith_jump(sh2_drc_dispatcher);
2825 rcache_invalidate();
2827 // sh2_drc_entry(SH2 *sh2)
2828 sh2_drc_entry = (void *)tcache_ptr;
2829 emith_sh2_drc_entry();
2830 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2831 emit_do_static_regs(0, arg2);
2832 emith_call(sh2_drc_test_irq);
2833 emith_jump(sh2_drc_dispatcher);
2835 // sh2_drc_write8(u32 a, u32 d)
2836 sh2_drc_write8 = (void *)tcache_ptr;
2837 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2838 emith_sh2_wcall(arg0, arg2);
2840 // sh2_drc_write16(u32 a, u32 d)
2841 sh2_drc_write16 = (void *)tcache_ptr;
2842 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2843 emith_sh2_wcall(arg0, arg2);
2847 #define MAKE_READ_WRAPPER(func) { \
2848 void *tmp = (void *)tcache_ptr; \
2851 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2852 emith_addf_r_r(arg2, arg0); \
2853 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2854 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2855 emith_adc_r_imm(arg2, 0x01000000); \
2856 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2857 emith_pop_and_ret(); \
2860 #define MAKE_WRITE_WRAPPER(func) { \
2861 void *tmp = (void *)tcache_ptr; \
2862 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2863 emith_addf_r_r(arg2, arg1); \
2864 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2865 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2866 emith_adc_r_imm(arg2, 0x01000000); \
2867 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2868 emith_move_r_r(arg2, CONTEXT_REG); \
2873 MAKE_READ_WRAPPER(sh2_drc_read8);
2874 MAKE_READ_WRAPPER(sh2_drc_read16);
2875 MAKE_READ_WRAPPER(sh2_drc_read32);
2876 MAKE_WRITE_WRAPPER(sh2_drc_write8);
2877 MAKE_WRITE_WRAPPER(sh2_drc_write16);
2878 MAKE_WRITE_WRAPPER(sh2_drc_write32);
2880 host_dasm_new_symbol(sh2_drc_read8);
2881 host_dasm_new_symbol(sh2_drc_read16);
2882 host_dasm_new_symbol(sh2_drc_read32);
2883 host_dasm_new_symbol(sh2_drc_write32);
2887 rcache_invalidate();
2889 host_dasm_new_symbol(sh2_drc_entry);
2890 host_dasm_new_symbol(sh2_drc_dispatcher);
2891 host_dasm_new_symbol(sh2_drc_exit);
2892 host_dasm_new_symbol(sh2_drc_test_irq);
2893 host_dasm_new_symbol(sh2_drc_write8);
2894 host_dasm_new_symbol(sh2_drc_write16);
2898 static void sh2_smc_rm_block_entry(struct block_desc *bd, int tcache_id, u32 ram_mask)
2900 struct block_link *bl, *bl_next, *bl_unresolved;
2904 dbg(2, " killing entry %08x-%08x, blkid %d,%d",
2905 bd->addr, bd->end_addr, tcache_id, bd - block_tables[tcache_id]);
2906 if (bd->addr == 0 || bd->entry_count == 0) {
2907 dbg(1, " killing dead block!? %08x", bd->addr);
2911 // remove from inval_lookup
2912 addr = bd->addr & ~(ADDR_TO_BLOCK_PAGE - 1);
2913 for (; addr < bd->end_addr; addr += ADDR_TO_BLOCK_PAGE) {
2914 i = (addr & ram_mask) / ADDR_TO_BLOCK_PAGE;
2915 rm_from_block_list(&inval_lookup[tcache_id][i], bd);
2919 bl_unresolved = unresolved_links[tcache_id];
2921 // remove from hash table, make incoming links unresolved
2922 // XXX: maybe patch branches w/flush instead?
2923 for (i = 0; i < bd->entry_count; i++) {
2924 rm_from_hashlist(&bd->entryp[i], tcache_id);
2926 // since we never reuse tcache space of dead blocks,
2927 // insert jump to dispatcher for blocks that are linked to this
2928 tcache_ptr = bd->entryp[i].tcache_ptr;
2929 emit_move_r_imm32(SHR_PC, bd->addr);
2931 emith_jump(sh2_drc_dispatcher);
2933 host_instructions_updated(bd->entryp[i].tcache_ptr, tcache_ptr);
2935 for (bl = bd->entryp[i].links; bl != NULL; ) {
2937 bl->next = bl_unresolved;
2944 unresolved_links[tcache_id] = bl_unresolved;
2946 bd->addr = bd->end_addr = 0;
2947 bd->entry_count = 0;
2950 static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask)
2952 struct block_list **blist = NULL, *entry;
2953 u32 from = ~0, to = 0;
2954 struct block_desc *block;
2956 blist = &inval_lookup[tcache_id][(a & mask) / ADDR_TO_BLOCK_PAGE];
2958 while (entry != NULL) {
2959 block = entry->block;
2960 if (block->addr <= a && a < block->end_addr) {
2961 if (block->addr < from)
2963 if (block->end_addr > to)
2964 to = block->end_addr;
2966 sh2_smc_rm_block_entry(block, tcache_id, mask);
2968 // entry lost, restart search
2972 entry = entry->next;
2975 // update range to not clear still alive blocks
2976 for (entry = *blist; entry != NULL; entry = entry->next) {
2977 block = entry->block;
2978 if (block->addr > a) {
2979 if (to > block->addr)
2983 if (from < block->end_addr)
2984 from = block->end_addr;
2990 u16 *p = drc_ram_blk + ((from & mask) >> shift);
2991 memset(p, 0, (to - from) >> (shift - 1));
2995 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
2997 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
2998 sh2_smc_rm_block(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
3001 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
3003 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3004 sh2_smc_rm_block(a, Pico32xMem->drcblk_da[cpuid],
3005 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
3008 int sh2_execute(SH2 *sh2c, int cycles)
3012 sh2c->cycles_timeslice = cycles;
3014 // cycles are kept in SHR_SR unused bits (upper 20)
3015 // bit11 contains T saved for delay slot
3016 // others are usual SH2 flags
3018 sh2c->sr |= cycles << 12;
3019 sh2_drc_entry(sh2c);
3022 ret_cycles = (signed int)sh2c->sr >> 12;
3024 dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
3026 return sh2c->cycles_timeslice - ret_cycles;
3030 void block_stats(void)
3032 int c, b, i, total = 0;
3034 printf("block stats:\n");
3035 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3036 for (i = 0; i < block_counts[b]; i++)
3037 if (block_tables[b][i].addr != 0)
3038 total += block_tables[b][i].refcount;
3040 for (c = 0; c < 10; c++) {
3041 struct block_desc *blk, *maxb = NULL;
3043 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
3044 for (i = 0; i < block_counts[b]; i++) {
3045 blk = &block_tables[b][i];
3046 if (blk->addr != 0 && blk->refcount > max) {
3047 max = blk->refcount;
3054 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
3055 (double)maxb->refcount / total * 100.0);
3059 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3060 for (i = 0; i < block_counts[b]; i++)
3061 block_tables[b][i].refcount = 0;
3064 #define block_stats()
3067 void sh2_drc_flush_all(void)
3075 void sh2_drc_mem_setup(SH2 *sh2)
3077 // fill the convenience pointers
3078 sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3079 sh2->p_da = Pico32xMem->data_array[sh2->is_slave];
3080 sh2->p_sdram = Pico32xMem->sdram;
3081 sh2->p_rom = Pico.rom;
3084 int sh2_drc_init(SH2 *sh2)
3088 if (block_tables[0] == NULL)
3090 for (i = 0; i < TCACHE_BUFFERS; i++) {
3091 block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0]));
3092 if (block_tables[i] == NULL)
3094 // max 2 block links (exits) per block
3095 block_link_pool[i] = calloc(block_link_pool_max_counts[i],
3096 sizeof(*block_link_pool[0]));
3097 if (block_link_pool[i] == NULL)
3100 inval_lookup[i] = calloc(ram_sizes[i] / ADDR_TO_BLOCK_PAGE,
3101 sizeof(inval_lookup[0]));
3102 if (inval_lookup[i] == NULL)
3105 hash_tables[i] = calloc(hash_table_sizes[i], sizeof(*hash_tables[0]));
3106 if (hash_tables[i] == NULL)
3109 memset(block_counts, 0, sizeof(block_counts));
3110 memset(block_link_pool_counts, 0, sizeof(block_link_pool_counts));
3113 tcache_ptr = tcache;
3114 sh2_generate_utils();
3115 host_instructions_updated(tcache, tcache_ptr);
3117 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
3118 for (i = 1; i < ARRAY_SIZE(tcache_bases); i++)
3119 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
3122 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
3123 tcache_dsm_ptrs[i] = tcache_bases[i];
3125 tcache_dsm_ptrs[0] = tcache;
3129 hash_collisions = 0;
3136 sh2_drc_finish(sh2);
3140 void sh2_drc_finish(SH2 *sh2)
3144 if (block_tables[0] == NULL)
3147 sh2_drc_flush_all();
3149 for (i = 0; i < TCACHE_BUFFERS; i++) {
3151 printf("~~~ tcache %d\n", i);
3152 tcache_dsm_ptrs[i] = tcache_bases[i];
3153 tcache_ptr = tcache_ptrs[i];
3157 if (block_tables[i] != NULL)
3158 free(block_tables[i]);
3159 block_tables[i] = NULL;
3160 if (block_link_pool[i] == NULL)
3161 free(block_link_pool[i]);
3162 block_link_pool[i] = NULL;
3164 if (inval_lookup[i] == NULL)
3165 free(inval_lookup[i]);
3166 inval_lookup[i] = NULL;
3168 if (hash_tables[i] != NULL) {
3169 free(hash_tables[i]);
3170 hash_tables[i] = NULL;
3177 #endif /* DRC_SH2 */
3179 static void *dr_get_pc_base(u32 pc, int is_slave)
3184 if ((pc & ~0x7ff) == 0) {
3186 ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3189 else if ((pc & 0xfffff000) == 0xc0000000) {
3191 ret = Pico32xMem->data_array[is_slave];
3194 else if ((pc & 0xc6000000) == 0x06000000) {
3196 ret = Pico32xMem->sdram;
3199 else if ((pc & 0xc6000000) == 0x02000000) {
3206 return (void *)-1; // NULL is valid value
3208 return (char *)ret - (pc & ~mask);
3211 void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
3212 u32 *end_literals_out)
3216 u32 end_pc, end_literals = 0;
3217 struct op_data *opd;
3218 int next_is_delay = 0;
3222 memset(op_flags, 0, BLOCK_INSN_LIMIT);
3224 dr_pc_base = dr_get_pc_base(base_pc, is_slave);
3226 // 1st pass: disassemble
3227 for (i = 0, pc = base_pc; ; i++, pc += 2) {
3228 // we need an ops[] entry after the last one initialized,
3229 // so do it before end_block checks
3231 opd->op = OP_UNHANDLED;
3233 opd->source = opd->dest = 0;
3237 if (next_is_delay) {
3238 op_flags[i] |= OF_DELAY_OP;
3241 else if (end_block || i >= BLOCK_INSN_LIMIT - 2)
3245 switch ((op & 0xf000) >> 12)
3247 /////////////////////////////////////////////
3254 case 0: // STC SR,Rn 0000nnnn00000010
3257 case 1: // STC GBR,Rn 0000nnnn00010010
3260 case 2: // STC VBR,Rn 0000nnnn00100010
3267 opd->source = BITMASK1(tmp);
3268 opd->dest = BITMASK1(GET_Rn());
3271 CHECK_UNHANDLED_BITS(0xd0, undefined);
3272 // BRAF Rm 0000mmmm00100011
3273 // BSRF Rm 0000mmmm00000011
3274 opd->op = OP_BRANCH_RF;
3276 opd->source = BITMASK1(opd->rm);
3277 opd->dest = BITMASK1(SHR_PC);
3279 opd->dest |= BITMASK1(SHR_PR);
3284 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
3285 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
3286 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
3287 opd->source = BITMASK3(GET_Rm(), SHR_R0, GET_Rn());
3290 // MUL.L Rm,Rn 0000nnnnmmmm0111
3291 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3292 opd->dest = BITMASK1(SHR_MACL);
3296 CHECK_UNHANDLED_BITS(0xf00, undefined);
3299 case 0: // CLRT 0000000000001000
3300 opd->op = OP_SETCLRT;
3301 opd->dest = BITMASK1(SHR_T);
3304 case 1: // SETT 0000000000011000
3305 opd->op = OP_SETCLRT;
3306 opd->dest = BITMASK1(SHR_T);
3309 case 2: // CLRMAC 0000000000101000
3310 opd->dest = BITMASK3(SHR_T, SHR_MACL, SHR_MACH);
3319 case 0: // NOP 0000000000001001
3320 CHECK_UNHANDLED_BITS(0xf00, undefined);
3322 case 1: // DIV0U 0000000000011001
3323 CHECK_UNHANDLED_BITS(0xf00, undefined);
3324 opd->dest = BITMASK2(SHR_SR, SHR_T);
3326 case 2: // MOVT Rn 0000nnnn00101001
3327 opd->source = BITMASK1(SHR_T);
3328 opd->dest = BITMASK1(GET_Rn());
3337 case 0: // STS MACH,Rn 0000nnnn00001010
3340 case 1: // STS MACL,Rn 0000nnnn00011010
3343 case 2: // STS PR,Rn 0000nnnn00101010
3350 opd->source = BITMASK1(tmp);
3351 opd->dest = BITMASK1(GET_Rn());
3354 CHECK_UNHANDLED_BITS(0xf00, undefined);
3357 case 0: // RTS 0000000000001011
3358 opd->op = OP_BRANCH_R;
3360 opd->source = BITMASK1(opd->rm);
3361 opd->dest = BITMASK1(SHR_PC);
3366 case 1: // SLEEP 0000000000011011
3370 case 2: // RTE 0000000000101011
3372 opd->source = BITMASK1(SHR_SP);
3373 opd->dest = BITMASK2(SHR_SR, SHR_PC);
3382 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
3383 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
3384 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
3385 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3386 opd->dest = BITMASK1(GET_Rn());
3388 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
3389 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3390 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3398 /////////////////////////////////////////////
3400 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
3401 opd->source = BITMASK1(GET_Rm());
3402 opd->source = BITMASK1(GET_Rn());
3403 opd->imm = (op & 0x0f) * 4;
3406 /////////////////////////////////////////////
3410 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
3411 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
3412 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
3413 opd->source = BITMASK1(GET_Rm());
3414 opd->source = BITMASK1(GET_Rn());
3416 case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
3417 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
3418 case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110
3419 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3420 opd->dest = BITMASK1(GET_Rn());
3422 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
3423 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3424 opd->dest = BITMASK1(SHR_SR);
3426 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
3427 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3428 opd->dest = BITMASK1(SHR_T);
3430 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
3431 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
3432 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
3433 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3434 opd->dest = BITMASK1(GET_Rn());
3436 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
3437 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3438 opd->dest = BITMASK1(SHR_T);
3440 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
3441 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3442 opd->dest = BITMASK1(GET_Rn());
3444 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
3445 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
3446 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3447 opd->dest = BITMASK1(SHR_MACL);
3454 /////////////////////////////////////////////
3458 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
3459 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
3460 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
3461 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
3462 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
3463 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3464 opd->dest = BITMASK1(SHR_T);
3466 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
3467 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_SR);
3468 opd->dest = BITMASK2(GET_Rn(), SHR_SR);
3470 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
3471 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
3472 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3473 opd->dest = BITMASK2(SHR_MACL, SHR_MACH);
3476 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
3477 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
3478 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3479 opd->dest = BITMASK1(GET_Rn());
3481 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
3482 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
3483 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_T);
3484 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3486 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
3487 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
3488 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3489 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3496 /////////////////////////////////////////////
3503 case 0: // SHLL Rn 0100nnnn00000000
3504 case 2: // SHAL Rn 0100nnnn00100000
3505 opd->source = BITMASK1(GET_Rn());
3506 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3508 case 1: // DT Rn 0100nnnn00010000
3509 opd->source = BITMASK1(GET_Rn());
3510 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3519 case 0: // SHLR Rn 0100nnnn00000001
3520 case 2: // SHAR Rn 0100nnnn00100001
3521 opd->source = BITMASK1(GET_Rn());
3522 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3524 case 1: // CMP/PZ Rn 0100nnnn00010001
3525 opd->source = BITMASK1(GET_Rn());
3526 opd->dest = BITMASK1(SHR_T);
3536 case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
3539 case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
3542 case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
3545 case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
3549 case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
3553 case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
3560 opd->source = BITMASK2(GET_Rn(), tmp);
3561 opd->dest = BITMASK1(GET_Rn());
3567 case 0x04: // ROTL Rn 0100nnnn00000100
3568 case 0x05: // ROTR Rn 0100nnnn00000101
3569 opd->source = BITMASK1(GET_Rn());
3570 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3572 case 0x24: // ROTCL Rn 0100nnnn00100100
3573 case 0x25: // ROTCR Rn 0100nnnn00100101
3574 opd->source = BITMASK2(GET_Rn(), SHR_T);
3575 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3577 case 0x15: // CMP/PL Rn 0100nnnn00010101
3578 opd->source = BITMASK1(GET_Rn());
3579 opd->dest = BITMASK1(SHR_T);
3589 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
3592 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
3595 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
3598 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
3602 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
3606 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
3613 opd->source = BITMASK1(GET_Rn());
3614 opd->dest = BITMASK2(GET_Rn(), tmp);
3621 // SHLL2 Rn 0100nnnn00001000
3622 // SHLR2 Rn 0100nnnn00001001
3625 // SHLL8 Rn 0100nnnn00011000
3626 // SHLR8 Rn 0100nnnn00011001
3629 // SHLL16 Rn 0100nnnn00101000
3630 // SHLR16 Rn 0100nnnn00101001
3635 opd->source = BITMASK1(GET_Rn());
3636 opd->dest = BITMASK1(GET_Rn());
3641 case 0: // LDS Rm,MACH 0100mmmm00001010
3644 case 1: // LDS Rm,MACL 0100mmmm00011010
3647 case 2: // LDS Rm,PR 0100mmmm00101010
3654 opd->source = BITMASK1(GET_Rn());
3655 opd->dest = BITMASK1(tmp);
3660 case 0: // JSR @Rm 0100mmmm00001011
3661 opd->dest = BITMASK1(SHR_PR);
3662 case 2: // JMP @Rm 0100mmmm00101011
3663 opd->op = OP_BRANCH_R;
3665 opd->source = BITMASK1(opd->rm);
3666 opd->dest |= BITMASK1(SHR_PC);
3671 case 1: // TAS.B @Rn 0100nnnn00011011
3672 opd->source = BITMASK1(GET_Rn());
3673 opd->dest = BITMASK1(SHR_T);
3683 case 0: // LDC Rm,SR 0100mmmm00001110
3686 case 1: // LDC Rm,GBR 0100mmmm00011110
3689 case 2: // LDC Rm,VBR 0100mmmm00101110
3696 opd->source = BITMASK1(GET_Rn());
3697 opd->dest = BITMASK1(tmp);
3700 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
3701 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3702 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3710 /////////////////////////////////////////////
3712 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
3713 opd->source = BITMASK1(GET_Rm());
3714 opd->dest = BITMASK1(GET_Rn());
3715 opd->imm = (op & 0x0f) * 4;
3718 /////////////////////////////////////////////
3722 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
3723 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
3724 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
3725 opd->dest = BITMASK1(GET_Rm());
3726 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
3727 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
3728 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
3729 opd->source = BITMASK1(GET_Rm());
3730 opd->dest |= BITMASK1(GET_Rn());
3732 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
3735 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
3736 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
3737 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
3738 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
3739 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
3740 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
3741 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
3742 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
3743 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
3745 opd->source = BITMASK1(GET_Rm());
3746 opd->dest = BITMASK1(GET_Rn());
3751 /////////////////////////////////////////////
3753 // ADD #imm,Rn 0111nnnniiiiiiii
3754 opd->source = opd->dest = BITMASK1(GET_Rn());
3755 opd->imm = (int)(signed char)op;
3758 /////////////////////////////////////////////
3760 switch (op & 0x0f00)
3762 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
3763 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3764 opd->imm = (op & 0x0f);
3766 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
3767 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3768 opd->imm = (op & 0x0f) * 2;
3770 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
3771 opd->source = BITMASK1(GET_Rm());
3772 opd->dest = BITMASK1(SHR_R0);
3773 opd->imm = (op & 0x0f);
3775 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
3776 opd->source = BITMASK1(GET_Rm());
3777 opd->dest = BITMASK1(SHR_R0);
3778 opd->imm = (op & 0x0f) * 2;
3780 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
3781 opd->source = BITMASK1(SHR_R0);
3782 opd->dest = BITMASK1(SHR_T);
3783 opd->imm = (int)(signed char)op;
3785 case 0x0d00: // BT/S label 10001101dddddddd
3786 case 0x0f00: // BF/S label 10001111dddddddd
3789 case 0x0900: // BT label 10001001dddddddd
3790 case 0x0b00: // BF label 10001011dddddddd
3791 opd->op = (op & 0x0200) ? OP_BRANCH_CF : OP_BRANCH_CT;
3792 opd->source = BITMASK1(SHR_T);
3793 opd->dest = BITMASK1(SHR_PC);
3794 opd->imm = ((signed int)(op << 24) >> 23);
3796 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
3797 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
3804 /////////////////////////////////////////////
3806 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
3807 opd->op = OP_LOAD_POOL;
3808 opd->source = BITMASK1(SHR_PC);
3809 opd->dest = BITMASK1(GET_Rn());
3810 opd->imm = pc + 4 + (op & 0xff) * 2;
3814 /////////////////////////////////////////////
3816 // BSR label 1011dddddddddddd
3817 opd->dest = BITMASK1(SHR_PR);
3819 // BRA label 1010dddddddddddd
3820 opd->op = OP_BRANCH;
3821 opd->dest |= BITMASK1(SHR_PC);
3822 opd->imm = ((signed int)(op << 20) >> 19);
3827 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
3828 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
3831 /////////////////////////////////////////////
3833 switch (op & 0x0f00)
3835 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
3836 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
3837 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
3838 opd->source = BITMASK2(SHR_GBR, SHR_R0);
3839 opd->size = (op & 0x300) >> 8;
3840 opd->imm = (op & 0xff) << opd->size;
3842 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
3843 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
3844 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
3845 opd->source = BITMASK1(SHR_GBR);
3846 opd->dest = BITMASK1(SHR_R0);
3847 opd->size = (op & 0x300) >> 8;
3848 opd->imm = (op & 0xff) << opd->size;
3850 case 0x0300: // TRAPA #imm 11000011iiiiiiii
3851 opd->source = BITMASK2(SHR_PC, SHR_SR);
3852 opd->dest = BITMASK1(SHR_PC);
3853 opd->imm = (op & 0xff) * 4;
3855 end_block = 1; // FIXME
3857 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
3858 opd->dest = BITMASK1(SHR_R0);
3859 opd->imm = (pc + 4 + (op & 0xff) * 4) & ~3;
3861 case 0x0800: // TST #imm,R0 11001000iiiiiiii
3862 opd->source = BITMASK1(SHR_R0);
3863 opd->dest = BITMASK1(SHR_T);
3864 opd->imm = op & 0xff;
3866 case 0x0900: // AND #imm,R0 11001001iiiiiiii
3867 opd->source = opd->dest = BITMASK1(SHR_R0);
3868 opd->imm = op & 0xff;
3870 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
3871 opd->source = opd->dest = BITMASK1(SHR_R0);
3872 opd->imm = op & 0xff;
3874 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
3875 opd->source = opd->dest = BITMASK1(SHR_R0);
3876 opd->imm = op & 0xff;
3878 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
3879 opd->source = BITMASK2(SHR_GBR, SHR_R0);
3880 opd->dest = BITMASK1(SHR_T);
3881 opd->imm = op & 0xff;
3884 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
3885 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
3886 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
3887 opd->source = BITMASK2(SHR_GBR, SHR_R0);
3888 opd->imm = op & 0xff;
3896 /////////////////////////////////////////////
3898 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
3899 opd->op = OP_LOAD_POOL;
3900 opd->source = BITMASK1(SHR_PC);
3901 opd->dest = BITMASK1(GET_Rn());
3902 opd->imm = (pc + 4 + (op & 0xff) * 2) & ~3;
3906 /////////////////////////////////////////////
3908 // MOV #imm,Rn 1110nnnniiiiiiii
3909 opd->dest = BITMASK1(GET_Rn());
3910 opd->imm = (u32)(signed int)(signed char)op;
3915 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
3916 is_slave ? 's' : 'm', op, pc);
3923 // 2nd pass: some analysis
3924 for (i = 0; i < i_end; i++) {
3927 // propagate T (TODO: DIV0U)
3928 if ((opd->op == OP_SETCLRT && !opd->imm) || opd->op == OP_BRANCH_CT)
3929 op_flags[i + 1] |= OF_T_CLEAR;
3930 else if ((opd->op == OP_SETCLRT && opd->imm) || opd->op == OP_BRANCH_CF)
3931 op_flags[i + 1] |= OF_T_SET;
3933 if ((op_flags[i] & OF_BTARGET) || (opd->dest & BITMASK1(SHR_T)))
3934 op_flags[i] &= ~(OF_T_SET | OF_T_CLEAR);
3936 op_flags[i + 1] |= op_flags[i] & (OF_T_SET | OF_T_CLEAR);
3938 if ((opd->op == OP_BRANCH_CT && (op_flags[i] & OF_T_SET))
3939 || (opd->op == OP_BRANCH_CF && (op_flags[i] & OF_T_CLEAR)))
3941 opd->op = OP_BRANCH;
3944 if (op_flags[i + 1] & OF_DELAY_OP) {
3949 else if (opd->op == OP_LOAD_POOL)
3951 if (opd->imm < end_pc + MAX_LITERAL_OFFSET) {
3952 if (end_literals < opd->imm + opd->size * 2)
3953 end_literals = opd->imm + opd->size * 2;
3957 end_pc = base_pc + i_end * 2;
3958 if (end_literals < end_pc)
3959 end_literals = end_pc;
3961 *end_pc_out = end_pc;
3962 if (end_literals_out != NULL)
3963 *end_literals_out = end_literals;
3966 // vim:shiftwidth=2:ts=2:expandtab