2 * vim:shiftwidth=2:expandtab
9 #include "../../pico/pico_int.h"
12 #include "../drc/cmn.h"
19 #define dbg(l,...) { \
20 if ((l) & DRC_DEBUG) \
21 elprintf(EL_STATUS, ##__VA_ARGS__); \
24 #include "mame/sh2dasm.h"
25 #include <platform/linux/host_dasm.h>
26 static int insns_compiled, hash_collisions, host_insn_count;
35 static u8 *tcache_dsm_ptrs[3];
36 static char sh2dasm_buff[64];
37 #define do_host_disasm(tcid) \
38 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
39 tcache_dsm_ptrs[tcid] = tcache_ptr
41 #define do_host_disasm(x)
44 #define BLOCK_CYCLE_LIMIT 100
45 #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
47 // we have 3 translation cache buffers, split from one drc/cmn buffer.
48 // BIOS shares tcache with data array because it's only used for init
49 // and can be discarded early
50 static const int tcache_sizes[3] = {
51 DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM
52 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
53 DRC_TCACHE_SIZE / 8, // ... slave
56 static u8 *tcache_bases[3];
57 static u8 *tcache_ptrs[3];
59 // ptr for code emiters
60 static u8 *tcache_ptr;
62 // host register tracking
65 HR_CACHED, // 'val' has sh2_reg_e
67 HR_CONST, // 'val' has constant
68 HR_TEMP, // reg used for temp storage
74 u16 stamp; // kind of a timestamp
78 // note: reg_temp[] must have at least the amount of
79 // registers used by handlers in worst case (currently 4)
81 #include "../drc/emit_arm.c"
83 static const int reg_map_g2h[] = {
92 static temp_reg_t reg_temp[] = {
102 #include "../drc/emit_x86.c"
104 static const int reg_map_g2h[] = {
113 // ax, cx, dx are usually temporaries by convention
114 static temp_reg_t reg_temp[] = {
132 typedef struct block_desc_ {
133 u32 addr; // SH2 PC address
134 u32 end_addr; // TODO rm?
135 void *tcache_ptr; // translated block for above PC
136 struct block_desc_ *next; // next block with the same PC hash
142 static const int block_max_counts[3] = {
147 static block_desc *block_tables[3];
148 static int block_counts[3];
151 #define MAX_HASH_ENTRIES 1024
152 #define HASH_MASK (MAX_HASH_ENTRIES - 1)
153 static void **hash_table;
155 extern void sh2_drc_entry(SH2 *sh2, void *block);
156 extern void sh2_drc_exit(void);
159 extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode);
160 static void REGPARM(1) sh2_test_irq(SH2 *sh2);
162 static void flush_tcache(int tcid)
164 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
165 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
166 block_counts[tcid], block_max_counts[tcid]);
168 block_counts[tcid] = 0;
169 tcache_ptrs[tcid] = tcache_bases[tcid];
170 if (tcid == 0) { // ROM, RAM
171 memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES);
172 memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram));
175 memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0]));
177 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
181 static void *dr_find_block(block_desc *tab, u32 addr)
183 for (tab = tab->next; tab != NULL; tab = tab->next)
184 if (tab->addr == addr)
188 return tab->tcache_ptr;
190 printf("block miss for %08x\n", addr);
194 static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id)
196 int *bcount = &block_counts[tcache_id];
199 if (*bcount >= block_max_counts[tcache_id])
202 bd = &block_tables[tcache_id][*bcount];
204 bd->tcache_ptr = tcache_ptr;
211 #define HASH_FUNC(hash_tab, addr) \
212 ((block_desc **)(hash_tab))[(addr) & HASH_MASK]
214 // ---------------------------------------------------------------
217 static u16 rcache_counter;
219 static temp_reg_t *rcache_evict(void)
221 // evict reg with oldest stamp
223 u16 min_stamp = (u16)-1;
225 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
226 if (reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY)
227 if (reg_temp[i].stamp <= min_stamp) {
228 min_stamp = reg_temp[i].stamp;
234 printf("no registers to evict, aborting\n");
239 if (reg_temp[i].type == HR_CACHED_DIRTY) {
241 emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4);
253 // note: must not be called when doing conditional code
254 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
259 // maybe already statically mapped?
266 // maybe already cached?
267 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
268 if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) &&
269 reg_temp[i].val == r)
271 reg_temp[i].stamp = rcache_counter;
272 if (mode != RC_GR_READ)
273 reg_temp[i].type = HR_CACHED_DIRTY;
274 return reg_temp[i].reg;
279 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
280 if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) {
289 if (mode != RC_GR_WRITE)
290 emith_ctx_read(tr->reg, r * 4);
292 tr->type = mode != RC_GR_READ ? HR_CACHED_DIRTY : HR_CACHED;
294 tr->stamp = rcache_counter;
298 static int rcache_get_tmp(void)
303 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
304 if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) {
316 static int rcache_get_arg_id(int arg)
319 host_arg2reg(r, arg);
321 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
322 if (reg_temp[i].reg == r)
325 if (i == ARRAY_SIZE(reg_temp))
326 // let's just say it's untracked arg reg
329 if (reg_temp[i].type == HR_CACHED_DIRTY) {
331 emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4);
333 else if (reg_temp[i].type == HR_TEMP) {
334 printf("arg %d reg %d already used, aborting\n", arg, r);
341 // get a reg to be used as function arg
342 // it's assumed that regs are cleaned before call
343 static int rcache_get_tmp_arg(int arg)
345 int id = rcache_get_arg_id(arg);
346 reg_temp[id].type = HR_TEMP;
348 return reg_temp[id].reg;
351 // same but caches reg. RC_GR_READ only.
352 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
354 int i, srcr, dstr, dstid;
356 dstid = rcache_get_arg_id(arg);
357 dstr = reg_temp[dstid].reg;
359 // maybe already statically mapped?
360 srcr = reg_map_g2h[r];
364 // maybe already cached?
365 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
366 if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) &&
367 reg_temp[i].val == r)
369 srcr = reg_temp[i].reg;
376 emith_ctx_read(srcr, r * 4);
380 emith_move_r_r(dstr, srcr);
382 reg_temp[dstid].stamp = ++rcache_counter;
383 reg_temp[dstid].type = HR_CACHED;
384 reg_temp[dstid].val = r;
388 static void rcache_free_tmp(int hr)
391 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
392 if (reg_temp[i].reg == hr)
395 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
396 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
400 reg_temp[i].type = HR_FREE;
403 static void rcache_clean(void)
406 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
407 if (reg_temp[i].type == HR_CACHED_DIRTY) {
409 emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4);
410 reg_temp[i].type = HR_CACHED;
414 static void rcache_invalidate(void)
417 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
418 reg_temp[i].type = HR_FREE;
422 static void rcache_flush(void)
428 // ---------------------------------------------------------------
430 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
432 // TODO: propagate this constant
433 int hr = rcache_get_reg(dst, RC_GR_WRITE);
434 emith_move_r_imm(hr, imm);
437 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
439 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
440 int hr_s = rcache_get_reg(src, RC_GR_READ);
442 emith_move_r_r(hr_d, hr_s);
445 // T must be clear, and comparison done just before this
446 static void emit_or_t_if_eq(int srr)
448 EMITH_SJMP_START(DCOND_NE);
449 emith_or_r_imm_c(DCOND_EQ, srr, T);
450 EMITH_SJMP_END(DCOND_NE);
453 // arguments must be ready
454 // reg cache must be clean before call
455 static int emit_memhandler_read(int size)
458 host_arg2reg(ctxr, 1);
459 emith_move_r_r(ctxr, CONTEXT_REG);
462 emith_call(p32x_sh2_read8);
465 emith_call(p32x_sh2_read16);
468 emith_call(p32x_sh2_read32);
472 // assuming arg0 and retval reg matches
473 return rcache_get_tmp_arg(0);
476 static void emit_memhandler_write(int size)
479 host_arg2reg(ctxr, 2);
480 emith_move_r_r(ctxr, CONTEXT_REG);
483 emith_call(p32x_sh2_write8);
486 emith_call(p32x_sh2_write16);
489 emith_call(p32x_sh2_write32);
496 static int emit_indirect_indexed_read(int rx, int ry, int size)
500 a0 = rcache_get_reg_arg(0, rx);
501 t = rcache_get_reg(ry, RC_GR_READ);
502 emith_add_r_r(a0, t);
503 return emit_memhandler_read(size);
507 static void emit_indirect_indexed_write(int rx, int ry, int wr, int size)
511 rcache_get_reg_arg(1, wr);
512 a0 = rcache_get_reg_arg(0, rx);
513 t = rcache_get_reg(ry, RC_GR_READ);
514 emith_add_r_r(a0, t);
515 emit_memhandler_write(size);
519 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
524 rcache_get_reg_arg(0, rn);
525 tmp = emit_memhandler_read(size);
526 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
527 rcache_free_tmp(tmp);
528 tmp = rcache_get_reg(rn, RC_GR_RMW);
529 emith_add_r_imm(tmp, 1 << size);
532 rcache_get_reg_arg(0, rm);
533 *rmr = emit_memhandler_read(size);
534 *rnr = rcache_get_tmp();
535 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
536 tmp = rcache_get_reg(rm, RC_GR_RMW);
537 emith_add_r_imm(tmp, 1 << size);
540 // fixup for saturated MAC, to be called from generated code
541 // FIXME: statically alloced regs need to be fixed
542 static void sh2_macl_sat_fixup(void)
544 if ((signed int)sh2->mach < 0 && sh2->mach < 0xffff8000)
546 sh2->mach = 0x00008000;
547 sh2->macl = 0x00000000;
549 else if ((signed int)sh2->mach > 0 && sh2->mach > 0x00007fff)
551 sh2->mach = 0x00007fff;
552 sh2->macl = 0xffffffff;
556 static void sh2_macw_sat_fixup(void)
558 signed int t = sh2->mach;
559 if (t < -1 || (t == -1 && !(sh2->macl & 0x80000000)))
561 sh2->mach = 0xffffffff; // ?
562 sh2->macl = 0x80000000;
564 else if (t > 0 || (t == 0 && (sh2->macl & 0x80000000)))
566 sh2->mach = 0x7fffffff;
567 sh2->macl = 0xffffffff;
574 #define CHECK_UNHANDLED_BITS(mask) { \
575 if ((op & (mask)) != 0) \
582 #define GET_Rm GET_Fx
587 #define CHECK_FX_LT(n) \
591 static void *sh2_translate(SH2 *sh2, block_desc *other_block)
594 block_desc *this_block;
595 unsigned int pc = sh2->pc;
596 int op, delayed_op = 0, test_irq = 0;
597 int tcache_id = 0, blkid = 0;
599 u32 tmp, tmp2, tmp3, tmp4, sr;
603 if ((tmp != 0 && tmp != 1 && tmp != 6) || sh2->pc == 0) {
604 printf("invalid PC, aborting: %08x\n", sh2->pc);
605 // FIXME: be less destructive
609 if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
610 // data_array, BIOS have separate tcache (shared)
611 tcache_id = 1 + sh2->is_slave;
614 tcache_ptr = tcache_ptrs[tcache_id];
615 this_block = dr_add_block(pc, tcache_id, &blkid);
617 tmp = tcache_ptr - tcache_bases[tcache_id];
618 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL) {
619 flush_tcache(tcache_id);
620 tcache_ptr = tcache_ptrs[tcache_id];
621 other_block = NULL; // also gone too due to flush
622 this_block = dr_add_block(pc, tcache_id, &blkid);
625 this_block->next = other_block;
626 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
627 HASH_FUNC(hash_table, pc) = this_block;
629 block_entry = tcache_ptr;
631 printf("== %csh2 block #%d,%d %08x -> %p\n", sh2->is_slave ? 's' : 'm',
632 tcache_id, block_counts[tcache_id], pc, block_entry);
633 if (other_block != NULL) {
634 printf(" hash collision with %08x\n", other_block->addr);
639 while (cycles < BLOCK_CYCLE_LIMIT || delayed_op)
644 op = p32x_sh2_read16(pc, sh2);
649 DasmSH2(sh2dasm_buff, pc, op);
650 printf("%08x %04x %s\n", pc, op, sh2dasm_buff);
657 switch ((op >> 12) & 0x0f)
659 /////////////////////////////////////////////
664 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
667 case 0: // STC SR,Rn 0000nnnn00000010
670 case 1: // STC GBR,Rn 0000nnnn00010010
673 case 2: // STC VBR,Rn 0000nnnn00100010
679 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
680 emith_move_r_r(tmp, tmp3);
682 emith_clear_msb(tmp, tmp, 20); // reserved bits defined by ISA as 0
685 CHECK_UNHANDLED_BITS(0xd0);
686 // BRAF Rm 0000mmmm00100011
687 // BSRF Rm 0000mmmm00000011
690 emit_move_r_imm32(SHR_PR, pc + 2);
691 tmp = rcache_get_reg(SHR_PPC, RC_GR_WRITE);
692 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
693 emith_move_r_r(tmp, tmp2);
694 emith_add_r_imm(tmp, pc + 2);
697 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
698 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
699 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
700 emit_indirect_indexed_write(SHR_R0, GET_Rn(), GET_Rm(), op & 3);
703 // MUL.L Rm,Rn 0000nnnnmmmm0111
704 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
705 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
706 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
707 emith_mul(tmp3, tmp2, tmp);
711 CHECK_UNHANDLED_BITS(0xf00);
714 case 0: // CLRT 0000000000001000
715 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
716 emith_bic_r_imm(tmp, T);
718 case 1: // SETT 0000000000011000
719 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
720 emith_or_r_imm(tmp, T);
722 case 2: // CLRMAC 0000000000101000
723 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
724 emith_move_r_imm(tmp, 0);
725 tmp = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
726 emith_move_r_imm(tmp, 0);
735 case 0: // NOP 0000000000001001
736 CHECK_UNHANDLED_BITS(0xf00);
738 case 1: // DIV0U 0000000000011001
739 CHECK_UNHANDLED_BITS(0xf00);
740 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
741 emith_bic_r_imm(tmp, M|Q|T);
743 case 2: // MOVT Rn 0000nnnn00101001
744 tmp = rcache_get_reg(SHR_SR, RC_GR_READ);
745 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
746 emith_clear_msb(tmp2, tmp, 31);
753 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
756 case 0: // STS MACH,Rn 0000nnnn00001010
759 case 1: // STS MACL,Rn 0000nnnn00011010
762 case 2: // STS PR,Rn 0000nnnn00101010
768 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
769 emith_move_r_r(tmp, tmp2);
772 CHECK_UNHANDLED_BITS(0xf00);
775 case 0: // RTS 0000000000001011
777 emit_move_r_r(SHR_PPC, SHR_PR);
780 case 1: // SLEEP 0000000000011011
781 emit_move_r_imm32(SHR_PC, pc - 2);
782 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
783 emith_clear_msb(tmp, tmp, 20); // clear cycles
787 case 2: // RTE 0000000000101011
791 rcache_get_reg_arg(0, SHR_SP);
792 tmp = emit_memhandler_read(2);
793 tmp2 = rcache_get_reg(SHR_PPC, RC_GR_WRITE);
794 emith_move_r_r(tmp2, tmp);
795 rcache_free_tmp(tmp);
798 tmp = rcache_get_reg_arg(0, SHR_SP);
799 emith_add_r_imm(tmp, 4);
800 tmp = emit_memhandler_read(2);
802 rcache_free_tmp(tmp);
803 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
804 emith_add_r_imm(tmp, 4*2);
812 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
813 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
814 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
815 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
816 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
818 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
820 emith_move_r_r(tmp2, tmp);
821 rcache_free_tmp(tmp);
823 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
824 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
825 tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ);
826 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
827 /* MS 16 MAC bits unused if saturated */
828 emith_tst_r_imm(tmp3, S);
829 EMITH_SJMP_START(DCOND_EQ);
830 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
831 EMITH_SJMP_END(DCOND_EQ);
832 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
833 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
834 rcache_free_tmp(tmp);
835 rcache_free_tmp(tmp2);
837 tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ);
838 emith_tst_r_imm(tmp3, S);
839 EMITH_SJMP_START(DCOND_EQ);
840 emith_call_cond(DCOND_NE, sh2_macl_sat_fixup);
841 EMITH_SJMP_END(DCOND_EQ);
848 /////////////////////////////////////////////
850 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
852 tmp = rcache_get_reg_arg(0, GET_Rn());
853 tmp2 = rcache_get_reg_arg(1, GET_Rm());
854 emith_add_r_imm(tmp, (op & 0x0f) * 4);
855 emit_memhandler_write(2);
861 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
862 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
863 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
865 rcache_get_reg_arg(0, GET_Rn());
866 rcache_get_reg_arg(1, GET_Rm());
867 emit_memhandler_write(op & 3);
869 case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
870 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
871 case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110
872 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
873 emith_sub_r_imm(tmp, (1 << (op & 3)));
875 rcache_get_reg_arg(0, GET_Rn());
876 rcache_get_reg_arg(1, GET_Rm());
877 emit_memhandler_write(op & 3);
879 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
880 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
881 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
882 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
883 emith_bic_r_imm(tmp, M|Q|T);
884 emith_tst_r_imm(tmp2, (1<<31));
885 EMITH_SJMP_START(DCOND_EQ);
886 emith_or_r_imm_c(DCOND_NE, tmp, Q);
887 EMITH_SJMP_END(DCOND_EQ);
888 emith_tst_r_imm(tmp3, (1<<31));
889 EMITH_SJMP_START(DCOND_EQ);
890 emith_or_r_imm_c(DCOND_NE, tmp, M);
891 EMITH_SJMP_END(DCOND_EQ);
892 emith_teq_r_r(tmp2, tmp3);
893 EMITH_SJMP_START(DCOND_PL);
894 emith_or_r_imm_c(DCOND_MI, tmp, T);
895 EMITH_SJMP_END(DCOND_PL);
897 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
898 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
899 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
900 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
901 emith_bic_r_imm(tmp, T);
902 emith_tst_r_r(tmp2, tmp3);
903 emit_or_t_if_eq(tmp);
905 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
906 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
907 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
908 emith_and_r_r(tmp, tmp2);
910 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
911 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
912 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
913 emith_eor_r_r(tmp, tmp2);
915 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
916 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
917 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
918 emith_or_r_r(tmp, tmp2);
920 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
921 tmp = rcache_get_tmp();
922 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
923 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
924 emith_eor_r_r_r(tmp, tmp2, tmp3);
925 tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
926 emith_bic_r_imm(tmp2, T);
927 emith_tst_r_imm(tmp, 0x000000ff);
928 emit_or_t_if_eq(tmp);
929 emith_tst_r_imm(tmp, 0x0000ff00);
930 emit_or_t_if_eq(tmp);
931 emith_tst_r_imm(tmp, 0x00ff0000);
932 emit_or_t_if_eq(tmp);
933 emith_tst_r_imm(tmp, 0xff000000);
934 emit_or_t_if_eq(tmp);
935 rcache_free_tmp(tmp);
937 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
938 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
939 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
940 emith_lsr(tmp, tmp, 16);
941 emith_or_r_r_lsl(tmp, tmp2, 16);
943 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
944 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
945 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
946 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
948 emith_sext(tmp, tmp2, 16);
950 emith_clear_msb(tmp, tmp2, 16);
951 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
952 tmp2 = rcache_get_tmp();
954 emith_sext(tmp2, tmp3, 16);
956 emith_clear_msb(tmp2, tmp3, 16);
957 emith_mul(tmp, tmp, tmp2);
958 rcache_free_tmp(tmp2);
959 // FIXME: causes timing issues in Doom?
965 /////////////////////////////////////////////
969 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
970 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
971 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
972 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
973 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
974 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
975 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
976 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
977 emith_bic_r_imm(tmp, T);
978 emith_cmp_r_r(tmp2, tmp3);
982 emit_or_t_if_eq(tmp);
985 EMITH_SJMP_START(DCOND_LO);
986 emith_or_r_imm_c(DCOND_HS, tmp, T);
987 EMITH_SJMP_END(DCOND_LO);
990 EMITH_SJMP_START(DCOND_LT);
991 emith_or_r_imm_c(DCOND_GE, tmp, T);
992 EMITH_SJMP_END(DCOND_LT);
995 EMITH_SJMP_START(DCOND_LS);
996 emith_or_r_imm_c(DCOND_HI, tmp, T);
997 EMITH_SJMP_END(DCOND_LS);
1000 EMITH_SJMP_START(DCOND_LE);
1001 emith_or_r_imm_c(DCOND_GT, tmp, T);
1002 EMITH_SJMP_END(DCOND_LE);
1006 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
1007 // Q1 = carry(Rn = (Rn << 1) | T)
1009 // Q2 = carry(Rn += Rm)
1011 // Q2 = carry(Rn -= Rm)
1013 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
1014 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1015 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1016 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1017 emith_set_carry(sr);
1018 emith_adcf_r_r(tmp2, tmp2);
1019 emith_carry_to_t(sr, 0); // keep Q1 in T for now
1020 tmp4 = rcache_get_tmp();
1021 emith_and_r_r_imm(tmp4, sr, M);
1022 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
1023 rcache_free_tmp(tmp4);
1024 // add or sub, invert T if carry to get Q1 ^ Q2
1025 // in: (Q ^ M) passed in Q, Q1 in T
1026 emith_sh2_div1_step(tmp2, tmp3, sr);
1027 emith_bic_r_imm(sr, Q);
1028 emith_tst_r_imm(sr, M);
1029 EMITH_SJMP_START(DCOND_EQ);
1030 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
1031 EMITH_SJMP_END(DCOND_EQ);
1032 emith_tst_r_imm(sr, T);
1033 EMITH_SJMP_START(DCOND_EQ);
1034 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
1035 EMITH_SJMP_END(DCOND_EQ);
1036 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
1038 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
1039 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1040 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1041 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1042 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1043 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
1045 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
1046 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
1047 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1048 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1050 emith_add_r_r(tmp, tmp2);
1052 emith_sub_r_r(tmp, tmp2);
1054 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
1055 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
1056 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1057 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1058 tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1059 if (op & 4) { // adc
1060 emith_set_carry(tmp3);
1061 emith_adcf_r_r(tmp, tmp2);
1062 emith_carry_to_t(tmp3, 0);
1064 emith_set_carry_sub(tmp3);
1065 emith_sbcf_r_r(tmp, tmp2);
1066 emith_carry_to_t(tmp3, 1);
1069 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
1070 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
1071 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1072 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1073 tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1074 emith_bic_r_imm(tmp3, T);
1076 emith_addf_r_r(tmp, tmp2);
1078 emith_subf_r_r(tmp, tmp2);
1079 EMITH_SJMP_START(DCOND_VC);
1080 emith_or_r_imm_c(DCOND_VS, tmp3, T);
1081 EMITH_SJMP_END(DCOND_VC);
1083 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
1084 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1085 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1086 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1087 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1088 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
1093 /////////////////////////////////////////////
1100 case 0: // SHLL Rn 0100nnnn00000000
1101 case 2: // SHAL Rn 0100nnnn00100000
1102 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1103 tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1104 emith_lslf(tmp, tmp, 1);
1105 emith_carry_to_t(tmp2, 0);
1107 case 1: // DT Rn 0100nnnn00010000
1108 if (p32x_sh2_read16(pc, sh2) == 0x8bfd) { // BF #-2
1109 emith_sh2_dtbf_loop();
1112 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1113 tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1114 emith_bic_r_imm(tmp2, T);
1115 emith_subf_r_imm(tmp, 1);
1116 emit_or_t_if_eq(tmp2);
1123 case 0: // SHLR Rn 0100nnnn00000001
1124 case 2: // SHAR Rn 0100nnnn00100001
1125 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1126 tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1128 emith_asrf(tmp, tmp, 1);
1130 emith_lsrf(tmp, tmp, 1);
1131 emith_carry_to_t(tmp2, 0);
1133 case 1: // CMP/PZ Rn 0100nnnn00010001
1134 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1135 tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1136 emith_bic_r_imm(tmp2, T);
1137 emith_cmp_r_imm(tmp, 0);
1138 EMITH_SJMP_START(DCOND_LT);
1139 emith_or_r_imm_c(DCOND_GE, tmp2, T);
1140 EMITH_SJMP_END(DCOND_LT);
1148 case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
1151 case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
1154 case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
1157 case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
1160 case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
1163 case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
1169 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1170 emith_sub_r_imm(tmp2, 4);
1172 rcache_get_reg_arg(0, GET_Rn());
1173 tmp3 = rcache_get_reg_arg(1, tmp);
1175 emith_clear_msb(tmp3, tmp3, 20); // reserved bits defined by ISA as 0
1176 emit_memhandler_write(2);
1182 case 0x04: // ROTL Rn 0100nnnn00000100
1183 case 0x05: // ROTR Rn 0100nnnn00000101
1184 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1185 tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1187 emith_rorf(tmp, tmp, 1);
1189 emith_rolf(tmp, tmp, 1);
1190 emith_carry_to_t(tmp2, 0);
1192 case 0x24: // ROTCL Rn 0100nnnn00100100
1193 case 0x25: // ROTCR Rn 0100nnnn00100101
1194 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1195 tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1196 emith_set_carry(tmp2);
1201 emith_carry_to_t(tmp2, 0);
1203 case 0x15: // CMP/PL Rn 0100nnnn00010101
1204 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1205 tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1206 emith_bic_r_imm(tmp2, T);
1207 emith_cmp_r_imm(tmp, 0);
1208 EMITH_SJMP_START(DCOND_LE);
1209 emith_or_r_imm_c(DCOND_GT, tmp2, T);
1210 EMITH_SJMP_END(DCOND_LE);
1218 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
1221 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
1224 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
1227 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
1230 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
1233 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
1240 rcache_get_reg_arg(0, GET_Rn());
1241 tmp2 = emit_memhandler_read(2);
1242 if (tmp == SHR_SR) {
1243 emith_write_sr(tmp2);
1246 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
1247 emith_move_r_r(tmp, tmp2);
1249 rcache_free_tmp(tmp2);
1250 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1251 emith_add_r_imm(tmp, 4);
1258 // SHLL2 Rn 0100nnnn00001000
1259 // SHLR2 Rn 0100nnnn00001001
1263 // SHLL8 Rn 0100nnnn00011000
1264 // SHLR8 Rn 0100nnnn00011001
1268 // SHLL16 Rn 0100nnnn00101000
1269 // SHLR16 Rn 0100nnnn00101001
1275 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1277 emith_lsr(tmp2, tmp2, tmp);
1279 emith_lsl(tmp2, tmp2, tmp);
1284 case 0: // LDS Rm,MACH 0100mmmm00001010
1287 case 1: // LDS Rm,MACL 0100mmmm00011010
1290 case 2: // LDS Rm,PR 0100mmmm00101010
1296 emit_move_r_r(tmp2, GET_Rn());
1301 case 0: // JSR @Rm 0100mmmm00001011
1302 case 2: // JMP @Rm 0100mmmm00101011
1305 emit_move_r_imm32(SHR_PR, pc + 2);
1306 emit_move_r_r(SHR_PPC, (op >> 8) & 0x0f);
1309 case 1: // TAS.B @Rn 0100nnnn00011011
1310 // XXX: is TAS working on 32X?
1312 rcache_get_reg_arg(0, GET_Rn());
1313 tmp = emit_memhandler_read(0);
1314 tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1315 emith_bic_r_imm(tmp2, T);
1316 emith_cmp_r_imm(tmp, 0);
1317 emit_or_t_if_eq(tmp2);
1319 emith_or_r_imm(tmp, 0x80);
1320 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
1321 emith_move_r_r(tmp2, tmp);
1322 rcache_free_tmp(tmp);
1323 rcache_get_reg_arg(0, GET_Rn());
1324 emit_memhandler_write(0);
1332 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1335 case 0: // LDC Rm,SR 0100mmmm00001110
1338 case 1: // LDC Rm,GBR 0100mmmm00011110
1341 case 2: // LDC Rm,VBR 0100mmmm00101110
1347 if (tmp2 == SHR_SR) {
1348 emith_write_sr(tmp);
1351 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
1352 emith_move_r_r(tmp2, tmp);
1356 // MAC @Rm+,@Rn+ 0100nnnnmmmm1111
1357 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
1358 emith_sext(tmp, tmp, 16);
1359 emith_sext(tmp2, tmp2, 16);
1360 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
1361 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1362 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1363 rcache_free_tmp(tmp);
1364 rcache_free_tmp(tmp2);
1366 // XXX: MACH should be untouched when S is set?
1367 tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ);
1368 emith_tst_r_imm(tmp3, S);
1369 EMITH_SJMP_START(DCOND_EQ);
1370 emith_call_cond(DCOND_NE, sh2_macw_sat_fixup);
1371 EMITH_SJMP_END(DCOND_EQ);
1372 rcache_invalidate();
1378 /////////////////////////////////////////////
1380 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
1382 tmp = rcache_get_reg_arg(0, GET_Rm());
1383 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1384 tmp = emit_memhandler_read(2);
1385 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1386 emith_move_r_r(tmp2, tmp);
1387 rcache_free_tmp(tmp);
1390 /////////////////////////////////////////////
1394 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
1395 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
1396 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
1397 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
1398 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
1399 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
1401 rcache_get_reg_arg(0, GET_Rm());
1402 tmp = emit_memhandler_read(op & 3);
1403 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1404 if ((op & 3) != 2) {
1405 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1407 emith_move_r_r(tmp2, tmp);
1408 rcache_free_tmp(tmp);
1409 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
1410 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
1411 emith_add_r_imm(tmp, (1 << (op & 3)));
1416 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
1417 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1420 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
1421 emith_move_r_r(tmp2, tmp);
1423 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
1424 emith_mvn_r_r(tmp2, tmp);
1426 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
1429 tmp3 = rcache_get_tmp();
1430 tmp4 = rcache_get_tmp();
1431 emith_lsr(tmp3, tmp, 16);
1432 emith_or_r_r_lsl(tmp3, tmp, 24);
1433 emith_and_r_r_imm(tmp4, tmp, 0xff00);
1434 emith_or_r_r_lsl(tmp3, tmp4, 8);
1435 emith_rol(tmp2, tmp3, 16);
1436 rcache_free_tmp(tmp4);
1438 rcache_free_tmp(tmp3);
1440 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
1441 emith_rol(tmp2, tmp, 16);
1443 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
1444 tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1445 emith_set_carry_sub(tmp3);
1446 emith_negcf_r_r(tmp2, tmp);
1447 emith_carry_to_t(tmp3, 1);
1449 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
1450 emith_neg_r_r(tmp2, tmp);
1452 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
1453 emith_clear_msb(tmp2, tmp, 24);
1455 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
1456 emith_clear_msb(tmp2, tmp, 16);
1458 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
1459 emith_sext(tmp2, tmp, 8);
1461 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
1462 emith_sext(tmp2, tmp, 16);
1469 /////////////////////////////////////////////
1471 // ADD #imm,Rn 0111nnnniiiiiiii
1472 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1473 if (op & 0x80) { // adding negative
1474 emith_sub_r_imm(tmp, -op & 0xff);
1476 emith_add_r_imm(tmp, op & 0xff);
1479 /////////////////////////////////////////////
1481 switch (op & 0x0f00)
1483 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
1484 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
1486 tmp = rcache_get_reg_arg(0, GET_Rm());
1487 tmp2 = rcache_get_reg_arg(1, SHR_R0);
1488 tmp3 = (op & 0x100) >> 8;
1489 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
1490 emit_memhandler_write(tmp3);
1492 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
1493 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
1495 tmp = rcache_get_reg_arg(0, GET_Rm());
1496 tmp3 = (op & 0x100) >> 8;
1497 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
1498 tmp = emit_memhandler_read(tmp3);
1499 tmp2 = rcache_get_reg(0, RC_GR_WRITE);
1500 emith_sext(tmp2, tmp, 8 << tmp3);
1501 rcache_free_tmp(tmp);
1503 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
1504 // XXX: could use cmn
1505 tmp = rcache_get_tmp();
1506 tmp2 = rcache_get_reg(0, RC_GR_READ);
1507 tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1508 emith_move_r_imm_s8(tmp, op & 0xff);
1509 emith_bic_r_imm(tmp3, T);
1510 emith_cmp_r_r(tmp2, tmp);
1511 emit_or_t_if_eq(tmp3);
1512 rcache_free_tmp(tmp);
1514 case 0x0d00: // BT/S label 10001101dddddddd
1515 case 0x0f00: // BF/S label 10001111dddddddd
1519 case 0x0900: // BT label 10001001dddddddd
1520 case 0x0b00: { // BF label 10001011dddddddd
1521 // jmp_cond ~ cond when guest doesn't jump
1522 int jmp_cond = (op & 0x0200) ? DCOND_NE : DCOND_EQ;
1523 int insn_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE;
1524 signed int offs = ((signed int)(op << 24) >> 23);
1525 tmp = rcache_get_reg(delayed_op ? SHR_PPC : SHR_PC, RC_GR_WRITE);
1526 emith_move_r_imm(tmp, pc + (delayed_op ? 2 : 0));
1528 EMITH_SJMP_START(jmp_cond);
1532 emith_sub_r_imm_c(insn_cond, tmp, -offs);
1534 emith_add_r_imm_c(insn_cond, tmp, offs);
1535 EMITH_SJMP_END(jmp_cond);
1543 /////////////////////////////////////////////
1545 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
1547 tmp = rcache_get_tmp_arg(0);
1548 emith_move_r_imm(tmp, pc + (op & 0xff) * 2 + 2);
1549 tmp = emit_memhandler_read(1);
1550 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1551 emith_sext(tmp2, tmp, 16);
1552 rcache_free_tmp(tmp);
1555 /////////////////////////////////////////////
1557 // BRA label 1010dddddddddddd
1560 tmp = ((signed int)(op << 20) >> 19);
1561 emit_move_r_imm32(SHR_PPC, pc + tmp + 2);
1565 /////////////////////////////////////////////
1567 // BSR label 1011dddddddddddd
1569 emit_move_r_imm32(SHR_PR, pc + 2);
1572 /////////////////////////////////////////////
1574 switch (op & 0x0f00)
1576 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
1577 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
1578 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
1580 tmp = rcache_get_reg_arg(0, SHR_GBR);
1581 tmp2 = rcache_get_reg_arg(1, SHR_R0);
1582 tmp3 = (op & 0x300) >> 8;
1583 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
1584 emit_memhandler_write(tmp3);
1586 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
1587 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
1588 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
1590 tmp = rcache_get_reg_arg(0, SHR_GBR);
1591 tmp3 = (op & 0x300) >> 8;
1592 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
1593 tmp = emit_memhandler_read(tmp3);
1594 tmp2 = rcache_get_reg(0, RC_GR_WRITE);
1596 emith_sext(tmp2, tmp, 8 << tmp3);
1598 emith_move_r_r(tmp2, tmp);
1599 rcache_free_tmp(tmp);
1601 case 0x0300: // TRAPA #imm 11000011iiiiiiii
1602 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1603 emith_sub_r_imm(tmp, 4*2);
1606 tmp = rcache_get_reg_arg(0, SHR_SP);
1607 emith_add_r_imm(tmp, 4);
1608 tmp = rcache_get_reg_arg(1, SHR_SR);
1609 emith_clear_msb(tmp, tmp, 20);
1610 emit_memhandler_write(2);
1612 rcache_get_reg_arg(0, SHR_SP);
1613 tmp = rcache_get_tmp_arg(1);
1614 emith_move_r_imm(tmp, pc);
1615 emit_memhandler_write(2);
1617 tmp = rcache_get_reg_arg(0, SHR_VBR);
1618 emith_add_r_imm(tmp, (op & 0xff) * 4);
1619 tmp = emit_memhandler_read(2);
1620 tmp2 = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1621 emith_move_r_r(tmp2, tmp);
1622 rcache_free_tmp(tmp);
1625 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
1626 emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3);
1628 case 0x0800: // TST #imm,R0 11001000iiiiiiii
1629 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
1630 tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1631 emith_bic_r_imm(tmp2, T);
1632 emith_tst_r_imm(tmp, op & 0xff);
1633 emit_or_t_if_eq(tmp2);
1635 case 0x0900: // AND #imm,R0 11001001iiiiiiii
1636 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
1637 emith_and_r_imm(tmp, op & 0xff);
1639 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
1640 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
1641 emith_eor_r_imm(tmp, op & 0xff);
1643 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
1644 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
1645 emith_or_r_imm(tmp, op & 0xff);
1647 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
1648 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
1649 tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
1650 emith_bic_r_imm(tmp2, T);
1651 emith_tst_r_imm(tmp, op & 0xff);
1652 emit_or_t_if_eq(tmp2);
1653 rcache_free_tmp(tmp);
1656 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
1657 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
1658 emith_and_r_imm(tmp, op & 0xff);
1659 emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0);
1662 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
1663 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
1664 emith_eor_r_imm(tmp, op & 0xff);
1665 emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0);
1668 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
1669 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
1670 emith_or_r_imm(tmp, op & 0xff);
1671 emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0);
1677 /////////////////////////////////////////////
1679 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
1681 tmp = rcache_get_tmp_arg(0);
1682 emith_move_r_imm(tmp, (pc + (op & 0xff) * 4 + 2) & ~3);
1683 tmp = emit_memhandler_read(2);
1684 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1685 emith_move_r_r(tmp2, tmp);
1686 rcache_free_tmp(tmp);
1689 /////////////////////////////////////////////
1691 // MOV #imm,Rn 1110nnnniiiiiiii
1692 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1693 emith_move_r_imm_s8(tmp, op & 0xff);
1698 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
1699 sh2->is_slave ? 's' : 'm', op, pc - 2);
1700 #ifdef DRC_DEBUG_INTERP
1701 emit_move_r_imm32(SHR_PC, pc - 2);
1703 emith_pass_arg_r(0, CONTEXT_REG);
1704 emith_pass_arg_imm(1, op);
1705 emith_call(sh2_do_op);
1711 if (delayed_op == 1)
1712 emit_move_r_r(SHR_PC, SHR_PPC);
1714 if (test_irq && delayed_op != 2) {
1716 emit_move_r_imm32(SHR_PC, pc);
1718 emith_pass_arg_r(0, CONTEXT_REG);
1719 emith_call(sh2_test_irq);
1722 if (delayed_op == 1)
1725 do_host_disasm(tcache_id);
1728 // delayed_op means some kind of branch - PC already handled
1730 emit_move_r_imm32(SHR_PC, pc);
1733 this_block->end_addr = pc;
1735 // mark memory blocks as containing compiled code
1736 if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
1738 u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
1739 tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
1740 tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
1741 Pico32xMem->drcblk_da[sh2->is_slave][tmp] = (blkid << 1) | 1;
1742 for (++tmp; tmp < tmp2; tmp++) {
1744 break; // dont overwrite overlay block
1745 drcblk[tmp] = blkid << 1;
1748 else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
1749 tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
1750 tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
1751 Pico32xMem->drcblk_ram[tmp] = (blkid << 1) | 1;
1752 for (++tmp; tmp < tmp2; tmp++) {
1753 if (Pico32xMem->drcblk_ram[tmp])
1755 Pico32xMem->drcblk_ram[tmp] = blkid << 1;
1759 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
1760 emith_sub_r_imm(tmp, cycles << 12);
1762 emith_jump(sh2_drc_exit);
1763 tcache_ptrs[tcache_id] = tcache_ptr;
1766 cache_flush_d_inval_i(block_entry, tcache_ptr);
1769 do_host_disasm(tcache_id);
1770 dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
1771 tcache_id, block_counts[tcache_id],
1772 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
1773 insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled);
1774 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
1775 dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
1784 do_host_disasm(tcache_id);
1789 void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
1791 // TODO: need to handle self-caused interrupts
1794 while (((signed int)sh2->sr >> 12) > 0)
1797 block_desc *bd = NULL;
1799 // FIXME: must avoid doing it so often..
1800 //sh2_test_irq(sh2);
1802 // we have full block id tables for data_array and RAM
1803 // BIOS goes to data_array table too
1804 if ((sh2->pc & 0xff000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
1805 int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
1807 bd = &block_tables[1 + sh2->is_slave][blkid >> 1];
1808 block = bd->tcache_ptr;
1812 else if ((sh2->pc & 0xc6000000) == 0x06000000) {
1813 int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
1815 bd = &block_tables[0][blkid >> 1];
1816 block = bd->tcache_ptr;
1820 else if ((sh2->pc & 0xc6000000) == 0x02000000) {
1821 bd = HASH_FUNC(hash_table, sh2->pc);
1824 if (bd->addr == sh2->pc)
1825 block = bd->tcache_ptr;
1827 block = dr_find_block(bd, sh2->pc);
1832 block = sh2_translate(sh2, bd);
1834 dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
1835 sh2->pc, block, (signed int)sh2->sr >> 12);
1840 sh2_drc_entry(sh2, block);
1844 static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a)
1847 block_desc *bd = btab + id;
1849 dbg(1, " killing block %08x", bd->addr);
1850 bd->addr = bd->end_addr = 0;
1852 while (p > drcblk && (p[-1] >> 1) == id)
1855 // check for possible overlay block
1856 if (p > 0 && p[-1] != 0) {
1857 bd = btab + (p[-1] >> 1);
1858 if (bd->addr <= a && a < bd->end_addr)
1859 sh2_smc_rm_block(drcblk, p - 1, btab, a);
1865 while ((*p >> 1) == id);
1868 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
1870 u16 *drcblk = Pico32xMem->drcblk_ram;
1871 u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT);
1873 dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
1874 sh2_smc_rm_block(drcblk, p, block_tables[0], a);
1877 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
1879 u16 *drcblk = Pico32xMem->drcblk_da[cpuid];
1880 u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT);
1882 dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
1883 sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a);
1886 void sh2_execute(SH2 *sh2c, int cycles)
1890 sh2c->cycles_aim += cycles;
1891 cycles = sh2c->cycles_aim - sh2c->cycles_done;
1893 // cycles are kept in SHR_SR unused bits (upper 20)
1895 sh2c->sr |= cycles << 12;
1896 sh2_drc_dispatcher(sh2c);
1898 sh2c->cycles_done += cycles - ((signed int)sh2c->sr >> 12);
1901 static void REGPARM(1) sh2_test_irq(SH2 *sh2)
1903 if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
1905 if (sh2->pending_irl > sh2->pending_int_irq)
1906 sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2);
1908 sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
1909 sh2->pending_int_irq = 0; // auto-clear
1910 sh2->pending_level = sh2->pending_irl;
1916 static void block_stats(void)
1918 int c, b, i, total = 0;
1920 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
1921 for (i = 0; i < block_counts[b]; i++)
1922 if (block_tables[b][i].addr != 0)
1923 total += block_tables[b][i].refcount;
1925 for (c = 0; c < 10; c++) {
1926 block_desc *blk, *maxb = NULL;
1928 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
1929 for (i = 0; i < block_counts[b]; i++) {
1930 blk = &block_tables[b][i];
1931 if (blk->addr != 0 && blk->refcount > max) {
1932 max = blk->refcount;
1939 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
1940 (double)maxb->refcount / total * 100.0);
1944 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
1945 for (i = 0; i < block_counts[b]; i++)
1946 block_tables[b][i].refcount = 0;
1949 #define block_stats()
1952 void sh2_drc_flush_all(void)
1960 int sh2_drc_init(SH2 *sh2)
1962 if (block_tables[0] == NULL) {
1967 cnt = block_max_counts[0] + block_max_counts[1] + block_max_counts[2];
1968 block_tables[0] = calloc(cnt, sizeof(*block_tables[0]));
1969 if (block_tables[0] == NULL)
1972 memset(block_counts, 0, sizeof(block_counts));
1973 tcache_bases[0] = tcache_ptrs[0] = tcache;
1975 for (i = 1; i < ARRAY_SIZE(block_tables); i++) {
1976 block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1];
1977 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
1981 PicoOpt |= POPT_DIS_VDP_FIFO;
1984 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
1985 tcache_dsm_ptrs[i] = tcache_bases[i];
1988 hash_collisions = 0;
1992 if (hash_table == NULL) {
1993 hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES);
1994 if (hash_table == NULL)
2001 void sh2_drc_finish(SH2 *sh2)
2003 if (block_tables[0] != NULL) {
2005 free(block_tables[0]);
2006 memset(block_tables, 0, sizeof(block_tables));
2011 if (hash_table != NULL) {