2 * vim:shiftwidth=2:expandtab
5 * - tcache, block descriptor, link buffer overflows result in sh2_translate()
6 * failure, followed by full tcache invalidation for that region
7 * - jumps between blocks are tracked for SMC handling (in block_links[])
14 #include "../../pico/pico_int.h"
17 #include "../drc/cmn.h"
25 #define dbg(l,...) { \
26 if ((l) & DRC_DEBUG) \
27 elprintf(EL_STATUS, ##__VA_ARGS__); \
30 #include "mame/sh2dasm.h"
31 #include <platform/linux/host_dasm.h>
32 static int insns_compiled, hash_collisions, host_insn_count;
41 static u8 *tcache_dsm_ptrs[3];
42 static char sh2dasm_buff[64];
43 #define do_host_disasm(tcid) \
44 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
45 tcache_dsm_ptrs[tcid] = tcache_ptr
47 #define do_host_disasm(x)
51 static void REGPARM(3) *sh2_drc_announce_entry(void *block, SH2 *sh2, u32 sr)
54 dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
55 sh2->pc, block, (signed int)sr >> 12);
61 #define BLOCK_CYCLE_LIMIT 100
62 #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
63 #define TCACHE_BUFFERS 3
65 // we have 3 translation cache buffers, split from one drc/cmn buffer.
66 // BIOS shares tcache with data array because it's only used for init
67 // and can be discarded early
68 // XXX: need to tune sizes
69 static const int tcache_sizes[TCACHE_BUFFERS] = {
70 DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM
71 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
72 DRC_TCACHE_SIZE / 8, // ... slave
75 static u8 *tcache_bases[TCACHE_BUFFERS];
76 static u8 *tcache_ptrs[TCACHE_BUFFERS];
78 // ptr for code emiters
79 static u8 *tcache_ptr;
81 typedef struct block_desc_ {
82 u32 addr; // SH2 PC address
83 u32 end_addr; // TODO rm?
84 void *tcache_ptr; // translated block for above PC
85 struct block_desc_ *next; // next block with the same PC hash
91 typedef struct block_link_ {
94 // struct block_link_ *next;
97 static const int block_max_counts[TCACHE_BUFFERS] = {
102 static block_desc *block_tables[TCACHE_BUFFERS];
103 static block_link *block_links[TCACHE_BUFFERS];
104 static int block_counts[TCACHE_BUFFERS];
105 static int block_link_counts[TCACHE_BUFFERS];
107 // host register tracking
110 HR_CACHED, // 'val' has sh2_reg_e
112 HR_CONST, // 'val' has constant
113 HR_TEMP, // reg used for temp storage
119 u16 stamp; // kind of a timestamp
123 // note: reg_temp[] must have at least the amount of
124 // registers used by handlers in worst case (currently 4)
126 #include "../drc/emit_arm.c"
128 static const int reg_map_g2h[] = {
137 static temp_reg_t reg_temp[] = {
146 #elif defined(__i386__)
147 #include "../drc/emit_x86.c"
149 static const int reg_map_g2h[] = {
158 // ax, cx, dx are usually temporaries by convention
159 static temp_reg_t reg_temp[] = {
167 #error unsupported arch
175 #define T_save 0x00000800
182 #define MAX_HASH_ENTRIES 1024
183 #define HASH_MASK (MAX_HASH_ENTRIES - 1)
184 static void **hash_table;
186 #define HASH_FUNC(hash_tab, addr) \
187 ((block_desc **)(hash_tab))[(addr) & HASH_MASK]
189 static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
190 static void (*sh2_drc_dispatcher)(void);
191 static void (*sh2_drc_exit)(void);
192 static void (*sh2_drc_test_irq)(void);
193 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
194 static void REGPARM(2) (*sh2_drc_write8_slot)(u32 a, u32 d);
195 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
196 static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d);
198 extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode);
200 static void flush_tcache(int tcid)
202 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
203 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
204 block_counts[tcid], block_max_counts[tcid]);
206 block_counts[tcid] = 0;
207 tcache_ptrs[tcid] = tcache_bases[tcid];
208 if (tcid == 0) { // ROM, RAM
209 memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES);
210 memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram));
213 memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0]));
215 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
219 // add block links (tracked branches)
220 static int dr_add_block_link(u32 target_pc, void *jump, int tcache_id)
222 block_link *bl = block_links[tcache_id];
223 int cnt = block_link_counts[tcache_id];
225 if (cnt >= block_max_counts[tcache_id] * 2) {
226 printf("bl overflow for tcache %d\n", tcache_id);
230 bl[cnt].target_pc = target_pc;
232 block_link_counts[tcache_id]++;
237 static void *dr_find_block(block_desc *tab, u32 addr)
239 for (tab = tab->next; tab != NULL; tab = tab->next)
240 if (tab->addr == addr)
244 return tab->tcache_ptr;
246 printf("block miss for %08x\n", addr);
250 static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id)
252 int *bcount = &block_counts[tcache_id];
255 if (*bcount >= block_max_counts[tcache_id]) {
256 printf("bd overflow for tcache %d\n", tcache_id);
260 bd = &block_tables[tcache_id][*bcount];
262 bd->tcache_ptr = tcache_ptr;
266 if ((addr & 0xc6000000) == 0x02000000) { // ROM
267 bd->next = HASH_FUNC(hash_table, addr);
268 HASH_FUNC(hash_table, addr) = bd;
270 if (bd->next != NULL) {
271 printf(" hash collision with %08x\n", bd->next->addr);
280 #define ADD_TO_ARRAY(array, count, item, failcode) \
281 array[count++] = item; \
282 if (count >= ARRAY_SIZE(array)) { \
283 printf("warning: " #array " overflow\n"); \
287 int find_in_array(u32 *array, size_t size, u32 what)
290 for (i = 0; i < size; i++)
291 if (what == array[i])
297 // ---------------------------------------------------------------
300 static u16 rcache_counter;
302 static temp_reg_t *rcache_evict(void)
304 // evict reg with oldest stamp
306 u16 min_stamp = (u16)-1;
308 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
309 if (reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY)
310 if (reg_temp[i].stamp <= min_stamp) {
311 min_stamp = reg_temp[i].stamp;
317 printf("no registers to evict, aborting\n");
322 if (reg_temp[i].type == HR_CACHED_DIRTY) {
324 emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4);
336 // note: must not be called when doing conditional code
337 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
342 // maybe already statically mapped?
349 // maybe already cached?
350 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
351 if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) &&
352 reg_temp[i].val == r)
354 reg_temp[i].stamp = rcache_counter;
355 if (mode != RC_GR_READ)
356 reg_temp[i].type = HR_CACHED_DIRTY;
357 return reg_temp[i].reg;
362 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
363 if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) {
372 if (mode != RC_GR_WRITE)
373 emith_ctx_read(tr->reg, r * 4);
375 tr->type = mode != RC_GR_READ ? HR_CACHED_DIRTY : HR_CACHED;
377 tr->stamp = rcache_counter;
381 static int rcache_get_tmp(void)
386 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
387 if (reg_temp[i].type == HR_FREE || reg_temp[i].type == HR_CONST) {
399 static int rcache_get_arg_id(int arg)
402 host_arg2reg(r, arg);
404 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
405 if (reg_temp[i].reg == r)
408 if (i == ARRAY_SIZE(reg_temp))
409 // let's just say it's untracked arg reg
412 if (reg_temp[i].type == HR_CACHED_DIRTY) {
414 emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4);
416 else if (reg_temp[i].type == HR_TEMP) {
417 printf("arg %d reg %d already used, aborting\n", arg, r);
424 // get a reg to be used as function arg
425 // it's assumed that regs are cleaned before call
426 static int rcache_get_tmp_arg(int arg)
428 int id = rcache_get_arg_id(arg);
429 reg_temp[id].type = HR_TEMP;
431 return reg_temp[id].reg;
434 // same but caches reg. RC_GR_READ only.
435 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
437 int i, srcr, dstr, dstid;
439 dstid = rcache_get_arg_id(arg);
440 dstr = reg_temp[dstid].reg;
442 // maybe already statically mapped?
443 srcr = reg_map_g2h[r];
447 // maybe already cached?
448 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
449 if ((reg_temp[i].type == HR_CACHED || reg_temp[i].type == HR_CACHED_DIRTY) &&
450 reg_temp[i].val == r)
452 srcr = reg_temp[i].reg;
459 emith_ctx_read(srcr, r * 4);
463 emith_move_r_r(dstr, srcr);
465 reg_temp[dstid].stamp = ++rcache_counter;
466 reg_temp[dstid].type = HR_CACHED;
467 reg_temp[dstid].val = r;
471 static void rcache_free_tmp(int hr)
474 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
475 if (reg_temp[i].reg == hr)
478 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
479 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
483 reg_temp[i].type = HR_FREE;
486 static void rcache_clean(void)
489 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
490 if (reg_temp[i].type == HR_CACHED_DIRTY) {
492 emith_ctx_write(reg_temp[i].reg, reg_temp[i].val * 4);
493 reg_temp[i].type = HR_CACHED;
497 static void rcache_invalidate(void)
500 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
501 reg_temp[i].type = HR_FREE;
505 static void rcache_flush(void)
511 // ---------------------------------------------------------------
513 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
515 // TODO: propagate this constant
516 int hr = rcache_get_reg(dst, RC_GR_WRITE);
517 emith_move_r_imm(hr, imm);
520 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
522 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
523 int hr_s = rcache_get_reg(src, RC_GR_READ);
525 emith_move_r_r(hr_d, hr_s);
528 // T must be clear, and comparison done just before this
529 static void emit_or_t_if_eq(int srr)
531 EMITH_SJMP_START(DCOND_NE);
532 emith_or_r_imm_c(DCOND_EQ, srr, T);
533 EMITH_SJMP_END(DCOND_NE);
536 // arguments must be ready
537 // reg cache must be clean before call
538 static int emit_memhandler_read(int size)
541 host_arg2reg(arg0, 0);
543 // must writeback cycles for poll detection stuff
544 if (reg_map_g2h[SHR_SR] != -1)
545 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
546 arg1 = rcache_get_tmp_arg(1);
547 emith_move_r_r(arg1, CONTEXT_REG);
550 if (Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
551 int tmp = rcache_get_tmp();
552 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
553 emith_cmp_r_imm(tmp, 0x02000000);
556 EMITH_SJMP3_START(DCOND_NE);
557 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
558 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
559 EMITH_SJMP3_MID(DCOND_NE);
560 emith_call_cond(DCOND_NE, p32x_sh2_read8);
564 EMITH_SJMP3_START(DCOND_NE);
565 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
566 EMITH_SJMP3_MID(DCOND_NE);
567 emith_call_cond(DCOND_NE, p32x_sh2_read16);
571 EMITH_SJMP3_START(DCOND_NE);
572 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
573 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
574 EMITH_SJMP3_MID(DCOND_NE);
575 emith_call_cond(DCOND_NE, p32x_sh2_read32);
585 emith_call(p32x_sh2_read8);
588 emith_call(p32x_sh2_read16);
591 emith_call(p32x_sh2_read32);
596 // assuming arg0 and retval reg matches
597 return rcache_get_tmp_arg(0);
600 static void emit_memhandler_write(int size, u32 pc, int delay)
603 host_arg2reg(ctxr, 2);
606 // XXX: consider inlining sh2_drc_write8
608 emith_call(sh2_drc_write8_slot);
610 emit_move_r_imm32(SHR_PC, pc);
612 emith_call(sh2_drc_write8);
617 emith_call(sh2_drc_write16_slot);
619 emit_move_r_imm32(SHR_PC, pc);
621 emith_call(sh2_drc_write16);
625 emith_move_r_r(ctxr, CONTEXT_REG);
626 emith_call(p32x_sh2_write32);
633 static int emit_indirect_indexed_read(int rx, int ry, int size)
637 a0 = rcache_get_reg_arg(0, rx);
638 t = rcache_get_reg(ry, RC_GR_READ);
639 emith_add_r_r(a0, t);
640 return emit_memhandler_read(size);
644 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
649 rcache_get_reg_arg(0, rn);
650 tmp = emit_memhandler_read(size);
651 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
652 rcache_free_tmp(tmp);
653 tmp = rcache_get_reg(rn, RC_GR_RMW);
654 emith_add_r_imm(tmp, 1 << size);
657 rcache_get_reg_arg(0, rm);
658 *rmr = emit_memhandler_read(size);
659 *rnr = rcache_get_tmp();
660 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
661 tmp = rcache_get_reg(rm, RC_GR_RMW);
662 emith_add_r_imm(tmp, 1 << size);
665 static void emit_do_static_regs(int is_write, int tmpr)
669 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
674 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
675 if (reg_map_g2h[i + 1] != r + 1)
681 // i, r point to last item
683 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
685 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
688 emith_ctx_write(r, i * 4);
690 emith_ctx_read(r, i * 4);
695 static void emit_block_entry(void)
697 int arg0, arg1, arg2;
699 host_arg2reg(arg0, 0);
700 host_arg2reg(arg1, 1);
701 host_arg2reg(arg2, 2);
704 emith_move_r_r(arg1, CONTEXT_REG);
705 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
706 emith_call(sh2_drc_announce_entry);
709 emith_tst_r_r(arg0, arg0);
710 EMITH_SJMP_START(DCOND_EQ);
711 emith_jump_reg_c(DCOND_NE, arg0);
712 EMITH_SJMP_END(DCOND_EQ);
715 static void REGPARM(3) *lookup_block(u32 pc, int is_slave, int *tcache_id)
717 block_desc *bd = NULL;
721 // we have full block id tables for data_array and RAM
722 // BIOS goes to data_array table too
723 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0) {
724 int blkid = Pico32xMem->drcblk_da[is_slave][(pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
725 *tcache_id = 1 + is_slave;
727 bd = &block_tables[*tcache_id][blkid >> 1];
728 block = bd->tcache_ptr;
732 else if ((pc & 0xc6000000) == 0x06000000) {
733 int blkid = Pico32xMem->drcblk_ram[(pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
735 bd = &block_tables[0][blkid >> 1];
736 block = bd->tcache_ptr;
740 else if ((pc & 0xc6000000) == 0x02000000) {
741 bd = HASH_FUNC(hash_table, pc);
745 block = bd->tcache_ptr;
747 block = dr_find_block(bd, pc);
758 void dr_link_blocks(void *target, u32 pc, int tcache_id)
760 block_link *bl = block_links[tcache_id];
761 int cnt = block_link_counts[tcache_id];
764 for (i = 0; i < cnt; i++) {
765 if (bl[i].target_pc == pc) {
766 dbg(1, "- link from %p", bl[i].jump);
767 emith_jump_patch(bl[i].jump, target);
768 // XXX: sync ARM caches (old jump should be fine)?
773 void *dr_prepare_ext_branch(u32 pc, SH2 *sh2, int tcache_id)
775 int target_tcache_id;
779 target = lookup_block(pc, sh2->is_slave, &target_tcache_id);
780 if (target_tcache_id == tcache_id) {
781 // allow linking blocks only from local cache
782 ret = dr_add_block_link(pc, tcache_ptr, tcache_id);
786 if (target == NULL || target_tcache_id != tcache_id)
787 target = sh2_drc_dispatcher;
795 #define DELAY_SAVE_T(sr) { \
796 emith_bic_r_imm(sr, T_save); \
797 emith_tst_r_imm(sr, T); \
798 EMITH_SJMP_START(DCOND_EQ); \
799 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
800 EMITH_SJMP_END(DCOND_EQ); \
801 drcf.use_saved_t = 1; \
804 #define FLUSH_CYCLES(sr) \
806 emith_sub_r_imm(sr, cycles << 12); \
810 #define CHECK_UNHANDLED_BITS(mask) { \
811 if ((op & (mask)) != 0) \
818 #define GET_Rm GET_Fx
823 #define CHECK_FX_LT(n) \
827 #define MAX_LOCAL_BRANCHES 32
829 // op_flags: data from 1st pass
830 #define OP_FLAGS(pc) op_flags[((pc) - base_pc) / 2]
831 #define OF_DELAY_OP (1 << 0)
833 static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
835 // XXX: maybe use structs instead?
836 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
837 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
838 int branch_target_count = 0;
839 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
840 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
841 int branch_patch_count = 0;
842 int pending_branch_cond = -1;
843 int pending_branch_pc = 0;
844 u8 op_flags[BLOCK_CYCLE_LIMIT + 1];
848 u32 use_saved_t:1; // delayed op modifies T
851 // PC of current, first, last, last_target_blk SH2 insn
852 u32 pc, base_pc, end_pc, out_pc;
854 block_desc *this_block;
865 if ((tmp != 0 && tmp != 1 && tmp != 6) || base_pc == 0) {
866 printf("invalid PC, aborting: %08x\n", base_pc);
867 // FIXME: be less destructive
871 tcache_ptr = tcache_ptrs[tcache_id];
872 this_block = dr_add_block(base_pc, tcache_id, &blkid_main);
873 if (this_block == NULL)
876 // predict tcache overflow
877 tmp = tcache_ptr - tcache_bases[tcache_id];
878 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
879 printf("tcache %d overflow\n", tcache_id);
883 block_entry = tcache_ptr;
884 dbg(1, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
885 tcache_id, blkid_main, base_pc, block_entry);
887 dr_link_blocks(tcache_ptr, base_pc, tcache_id);
889 // 1st pass: scan forward for local branches
890 memset(op_flags, 0, sizeof(op_flags));
891 for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT; cycles++, pc += 2) {
892 op = p32x_sh2_read16(pc, sh2);
893 if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR
894 signed int offs = ((signed int)(op << 20) >> 19);
896 OP_FLAGS(pc) |= OF_DELAY_OP;
897 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 2,);
900 if ((op & 0xf000) == 0) {
902 if (op == 0x1b) // SLEEP
904 if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) { // BRAF, BSRF, RTS, RTE
906 OP_FLAGS(pc) |= OF_DELAY_OP;
911 if ((op & 0xf0df) == 0x400b) { // JMP, JSR
913 OP_FLAGS(pc) |= OF_DELAY_OP;
916 if ((op & 0xf900) == 0x8900) { // BT(S), BF(S)
917 signed int offs = ((signed int)(op << 24) >> 23);
919 OP_FLAGS(pc + 2) |= OF_DELAY_OP;
920 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 4, break);
922 if ((op & 0xff00) == 0xc300) // TRAPA
928 // clean branch_targets that are not really local,
929 // and that land on delay slots
930 for (i = 0, tmp = 0; i < branch_target_count; i++) {
931 pc = branch_target_pc[i];
932 if (base_pc <= pc && pc <= end_pc && !(OP_FLAGS(pc) & OF_DELAY_OP))
933 branch_target_pc[tmp++] = branch_target_pc[i];
935 branch_target_count = tmp;
936 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
938 // -------------------------------------------------
939 // 2nd pass: actual compilation
942 for (cycles = 0; pc <= end_pc || drcf.delayed_op; )
946 if (drcf.delayed_op > 0)
949 i = find_in_array(branch_target_pc, branch_target_count, pc);
954 /* make "subblock" - just a mid-block entry */
955 block_desc *subblock;
959 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
962 do_host_disasm(tcache_id);
964 subblock = dr_add_block(pc, tcache_id, &blkid);
965 if (subblock == NULL)
967 subblock->end_addr = pc;
969 if (tcache_id != 0) { // data array, BIOS
970 drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
971 drcblk += (pc & 0x00fff) >> SH2_DRCBLK_DA_SHIFT;
972 *drcblk = (blkid << 1) | 1;
973 } else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
974 drcblk = Pico32xMem->drcblk_ram;
975 drcblk += (pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
976 *drcblk = (blkid << 1) | 1;
979 dbg(1, "-- %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
980 tcache_id, blkid, pc, tcache_ptr);
982 // since we made a block entry, link any other blocks that jump to current pc
983 dr_link_blocks(tcache_ptr, pc, tcache_id);
985 branch_target_ptr[i] = tcache_ptr;
988 emit_move_r_imm32(SHR_PC, pc);
992 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
993 emith_cmp_r_imm(sr, 0);
994 emith_jump_cond(DCOND_LE, sh2_drc_exit);
997 op = p32x_sh2_read16(pc, sh2);
1002 DasmSH2(sh2dasm_buff, pc, op);
1003 printf("%08x %04x %s\n", pc, op, sh2dasm_buff);
1010 switch ((op >> 12) & 0x0f)
1012 /////////////////////////////////////////////
1017 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1020 case 0: // STC SR,Rn 0000nnnn00000010
1023 case 1: // STC GBR,Rn 0000nnnn00010010
1026 case 2: // STC VBR,Rn 0000nnnn00100010
1032 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
1033 emith_move_r_r(tmp, tmp3);
1035 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
1038 CHECK_UNHANDLED_BITS(0xd0);
1039 // BRAF Rm 0000mmmm00100011
1040 // BSRF Rm 0000mmmm00000011
1042 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1043 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1044 emith_move_r_r(tmp, tmp2);
1046 emith_add_r_imm(tmp, pc + 2);
1048 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
1049 emith_move_r_imm(tmp3, pc + 2);
1050 emith_add_r_r(tmp, tmp3);
1055 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
1056 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
1057 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
1059 tmp = rcache_get_reg_arg(1, GET_Rm());
1060 tmp2 = rcache_get_reg_arg(0, SHR_R0);
1061 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1062 emith_add_r_r(tmp2, tmp3);
1063 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1066 // MUL.L Rm,Rn 0000nnnnmmmm0111
1067 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1068 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1069 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1070 emith_mul(tmp3, tmp2, tmp);
1074 CHECK_UNHANDLED_BITS(0xf00);
1077 case 0: // CLRT 0000000000001000
1078 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1079 if (drcf.delayed_op)
1081 emith_bic_r_imm(sr, T);
1083 case 1: // SETT 0000000000011000
1084 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1085 if (drcf.delayed_op)
1087 emith_or_r_imm(sr, T);
1089 case 2: // CLRMAC 0000000000101000
1090 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1091 emith_move_r_imm(tmp, 0);
1092 tmp = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1093 emith_move_r_imm(tmp, 0);
1102 case 0: // NOP 0000000000001001
1103 CHECK_UNHANDLED_BITS(0xf00);
1105 case 1: // DIV0U 0000000000011001
1106 CHECK_UNHANDLED_BITS(0xf00);
1107 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1108 if (drcf.delayed_op)
1110 emith_bic_r_imm(sr, M|Q|T);
1112 case 2: // MOVT Rn 0000nnnn00101001
1113 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1114 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1115 emith_clear_msb(tmp2, sr, 31);
1122 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1125 case 0: // STS MACH,Rn 0000nnnn00001010
1128 case 1: // STS MACL,Rn 0000nnnn00011010
1131 case 2: // STS PR,Rn 0000nnnn00101010
1137 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1138 emith_move_r_r(tmp, tmp2);
1141 CHECK_UNHANDLED_BITS(0xf00);
1144 case 0: // RTS 0000000000001011
1146 emit_move_r_r(SHR_PC, SHR_PR);
1150 case 1: // SLEEP 0000000000011011
1151 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
1152 emith_clear_msb(tmp, tmp, 20); // clear cycles
1153 out_pc = out_pc - 2;
1156 case 2: // RTE 0000000000101011
1160 rcache_get_reg_arg(0, SHR_SP);
1161 tmp = emit_memhandler_read(2);
1162 tmp2 = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1163 emith_move_r_r(tmp2, tmp);
1164 rcache_free_tmp(tmp);
1167 tmp = rcache_get_reg_arg(0, SHR_SP);
1168 emith_add_r_imm(tmp, 4);
1169 tmp = emit_memhandler_read(2);
1170 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1171 emith_write_sr(sr, tmp);
1172 rcache_free_tmp(tmp);
1173 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1174 emith_add_r_imm(tmp, 4*2);
1183 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1184 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1185 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1186 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1187 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1188 if ((op & 3) != 2) {
1189 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1191 emith_move_r_r(tmp2, tmp);
1192 rcache_free_tmp(tmp);
1194 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1195 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1196 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1197 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1198 /* MS 16 MAC bits unused if saturated */
1199 emith_tst_r_imm(sr, S);
1200 EMITH_SJMP_START(DCOND_EQ);
1201 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1202 EMITH_SJMP_END(DCOND_EQ);
1203 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1204 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1205 rcache_free_tmp(tmp2);
1206 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1207 emith_tst_r_imm(sr, S);
1209 EMITH_JMP_START(DCOND_EQ);
1210 emith_asr(tmp, tmp4, 15);
1211 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1212 EMITH_SJMP_START(DCOND_GE);
1213 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1214 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1215 EMITH_SJMP_END(DCOND_GE);
1216 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1217 EMITH_SJMP_START(DCOND_LE);
1218 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1219 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1220 EMITH_SJMP_END(DCOND_LE);
1221 EMITH_JMP_END(DCOND_EQ);
1223 rcache_free_tmp(tmp);
1229 /////////////////////////////////////////////
1231 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1233 tmp = rcache_get_reg_arg(0, GET_Rn());
1234 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1235 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1236 emit_memhandler_write(2, pc, drcf.delayed_op);
1242 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1243 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1244 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1246 rcache_get_reg_arg(0, GET_Rn());
1247 rcache_get_reg_arg(1, GET_Rm());
1248 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1250 case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
1251 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
1252 case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110
1253 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1254 emith_sub_r_imm(tmp, (1 << (op & 3)));
1256 rcache_get_reg_arg(0, GET_Rn());
1257 rcache_get_reg_arg(1, GET_Rm());
1258 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1260 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1261 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1262 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1263 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1264 if (drcf.delayed_op)
1266 emith_bic_r_imm(sr, M|Q|T);
1267 emith_tst_r_imm(tmp2, (1<<31));
1268 EMITH_SJMP_START(DCOND_EQ);
1269 emith_or_r_imm_c(DCOND_NE, sr, Q);
1270 EMITH_SJMP_END(DCOND_EQ);
1271 emith_tst_r_imm(tmp3, (1<<31));
1272 EMITH_SJMP_START(DCOND_EQ);
1273 emith_or_r_imm_c(DCOND_NE, sr, M);
1274 EMITH_SJMP_END(DCOND_EQ);
1275 emith_teq_r_r(tmp2, tmp3);
1276 EMITH_SJMP_START(DCOND_PL);
1277 emith_or_r_imm_c(DCOND_MI, sr, T);
1278 EMITH_SJMP_END(DCOND_PL);
1280 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1281 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1282 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1283 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1284 if (drcf.delayed_op)
1286 emith_bic_r_imm(sr, T);
1287 emith_tst_r_r(tmp2, tmp3);
1288 emit_or_t_if_eq(sr);
1290 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1291 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1292 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1293 emith_and_r_r(tmp, tmp2);
1295 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1296 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1297 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1298 emith_eor_r_r(tmp, tmp2);
1300 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1301 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1302 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1303 emith_or_r_r(tmp, tmp2);
1305 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1306 tmp = rcache_get_tmp();
1307 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1308 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1309 emith_eor_r_r_r(tmp, tmp2, tmp3);
1310 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1311 if (drcf.delayed_op)
1313 emith_bic_r_imm(sr, T);
1314 emith_tst_r_imm(tmp, 0x000000ff);
1315 emit_or_t_if_eq(tmp);
1316 emith_tst_r_imm(tmp, 0x0000ff00);
1317 emit_or_t_if_eq(tmp);
1318 emith_tst_r_imm(tmp, 0x00ff0000);
1319 emit_or_t_if_eq(tmp);
1320 emith_tst_r_imm(tmp, 0xff000000);
1321 emit_or_t_if_eq(tmp);
1322 rcache_free_tmp(tmp);
1324 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1325 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1326 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1327 emith_lsr(tmp, tmp, 16);
1328 emith_or_r_r_lsl(tmp, tmp2, 16);
1330 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1331 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1332 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1333 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1335 emith_sext(tmp, tmp2, 16);
1337 emith_clear_msb(tmp, tmp2, 16);
1338 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1339 tmp2 = rcache_get_tmp();
1341 emith_sext(tmp2, tmp3, 16);
1343 emith_clear_msb(tmp2, tmp3, 16);
1344 emith_mul(tmp, tmp, tmp2);
1345 rcache_free_tmp(tmp2);
1346 // FIXME: causes timing issues in Doom?
1352 /////////////////////////////////////////////
1356 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
1357 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
1358 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
1359 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
1360 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
1361 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1362 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1363 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1364 if (drcf.delayed_op)
1366 emith_bic_r_imm(sr, T);
1367 emith_cmp_r_r(tmp2, tmp3);
1370 case 0x00: // CMP/EQ
1371 emit_or_t_if_eq(sr);
1373 case 0x02: // CMP/HS
1374 EMITH_SJMP_START(DCOND_LO);
1375 emith_or_r_imm_c(DCOND_HS, sr, T);
1376 EMITH_SJMP_END(DCOND_LO);
1378 case 0x03: // CMP/GE
1379 EMITH_SJMP_START(DCOND_LT);
1380 emith_or_r_imm_c(DCOND_GE, sr, T);
1381 EMITH_SJMP_END(DCOND_LT);
1383 case 0x06: // CMP/HI
1384 EMITH_SJMP_START(DCOND_LS);
1385 emith_or_r_imm_c(DCOND_HI, sr, T);
1386 EMITH_SJMP_END(DCOND_LS);
1388 case 0x07: // CMP/GT
1389 EMITH_SJMP_START(DCOND_LE);
1390 emith_or_r_imm_c(DCOND_GT, sr, T);
1391 EMITH_SJMP_END(DCOND_LE);
1395 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
1396 // Q1 = carry(Rn = (Rn << 1) | T)
1398 // Q2 = carry(Rn += Rm)
1400 // Q2 = carry(Rn -= Rm)
1402 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
1403 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1404 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1405 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1406 if (drcf.delayed_op)
1408 emith_tpop_carry(sr, 0);
1409 emith_adcf_r_r(tmp2, tmp2);
1410 emith_tpush_carry(sr, 0); // keep Q1 in T for now
1411 tmp4 = rcache_get_tmp();
1412 emith_and_r_r_imm(tmp4, sr, M);
1413 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
1414 rcache_free_tmp(tmp4);
1415 // add or sub, invert T if carry to get Q1 ^ Q2
1416 // in: (Q ^ M) passed in Q, Q1 in T
1417 emith_sh2_div1_step(tmp2, tmp3, sr);
1418 emith_bic_r_imm(sr, Q);
1419 emith_tst_r_imm(sr, M);
1420 EMITH_SJMP_START(DCOND_EQ);
1421 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
1422 EMITH_SJMP_END(DCOND_EQ);
1423 emith_tst_r_imm(sr, T);
1424 EMITH_SJMP_START(DCOND_EQ);
1425 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
1426 EMITH_SJMP_END(DCOND_EQ);
1427 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
1429 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
1430 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1431 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1432 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1433 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1434 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
1436 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
1437 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
1438 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1439 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1441 emith_add_r_r(tmp, tmp2);
1443 emith_sub_r_r(tmp, tmp2);
1445 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
1446 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
1447 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1448 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1449 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1450 if (drcf.delayed_op)
1452 if (op & 4) { // adc
1453 emith_tpop_carry(sr, 0);
1454 emith_adcf_r_r(tmp, tmp2);
1455 emith_tpush_carry(sr, 0);
1457 emith_tpop_carry(sr, 1);
1458 emith_sbcf_r_r(tmp, tmp2);
1459 emith_tpush_carry(sr, 1);
1462 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
1463 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
1464 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1465 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1466 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1467 if (drcf.delayed_op)
1469 emith_bic_r_imm(sr, T);
1471 emith_addf_r_r(tmp, tmp2);
1473 emith_subf_r_r(tmp, tmp2);
1474 EMITH_SJMP_START(DCOND_VC);
1475 emith_or_r_imm_c(DCOND_VS, sr, T);
1476 EMITH_SJMP_END(DCOND_VC);
1478 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
1479 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1480 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1481 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1482 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1483 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
1488 /////////////////////////////////////////////
1495 case 0: // SHLL Rn 0100nnnn00000000
1496 case 2: // SHAL Rn 0100nnnn00100000
1497 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1498 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1499 if (drcf.delayed_op)
1501 emith_tpop_carry(sr, 0); // dummy
1502 emith_lslf(tmp, tmp, 1);
1503 emith_tpush_carry(sr, 0);
1505 case 1: // DT Rn 0100nnnn00010000
1506 if (p32x_sh2_read16(pc, sh2) == 0x8bfd) { // BF #-2
1507 emith_sh2_dtbf_loop();
1510 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1511 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1512 if (drcf.delayed_op)
1514 emith_bic_r_imm(sr, T);
1515 emith_subf_r_imm(tmp, 1);
1516 emit_or_t_if_eq(sr);
1523 case 0: // SHLR Rn 0100nnnn00000001
1524 case 2: // SHAR Rn 0100nnnn00100001
1525 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1526 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1527 if (drcf.delayed_op)
1529 emith_tpop_carry(sr, 0); // dummy
1531 emith_asrf(tmp, tmp, 1);
1533 emith_lsrf(tmp, tmp, 1);
1534 emith_tpush_carry(sr, 0);
1536 case 1: // CMP/PZ Rn 0100nnnn00010001
1537 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1538 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1539 if (drcf.delayed_op)
1541 emith_bic_r_imm(sr, T);
1542 emith_cmp_r_imm(tmp, 0);
1543 EMITH_SJMP_START(DCOND_LT);
1544 emith_or_r_imm_c(DCOND_GE, sr, T);
1545 EMITH_SJMP_END(DCOND_LT);
1553 case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
1556 case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
1559 case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
1562 case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
1565 case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
1568 case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
1574 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1575 emith_sub_r_imm(tmp2, 4);
1577 rcache_get_reg_arg(0, GET_Rn());
1578 tmp3 = rcache_get_reg_arg(1, tmp);
1580 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
1581 emit_memhandler_write(2, pc, drcf.delayed_op);
1587 case 0x04: // ROTL Rn 0100nnnn00000100
1588 case 0x05: // ROTR Rn 0100nnnn00000101
1589 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1590 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1591 if (drcf.delayed_op)
1593 emith_tpop_carry(sr, 0); // dummy
1595 emith_rorf(tmp, tmp, 1);
1597 emith_rolf(tmp, tmp, 1);
1598 emith_tpush_carry(sr, 0);
1600 case 0x24: // ROTCL Rn 0100nnnn00100100
1601 case 0x25: // ROTCR Rn 0100nnnn00100101
1602 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1603 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1604 if (drcf.delayed_op)
1606 emith_tpop_carry(sr, 0);
1611 emith_tpush_carry(sr, 0);
1613 case 0x15: // CMP/PL Rn 0100nnnn00010101
1614 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1615 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1616 if (drcf.delayed_op)
1618 emith_bic_r_imm(sr, T);
1619 emith_cmp_r_imm(tmp, 0);
1620 EMITH_SJMP_START(DCOND_LE);
1621 emith_or_r_imm_c(DCOND_GT, sr, T);
1622 EMITH_SJMP_END(DCOND_LE);
1630 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
1633 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
1636 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
1639 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
1642 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
1645 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
1652 rcache_get_reg_arg(0, GET_Rn());
1653 tmp2 = emit_memhandler_read(2);
1654 if (tmp == SHR_SR) {
1655 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1656 if (drcf.delayed_op)
1658 emith_write_sr(sr, tmp2);
1661 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
1662 emith_move_r_r(tmp, tmp2);
1664 rcache_free_tmp(tmp2);
1665 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1666 emith_add_r_imm(tmp, 4);
1673 // SHLL2 Rn 0100nnnn00001000
1674 // SHLR2 Rn 0100nnnn00001001
1678 // SHLL8 Rn 0100nnnn00011000
1679 // SHLR8 Rn 0100nnnn00011001
1683 // SHLL16 Rn 0100nnnn00101000
1684 // SHLR16 Rn 0100nnnn00101001
1690 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1692 emith_lsr(tmp2, tmp2, tmp);
1694 emith_lsl(tmp2, tmp2, tmp);
1699 case 0: // LDS Rm,MACH 0100mmmm00001010
1702 case 1: // LDS Rm,MACL 0100mmmm00011010
1705 case 2: // LDS Rm,PR 0100mmmm00101010
1711 emit_move_r_r(tmp2, GET_Rn());
1716 case 0: // JSR @Rm 0100mmmm00001011
1717 case 2: // JMP @Rm 0100mmmm00101011
1720 emit_move_r_imm32(SHR_PR, pc + 2);
1721 emit_move_r_r(SHR_PC, (op >> 8) & 0x0f);
1725 case 1: // TAS.B @Rn 0100nnnn00011011
1726 // XXX: is TAS working on 32X?
1728 rcache_get_reg_arg(0, GET_Rn());
1729 tmp = emit_memhandler_read(0);
1730 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1731 if (drcf.delayed_op)
1733 emith_bic_r_imm(sr, T);
1734 emith_cmp_r_imm(tmp, 0);
1735 emit_or_t_if_eq(sr);
1737 emith_or_r_imm(tmp, 0x80);
1738 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
1739 emith_move_r_r(tmp2, tmp);
1740 rcache_free_tmp(tmp);
1741 rcache_get_reg_arg(0, GET_Rn());
1742 emit_memhandler_write(0, pc, drcf.delayed_op);
1750 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1753 case 0: // LDC Rm,SR 0100mmmm00001110
1756 case 1: // LDC Rm,GBR 0100mmmm00011110
1759 case 2: // LDC Rm,VBR 0100mmmm00101110
1765 if (tmp2 == SHR_SR) {
1766 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1767 if (drcf.delayed_op)
1769 emith_write_sr(sr, tmp);
1772 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
1773 emith_move_r_r(tmp2, tmp);
1777 // MAC @Rm+,@Rn+ 0100nnnnmmmm1111
1778 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
1779 emith_sext(tmp, tmp, 16);
1780 emith_sext(tmp2, tmp2, 16);
1781 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
1782 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1783 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1784 rcache_free_tmp(tmp2);
1785 // XXX: MACH should be untouched when S is set?
1786 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1787 emith_tst_r_imm(sr, S);
1788 EMITH_JMP_START(DCOND_EQ);
1790 emith_asr(tmp, tmp3, 31);
1791 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
1792 EMITH_JMP_START(DCOND_EQ);
1793 emith_move_r_imm(tmp3, 0x80000000);
1794 emith_tst_r_r(tmp4, tmp4);
1795 EMITH_SJMP_START(DCOND_MI);
1796 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
1797 EMITH_SJMP_END(DCOND_MI);
1798 EMITH_JMP_END(DCOND_EQ);
1800 EMITH_JMP_END(DCOND_EQ);
1801 rcache_free_tmp(tmp);
1807 /////////////////////////////////////////////
1809 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
1811 tmp = rcache_get_reg_arg(0, GET_Rm());
1812 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1813 tmp = emit_memhandler_read(2);
1814 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1815 emith_move_r_r(tmp2, tmp);
1816 rcache_free_tmp(tmp);
1819 /////////////////////////////////////////////
1823 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
1824 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
1825 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
1826 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
1827 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
1828 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
1830 rcache_get_reg_arg(0, GET_Rm());
1831 tmp = emit_memhandler_read(op & 3);
1832 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1833 if ((op & 3) != 2) {
1834 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1836 emith_move_r_r(tmp2, tmp);
1837 rcache_free_tmp(tmp);
1838 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
1839 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
1840 emith_add_r_imm(tmp, (1 << (op & 3)));
1845 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
1846 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1849 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
1850 emith_move_r_r(tmp2, tmp);
1852 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
1853 emith_mvn_r_r(tmp2, tmp);
1855 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
1858 tmp3 = rcache_get_tmp();
1859 tmp4 = rcache_get_tmp();
1860 emith_lsr(tmp3, tmp, 16);
1861 emith_or_r_r_lsl(tmp3, tmp, 24);
1862 emith_and_r_r_imm(tmp4, tmp, 0xff00);
1863 emith_or_r_r_lsl(tmp3, tmp4, 8);
1864 emith_rol(tmp2, tmp3, 16);
1865 rcache_free_tmp(tmp4);
1867 rcache_free_tmp(tmp3);
1869 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
1870 emith_rol(tmp2, tmp, 16);
1872 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
1873 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1874 if (drcf.delayed_op)
1876 emith_tpop_carry(sr, 1);
1877 emith_negcf_r_r(tmp2, tmp);
1878 emith_tpush_carry(sr, 1);
1880 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
1881 emith_neg_r_r(tmp2, tmp);
1883 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
1884 emith_clear_msb(tmp2, tmp, 24);
1886 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
1887 emith_clear_msb(tmp2, tmp, 16);
1889 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
1890 emith_sext(tmp2, tmp, 8);
1892 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
1893 emith_sext(tmp2, tmp, 16);
1900 /////////////////////////////////////////////
1902 // ADD #imm,Rn 0111nnnniiiiiiii
1903 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1904 if (op & 0x80) { // adding negative
1905 emith_sub_r_imm(tmp, -op & 0xff);
1907 emith_add_r_imm(tmp, op & 0xff);
1910 /////////////////////////////////////////////
1912 switch (op & 0x0f00)
1914 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
1915 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
1917 tmp = rcache_get_reg_arg(0, GET_Rm());
1918 tmp2 = rcache_get_reg_arg(1, SHR_R0);
1919 tmp3 = (op & 0x100) >> 8;
1920 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
1921 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
1923 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
1924 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
1926 tmp = rcache_get_reg_arg(0, GET_Rm());
1927 tmp3 = (op & 0x100) >> 8;
1928 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
1929 tmp = emit_memhandler_read(tmp3);
1930 tmp2 = rcache_get_reg(0, RC_GR_WRITE);
1931 emith_sext(tmp2, tmp, 8 << tmp3);
1932 rcache_free_tmp(tmp);
1934 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
1935 // XXX: could use cmn
1936 tmp = rcache_get_tmp();
1937 tmp2 = rcache_get_reg(0, RC_GR_READ);
1938 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1939 if (drcf.delayed_op)
1941 emith_move_r_imm_s8(tmp, op & 0xff);
1942 emith_bic_r_imm(sr, T);
1943 emith_cmp_r_r(tmp2, tmp);
1944 emit_or_t_if_eq(sr);
1945 rcache_free_tmp(tmp);
1947 case 0x0d00: // BT/S label 10001101dddddddd
1948 case 0x0f00: // BF/S label 10001111dddddddd
1952 case 0x0900: // BT label 10001001dddddddd
1953 case 0x0b00: // BF label 10001011dddddddd
1954 // will handle conditional branches later
1955 pending_branch_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE;
1956 i = ((signed int)(op << 24) >> 23);
1957 pending_branch_pc = pc + i + 2;
1963 /////////////////////////////////////////////
1965 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
1967 tmp = rcache_get_tmp_arg(0);
1968 emith_move_r_imm(tmp, pc + (op & 0xff) * 2 + 2);
1969 tmp = emit_memhandler_read(1);
1970 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1971 emith_sext(tmp2, tmp, 16);
1972 rcache_free_tmp(tmp);
1975 /////////////////////////////////////////////
1977 // BRA label 1010dddddddddddd
1979 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1980 tmp = ((signed int)(op << 20) >> 19);
1981 out_pc = pc + tmp + 2;
1983 emith_clear_msb(sr, sr, 20); // burn cycles
1987 /////////////////////////////////////////////
1989 // BSR label 1011dddddddddddd
1991 emit_move_r_imm32(SHR_PR, pc + 2);
1992 tmp = ((signed int)(op << 20) >> 19);
1993 out_pc = pc + tmp + 2;
1997 /////////////////////////////////////////////
1999 switch (op & 0x0f00)
2001 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
2002 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
2003 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
2005 tmp = rcache_get_reg_arg(0, SHR_GBR);
2006 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2007 tmp3 = (op & 0x300) >> 8;
2008 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
2009 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
2011 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
2012 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
2013 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
2015 tmp = rcache_get_reg_arg(0, SHR_GBR);
2016 tmp3 = (op & 0x300) >> 8;
2017 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
2018 tmp = emit_memhandler_read(tmp3);
2019 tmp2 = rcache_get_reg(0, RC_GR_WRITE);
2021 emith_sext(tmp2, tmp, 8 << tmp3);
2023 emith_move_r_r(tmp2, tmp);
2024 rcache_free_tmp(tmp);
2026 case 0x0300: // TRAPA #imm 11000011iiiiiiii
2027 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2028 emith_sub_r_imm(tmp, 4*2);
2031 tmp = rcache_get_reg_arg(0, SHR_SP);
2032 emith_add_r_imm(tmp, 4);
2033 tmp = rcache_get_reg_arg(1, SHR_SR);
2034 emith_clear_msb(tmp, tmp, 22);
2035 emit_memhandler_write(2, pc, drcf.delayed_op);
2037 rcache_get_reg_arg(0, SHR_SP);
2038 tmp = rcache_get_tmp_arg(1);
2039 emith_move_r_imm(tmp, pc);
2040 emit_memhandler_write(2, pc, drcf.delayed_op);
2042 tmp = rcache_get_reg_arg(0, SHR_VBR);
2043 emith_add_r_imm(tmp, (op & 0xff) * 4);
2044 tmp = emit_memhandler_read(2);
2045 tmp2 = rcache_get_reg(SHR_PC, RC_GR_WRITE);
2046 emith_move_r_r(tmp2, tmp);
2047 rcache_free_tmp(tmp);
2051 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
2052 emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3);
2054 case 0x0800: // TST #imm,R0 11001000iiiiiiii
2055 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
2056 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2057 if (drcf.delayed_op)
2059 emith_bic_r_imm(sr, T);
2060 emith_tst_r_imm(tmp, op & 0xff);
2061 emit_or_t_if_eq(sr);
2063 case 0x0900: // AND #imm,R0 11001001iiiiiiii
2064 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2065 emith_and_r_imm(tmp, op & 0xff);
2067 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
2068 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2069 emith_eor_r_imm(tmp, op & 0xff);
2071 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
2072 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2073 emith_or_r_imm(tmp, op & 0xff);
2075 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
2076 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2077 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2078 if (drcf.delayed_op)
2080 emith_bic_r_imm(sr, T);
2081 emith_tst_r_imm(tmp, op & 0xff);
2082 emit_or_t_if_eq(sr);
2083 rcache_free_tmp(tmp);
2086 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2087 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2088 emith_and_r_imm(tmp, op & 0xff);
2090 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2091 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2092 emith_eor_r_imm(tmp, op & 0xff);
2094 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2095 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2096 emith_or_r_imm(tmp, op & 0xff);
2098 tmp2 = rcache_get_tmp_arg(1);
2099 emith_move_r_r(tmp2, tmp);
2100 rcache_free_tmp(tmp);
2101 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2102 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2103 emith_add_r_r(tmp3, tmp4);
2104 emit_memhandler_write(0, pc, drcf.delayed_op);
2110 /////////////////////////////////////////////
2112 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
2114 tmp = rcache_get_tmp_arg(0);
2115 emith_move_r_imm(tmp, (pc + (op & 0xff) * 4 + 2) & ~3);
2116 tmp = emit_memhandler_read(2);
2117 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2118 emith_move_r_r(tmp2, tmp);
2119 rcache_free_tmp(tmp);
2122 /////////////////////////////////////////////
2124 // MOV #imm,Rn 1110nnnniiiiiiii
2125 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2126 emith_move_r_imm_s8(tmp, op & 0xff);
2131 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
2132 sh2->is_slave ? 's' : 'm', op, pc - 2);
2133 #ifdef DRC_DEBUG_INTERP
2134 emit_move_r_imm32(SHR_PC, pc - 2);
2136 emith_pass_arg_r(0, CONTEXT_REG);
2137 emith_pass_arg_imm(1, op);
2138 emith_call(sh2_do_op);
2144 // conditional branch handling (with/without delay)
2145 if (pending_branch_cond != -1 && drcf.delayed_op != 2)
2147 u32 target_pc = pending_branch_pc;
2150 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2154 if (drcf.use_saved_t)
2155 emith_tst_r_imm(sr, T_save);
2157 emith_tst_r_imm(sr, T);
2159 if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0) {
2161 // XXX: jumps back can be linked already
2162 branch_patch_pc[branch_patch_count] = target_pc;
2163 branch_patch_ptr[branch_patch_count] = tcache_ptr;
2164 emith_jump_cond_patchable(pending_branch_cond, tcache_ptr);
2166 branch_patch_count++;
2167 if (branch_patch_count == MAX_LOCAL_BRANCHES) {
2168 printf("warning: too many local branches\n");
2173 // can't resolve branch locally, make a block exit
2174 emit_move_r_imm32(SHR_PC, target_pc);
2177 target = dr_prepare_ext_branch(target_pc, sh2, tcache_id);
2180 emith_jump_cond_patchable(pending_branch_cond, target);
2183 drcf.use_saved_t = 0;
2184 pending_branch_cond = -1;
2188 // XXX: delay slots..
2189 if (drcf.test_irq && drcf.delayed_op != 2) {
2190 if (!drcf.delayed_op)
2191 emit_move_r_imm32(SHR_PC, pc);
2192 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2195 emith_call(sh2_drc_test_irq);
2199 do_host_disasm(tcache_id);
2201 if (out_pc != 0 && drcf.delayed_op != 2)
2205 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2209 if (out_pc == (u32)-1) {
2210 // indirect jump -> back to dispatcher
2211 emith_jump(sh2_drc_dispatcher);
2216 emit_move_r_imm32(SHR_PC, out_pc);
2219 target = dr_prepare_ext_branch(out_pc, sh2, tcache_id);
2222 emith_jump_patchable(target);
2225 // link local branches
2226 for (i = 0; i < branch_patch_count; i++) {
2229 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2230 target = branch_target_ptr[t];
2231 if (target == NULL) {
2232 // flush pc and go back to dispatcher (should no longer happen)
2233 printf("stray branch to %08x %p\n", branch_patch_pc[i], tcache_ptr);
2234 target = tcache_ptr;
2235 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2237 emith_jump(sh2_drc_dispatcher);
2239 emith_jump_patch(branch_patch_ptr[i], target);
2242 this_block->end_addr = pc;
2244 // mark memory blocks as containing compiled code
2245 if (tcache_id != 0) {
2247 u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
2248 tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
2249 tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
2250 drcblk[tmp] = (blkid_main << 1) | 1;
2251 for (++tmp; tmp < tmp2; tmp++) {
2253 continue; // dont overwrite overlay block(s)
2254 drcblk[tmp] = blkid_main << 1;
2257 else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
2258 tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
2259 tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
2260 Pico32xMem->drcblk_ram[tmp] = (blkid_main << 1) | 1;
2261 for (++tmp; tmp < tmp2; tmp++) {
2262 if (Pico32xMem->drcblk_ram[tmp])
2264 Pico32xMem->drcblk_ram[tmp] = blkid_main << 1;
2268 tcache_ptrs[tcache_id] = tcache_ptr;
2271 cache_flush_d_inval_i(block_entry, tcache_ptr);
2274 do_host_disasm(tcache_id);
2275 dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2276 tcache_id, block_counts[tcache_id],
2277 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2278 insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled);
2279 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2280 dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2283 tcache_dsm_ptrs[tcache_id] = block_entry;
2284 do_host_disasm(tcache_id);
2295 static void sh2_generate_utils(void)
2297 int arg0, arg1, arg2, sr, tmp;
2298 void *sh2_drc_write_end, *sh2_drc_write_slot_end;
2300 host_arg2reg(arg0, 0);
2301 host_arg2reg(arg1, 1);
2302 host_arg2reg(arg2, 2);
2303 emith_move_r_r(arg0, arg0); // nop
2305 // sh2_drc_exit(void)
2306 sh2_drc_exit = (void *)tcache_ptr;
2307 emit_do_static_regs(1, arg2);
2308 emith_sh2_drc_exit();
2310 // sh2_drc_dispatcher(void)
2311 sh2_drc_dispatcher = (void *)tcache_ptr;
2312 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2313 emith_cmp_r_imm(sr, 0);
2314 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2315 rcache_invalidate();
2316 emith_ctx_read(arg0, SHR_PC * 4);
2317 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2318 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2319 emith_call(lookup_block);
2321 // lookup failed, call sh2_translate()
2322 emith_move_r_r(arg0, CONTEXT_REG);
2323 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2324 emith_call(sh2_translate);
2326 // sh2_translate() failed, flush cache and retry
2327 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2328 emith_call(flush_tcache);
2329 emith_move_r_r(arg0, CONTEXT_REG);
2330 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2331 emith_call(sh2_translate);
2333 // XXX: can't translate, fail
2336 // sh2_drc_test_irq(void)
2337 // assumes it's called from main function (may jump to dispatcher)
2338 sh2_drc_test_irq = (void *)tcache_ptr;
2339 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2340 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2341 emith_lsr(arg0, sr, I_SHIFT);
2342 emith_and_r_imm(arg0, 0x0f);
2343 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2344 EMITH_SJMP_START(DCOND_GT);
2345 emith_ret_c(DCOND_LE); // nope, return
2346 EMITH_SJMP_END(DCOND_GT);
2348 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2349 emith_sub_r_imm(tmp, 4*2);
2352 tmp = rcache_get_reg_arg(0, SHR_SP);
2353 emith_add_r_imm(tmp, 4);
2354 tmp = rcache_get_reg_arg(1, SHR_SR);
2355 emith_clear_msb(tmp, tmp, 22);
2356 emith_move_r_r(arg2, CONTEXT_REG);
2357 emith_call(p32x_sh2_write32);
2358 rcache_invalidate();
2360 rcache_get_reg_arg(0, SHR_SP);
2361 emith_ctx_read(arg1, SHR_PC * 4);
2362 emith_move_r_r(arg2, CONTEXT_REG);
2363 emith_call(p32x_sh2_write32);
2364 rcache_invalidate();
2365 // update I, cycles, do callback
2366 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2367 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2368 emith_bic_r_imm(sr, I);
2369 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2370 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2372 emith_move_r_r(arg0, CONTEXT_REG);
2373 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2375 emith_lsl(arg0, arg0, 2);
2376 emith_ctx_read(arg1, SHR_VBR * 4);
2377 emith_add_r_r(arg0, arg1);
2378 emit_memhandler_read(2);
2379 emith_ctx_write(arg0, SHR_PC * 4);
2381 emith_add_r_imm(xSP, 4); // fix stack
2383 emith_jump(sh2_drc_dispatcher);
2384 rcache_invalidate();
2386 // sh2_drc_entry(SH2 *sh2)
2387 sh2_drc_entry = (void *)tcache_ptr;
2388 emith_sh2_drc_entry();
2389 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2390 emit_do_static_regs(0, arg2);
2391 emith_call(sh2_drc_test_irq);
2392 emith_jump(sh2_drc_dispatcher);
2394 // write-caused irq detection
2395 sh2_drc_write_end = tcache_ptr;
2396 emith_tst_r_r(arg0, arg0);
2397 EMITH_SJMP_START(DCOND_NE);
2398 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); // return
2399 EMITH_SJMP_END(DCOND_NE);
2400 // since PC is up to date, jump to it's block instead of returning
2401 emith_call(sh2_drc_test_irq);
2402 emith_jump_ctx(offsetof(SH2, drc_tmp));
2404 // write-caused irq detection for writes in delay slot
2405 sh2_drc_write_slot_end = tcache_ptr;
2406 emith_tst_r_r(arg0, arg0);
2407 EMITH_SJMP_START(DCOND_NE);
2408 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp));
2409 EMITH_SJMP_END(DCOND_NE);
2410 // just burn cycles to get back to dispatcher after branch is handled
2411 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2412 emith_ctx_write(sr, offsetof(SH2, irq_cycles));
2413 emith_clear_msb(sr, sr, 20); // clear cycles
2415 emith_jump_ctx(offsetof(SH2, drc_tmp));
2417 // sh2_drc_write8(u32 a, u32 d)
2418 sh2_drc_write8 = (void *)tcache_ptr;
2419 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2420 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2421 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2423 // sh2_drc_write16(u32 a, u32 d)
2424 sh2_drc_write16 = (void *)tcache_ptr;
2425 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2426 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2427 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2429 // sh2_drc_write8_slot(u32 a, u32 d)
2430 sh2_drc_write8_slot = (void *)tcache_ptr;
2431 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2432 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2433 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2435 // sh2_drc_write16_slot(u32 a, u32 d)
2436 sh2_drc_write16_slot = (void *)tcache_ptr;
2437 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2438 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2439 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2441 rcache_invalidate();
2443 host_dasm_new_symbol(sh2_drc_entry);
2444 host_dasm_new_symbol(sh2_drc_dispatcher);
2445 host_dasm_new_symbol(sh2_drc_exit);
2446 host_dasm_new_symbol(sh2_drc_test_irq);
2447 host_dasm_new_symbol(sh2_drc_write_end);
2448 host_dasm_new_symbol(sh2_drc_write_slot_end);
2449 host_dasm_new_symbol(sh2_drc_write8);
2450 host_dasm_new_symbol(sh2_drc_write8_slot);
2451 host_dasm_new_symbol(sh2_drc_write16);
2452 host_dasm_new_symbol(sh2_drc_write16_slot);
2456 static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a)
2459 block_desc *bd = btab + id;
2461 // FIXME: skip subblocks; do both directions
2462 // FIXME: collect all branches
2463 dbg(1, " killing block %08x", bd->addr);
2464 bd->addr = bd->end_addr = 0;
2466 while (p > drcblk && (p[-1] >> 1) == id)
2469 // check for possible overlay block
2470 if (p > 0 && p[-1] != 0) {
2471 bd = btab + (p[-1] >> 1);
2472 if (bd->addr <= a && a < bd->end_addr)
2473 sh2_smc_rm_block(drcblk, p - 1, btab, a);
2479 while ((*p >> 1) == id);
2482 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
2484 u16 *drcblk = Pico32xMem->drcblk_ram;
2485 u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT);
2487 dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
2488 sh2_smc_rm_block(drcblk, p, block_tables[0], a);
2491 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
2493 u16 *drcblk = Pico32xMem->drcblk_da[cpuid];
2494 u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT);
2496 dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
2497 sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a);
2500 void sh2_execute(SH2 *sh2c, int cycles)
2505 sh2c->cycles_aim += cycles;
2506 cycles = sh2c->cycles_aim - sh2c->cycles_done;
2508 // cycles are kept in SHR_SR unused bits (upper 20)
2509 // bit19 contains T saved for delay slot
2510 // others are usual SH2 flags
2512 sh2c->sr |= cycles << 12;
2513 sh2_drc_entry(sh2c);
2516 ret_cycles = (signed int)sh2c->sr >> 12;
2518 printf("warning: drc returned with cycles: %d\n", ret_cycles);
2520 sh2c->cycles_done += cycles - ret_cycles;
2524 static void block_stats(void)
2526 int c, b, i, total = 0;
2528 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
2529 for (i = 0; i < block_counts[b]; i++)
2530 if (block_tables[b][i].addr != 0)
2531 total += block_tables[b][i].refcount;
2533 for (c = 0; c < 10; c++) {
2534 block_desc *blk, *maxb = NULL;
2536 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
2537 for (i = 0; i < block_counts[b]; i++) {
2538 blk = &block_tables[b][i];
2539 if (blk->addr != 0 && blk->refcount > max) {
2540 max = blk->refcount;
2547 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
2548 (double)maxb->refcount / total * 100.0);
2552 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
2553 for (i = 0; i < block_counts[b]; i++)
2554 block_tables[b][i].refcount = 0;
2557 #define block_stats()
2560 void sh2_drc_flush_all(void)
2568 int sh2_drc_init(SH2 *sh2)
2572 if (block_tables[0] == NULL)
2574 for (i = 0; i < TCACHE_BUFFERS; i++) {
2575 block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0]));
2576 if (block_tables[i] == NULL)
2578 // max 2 block links (exits) per block
2579 block_links[i] = calloc(block_max_counts[i] * 2, sizeof(*block_links[0]));
2580 if (block_links[i] == NULL)
2583 memset(block_counts, 0, sizeof(block_counts));
2584 memset(block_link_counts, 0, sizeof(block_link_counts));
2587 tcache_ptr = tcache;
2588 sh2_generate_utils();
2590 cache_flush_d_inval_i(tcache, tcache_ptr);
2593 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
2594 for (i = 1; i < ARRAY_SIZE(tcache_bases); i++)
2595 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
2598 PicoOpt |= POPT_DIS_VDP_FIFO;
2601 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
2602 tcache_dsm_ptrs[i] = tcache_bases[i];
2604 tcache_dsm_ptrs[0] = tcache;
2608 hash_collisions = 0;
2612 if (hash_table == NULL) {
2613 hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES);
2614 if (hash_table == NULL)
2621 sh2_drc_finish(sh2);
2625 void sh2_drc_finish(SH2 *sh2)
2629 if (block_tables[0] != NULL) {
2632 for (i = 0; i < TCACHE_BUFFERS; i++) {
2634 printf("~~~ tcache %d\n", i);
2635 tcache_dsm_ptrs[i] = tcache_bases[i];
2636 tcache_ptr = tcache_ptrs[i];
2640 if (block_tables[i] != NULL)
2641 free(block_tables[i]);
2642 block_tables[i] = NULL;
2643 if (block_links[i] == NULL)
2644 free(block_links[i]);
2645 block_links[i] = NULL;
2651 if (hash_table != NULL) {