5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * - tcache, block descriptor, link buffer overflows result in sh2_translate()
10 * failure, followed by full tcache invalidation for that region
11 * - jumps between blocks are tracked for SMC handling (in block_links[]),
12 * except jumps between different tcaches
13 * - non-main block entries are called subblocks, as they have same tracking
14 * structures that main blocks have.
17 * - static register allocation
18 * - remaining register caching and tracking in temporaries
19 * - block-local branch linking
20 * - block linking (except between tcaches)
21 * - some constant propagation
24 * - better constant propagation
33 #include "../../pico/pico_int.h"
36 #include "../drc/cmn.h"
40 #define PROPAGATE_CONSTANTS 1
41 #define LINK_BRANCHES 1
44 #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
46 // max literal offset from the block end
47 #define MAX_LITERAL_OFFSET 32*2
48 #define MAX_LITERALS (BLOCK_CYCLE_LIMIT / 4)
49 #define MAX_LOCAL_BRANCHES 32
52 #define FETCH_OP(pc) \
56 ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
70 #define dbg(l,...) { \
71 if ((l) & DRC_DEBUG) \
72 elprintf(EL_STATUS, ##__VA_ARGS__); \
75 #include "mame/sh2dasm.h"
76 #include <platform/libpicofe/linux/host_dasm.h>
77 static int insns_compiled, hash_collisions, host_insn_count;
86 static u8 *tcache_dsm_ptrs[3];
87 static char sh2dasm_buff[64];
88 #define do_host_disasm(tcid) \
89 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
90 tcache_dsm_ptrs[tcid] = tcache_ptr
92 #define do_host_disasm(x)
95 #if (DRC_DEBUG & 8) || defined(PDB)
96 static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
99 dbg(8, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
100 sh2->pc, block, (signed int)sr >> 12);
101 pdb_step(sh2, sh2->pc);
108 #define TCACHE_BUFFERS 3
110 // we have 3 translation cache buffers, split from one drc/cmn buffer.
111 // BIOS shares tcache with data array because it's only used for init
112 // and can be discarded early
113 // XXX: need to tune sizes
114 static const int tcache_sizes[TCACHE_BUFFERS] = {
115 DRC_TCACHE_SIZE * 6 / 8, // ROM (rarely used), DRAM
116 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
117 DRC_TCACHE_SIZE / 8, // ... slave
120 static u8 *tcache_bases[TCACHE_BUFFERS];
121 static u8 *tcache_ptrs[TCACHE_BUFFERS];
123 // ptr for code emiters
124 static u8 *tcache_ptr;
126 typedef struct block_desc_ {
127 u32 addr; // SH2 PC address
128 u32 end_addr; // address after last op
129 void *tcache_ptr; // translated block for above PC
130 struct block_desc_ *next; // next block with the same PC hash
136 typedef struct block_link_ {
138 void *jump; // insn address
139 // struct block_link_ *next;
142 static const int block_max_counts[TCACHE_BUFFERS] = {
147 static block_desc *block_tables[TCACHE_BUFFERS];
148 static block_link *block_links[TCACHE_BUFFERS];
149 static int block_counts[TCACHE_BUFFERS];
150 static int block_link_counts[TCACHE_BUFFERS];
152 // used for invalidation
153 static const int ram_sizes[TCACHE_BUFFERS] = {
158 #define ADDR_TO_BLOCK_PAGE 0x100
162 struct block_list *next;
165 // array of pointers to block_lists for RAM and 2 data arrays
166 // each array has len: sizeof(mem) / ADDR_TO_BLOCK_PAGE
167 static struct block_list **inval_lookup[TCACHE_BUFFERS];
169 // host register tracking
172 HR_CACHED, // 'val' has sh2_reg_e
173 // HR_CONST, // 'val' has a constant
174 HR_TEMP, // reg used for temp storage
178 HRF_DIRTY = 1 << 0, // reg has "dirty" value to be written to ctx
179 HRF_LOCKED = 1 << 1, // HR_CACHED can't be evicted
183 u32 hreg:5; // "host" reg
184 u32 greg:5; // "guest" reg
187 u32 stamp:16; // kind of a timestamp
190 // note: reg_temp[] must have at least the amount of
191 // registers used by handlers in worst case (currently 4)
193 #include "../drc/emit_arm.c"
195 static const int reg_map_g2h[] = {
199 -1, -1, -1, 9, // r12 .. sp
200 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
201 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
204 static temp_reg_t reg_temp[] = {
213 #elif defined(__i386__)
214 #include "../drc/emit_x86.c"
216 static const int reg_map_g2h[] = {
225 // ax, cx, dx are usually temporaries by convention
226 static temp_reg_t reg_temp[] = {
234 #error unsupported arch
242 #define T_save 0x00000800
249 #define MAX_HASH_ENTRIES 1024
250 #define HASH_MASK (MAX_HASH_ENTRIES - 1)
251 static void **hash_table;
253 #define HASH_FUNC(hash_tab, addr) \
254 ((block_desc **)(hash_tab))[(addr) & HASH_MASK]
256 static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
257 static void (*sh2_drc_dispatcher)(void);
258 static void (*sh2_drc_exit)(void);
259 static void (*sh2_drc_test_irq)(void);
261 static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
262 static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
263 static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
264 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
265 static void REGPARM(2) (*sh2_drc_write8_slot)(u32 a, u32 d);
266 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
267 static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d);
268 static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
270 // address space stuff
271 static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
275 if ((a & ~0x7ff) == 0) {
277 poffs = offsetof(SH2, p_bios);
280 else if ((a & 0xfffff000) == 0xc0000000) {
282 poffs = offsetof(SH2, p_da);
285 else if ((a & 0xc6000000) == 0x06000000) {
287 poffs = offsetof(SH2, p_sdram);
290 else if ((a & 0xc6000000) == 0x02000000) {
292 poffs = offsetof(SH2, p_rom);
299 static block_desc *dr_get_bd(u32 pc, int is_slave, int *tcache_id)
303 // we have full block id tables for data_array and RAM
304 // BIOS goes to data_array table too
305 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0) {
306 int blkid = Pico32xMem->drcblk_da[is_slave][(pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
307 *tcache_id = 1 + is_slave;
309 return &block_tables[*tcache_id][blkid >> 1];
312 else if ((pc & 0xc6000000) == 0x06000000) {
313 int blkid = Pico32xMem->drcblk_ram[(pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
315 return &block_tables[0][blkid >> 1];
318 else if ((pc & 0xc6000000) == 0x02000000) {
319 block_desc *bd = HASH_FUNC(hash_table, pc);
321 for (; bd != NULL; bd = bd->next)
329 // ---------------------------------------------------------------
332 static void add_to_block_list(struct block_list **blist, block_desc *block)
334 struct block_list *added = malloc(sizeof(*added));
336 elprintf(EL_ANOMALY, "drc OOM (1)");
339 added->block = block;
340 added->next = *blist;
344 static void rm_from_block_list(struct block_list **blist, block_desc *block)
346 struct block_list *prev = NULL, *current = *blist;
347 for (; current != NULL; prev = current, current = current->next) {
348 if (current->block == block) {
350 *blist = current->next;
352 prev->next = current->next;
357 dbg(1, "can't rm block %p (%08x-%08x)",
358 block, block->addr, block->end_addr);
361 static void rm_block_list(struct block_list **blist)
363 struct block_list *tmp, *current = *blist;
364 while (current != NULL) {
366 current = current->next;
372 static void REGPARM(1) flush_tcache(int tcid)
376 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
377 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
378 block_counts[tcid], block_max_counts[tcid]);
380 block_counts[tcid] = 0;
381 block_link_counts[tcid] = 0;
382 tcache_ptrs[tcid] = tcache_bases[tcid];
383 if (tcid == 0) { // ROM, RAM
384 memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES);
385 memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram));
388 memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0]));
390 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
393 for (i = 0; i < ram_sizes[tcid] / ADDR_TO_BLOCK_PAGE; i++)
394 rm_block_list(&inval_lookup[tcid][i]);
398 // add block links (tracked branches)
399 static int dr_add_block_link(u32 target_pc, void *jump, int tcache_id)
401 block_link *bl = block_links[tcache_id];
402 int cnt = block_link_counts[tcache_id];
404 if (cnt >= block_max_counts[tcache_id] * 2) {
405 dbg(1, "bl overflow for tcache %d\n", tcache_id);
409 bl[cnt].target_pc = target_pc;
411 block_link_counts[tcache_id]++;
417 static block_desc *dr_add_block(u32 addr, u32 end_addr, int is_slave, int *blk_id)
423 bd = dr_get_bd(addr, is_slave, &tcache_id);
425 dbg(2, "block override for %08x", addr);
426 bd->tcache_ptr = tcache_ptr;
427 bd->end_addr = end_addr;
428 *blk_id = bd - block_tables[tcache_id];
432 bcount = &block_counts[tcache_id];
433 if (*bcount >= block_max_counts[tcache_id]) {
434 dbg(1, "bd overflow for tcache %d", tcache_id);
438 (*bcount)++; // not using descriptor 0
440 bd = &block_tables[tcache_id][*bcount];
442 bd->end_addr = end_addr;
443 bd->tcache_ptr = tcache_ptr;
447 if ((addr & 0xc6000000) == 0x02000000) { // ROM
448 bd->next = HASH_FUNC(hash_table, addr);
449 HASH_FUNC(hash_table, addr) = bd;
451 if (bd->next != NULL) {
452 printf(" hash collision with %08x\n", bd->next->addr);
461 static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id)
463 block_desc *bd = NULL;
466 bd = dr_get_bd(pc, is_slave, tcache_id);
468 block = bd->tcache_ptr;
477 static void *dr_failure(void)
479 lprintf("recompilation failed\n");
483 static void *dr_prepare_ext_branch(u32 pc, SH2 *sh2, int tcache_id)
486 int target_tcache_id;
490 target = dr_lookup_block(pc, sh2->is_slave, &target_tcache_id);
491 if (target_tcache_id == tcache_id) {
492 // allow linking blocks only from local cache
493 ret = dr_add_block_link(pc, tcache_ptr, tcache_id);
497 if (target == NULL || target_tcache_id != tcache_id)
498 target = sh2_drc_dispatcher;
502 return sh2_drc_dispatcher;
506 static void dr_link_blocks(void *target, u32 pc, int tcache_id)
509 block_link *bl = block_links[tcache_id];
510 int cnt = block_link_counts[tcache_id];
513 for (i = 0; i < cnt; i++) {
514 if (bl[i].target_pc == pc) {
515 dbg(2, "- link from %p", bl[i].jump);
516 emith_jump_patch(bl[i].jump, target);
517 // XXX: sync ARM caches (old jump should be fine)?
523 #define ADD_TO_ARRAY(array, count, item, failcode) \
524 array[count++] = item; \
525 if (count >= ARRAY_SIZE(array)) { \
526 dbg(1, "warning: " #array " overflow"); \
530 static int find_in_array(u32 *array, size_t size, u32 what)
533 for (i = 0; i < size; i++)
534 if (what == array[i])
540 // ---------------------------------------------------------------
542 // register cache / constant propagation stuff
549 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking);
551 // guest regs with constants
552 static u32 dr_gcregs[24];
553 // a mask of constant/dirty regs
554 static u32 dr_gcregs_mask;
555 static u32 dr_gcregs_dirty;
557 #if PROPAGATE_CONSTANTS
558 static void gconst_new(sh2_reg_e r, u32 val)
562 dr_gcregs_mask |= 1 << r;
563 dr_gcregs_dirty |= 1 << r;
566 // throw away old r that we might have cached
567 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
568 if ((reg_temp[i].type == HR_CACHED) &&
569 reg_temp[i].greg == r) {
570 reg_temp[i].type = HR_FREE;
571 reg_temp[i].flags = 0;
577 static int gconst_get(sh2_reg_e r, u32 *val)
579 if (dr_gcregs_mask & (1 << r)) {
586 static int gconst_check(sh2_reg_e r)
588 if ((dr_gcregs_mask | dr_gcregs_dirty) & (1 << r))
593 // update hr if dirty, else do nothing
594 static int gconst_try_read(int hr, sh2_reg_e r)
596 if (dr_gcregs_dirty & (1 << r)) {
597 emith_move_r_imm(hr, dr_gcregs[r]);
598 dr_gcregs_dirty &= ~(1 << r);
604 static void gconst_check_evict(sh2_reg_e r)
606 if (dr_gcregs_mask & (1 << r))
607 // no longer cached in reg, make dirty again
608 dr_gcregs_dirty |= 1 << r;
611 static void gconst_kill(sh2_reg_e r)
613 dr_gcregs_mask &= ~(1 << r);
614 dr_gcregs_dirty &= ~(1 << r);
617 static void gconst_clean(void)
621 for (i = 0; i < ARRAY_SIZE(dr_gcregs); i++)
622 if (dr_gcregs_dirty & (1 << i)) {
623 // using RC_GR_READ here: it will call gconst_try_read,
624 // cache the reg and mark it dirty.
625 rcache_get_reg_(i, RC_GR_READ, 0);
629 static void gconst_invalidate(void)
631 dr_gcregs_mask = dr_gcregs_dirty = 0;
634 static u16 rcache_counter;
636 static temp_reg_t *rcache_evict(void)
638 // evict reg with oldest stamp
640 u16 min_stamp = (u16)-1;
642 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
643 if (reg_temp[i].type == HR_CACHED && !(reg_temp[i].flags & HRF_LOCKED) &&
644 reg_temp[i].stamp <= min_stamp) {
645 min_stamp = reg_temp[i].stamp;
651 printf("no registers to evict, aborting\n");
656 if (reg_temp[i].type == HR_CACHED) {
657 if (reg_temp[i].flags & HRF_DIRTY)
659 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
660 gconst_check_evict(reg_temp[i].greg);
663 reg_temp[i].type = HR_FREE;
664 reg_temp[i].flags = 0;
668 static int get_reg_static(sh2_reg_e r, rc_gr_mode mode)
670 int i = reg_map_g2h[r];
672 if (mode != RC_GR_WRITE)
673 gconst_try_read(i, r);
678 // note: must not be called when doing conditional code
679 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking)
684 // maybe statically mapped?
685 ret = get_reg_static(r, mode);
691 // maybe already cached?
692 // if so, prefer against gconst (they must be in sync)
693 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
694 if (reg_temp[i].type == HR_CACHED && reg_temp[i].greg == r) {
695 reg_temp[i].stamp = rcache_counter;
696 if (mode != RC_GR_READ)
697 reg_temp[i].flags |= HRF_DIRTY;
698 ret = reg_temp[i].hreg;
704 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
705 if (reg_temp[i].type == HR_FREE) {
714 tr->type = HR_CACHED;
716 tr->flags |= HRF_LOCKED;
717 if (mode != RC_GR_READ)
718 tr->flags |= HRF_DIRTY;
720 tr->stamp = rcache_counter;
723 if (mode != RC_GR_WRITE) {
724 if (gconst_check(r)) {
725 if (gconst_try_read(ret, r))
726 tr->flags |= HRF_DIRTY;
729 emith_ctx_read(tr->hreg, r * 4);
733 if (mode != RC_GR_READ)
739 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
741 return rcache_get_reg_(r, mode, 1);
744 static int rcache_get_tmp(void)
749 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
750 if (reg_temp[i].type == HR_FREE) {
762 static int rcache_get_arg_id(int arg)
765 host_arg2reg(r, arg);
767 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
768 if (reg_temp[i].hreg == r)
771 if (i == ARRAY_SIZE(reg_temp)) // can't happen
774 if (reg_temp[i].type == HR_CACHED) {
776 if (reg_temp[i].flags & HRF_DIRTY)
777 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
778 gconst_check_evict(reg_temp[i].greg);
780 else if (reg_temp[i].type == HR_TEMP) {
781 printf("arg %d reg %d already used, aborting\n", arg, r);
785 reg_temp[i].type = HR_FREE;
786 reg_temp[i].flags = 0;
791 // get a reg to be used as function arg
792 static int rcache_get_tmp_arg(int arg)
794 int id = rcache_get_arg_id(arg);
795 reg_temp[id].type = HR_TEMP;
797 return reg_temp[id].hreg;
800 // same but caches a reg. RC_GR_READ only.
801 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
803 int i, srcr, dstr, dstid;
804 int dirty = 0, src_dirty = 0;
806 dstid = rcache_get_arg_id(arg);
807 dstr = reg_temp[dstid].hreg;
809 // maybe already statically mapped?
810 srcr = get_reg_static(r, RC_GR_READ);
814 // maybe already cached?
815 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
816 if ((reg_temp[i].type == HR_CACHED) &&
817 reg_temp[i].greg == r)
819 srcr = reg_temp[i].hreg;
820 if (reg_temp[i].flags & HRF_DIRTY)
828 if (gconst_check(r)) {
829 if (gconst_try_read(srcr, r))
833 emith_ctx_read(srcr, r * 4);
837 emith_move_r_r(dstr, srcr);
843 // must clean, callers might want to modify the arg before call
844 emith_ctx_write(dstr, r * 4);
847 reg_temp[dstid].flags |= HRF_DIRTY;
850 reg_temp[dstid].stamp = ++rcache_counter;
851 reg_temp[dstid].type = HR_CACHED;
852 reg_temp[dstid].greg = r;
853 reg_temp[dstid].flags |= HRF_LOCKED;
857 static void rcache_free_tmp(int hr)
860 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
861 if (reg_temp[i].hreg == hr)
864 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
865 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
869 reg_temp[i].type = HR_FREE;
870 reg_temp[i].flags = 0;
873 static void rcache_unlock(int hr)
876 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
877 if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr)
878 reg_temp[i].flags &= ~HRF_LOCKED;
881 static void rcache_unlock_all(void)
884 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
885 reg_temp[i].flags &= ~HRF_LOCKED;
888 static void rcache_clean(void)
893 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
894 if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) {
896 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
897 reg_temp[i].flags &= ~HRF_DIRTY;
901 static void rcache_invalidate(void)
904 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
905 reg_temp[i].type = HR_FREE;
906 reg_temp[i].flags = 0;
913 static void rcache_flush(void)
919 // ---------------------------------------------------------------
921 static int emit_get_rbase_and_offs(u32 a, u32 *offs)
927 poffs = dr_ctx_get_mem_ptr(a, &mask);
931 // XXX: could use some related reg
932 hr = rcache_get_tmp();
933 emith_ctx_read(hr, poffs);
934 emith_add_r_imm(hr, a & mask & ~0xff);
935 *offs = a & 0xff; // XXX: ARM oriented..
939 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
941 #if PROPAGATE_CONSTANTS
942 gconst_new(dst, imm);
944 int hr = rcache_get_reg(dst, RC_GR_WRITE);
945 emith_move_r_imm(hr, imm);
949 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
951 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
952 int hr_s = rcache_get_reg(src, RC_GR_READ);
954 emith_move_r_r(hr_d, hr_s);
957 // T must be clear, and comparison done just before this
958 static void emit_or_t_if_eq(int srr)
960 EMITH_SJMP_START(DCOND_NE);
961 emith_or_r_imm_c(DCOND_EQ, srr, T);
962 EMITH_SJMP_END(DCOND_NE);
965 // arguments must be ready
966 // reg cache must be clean before call
967 static int emit_memhandler_read_(int size, int ram_check)
970 host_arg2reg(arg0, 0);
974 // must writeback cycles for poll detection stuff
976 if (reg_map_g2h[SHR_SR] != -1)
977 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
979 arg1 = rcache_get_tmp_arg(1);
980 emith_move_r_r(arg1, CONTEXT_REG);
983 if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
984 int tmp = rcache_get_tmp();
985 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
986 emith_cmp_r_imm(tmp, 0x02000000);
989 EMITH_SJMP3_START(DCOND_NE);
990 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
991 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
992 EMITH_SJMP3_MID(DCOND_NE);
993 emith_call_cond(DCOND_NE, sh2_drc_read8);
997 EMITH_SJMP3_START(DCOND_NE);
998 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
999 EMITH_SJMP3_MID(DCOND_NE);
1000 emith_call_cond(DCOND_NE, sh2_drc_read16);
1004 EMITH_SJMP3_START(DCOND_NE);
1005 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1006 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
1007 EMITH_SJMP3_MID(DCOND_NE);
1008 emith_call_cond(DCOND_NE, sh2_drc_read32);
1018 emith_call(sh2_drc_read8);
1021 emith_call(sh2_drc_read16);
1024 emith_call(sh2_drc_read32);
1028 rcache_invalidate();
1030 if (reg_map_g2h[SHR_SR] != -1)
1031 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1033 // assuming arg0 and retval reg matches
1034 return rcache_get_tmp_arg(0);
1037 static int emit_memhandler_read(int size)
1039 return emit_memhandler_read_(size, 1);
1042 static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size)
1044 int hr, hr2, ram_check = 1;
1047 if (gconst_get(rs, &val)) {
1048 hr = emit_get_rbase_and_offs(val + offs, &offs2);
1050 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1053 emith_read8_r_r_offs(hr2, hr, offs2 ^ 1);
1054 emith_sext(hr2, hr2, 8);
1057 emith_read16_r_r_offs(hr2, hr, offs2);
1058 emith_sext(hr2, hr2, 16);
1061 emith_read_r_r_offs(hr2, hr, offs2);
1062 emith_ror(hr2, hr2, 16);
1065 rcache_free_tmp(hr);
1072 hr = rcache_get_reg_arg(0, rs);
1074 emith_add_r_imm(hr, offs);
1075 hr = emit_memhandler_read_(size, ram_check);
1076 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1078 emith_sext(hr2, hr, (size == 1) ? 16 : 8);
1080 emith_move_r_r(hr2, hr);
1081 rcache_free_tmp(hr);
1086 static void emit_memhandler_write(int size, u32 pc, int delay)
1089 host_arg2reg(ctxr, 2);
1090 if (reg_map_g2h[SHR_SR] != -1)
1091 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1095 // XXX: consider inlining sh2_drc_write8
1097 emith_call(sh2_drc_write8_slot);
1099 emit_move_r_imm32(SHR_PC, pc);
1101 emith_call(sh2_drc_write8);
1106 emith_call(sh2_drc_write16_slot);
1108 emit_move_r_imm32(SHR_PC, pc);
1110 emith_call(sh2_drc_write16);
1114 emith_move_r_r(ctxr, CONTEXT_REG);
1115 emith_call(sh2_drc_write32);
1119 if (reg_map_g2h[SHR_SR] != -1)
1120 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1121 rcache_invalidate();
1125 static int emit_indirect_indexed_read(int rx, int ry, int size)
1128 a0 = rcache_get_reg_arg(0, rx);
1129 t = rcache_get_reg(ry, RC_GR_READ);
1130 emith_add_r_r(a0, t);
1131 return emit_memhandler_read(size);
1135 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
1139 rcache_get_reg_arg(0, rn);
1140 tmp = emit_memhandler_read(size);
1141 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
1142 rcache_free_tmp(tmp);
1143 tmp = rcache_get_reg(rn, RC_GR_RMW);
1144 emith_add_r_imm(tmp, 1 << size);
1147 rcache_get_reg_arg(0, rm);
1148 *rmr = emit_memhandler_read(size);
1149 *rnr = rcache_get_tmp();
1150 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
1151 tmp = rcache_get_reg(rm, RC_GR_RMW);
1152 emith_add_r_imm(tmp, 1 << size);
1156 static void emit_do_static_regs(int is_write, int tmpr)
1160 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
1165 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
1166 if (reg_map_g2h[i + 1] != r + 1)
1172 // i, r point to last item
1174 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1176 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1179 emith_ctx_write(r, i * 4);
1181 emith_ctx_read(r, i * 4);
1186 static void emit_block_entry(void)
1190 host_arg2reg(arg0, 0);
1192 #if (DRC_DEBUG & 8) || defined(PDB)
1194 host_arg2reg(arg1, 1);
1195 host_arg2reg(arg2, 2);
1197 emit_do_static_regs(1, arg2);
1198 emith_move_r_r(arg1, CONTEXT_REG);
1199 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
1200 emith_call(sh2_drc_log_entry);
1201 rcache_invalidate();
1203 emith_tst_r_r(arg0, arg0);
1204 EMITH_SJMP_START(DCOND_EQ);
1205 emith_jump_reg_c(DCOND_NE, arg0);
1206 EMITH_SJMP_END(DCOND_EQ);
1209 #define DELAYED_OP \
1212 #define DELAY_SAVE_T(sr) { \
1213 emith_bic_r_imm(sr, T_save); \
1214 emith_tst_r_imm(sr, T); \
1215 EMITH_SJMP_START(DCOND_EQ); \
1216 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
1217 EMITH_SJMP_END(DCOND_EQ); \
1218 drcf.use_saved_t = 1; \
1221 #define FLUSH_CYCLES(sr) \
1223 emith_sub_r_imm(sr, cycles << 12); \
1227 #define CHECK_UNHANDLED_BITS(mask) { \
1228 if ((op & (mask)) != 0) \
1235 #define GET_Rm GET_Fx
1240 #define CHECK_FX_LT(n) \
1241 if (GET_Fx() >= n) \
1244 static void *dr_get_pc_base(u32 pc, int is_slave);
1246 static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
1248 // XXX: maybe use structs instead?
1249 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
1250 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
1251 int branch_target_blkid[MAX_LOCAL_BRANCHES];
1252 int branch_target_count = 0;
1253 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
1254 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
1255 int branch_patch_count = 0;
1256 u32 literal_addr[MAX_LITERALS];
1257 int literal_addr_count = 0;
1258 int pending_branch_cond = -1;
1259 int pending_branch_pc = 0;
1260 u8 op_flags[BLOCK_CYCLE_LIMIT];
1264 u32 use_saved_t:1; // delayed op modifies T
1267 // PC of current, first, last, last_target_blk SH2 insn
1268 u32 pc, base_pc, end_pc, out_pc;
1270 block_desc *this_block;
1281 // get base/validate PC
1282 dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave);
1283 if (dr_pc_base == (void *)-1) {
1284 printf("invalid PC, aborting: %08x\n", base_pc);
1285 // FIXME: be less destructive
1289 tcache_ptr = tcache_ptrs[tcache_id];
1291 // predict tcache overflow
1292 tmp = tcache_ptr - tcache_bases[tcache_id];
1293 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
1294 dbg(1, "tcache %d overflow", tcache_id);
1298 // 1st pass: scan forward for local branches
1299 scan_block(base_pc, sh2->is_slave, op_flags, &end_pc);
1301 this_block = dr_add_block(base_pc, end_pc + MAX_LITERAL_OFFSET, // XXX
1302 sh2->is_slave, &blkid_main);
1303 if (this_block == NULL)
1306 block_entry = tcache_ptr;
1307 dbg(2, "== %csh2 block #%d,%d %08x-%08x -> %p", sh2->is_slave ? 's' : 'm',
1308 tcache_id, blkid_main, base_pc, end_pc, block_entry);
1310 dr_link_blocks(tcache_ptr, base_pc, tcache_id);
1312 // collect branch_targets that don't land on delay slots
1313 for (pc = base_pc; pc <= end_pc; pc += 2) {
1314 if (!(OP_FLAGS(pc) & OF_TARGET))
1316 if (OP_FLAGS(pc) & OF_DELAY_OP) {
1317 OP_FLAGS(pc) &= ~OF_TARGET;
1320 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
1323 if (branch_target_count > 0) {
1324 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
1325 memset(branch_target_blkid, 0, sizeof(branch_target_blkid[0]) * branch_target_count);
1328 // -------------------------------------------------
1329 // 2nd pass: actual compilation
1332 for (cycles = 0; pc <= end_pc || drcf.delayed_op; )
1336 if (drcf.delayed_op > 0)
1341 if ((OP_FLAGS(pc) & OF_TARGET) || pc == base_pc)
1343 i = find_in_array(branch_target_pc, branch_target_count, pc);
1346 /* make "subblock" - just a mid-block entry */
1347 block_desc *subblock;
1349 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1351 // decide if to flush rcache
1352 if ((op & 0xf0ff) == 0x4010 && FETCH_OP(pc + 2) == 0x8bfd) // DT; BF #-2
1356 do_host_disasm(tcache_id);
1358 dbg(2, "-- %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
1359 tcache_id, branch_target_blkid[i], pc, tcache_ptr);
1361 subblock = dr_add_block(pc, end_pc + MAX_LITERAL_OFFSET, // XXX
1362 sh2->is_slave, &branch_target_blkid[i]);
1363 if (subblock == NULL)
1366 // since we made a block entry, link any other blocks that jump to current pc
1367 dr_link_blocks(tcache_ptr, pc, tcache_id);
1370 branch_target_ptr[i] = tcache_ptr;
1373 emit_move_r_imm32(SHR_PC, pc);
1377 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1378 emith_cmp_r_imm(sr, 0);
1379 emith_jump_cond(DCOND_LE, sh2_drc_exit);
1380 do_host_disasm(tcache_id);
1381 rcache_unlock_all();
1388 DasmSH2(sh2dasm_buff, pc, op);
1389 printf("%08x %04x %s\n", pc, op, sh2dasm_buff);
1392 //if (out_pc != 0 && out_pc != (u32)-1)
1393 // emit_move_r_imm32(SHR_PC, out_pc);
1395 if (!drcf.delayed_op) {
1396 emit_move_r_imm32(SHR_PC, pc);
1397 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1399 // rcache_clean(); // FIXME
1401 emit_do_static_regs(1, 0);
1402 emith_pass_arg_r(0, CONTEXT_REG);
1403 emith_call(do_sh2_cmp);
1415 switch ((op >> 12) & 0x0f)
1417 /////////////////////////////////////////////
1422 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1425 case 0: // STC SR,Rn 0000nnnn00000010
1428 case 1: // STC GBR,Rn 0000nnnn00010010
1431 case 2: // STC VBR,Rn 0000nnnn00100010
1437 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
1438 emith_move_r_r(tmp, tmp3);
1440 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
1443 CHECK_UNHANDLED_BITS(0xd0);
1444 // BRAF Rm 0000mmmm00100011
1445 // BSRF Rm 0000mmmm00000011
1447 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1448 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1449 emith_move_r_r(tmp, tmp2);
1451 emith_add_r_imm(tmp, pc + 2);
1453 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
1454 emith_move_r_imm(tmp3, pc + 2);
1455 emith_add_r_r(tmp, tmp3);
1460 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
1461 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
1462 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
1464 tmp = rcache_get_reg_arg(1, GET_Rm());
1465 tmp2 = rcache_get_reg_arg(0, SHR_R0);
1466 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1467 emith_add_r_r(tmp2, tmp3);
1468 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1471 // MUL.L Rm,Rn 0000nnnnmmmm0111
1472 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1473 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1474 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1475 emith_mul(tmp3, tmp2, tmp);
1479 CHECK_UNHANDLED_BITS(0xf00);
1482 case 0: // CLRT 0000000000001000
1483 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1484 if (drcf.delayed_op)
1486 emith_bic_r_imm(sr, T);
1488 case 1: // SETT 0000000000011000
1489 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1490 if (drcf.delayed_op)
1492 emith_or_r_imm(sr, T);
1494 case 2: // CLRMAC 0000000000101000
1495 emit_move_r_imm32(SHR_MACL, 0);
1496 emit_move_r_imm32(SHR_MACH, 0);
1505 case 0: // NOP 0000000000001001
1506 CHECK_UNHANDLED_BITS(0xf00);
1508 case 1: // DIV0U 0000000000011001
1509 CHECK_UNHANDLED_BITS(0xf00);
1510 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1511 if (drcf.delayed_op)
1513 emith_bic_r_imm(sr, M|Q|T);
1515 case 2: // MOVT Rn 0000nnnn00101001
1516 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1517 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1518 emith_clear_msb(tmp2, sr, 31);
1525 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1528 case 0: // STS MACH,Rn 0000nnnn00001010
1531 case 1: // STS MACL,Rn 0000nnnn00011010
1534 case 2: // STS PR,Rn 0000nnnn00101010
1540 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1541 emith_move_r_r(tmp, tmp2);
1544 CHECK_UNHANDLED_BITS(0xf00);
1547 case 0: // RTS 0000000000001011
1549 emit_move_r_r(SHR_PC, SHR_PR);
1553 case 1: // SLEEP 0000000000011011
1554 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
1555 emith_clear_msb(tmp, tmp, 20); // clear cycles
1556 out_pc = out_pc - 2;
1559 case 2: // RTE 0000000000101011
1562 emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2);
1564 tmp = rcache_get_reg_arg(0, SHR_SP);
1565 emith_add_r_imm(tmp, 4);
1566 tmp = emit_memhandler_read(2);
1567 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1568 emith_write_sr(sr, tmp);
1569 rcache_free_tmp(tmp);
1570 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1571 emith_add_r_imm(tmp, 4*2);
1580 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1581 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1582 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1583 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1584 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1585 if ((op & 3) != 2) {
1586 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1588 emith_move_r_r(tmp2, tmp);
1589 rcache_free_tmp(tmp);
1591 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1592 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1593 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1594 /* MS 16 MAC bits unused if saturated */
1595 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1596 emith_tst_r_imm(sr, S);
1597 EMITH_SJMP_START(DCOND_EQ);
1598 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1599 EMITH_SJMP_END(DCOND_EQ);
1601 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1602 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1603 rcache_free_tmp(tmp2);
1604 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1605 emith_tst_r_imm(sr, S);
1607 EMITH_JMP_START(DCOND_EQ);
1608 emith_asr(tmp, tmp4, 15);
1609 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1610 EMITH_SJMP_START(DCOND_GE);
1611 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1612 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1613 EMITH_SJMP_END(DCOND_GE);
1614 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1615 EMITH_SJMP_START(DCOND_LE);
1616 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1617 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1618 EMITH_SJMP_END(DCOND_LE);
1619 EMITH_JMP_END(DCOND_EQ);
1621 rcache_free_tmp(tmp);
1627 /////////////////////////////////////////////
1629 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1631 tmp = rcache_get_reg_arg(0, GET_Rn());
1632 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1634 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1635 emit_memhandler_write(2, pc, drcf.delayed_op);
1641 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1642 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1643 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1645 rcache_get_reg_arg(0, GET_Rn());
1646 rcache_get_reg_arg(1, GET_Rm());
1647 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1649 case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
1650 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
1651 case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110
1652 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1653 emith_sub_r_imm(tmp, (1 << (op & 3)));
1655 rcache_get_reg_arg(0, GET_Rn());
1656 rcache_get_reg_arg(1, GET_Rm());
1657 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1659 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1660 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1661 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1662 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1663 if (drcf.delayed_op)
1665 emith_bic_r_imm(sr, M|Q|T);
1666 emith_tst_r_imm(tmp2, (1<<31));
1667 EMITH_SJMP_START(DCOND_EQ);
1668 emith_or_r_imm_c(DCOND_NE, sr, Q);
1669 EMITH_SJMP_END(DCOND_EQ);
1670 emith_tst_r_imm(tmp3, (1<<31));
1671 EMITH_SJMP_START(DCOND_EQ);
1672 emith_or_r_imm_c(DCOND_NE, sr, M);
1673 EMITH_SJMP_END(DCOND_EQ);
1674 emith_teq_r_r(tmp2, tmp3);
1675 EMITH_SJMP_START(DCOND_PL);
1676 emith_or_r_imm_c(DCOND_MI, sr, T);
1677 EMITH_SJMP_END(DCOND_PL);
1679 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1680 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1681 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1682 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1683 if (drcf.delayed_op)
1685 emith_bic_r_imm(sr, T);
1686 emith_tst_r_r(tmp2, tmp3);
1687 emit_or_t_if_eq(sr);
1689 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1690 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1691 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1692 emith_and_r_r(tmp, tmp2);
1694 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1695 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1696 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1697 emith_eor_r_r(tmp, tmp2);
1699 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1700 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1701 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1702 emith_or_r_r(tmp, tmp2);
1704 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1705 tmp = rcache_get_tmp();
1706 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1707 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1708 emith_eor_r_r_r(tmp, tmp2, tmp3);
1709 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1710 if (drcf.delayed_op)
1712 emith_bic_r_imm(sr, T);
1713 emith_tst_r_imm(tmp, 0x000000ff);
1714 emit_or_t_if_eq(tmp);
1715 emith_tst_r_imm(tmp, 0x0000ff00);
1716 emit_or_t_if_eq(tmp);
1717 emith_tst_r_imm(tmp, 0x00ff0000);
1718 emit_or_t_if_eq(tmp);
1719 emith_tst_r_imm(tmp, 0xff000000);
1720 emit_or_t_if_eq(tmp);
1721 rcache_free_tmp(tmp);
1723 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1724 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1725 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1726 emith_lsr(tmp, tmp, 16);
1727 emith_or_r_r_lsl(tmp, tmp2, 16);
1729 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1730 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1731 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1732 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1734 emith_sext(tmp, tmp2, 16);
1736 emith_clear_msb(tmp, tmp2, 16);
1737 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1738 tmp2 = rcache_get_tmp();
1740 emith_sext(tmp2, tmp3, 16);
1742 emith_clear_msb(tmp2, tmp3, 16);
1743 emith_mul(tmp, tmp, tmp2);
1744 rcache_free_tmp(tmp2);
1749 /////////////////////////////////////////////
1753 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
1754 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
1755 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
1756 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
1757 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
1758 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1759 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1760 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1761 if (drcf.delayed_op)
1763 emith_bic_r_imm(sr, T);
1764 emith_cmp_r_r(tmp2, tmp3);
1767 case 0x00: // CMP/EQ
1768 emit_or_t_if_eq(sr);
1770 case 0x02: // CMP/HS
1771 EMITH_SJMP_START(DCOND_LO);
1772 emith_or_r_imm_c(DCOND_HS, sr, T);
1773 EMITH_SJMP_END(DCOND_LO);
1775 case 0x03: // CMP/GE
1776 EMITH_SJMP_START(DCOND_LT);
1777 emith_or_r_imm_c(DCOND_GE, sr, T);
1778 EMITH_SJMP_END(DCOND_LT);
1780 case 0x06: // CMP/HI
1781 EMITH_SJMP_START(DCOND_LS);
1782 emith_or_r_imm_c(DCOND_HI, sr, T);
1783 EMITH_SJMP_END(DCOND_LS);
1785 case 0x07: // CMP/GT
1786 EMITH_SJMP_START(DCOND_LE);
1787 emith_or_r_imm_c(DCOND_GT, sr, T);
1788 EMITH_SJMP_END(DCOND_LE);
1792 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
1793 // Q1 = carry(Rn = (Rn << 1) | T)
1795 // Q2 = carry(Rn += Rm)
1797 // Q2 = carry(Rn -= Rm)
1799 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
1800 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1801 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1802 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1803 if (drcf.delayed_op)
1805 emith_tpop_carry(sr, 0);
1806 emith_adcf_r_r(tmp2, tmp2);
1807 emith_tpush_carry(sr, 0); // keep Q1 in T for now
1808 tmp4 = rcache_get_tmp();
1809 emith_and_r_r_imm(tmp4, sr, M);
1810 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
1811 rcache_free_tmp(tmp4);
1812 // add or sub, invert T if carry to get Q1 ^ Q2
1813 // in: (Q ^ M) passed in Q, Q1 in T
1814 emith_sh2_div1_step(tmp2, tmp3, sr);
1815 emith_bic_r_imm(sr, Q);
1816 emith_tst_r_imm(sr, M);
1817 EMITH_SJMP_START(DCOND_EQ);
1818 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
1819 EMITH_SJMP_END(DCOND_EQ);
1820 emith_tst_r_imm(sr, T);
1821 EMITH_SJMP_START(DCOND_EQ);
1822 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
1823 EMITH_SJMP_END(DCOND_EQ);
1824 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
1826 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
1827 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1828 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1829 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1830 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1831 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
1834 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
1835 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
1836 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1837 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1839 emith_add_r_r(tmp, tmp2);
1841 emith_sub_r_r(tmp, tmp2);
1843 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
1844 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
1845 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1846 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1847 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1848 if (drcf.delayed_op)
1850 if (op & 4) { // adc
1851 emith_tpop_carry(sr, 0);
1852 emith_adcf_r_r(tmp, tmp2);
1853 emith_tpush_carry(sr, 0);
1855 emith_tpop_carry(sr, 1);
1856 emith_sbcf_r_r(tmp, tmp2);
1857 emith_tpush_carry(sr, 1);
1860 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
1861 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
1862 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1863 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1864 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1865 if (drcf.delayed_op)
1867 emith_bic_r_imm(sr, T);
1869 emith_addf_r_r(tmp, tmp2);
1871 emith_subf_r_r(tmp, tmp2);
1872 EMITH_SJMP_START(DCOND_VC);
1873 emith_or_r_imm_c(DCOND_VS, sr, T);
1874 EMITH_SJMP_END(DCOND_VC);
1876 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
1877 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1878 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1879 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1880 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1881 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
1887 /////////////////////////////////////////////
1894 case 0: // SHLL Rn 0100nnnn00000000
1895 case 2: // SHAL Rn 0100nnnn00100000
1896 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1897 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1898 if (drcf.delayed_op)
1900 emith_tpop_carry(sr, 0); // dummy
1901 emith_lslf(tmp, tmp, 1);
1902 emith_tpush_carry(sr, 0);
1904 case 1: // DT Rn 0100nnnn00010000
1905 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1906 if (drcf.delayed_op)
1909 if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
1910 if (gconst_get(GET_Rn(), &tmp)) {
1911 // XXX: limit burned cycles
1912 emit_move_r_imm32(GET_Rn(), 0);
1913 emith_or_r_imm(sr, T);
1914 cycles += tmp * 4 + 1; // +1 syncs with noconst version, not sure why
1918 emith_sh2_dtbf_loop();
1922 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1923 emith_bic_r_imm(sr, T);
1924 emith_subf_r_imm(tmp, 1);
1925 emit_or_t_if_eq(sr);
1932 case 0: // SHLR Rn 0100nnnn00000001
1933 case 2: // SHAR Rn 0100nnnn00100001
1934 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1935 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1936 if (drcf.delayed_op)
1938 emith_tpop_carry(sr, 0); // dummy
1940 emith_asrf(tmp, tmp, 1);
1942 emith_lsrf(tmp, tmp, 1);
1943 emith_tpush_carry(sr, 0);
1945 case 1: // CMP/PZ Rn 0100nnnn00010001
1946 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1947 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1948 if (drcf.delayed_op)
1950 emith_bic_r_imm(sr, T);
1951 emith_cmp_r_imm(tmp, 0);
1952 EMITH_SJMP_START(DCOND_LT);
1953 emith_or_r_imm_c(DCOND_GE, sr, T);
1954 EMITH_SJMP_END(DCOND_LT);
1962 case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
1965 case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
1968 case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
1971 case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
1975 case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
1979 case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
1986 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1987 emith_sub_r_imm(tmp2, 4);
1989 rcache_get_reg_arg(0, GET_Rn());
1990 tmp3 = rcache_get_reg_arg(1, tmp);
1992 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
1993 emit_memhandler_write(2, pc, drcf.delayed_op);
1999 case 0x04: // ROTL Rn 0100nnnn00000100
2000 case 0x05: // ROTR Rn 0100nnnn00000101
2001 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2002 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2003 if (drcf.delayed_op)
2005 emith_tpop_carry(sr, 0); // dummy
2007 emith_rorf(tmp, tmp, 1);
2009 emith_rolf(tmp, tmp, 1);
2010 emith_tpush_carry(sr, 0);
2012 case 0x24: // ROTCL Rn 0100nnnn00100100
2013 case 0x25: // ROTCR Rn 0100nnnn00100101
2014 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2015 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2016 if (drcf.delayed_op)
2018 emith_tpop_carry(sr, 0);
2023 emith_tpush_carry(sr, 0);
2025 case 0x15: // CMP/PL Rn 0100nnnn00010101
2026 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2027 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2028 if (drcf.delayed_op)
2030 emith_bic_r_imm(sr, T);
2031 emith_cmp_r_imm(tmp, 0);
2032 EMITH_SJMP_START(DCOND_LE);
2033 emith_or_r_imm_c(DCOND_GT, sr, T);
2034 EMITH_SJMP_END(DCOND_LE);
2042 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
2045 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
2048 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
2051 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
2055 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
2059 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
2066 rcache_get_reg_arg(0, GET_Rn());
2067 tmp2 = emit_memhandler_read(2);
2068 if (tmp == SHR_SR) {
2069 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2070 if (drcf.delayed_op)
2072 emith_write_sr(sr, tmp2);
2075 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
2076 emith_move_r_r(tmp, tmp2);
2078 rcache_free_tmp(tmp2);
2079 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2080 emith_add_r_imm(tmp, 4);
2087 // SHLL2 Rn 0100nnnn00001000
2088 // SHLR2 Rn 0100nnnn00001001
2092 // SHLL8 Rn 0100nnnn00011000
2093 // SHLR8 Rn 0100nnnn00011001
2097 // SHLL16 Rn 0100nnnn00101000
2098 // SHLR16 Rn 0100nnnn00101001
2104 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2106 emith_lsr(tmp2, tmp2, tmp);
2108 emith_lsl(tmp2, tmp2, tmp);
2113 case 0: // LDS Rm,MACH 0100mmmm00001010
2116 case 1: // LDS Rm,MACL 0100mmmm00011010
2119 case 2: // LDS Rm,PR 0100mmmm00101010
2125 emit_move_r_r(tmp2, GET_Rn());
2130 case 0: // JSR @Rm 0100mmmm00001011
2131 case 2: // JMP @Rm 0100mmmm00101011
2134 emit_move_r_imm32(SHR_PR, pc + 2);
2135 emit_move_r_r(SHR_PC, (op >> 8) & 0x0f);
2139 case 1: // TAS.B @Rn 0100nnnn00011011
2140 // XXX: is TAS working on 32X?
2141 rcache_get_reg_arg(0, GET_Rn());
2142 tmp = emit_memhandler_read(0);
2143 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2144 if (drcf.delayed_op)
2146 emith_bic_r_imm(sr, T);
2147 emith_cmp_r_imm(tmp, 0);
2148 emit_or_t_if_eq(sr);
2150 emith_or_r_imm(tmp, 0x80);
2151 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
2152 emith_move_r_r(tmp2, tmp);
2153 rcache_free_tmp(tmp);
2154 rcache_get_reg_arg(0, GET_Rn());
2155 emit_memhandler_write(0, pc, drcf.delayed_op);
2163 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2166 case 0: // LDC Rm,SR 0100mmmm00001110
2169 case 1: // LDC Rm,GBR 0100mmmm00011110
2172 case 2: // LDC Rm,VBR 0100mmmm00101110
2178 if (tmp2 == SHR_SR) {
2179 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2180 if (drcf.delayed_op)
2182 emith_write_sr(sr, tmp);
2185 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
2186 emith_move_r_r(tmp2, tmp);
2190 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
2191 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
2192 emith_sext(tmp, tmp, 16);
2193 emith_sext(tmp2, tmp2, 16);
2194 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
2195 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
2196 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
2197 rcache_free_tmp(tmp2);
2198 // XXX: MACH should be untouched when S is set?
2199 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2200 emith_tst_r_imm(sr, S);
2201 EMITH_JMP_START(DCOND_EQ);
2203 emith_asr(tmp, tmp3, 31);
2204 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
2205 EMITH_JMP_START(DCOND_EQ);
2206 emith_move_r_imm(tmp3, 0x80000000);
2207 emith_tst_r_r(tmp4, tmp4);
2208 EMITH_SJMP_START(DCOND_MI);
2209 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
2210 EMITH_SJMP_END(DCOND_MI);
2211 EMITH_JMP_END(DCOND_EQ);
2213 EMITH_JMP_END(DCOND_EQ);
2214 rcache_free_tmp(tmp);
2220 /////////////////////////////////////////////
2222 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
2223 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2);
2226 /////////////////////////////////////////////
2230 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
2231 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
2232 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
2233 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
2234 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
2235 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
2236 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), 0, op & 3);
2237 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
2238 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
2239 emith_add_r_imm(tmp, (1 << (op & 3)));
2244 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
2245 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2248 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
2249 emith_move_r_r(tmp2, tmp);
2251 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
2252 emith_mvn_r_r(tmp2, tmp);
2254 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
2257 tmp3 = rcache_get_tmp();
2258 tmp4 = rcache_get_tmp();
2259 emith_lsr(tmp3, tmp, 16);
2260 emith_or_r_r_lsl(tmp3, tmp, 24);
2261 emith_and_r_r_imm(tmp4, tmp, 0xff00);
2262 emith_or_r_r_lsl(tmp3, tmp4, 8);
2263 emith_rol(tmp2, tmp3, 16);
2264 rcache_free_tmp(tmp4);
2266 rcache_free_tmp(tmp3);
2268 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
2269 emith_rol(tmp2, tmp, 16);
2271 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
2272 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2273 if (drcf.delayed_op)
2275 emith_tpop_carry(sr, 1);
2276 emith_negcf_r_r(tmp2, tmp);
2277 emith_tpush_carry(sr, 1);
2279 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
2280 emith_neg_r_r(tmp2, tmp);
2282 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
2283 emith_clear_msb(tmp2, tmp, 24);
2285 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
2286 emith_clear_msb(tmp2, tmp, 16);
2288 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
2289 emith_sext(tmp2, tmp, 8);
2291 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
2292 emith_sext(tmp2, tmp, 16);
2299 /////////////////////////////////////////////
2301 // ADD #imm,Rn 0111nnnniiiiiiii
2302 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2303 if (op & 0x80) { // adding negative
2304 emith_sub_r_imm(tmp, -op & 0xff);
2306 emith_add_r_imm(tmp, op & 0xff);
2309 /////////////////////////////////////////////
2311 switch (op & 0x0f00)
2313 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
2314 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
2316 tmp = rcache_get_reg_arg(0, GET_Rm());
2317 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2318 tmp3 = (op & 0x100) >> 8;
2320 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
2321 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
2323 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
2324 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
2325 tmp = (op & 0x100) >> 8;
2326 emit_memhandler_read_rr(SHR_R0, GET_Rm(), (op & 0x0f) << tmp, tmp);
2328 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
2329 // XXX: could use cmn
2330 tmp = rcache_get_tmp();
2331 tmp2 = rcache_get_reg(0, RC_GR_READ);
2332 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2333 if (drcf.delayed_op)
2335 emith_move_r_imm_s8(tmp, op & 0xff);
2336 emith_bic_r_imm(sr, T);
2337 emith_cmp_r_r(tmp2, tmp);
2338 emit_or_t_if_eq(sr);
2339 rcache_free_tmp(tmp);
2341 case 0x0d00: // BT/S label 10001101dddddddd
2342 case 0x0f00: // BF/S label 10001111dddddddd
2345 case 0x0900: // BT label 10001001dddddddd
2346 case 0x0b00: // BF label 10001011dddddddd
2347 // will handle conditional branches later
2348 pending_branch_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE;
2349 i = ((signed int)(op << 24) >> 23);
2350 pending_branch_pc = pc + i + 2;
2355 /////////////////////////////////////////////
2357 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
2358 tmp = pc + (op & 0xff) * 2 + 2;
2359 #if PROPAGATE_CONSTANTS
2360 if (tmp < end_pc + MAX_LITERAL_OFFSET && literal_addr_count < MAX_LITERALS) {
2361 ADD_TO_ARRAY(literal_addr, literal_addr_count, tmp,);
2362 gconst_new(GET_Rn(), (u32)(int)(signed short)FETCH_OP(tmp));
2367 tmp2 = rcache_get_tmp_arg(0);
2368 emith_move_r_imm(tmp2, tmp);
2369 tmp2 = emit_memhandler_read(1);
2370 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2371 emith_sext(tmp3, tmp2, 16);
2372 rcache_free_tmp(tmp2);
2376 /////////////////////////////////////////////
2378 // BRA label 1010dddddddddddd
2380 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2381 tmp = ((signed int)(op << 20) >> 19);
2382 out_pc = pc + tmp + 2;
2384 emith_clear_msb(sr, sr, 20); // burn cycles
2388 /////////////////////////////////////////////
2390 // BSR label 1011dddddddddddd
2392 emit_move_r_imm32(SHR_PR, pc + 2);
2393 tmp = ((signed int)(op << 20) >> 19);
2394 out_pc = pc + tmp + 2;
2398 /////////////////////////////////////////////
2400 switch (op & 0x0f00)
2402 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
2403 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
2404 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
2406 tmp = rcache_get_reg_arg(0, SHR_GBR);
2407 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2408 tmp3 = (op & 0x300) >> 8;
2409 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
2410 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
2412 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
2413 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
2414 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
2415 tmp = (op & 0x300) >> 8;
2416 emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp);
2418 case 0x0300: // TRAPA #imm 11000011iiiiiiii
2419 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2420 emith_sub_r_imm(tmp, 4*2);
2422 tmp = rcache_get_reg_arg(0, SHR_SP);
2423 emith_add_r_imm(tmp, 4);
2424 tmp = rcache_get_reg_arg(1, SHR_SR);
2425 emith_clear_msb(tmp, tmp, 22);
2426 emit_memhandler_write(2, pc, drcf.delayed_op);
2428 rcache_get_reg_arg(0, SHR_SP);
2429 tmp = rcache_get_tmp_arg(1);
2430 emith_move_r_imm(tmp, pc);
2431 emit_memhandler_write(2, pc, drcf.delayed_op);
2433 emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
2437 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
2438 emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3);
2440 case 0x0800: // TST #imm,R0 11001000iiiiiiii
2441 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
2442 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2443 if (drcf.delayed_op)
2445 emith_bic_r_imm(sr, T);
2446 emith_tst_r_imm(tmp, op & 0xff);
2447 emit_or_t_if_eq(sr);
2449 case 0x0900: // AND #imm,R0 11001001iiiiiiii
2450 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2451 emith_and_r_imm(tmp, op & 0xff);
2453 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
2454 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2455 emith_eor_r_imm(tmp, op & 0xff);
2457 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
2458 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2459 emith_or_r_imm(tmp, op & 0xff);
2461 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
2462 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2463 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2464 if (drcf.delayed_op)
2466 emith_bic_r_imm(sr, T);
2467 emith_tst_r_imm(tmp, op & 0xff);
2468 emit_or_t_if_eq(sr);
2469 rcache_free_tmp(tmp);
2472 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2473 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2474 emith_and_r_imm(tmp, op & 0xff);
2476 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2477 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2478 emith_eor_r_imm(tmp, op & 0xff);
2480 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2481 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2482 emith_or_r_imm(tmp, op & 0xff);
2484 tmp2 = rcache_get_tmp_arg(1);
2485 emith_move_r_r(tmp2, tmp);
2486 rcache_free_tmp(tmp);
2487 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2488 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2489 emith_add_r_r(tmp3, tmp4);
2490 emit_memhandler_write(0, pc, drcf.delayed_op);
2496 /////////////////////////////////////////////
2498 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
2499 tmp = (pc + (op & 0xff) * 4 + 2) & ~3;
2500 #if PROPAGATE_CONSTANTS
2501 if (tmp < end_pc + MAX_LITERAL_OFFSET && literal_addr_count < MAX_LITERALS) {
2502 ADD_TO_ARRAY(literal_addr, literal_addr_count, tmp,);
2503 gconst_new(GET_Rn(), FETCH32(tmp));
2508 tmp2 = rcache_get_tmp_arg(0);
2509 emith_move_r_imm(tmp2, tmp);
2510 tmp2 = emit_memhandler_read(2);
2511 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2512 emith_move_r_r(tmp3, tmp2);
2513 rcache_free_tmp(tmp2);
2517 /////////////////////////////////////////////
2519 // MOV #imm,Rn 1110nnnniiiiiiii
2520 emit_move_r_imm32(GET_Rn(), (u32)(signed int)(signed char)op);
2525 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
2526 sh2->is_slave ? 's' : 'm', op, pc - 2);
2531 rcache_unlock_all();
2533 // conditional branch handling (with/without delay)
2534 if (pending_branch_cond != -1 && drcf.delayed_op != 2)
2536 u32 target_pc = pending_branch_pc;
2537 int ctaken = drcf.delayed_op ? 1 : 2;
2540 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2542 if (drcf.use_saved_t)
2543 emith_tst_r_imm(sr, T_save);
2545 emith_tst_r_imm(sr, T);
2548 emith_sub_r_imm_c(pending_branch_cond, sr, ctaken<<12);
2552 if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0) {
2554 // XXX: jumps back can be linked already
2555 branch_patch_pc[branch_patch_count] = target_pc;
2556 branch_patch_ptr[branch_patch_count] = tcache_ptr;
2557 emith_jump_cond_patchable(pending_branch_cond, tcache_ptr);
2559 branch_patch_count++;
2560 if (branch_patch_count == MAX_LOCAL_BRANCHES) {
2561 dbg(1, "warning: too many local branches");
2568 // can't resolve branch locally, make a block exit
2569 emit_move_r_imm32(SHR_PC, target_pc);
2572 target = dr_prepare_ext_branch(target_pc, sh2, tcache_id);
2575 emith_jump_cond_patchable(pending_branch_cond, target);
2578 drcf.use_saved_t = 0;
2579 pending_branch_cond = -1;
2583 // XXX: delay slots..
2584 if (drcf.test_irq && drcf.delayed_op != 2) {
2585 if (!drcf.delayed_op)
2586 emit_move_r_imm32(SHR_PC, pc);
2587 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2590 emith_call(sh2_drc_test_irq);
2594 do_host_disasm(tcache_id);
2596 if (out_pc != 0 && drcf.delayed_op != 2)
2600 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2604 if (out_pc == (u32)-1) {
2605 // indirect jump -> back to dispatcher
2606 emith_jump(sh2_drc_dispatcher);
2611 emit_move_r_imm32(SHR_PC, out_pc);
2614 target = dr_prepare_ext_branch(out_pc, sh2, tcache_id);
2617 emith_jump_patchable(target);
2620 // link local branches
2621 for (i = 0; i < branch_patch_count; i++) {
2624 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2625 target = branch_target_ptr[t];
2626 if (target == NULL) {
2627 // flush pc and go back to dispatcher (this should no longer happen)
2628 dbg(1, "stray branch to %08x %p", branch_patch_pc[i], tcache_ptr);
2629 target = tcache_ptr;
2630 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2632 emith_jump(sh2_drc_dispatcher);
2634 emith_jump_patch(branch_patch_ptr[i], target);
2639 // mark memory blocks as containing compiled code
2640 // override any overlay blocks as they become unreachable anyway
2641 if (tcache_id != 0 || (this_block->addr & 0xc7fc0000) == 0x06000000)
2643 u16 *p, *drc_ram_blk = NULL;
2644 u32 addr, mask = 0, shift = 0;
2646 if (tcache_id != 0) {
2648 drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave];
2649 shift = SH2_DRCBLK_DA_SHIFT;
2652 else if ((this_block->addr & 0xc7fc0000) == 0x06000000) {
2654 drc_ram_blk = Pico32xMem->drcblk_ram;
2655 shift = SH2_DRCBLK_RAM_SHIFT;
2659 drc_ram_blk[(base_pc & mask) >> shift] = (blkid_main << 1) | 1;
2660 for (pc = base_pc + 2; pc < end_pc; pc += 2) {
2661 p = &drc_ram_blk[(pc & mask) >> shift];
2662 *p = blkid_main << 1;
2665 // mark block entries (used by dr_get_bd())
2666 for (i = 0; i < branch_target_count; i++)
2667 if (branch_target_blkid[i] != 0)
2668 drc_ram_blk[(branch_target_pc[i] & mask) >> shift] =
2669 (branch_target_blkid[i] << 1) | 1;
2672 for (i = 0; i < literal_addr_count; i++) {
2673 tmp = literal_addr[i];
2674 p = &drc_ram_blk[(tmp & mask) >> shift];
2675 *p = blkid_main << 1;
2676 if (!(tmp & 3) && shift == 1)
2677 p[1] = p[0]; // assume long
2680 // add to invalidation lookup lists
2681 addr = base_pc & ~(ADDR_TO_BLOCK_PAGE - 1);
2682 for (; addr < end_pc + MAX_LITERAL_OFFSET; addr += ADDR_TO_BLOCK_PAGE) {
2683 i = (addr & mask) / ADDR_TO_BLOCK_PAGE;
2684 add_to_block_list(&inval_lookup[tcache_id][i], this_block);
2688 tcache_ptrs[tcache_id] = tcache_ptr;
2690 host_instructions_updated(block_entry, tcache_ptr);
2692 do_host_disasm(tcache_id);
2693 dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2694 tcache_id, blkid_main,
2695 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2696 insns_compiled, host_insn_count, (float)host_insn_count / insns_compiled);
2697 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2698 dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2701 tcache_dsm_ptrs[tcache_id] = block_entry;
2702 do_host_disasm(tcache_id);
2713 static void sh2_generate_utils(void)
2715 int arg0, arg1, arg2, sr, tmp;
2716 void *sh2_drc_write_end, *sh2_drc_write_slot_end;
2718 sh2_drc_write32 = p32x_sh2_write32;
2719 sh2_drc_read8 = p32x_sh2_read8;
2720 sh2_drc_read16 = p32x_sh2_read16;
2721 sh2_drc_read32 = p32x_sh2_read32;
2723 host_arg2reg(arg0, 0);
2724 host_arg2reg(arg1, 1);
2725 host_arg2reg(arg2, 2);
2726 emith_move_r_r(arg0, arg0); // nop
2728 // sh2_drc_exit(void)
2729 sh2_drc_exit = (void *)tcache_ptr;
2730 emit_do_static_regs(1, arg2);
2731 emith_sh2_drc_exit();
2733 // sh2_drc_dispatcher(void)
2734 sh2_drc_dispatcher = (void *)tcache_ptr;
2735 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2736 emith_cmp_r_imm(sr, 0);
2737 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2738 rcache_invalidate();
2739 emith_ctx_read(arg0, SHR_PC * 4);
2740 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2741 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2742 emith_call(dr_lookup_block);
2744 // lookup failed, call sh2_translate()
2745 emith_move_r_r(arg0, CONTEXT_REG);
2746 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2747 emith_call(sh2_translate);
2749 // sh2_translate() failed, flush cache and retry
2750 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2751 emith_call(flush_tcache);
2752 emith_move_r_r(arg0, CONTEXT_REG);
2753 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2754 emith_call(sh2_translate);
2756 // XXX: can't translate, fail
2757 emith_call(dr_failure);
2759 // sh2_drc_test_irq(void)
2760 // assumes it's called from main function (may jump to dispatcher)
2761 sh2_drc_test_irq = (void *)tcache_ptr;
2762 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2763 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2764 emith_lsr(arg0, sr, I_SHIFT);
2765 emith_and_r_imm(arg0, 0x0f);
2766 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2767 EMITH_SJMP_START(DCOND_GT);
2768 emith_ret_c(DCOND_LE); // nope, return
2769 EMITH_SJMP_END(DCOND_GT);
2771 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2772 emith_sub_r_imm(tmp, 4*2);
2775 tmp = rcache_get_reg_arg(0, SHR_SP);
2776 emith_add_r_imm(tmp, 4);
2777 tmp = rcache_get_reg_arg(1, SHR_SR);
2778 emith_clear_msb(tmp, tmp, 22);
2779 emith_move_r_r(arg2, CONTEXT_REG);
2780 emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
2781 rcache_invalidate();
2783 rcache_get_reg_arg(0, SHR_SP);
2784 emith_ctx_read(arg1, SHR_PC * 4);
2785 emith_move_r_r(arg2, CONTEXT_REG);
2786 emith_call(p32x_sh2_write32);
2787 rcache_invalidate();
2788 // update I, cycles, do callback
2789 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2790 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2791 emith_bic_r_imm(sr, I);
2792 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2793 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2795 emith_move_r_r(arg0, CONTEXT_REG);
2796 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2798 emith_lsl(arg0, arg0, 2);
2799 emith_ctx_read(arg1, SHR_VBR * 4);
2800 emith_add_r_r(arg0, arg1);
2801 emit_memhandler_read(2);
2802 emith_ctx_write(arg0, SHR_PC * 4);
2804 emith_add_r_imm(xSP, 4); // fix stack
2806 emith_jump(sh2_drc_dispatcher);
2807 rcache_invalidate();
2809 // sh2_drc_entry(SH2 *sh2)
2810 sh2_drc_entry = (void *)tcache_ptr;
2811 emith_sh2_drc_entry();
2812 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2813 emit_do_static_regs(0, arg2);
2814 emith_call(sh2_drc_test_irq);
2815 emith_jump(sh2_drc_dispatcher);
2817 // write-caused irq detection
2818 sh2_drc_write_end = tcache_ptr;
2819 emith_tst_r_r(arg0, arg0);
2820 EMITH_SJMP_START(DCOND_NE);
2821 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); // return
2822 EMITH_SJMP_END(DCOND_NE);
2823 emith_call(sh2_drc_test_irq);
2824 emith_jump_ctx(offsetof(SH2, drc_tmp));
2826 // write-caused irq detection for writes in delay slot
2827 sh2_drc_write_slot_end = tcache_ptr;
2828 emith_tst_r_r(arg0, arg0);
2829 EMITH_SJMP_START(DCOND_NE);
2830 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp));
2831 EMITH_SJMP_END(DCOND_NE);
2832 // just burn cycles to get back to dispatcher after branch is handled
2833 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2834 emith_ctx_write(sr, offsetof(SH2, irq_cycles));
2835 emith_clear_msb(sr, sr, 20); // clear cycles
2837 emith_jump_ctx(offsetof(SH2, drc_tmp));
2839 // sh2_drc_write8(u32 a, u32 d)
2840 sh2_drc_write8 = (void *)tcache_ptr;
2841 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2842 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2843 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2845 // sh2_drc_write16(u32 a, u32 d)
2846 sh2_drc_write16 = (void *)tcache_ptr;
2847 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2848 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2849 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2851 // sh2_drc_write8_slot(u32 a, u32 d)
2852 sh2_drc_write8_slot = (void *)tcache_ptr;
2853 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2854 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2855 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2857 // sh2_drc_write16_slot(u32 a, u32 d)
2858 sh2_drc_write16_slot = (void *)tcache_ptr;
2859 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2860 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2861 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2865 #define MAKE_READ_WRAPPER(func) { \
2866 void *tmp = (void *)tcache_ptr; \
2869 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2870 emith_addf_r_r(arg2, arg0); \
2871 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2872 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2873 emith_adc_r_imm(arg2, 0x01000000); \
2874 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2875 emith_pop_and_ret(); \
2878 #define MAKE_WRITE_WRAPPER(func) { \
2879 void *tmp = (void *)tcache_ptr; \
2880 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2881 emith_addf_r_r(arg2, arg1); \
2882 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2883 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2884 emith_adc_r_imm(arg2, 0x01000000); \
2885 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2886 emith_move_r_r(arg2, CONTEXT_REG); \
2891 MAKE_READ_WRAPPER(sh2_drc_read8);
2892 MAKE_READ_WRAPPER(sh2_drc_read16);
2893 MAKE_READ_WRAPPER(sh2_drc_read32);
2894 MAKE_WRITE_WRAPPER(sh2_drc_write8);
2895 MAKE_WRITE_WRAPPER(sh2_drc_write8_slot);
2896 MAKE_WRITE_WRAPPER(sh2_drc_write16);
2897 MAKE_WRITE_WRAPPER(sh2_drc_write16_slot);
2898 MAKE_WRITE_WRAPPER(sh2_drc_write32);
2900 host_dasm_new_symbol(sh2_drc_read8);
2901 host_dasm_new_symbol(sh2_drc_read16);
2902 host_dasm_new_symbol(sh2_drc_read32);
2903 host_dasm_new_symbol(sh2_drc_write32);
2907 rcache_invalidate();
2909 host_dasm_new_symbol(sh2_drc_entry);
2910 host_dasm_new_symbol(sh2_drc_dispatcher);
2911 host_dasm_new_symbol(sh2_drc_exit);
2912 host_dasm_new_symbol(sh2_drc_test_irq);
2913 host_dasm_new_symbol(sh2_drc_write_end);
2914 host_dasm_new_symbol(sh2_drc_write_slot_end);
2915 host_dasm_new_symbol(sh2_drc_write8);
2916 host_dasm_new_symbol(sh2_drc_write8_slot);
2917 host_dasm_new_symbol(sh2_drc_write16);
2918 host_dasm_new_symbol(sh2_drc_write16_slot);
2922 static void sh2_smc_rm_block_entry(block_desc *bd, int tcache_id, u32 ram_mask)
2927 // XXX: kill links somehow?
2928 dbg(2, " killing entry %08x-%08x, blkid %d,%d",
2929 bd->addr, bd->end_addr, tcache_id, bd - block_tables[tcache_id]);
2930 if (bd->addr == 0 || bd->tcache_ptr == NULL) {
2931 dbg(1, " killing dead block!? %08x", bd->addr);
2935 // remove from inval_lookup
2936 addr = bd->addr & ~(ADDR_TO_BLOCK_PAGE - 1);
2937 for (; addr < bd->end_addr; addr += ADDR_TO_BLOCK_PAGE) {
2938 i = (addr & ram_mask) / ADDR_TO_BLOCK_PAGE;
2939 rm_from_block_list(&inval_lookup[tcache_id][i], bd);
2942 // since we never reuse space of dead blocks,
2943 // insert jump to dispatcher for blocks that are linked to this point
2944 //emith_jump_at(bd->tcache_ptr, sh2_drc_dispatcher);
2946 // attempt to handle self-modifying blocks by exiting at nearest known PC
2948 tcache_ptr = bd->tcache_ptr;
2949 emit_move_r_imm32(SHR_PC, bd->addr);
2951 emith_jump(sh2_drc_dispatcher);
2953 host_instructions_updated(bd->tcache_ptr, tcache_ptr);
2956 bd->addr = bd->end_addr = 0;
2959 static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask)
2961 struct block_list **blist = NULL, *entry;
2962 u32 from = ~0, to = 0;
2965 blist = &inval_lookup[tcache_id][(a & mask) / ADDR_TO_BLOCK_PAGE];
2967 while (entry != NULL) {
2968 block = entry->block;
2969 if (block->addr <= a && a < block->end_addr) {
2970 if (block->addr < from)
2972 if (block->end_addr > to)
2973 to = block->end_addr;
2975 sh2_smc_rm_block_entry(block, tcache_id, mask);
2977 // entry lost, restart search
2981 entry = entry->next;
2984 // clear entry points
2986 u16 *p = drc_ram_blk + ((from & mask) >> shift);
2987 memset(p, 0, (to - from) >> (shift - 1));
2991 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
2993 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
2994 sh2_smc_rm_block(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
2997 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
2999 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3000 sh2_smc_rm_block(a, Pico32xMem->drcblk_da[cpuid],
3001 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
3004 int sh2_execute(SH2 *sh2c, int cycles)
3008 sh2c->cycles_timeslice = cycles;
3010 // cycles are kept in SHR_SR unused bits (upper 20)
3011 // bit11 contains T saved for delay slot
3012 // others are usual SH2 flags
3014 sh2c->sr |= cycles << 12;
3015 sh2_drc_entry(sh2c);
3018 ret_cycles = (signed int)sh2c->sr >> 12;
3020 dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
3022 return sh2c->cycles_timeslice - ret_cycles;
3026 void block_stats(void)
3028 int c, b, i, total = 0;
3030 printf("block stats:\n");
3031 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3032 for (i = 0; i < block_counts[b]; i++)
3033 if (block_tables[b][i].addr != 0)
3034 total += block_tables[b][i].refcount;
3036 for (c = 0; c < 10; c++) {
3037 block_desc *blk, *maxb = NULL;
3039 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
3040 for (i = 0; i < block_counts[b]; i++) {
3041 blk = &block_tables[b][i];
3042 if (blk->addr != 0 && blk->refcount > max) {
3043 max = blk->refcount;
3050 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
3051 (double)maxb->refcount / total * 100.0);
3055 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3056 for (i = 0; i < block_counts[b]; i++)
3057 block_tables[b][i].refcount = 0;
3060 #define block_stats()
3063 void sh2_drc_flush_all(void)
3071 void sh2_drc_mem_setup(SH2 *sh2)
3073 // fill the convenience pointers
3074 sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3075 sh2->p_da = Pico32xMem->data_array[sh2->is_slave];
3076 sh2->p_sdram = Pico32xMem->sdram;
3077 sh2->p_rom = Pico.rom;
3080 int sh2_drc_init(SH2 *sh2)
3084 if (block_tables[0] == NULL)
3086 for (i = 0; i < TCACHE_BUFFERS; i++) {
3087 block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0]));
3088 if (block_tables[i] == NULL)
3090 // max 2 block links (exits) per block
3091 block_links[i] = calloc(block_max_counts[i] * 2, sizeof(*block_links[0]));
3092 if (block_links[i] == NULL)
3095 inval_lookup[i] = calloc(ram_sizes[i] / ADDR_TO_BLOCK_PAGE,
3096 sizeof(inval_lookup[0]));
3097 if (inval_lookup[i] == NULL)
3100 memset(block_counts, 0, sizeof(block_counts));
3101 memset(block_link_counts, 0, sizeof(block_link_counts));
3104 tcache_ptr = tcache;
3105 sh2_generate_utils();
3106 host_instructions_updated(tcache, tcache_ptr);
3108 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
3109 for (i = 1; i < ARRAY_SIZE(tcache_bases); i++)
3110 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
3113 PicoOpt |= POPT_DIS_VDP_FIFO;
3116 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
3117 tcache_dsm_ptrs[i] = tcache_bases[i];
3119 tcache_dsm_ptrs[0] = tcache;
3123 hash_collisions = 0;
3127 if (hash_table == NULL) {
3128 hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES);
3129 if (hash_table == NULL)
3136 sh2_drc_finish(sh2);
3140 void sh2_drc_finish(SH2 *sh2)
3144 sh2_drc_flush_all();
3146 if (block_tables[0] != NULL) {
3149 for (i = 0; i < TCACHE_BUFFERS; i++) {
3151 printf("~~~ tcache %d\n", i);
3152 tcache_dsm_ptrs[i] = tcache_bases[i];
3153 tcache_ptr = tcache_ptrs[i];
3157 if (block_tables[i] != NULL)
3158 free(block_tables[i]);
3159 block_tables[i] = NULL;
3160 if (block_links[i] == NULL)
3161 free(block_links[i]);
3162 block_links[i] = NULL;
3164 if (inval_lookup[i] == NULL)
3165 free(inval_lookup[i]);
3166 inval_lookup[i] = NULL;
3172 if (hash_table != NULL) {
3178 #endif /* DRC_SH2 */
3180 static void *dr_get_pc_base(u32 pc, int is_slave)
3185 if ((pc & ~0x7ff) == 0) {
3187 ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3190 else if ((pc & 0xfffff000) == 0xc0000000) {
3192 ret = Pico32xMem->data_array[is_slave];
3195 else if ((pc & 0xc6000000) == 0x06000000) {
3197 ret = Pico32xMem->sdram;
3200 else if ((pc & 0xc6000000) == 0x02000000) {
3207 return (void *)-1; // NULL is valid value
3209 return (char *)ret - (pc & ~mask);
3212 void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc)
3218 memset(op_flags, 0, BLOCK_CYCLE_LIMIT);
3220 dr_pc_base = dr_get_pc_base(base_pc, is_slave);
3222 for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT-1; cycles++, pc += 2) {
3224 if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR
3225 signed int offs = ((signed int)(op << 20) >> 19);
3227 OP_FLAGS(pc) |= OF_DELAY_OP;
3228 target = pc + offs + 2;
3229 if (base_pc <= target && target < base_pc + BLOCK_CYCLE_LIMIT * 2)
3230 OP_FLAGS(target) |= OF_TARGET;
3233 if ((op & 0xf000) == 0) {
3235 if (op == 0x1b) // SLEEP
3237 // BRAF, BSRF, RTS, RTE
3238 if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) {
3240 OP_FLAGS(pc) |= OF_DELAY_OP;
3245 if ((op & 0xf0df) == 0x400b) { // JMP, JSR
3247 OP_FLAGS(pc) |= OF_DELAY_OP;
3250 if ((op & 0xf900) == 0x8900) { // BT(S), BF(S)
3251 signed int offs = ((signed int)(op << 24) >> 23);
3253 OP_FLAGS(pc + 2) |= OF_DELAY_OP;
3254 target = pc + offs + 4;
3255 if (base_pc <= target && target < base_pc + BLOCK_CYCLE_LIMIT * 2)
3256 OP_FLAGS(target) |= OF_TARGET;
3258 if ((op & 0xff00) == 0xc300) // TRAPA
3264 // vim:shiftwidth=2:ts=2:expandtab