5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * - tcache, block descriptor, link buffer overflows result in sh2_translate()
10 * failure, followed by full tcache invalidation for that region
11 * - jumps between blocks are tracked for SMC handling (in block_links[]),
12 * except jumps between different tcaches
13 * - non-main block entries are called subblocks, as they have same tracking
14 * structures that main blocks have.
17 * - static register allocation
18 * - remaining register caching and tracking in temporaries
19 * - block-local branch linking
20 * - block linking (except between tcaches)
21 * - some constant propagation
24 * - better constant propagation
33 #include "../../pico/pico_int.h"
36 #include "../drc/cmn.h"
40 #define PROPAGATE_CONSTANTS 1
41 #define LINK_BRANCHES 1
44 #define BLOCK_CYCLE_LIMIT 100
45 #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
47 // max literal offset from the block end
48 #define MAX_LITERAL_OFFSET 32*2
49 #define MAX_LITERALS (BLOCK_CYCLE_LIMIT / 4)
50 #define MAX_LOCAL_BRANCHES 32
58 #define dbg(l,...) { \
59 if ((l) & DRC_DEBUG) \
60 elprintf(EL_STATUS, ##__VA_ARGS__); \
63 #include "mame/sh2dasm.h"
64 #include <platform/linux/host_dasm.h>
65 static int insns_compiled, hash_collisions, host_insn_count;
74 static u8 *tcache_dsm_ptrs[3];
75 static char sh2dasm_buff[64];
76 #define do_host_disasm(tcid) \
77 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
78 tcache_dsm_ptrs[tcid] = tcache_ptr
80 #define do_host_disasm(x)
83 #if (DRC_DEBUG & 8) || defined(PDB)
84 static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
87 dbg(8, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
88 sh2->pc, block, (signed int)sr >> 12);
89 pdb_step(sh2, sh2->pc);
96 #define TCACHE_BUFFERS 3
98 // we have 3 translation cache buffers, split from one drc/cmn buffer.
99 // BIOS shares tcache with data array because it's only used for init
100 // and can be discarded early
101 // XXX: need to tune sizes
102 static const int tcache_sizes[TCACHE_BUFFERS] = {
103 DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM
104 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
105 DRC_TCACHE_SIZE / 8, // ... slave
108 static u8 *tcache_bases[TCACHE_BUFFERS];
109 static u8 *tcache_ptrs[TCACHE_BUFFERS];
111 // ptr for code emiters
112 static u8 *tcache_ptr;
114 typedef struct block_desc_ {
115 u32 addr; // SH2 PC address
116 void *tcache_ptr; // translated block for above PC
117 struct block_desc_ *next; // next block with the same PC hash
123 typedef struct block_link_ {
125 void *jump; // insn address
126 // struct block_link_ *next;
129 static const int block_max_counts[TCACHE_BUFFERS] = {
134 static block_desc *block_tables[TCACHE_BUFFERS];
135 static block_link *block_links[TCACHE_BUFFERS];
136 static int block_counts[TCACHE_BUFFERS];
137 static int block_link_counts[TCACHE_BUFFERS];
139 // host register tracking
142 HR_CACHED, // 'val' has sh2_reg_e
143 // HR_CONST, // 'val' has a constant
144 HR_TEMP, // reg used for temp storage
148 HRF_DIRTY = 1 << 0, // reg has "dirty" value to be written to ctx
149 HRF_LOCKED = 1 << 1, // HR_CACHED can't be evicted
153 u32 hreg:5; // "host" reg
154 u32 greg:5; // "guest" reg
157 u32 stamp:16; // kind of a timestamp
160 // note: reg_temp[] must have at least the amount of
161 // registers used by handlers in worst case (currently 4)
163 #include "../drc/emit_arm.c"
165 static const int reg_map_g2h[] = {
174 static temp_reg_t reg_temp[] = {
183 #elif defined(__i386__)
184 #include "../drc/emit_x86.c"
186 static const int reg_map_g2h[] = {
195 // ax, cx, dx are usually temporaries by convention
196 static temp_reg_t reg_temp[] = {
204 #error unsupported arch
212 #define T_save 0x00000800
219 #define MAX_HASH_ENTRIES 1024
220 #define HASH_MASK (MAX_HASH_ENTRIES - 1)
221 static void **hash_table;
223 #define HASH_FUNC(hash_tab, addr) \
224 ((block_desc **)(hash_tab))[(addr) & HASH_MASK]
226 static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
227 static void (*sh2_drc_dispatcher)(void);
228 static void (*sh2_drc_exit)(void);
229 static void (*sh2_drc_test_irq)(void);
231 static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
232 static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
233 static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
234 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
235 static void REGPARM(2) (*sh2_drc_write8_slot)(u32 a, u32 d);
236 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
237 static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d);
238 static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
240 extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode);
242 // address space stuff
243 static void *dr_get_pc_base(u32 pc, int is_slave)
248 if ((pc & ~0x7ff) == 0) {
250 ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
253 else if ((pc & 0xfffff000) == 0xc0000000) {
255 ret = Pico32xMem->data_array[is_slave];
258 else if ((pc & 0xc6000000) == 0x06000000) {
260 ret = Pico32xMem->sdram;
263 else if ((pc & 0xc6000000) == 0x02000000) {
270 return (void *)-1; // NULL is valid value
272 return (char *)ret - (pc & ~mask);
275 static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
279 if ((a & ~0x7ff) == 0) {
281 poffs = offsetof(SH2, p_bios);
284 else if ((a & 0xfffff000) == 0xc0000000) {
286 poffs = offsetof(SH2, p_da);
289 else if ((a & 0xc6000000) == 0x06000000) {
291 poffs = offsetof(SH2, p_sdram);
294 else if ((a & 0xc6000000) == 0x02000000) {
296 poffs = offsetof(SH2, p_rom);
303 static block_desc *dr_get_bd(u32 pc, int is_slave, int *tcache_id)
307 // we have full block id tables for data_array and RAM
308 // BIOS goes to data_array table too
309 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0) {
310 int blkid = Pico32xMem->drcblk_da[is_slave][(pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
311 *tcache_id = 1 + is_slave;
313 return &block_tables[*tcache_id][blkid >> 1];
316 else if ((pc & 0xc6000000) == 0x06000000) {
317 int blkid = Pico32xMem->drcblk_ram[(pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
319 return &block_tables[0][blkid >> 1];
322 else if ((pc & 0xc6000000) == 0x02000000) {
323 block_desc *bd = HASH_FUNC(hash_table, pc);
325 for (; bd != NULL; bd = bd->next)
333 // ---------------------------------------------------------------
336 static void REGPARM(1) flush_tcache(int tcid)
338 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
339 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
340 block_counts[tcid], block_max_counts[tcid]);
342 block_counts[tcid] = 0;
343 block_link_counts[tcid] = 0;
344 tcache_ptrs[tcid] = tcache_bases[tcid];
345 if (tcid == 0) { // ROM, RAM
346 memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES);
347 memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram));
350 memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0]));
352 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
357 // add block links (tracked branches)
358 static int dr_add_block_link(u32 target_pc, void *jump, int tcache_id)
360 block_link *bl = block_links[tcache_id];
361 int cnt = block_link_counts[tcache_id];
363 if (cnt >= block_max_counts[tcache_id] * 2) {
364 dbg(1, "bl overflow for tcache %d\n", tcache_id);
368 bl[cnt].target_pc = target_pc;
370 block_link_counts[tcache_id]++;
376 static block_desc *dr_add_block(u32 addr, int is_slave, int *blk_id)
382 bd = dr_get_bd(addr, is_slave, &tcache_id);
384 dbg(2, "block override for %08x", addr);
385 bd->tcache_ptr = tcache_ptr;
386 *blk_id = bd - block_tables[tcache_id];
390 bcount = &block_counts[tcache_id];
391 if (*bcount >= block_max_counts[tcache_id]) {
392 dbg(1, "bd overflow for tcache %d", tcache_id);
396 (*bcount)++; // not using descriptor 0
398 bd = &block_tables[tcache_id][*bcount];
400 bd->tcache_ptr = tcache_ptr;
404 if ((addr & 0xc6000000) == 0x02000000) { // ROM
405 bd->next = HASH_FUNC(hash_table, addr);
406 HASH_FUNC(hash_table, addr) = bd;
408 if (bd->next != NULL) {
409 printf(" hash collision with %08x\n", bd->next->addr);
418 static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id)
420 block_desc *bd = NULL;
423 bd = dr_get_bd(pc, is_slave, tcache_id);
425 block = bd->tcache_ptr;
434 static void *dr_prepare_ext_branch(u32 pc, SH2 *sh2, int tcache_id)
437 int target_tcache_id;
441 target = dr_lookup_block(pc, sh2->is_slave, &target_tcache_id);
442 if (target_tcache_id == tcache_id) {
443 // allow linking blocks only from local cache
444 ret = dr_add_block_link(pc, tcache_ptr, tcache_id);
448 if (target == NULL || target_tcache_id != tcache_id)
449 target = sh2_drc_dispatcher;
453 return sh2_drc_dispatcher;
457 static void dr_link_blocks(void *target, u32 pc, int tcache_id)
460 block_link *bl = block_links[tcache_id];
461 int cnt = block_link_counts[tcache_id];
464 for (i = 0; i < cnt; i++) {
465 if (bl[i].target_pc == pc) {
466 dbg(2, "- link from %p", bl[i].jump);
467 emith_jump_patch(bl[i].jump, target);
468 // XXX: sync ARM caches (old jump should be fine)?
474 #define ADD_TO_ARRAY(array, count, item, failcode) \
475 array[count++] = item; \
476 if (count >= ARRAY_SIZE(array)) { \
477 dbg(1, "warning: " #array " overflow"); \
481 static int find_in_array(u32 *array, size_t size, u32 what)
484 for (i = 0; i < size; i++)
485 if (what == array[i])
491 // ---------------------------------------------------------------
493 // register cache / constant propagation stuff
500 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking);
502 // guest regs with constants
503 static u32 dr_gcregs[24];
504 // a mask of constant/dirty regs
505 static u32 dr_gcregs_mask;
506 static u32 dr_gcregs_dirty;
508 #if PROPAGATE_CONSTANTS
509 static void gconst_new(sh2_reg_e r, u32 val)
513 dr_gcregs_mask |= 1 << r;
514 dr_gcregs_dirty |= 1 << r;
517 // throw away old r that we might have cached
518 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
519 if ((reg_temp[i].type == HR_CACHED) &&
520 reg_temp[i].greg == r) {
521 reg_temp[i].type = HR_FREE;
522 reg_temp[i].flags = 0;
528 static int gconst_get(sh2_reg_e r, u32 *val)
530 if (dr_gcregs_mask & (1 << r)) {
537 static int gconst_check(sh2_reg_e r)
539 if ((dr_gcregs_mask | dr_gcregs_dirty) & (1 << r))
544 // update hr if dirty, else do nothing
545 static int gconst_try_read(int hr, sh2_reg_e r)
547 if (dr_gcregs_dirty & (1 << r)) {
548 emith_move_r_imm(hr, dr_gcregs[r]);
549 dr_gcregs_dirty &= ~(1 << r);
555 static void gconst_check_evict(sh2_reg_e r)
557 if (dr_gcregs_mask & (1 << r))
558 // no longer cached in reg, make dirty again
559 dr_gcregs_dirty |= 1 << r;
562 static void gconst_kill(sh2_reg_e r)
564 dr_gcregs_mask &= ~(1 << r);
565 dr_gcregs_dirty &= ~(1 << r);
568 static void gconst_clean(void)
572 for (i = 0; i < ARRAY_SIZE(dr_gcregs); i++)
573 if (dr_gcregs_dirty & (1 << i)) {
574 // using RC_GR_READ here: it will call gconst_try_read,
575 // cache the reg and mark it dirty.
576 rcache_get_reg_(i, RC_GR_READ, 0);
580 static void gconst_invalidate(void)
582 dr_gcregs_mask = dr_gcregs_dirty = 0;
585 static u16 rcache_counter;
587 static temp_reg_t *rcache_evict(void)
589 // evict reg with oldest stamp
591 u16 min_stamp = (u16)-1;
593 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
594 if (reg_temp[i].type == HR_CACHED && !(reg_temp[i].flags & HRF_LOCKED) &&
595 reg_temp[i].stamp <= min_stamp) {
596 min_stamp = reg_temp[i].stamp;
602 printf("no registers to evict, aborting\n");
607 if (reg_temp[i].type == HR_CACHED) {
608 if (reg_temp[i].flags & HRF_DIRTY)
610 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
611 gconst_check_evict(reg_temp[i].greg);
614 reg_temp[i].type = HR_FREE;
615 reg_temp[i].flags = 0;
619 static int get_reg_static(sh2_reg_e r, rc_gr_mode mode)
621 int i = reg_map_g2h[r];
623 if (mode != RC_GR_WRITE)
624 gconst_try_read(i, r);
629 // note: must not be called when doing conditional code
630 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking)
635 // maybe statically mapped?
636 ret = get_reg_static(r, mode);
642 // maybe already cached?
643 // if so, prefer against gconst (they must be in sync)
644 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
645 if (reg_temp[i].type == HR_CACHED && reg_temp[i].greg == r) {
646 reg_temp[i].stamp = rcache_counter;
647 if (mode != RC_GR_READ)
648 reg_temp[i].flags |= HRF_DIRTY;
649 ret = reg_temp[i].hreg;
655 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
656 if (reg_temp[i].type == HR_FREE) {
665 tr->type = HR_CACHED;
667 tr->flags |= HRF_LOCKED;
668 if (mode != RC_GR_READ)
669 tr->flags |= HRF_DIRTY;
671 tr->stamp = rcache_counter;
674 if (mode != RC_GR_WRITE) {
675 if (gconst_check(r)) {
676 if (gconst_try_read(ret, r))
677 tr->flags |= HRF_DIRTY;
680 emith_ctx_read(tr->hreg, r * 4);
684 if (mode != RC_GR_READ)
690 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
692 return rcache_get_reg_(r, mode, 1);
695 static int rcache_get_tmp(void)
700 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
701 if (reg_temp[i].type == HR_FREE) {
713 static int rcache_get_arg_id(int arg)
716 host_arg2reg(r, arg);
718 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
719 if (reg_temp[i].hreg == r)
722 if (i == ARRAY_SIZE(reg_temp)) // can't happen
725 if (reg_temp[i].type == HR_CACHED) {
727 if (reg_temp[i].flags & HRF_DIRTY)
728 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
729 gconst_check_evict(reg_temp[i].greg);
731 else if (reg_temp[i].type == HR_TEMP) {
732 printf("arg %d reg %d already used, aborting\n", arg, r);
736 reg_temp[i].type = HR_FREE;
737 reg_temp[i].flags = 0;
742 // get a reg to be used as function arg
743 static int rcache_get_tmp_arg(int arg)
745 int id = rcache_get_arg_id(arg);
746 reg_temp[id].type = HR_TEMP;
748 return reg_temp[id].hreg;
751 // same but caches a reg. RC_GR_READ only.
752 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
754 int i, srcr, dstr, dstid;
755 int dirty = 0, src_dirty = 0;
757 dstid = rcache_get_arg_id(arg);
758 dstr = reg_temp[dstid].hreg;
760 // maybe already statically mapped?
761 srcr = get_reg_static(r, RC_GR_READ);
765 // maybe already cached?
766 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
767 if ((reg_temp[i].type == HR_CACHED) &&
768 reg_temp[i].greg == r)
770 srcr = reg_temp[i].hreg;
771 if (reg_temp[i].flags & HRF_DIRTY)
779 if (gconst_check(r)) {
780 if (gconst_try_read(srcr, r))
784 emith_ctx_read(srcr, r * 4);
788 emith_move_r_r(dstr, srcr);
794 // must clean, callers might want to modify the arg before call
795 emith_ctx_write(dstr, r * 4);
798 reg_temp[dstid].flags |= HRF_DIRTY;
801 reg_temp[dstid].stamp = ++rcache_counter;
802 reg_temp[dstid].type = HR_CACHED;
803 reg_temp[dstid].greg = r;
804 reg_temp[dstid].flags |= HRF_LOCKED;
808 static void rcache_free_tmp(int hr)
811 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
812 if (reg_temp[i].hreg == hr)
815 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
816 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
820 reg_temp[i].type = HR_FREE;
821 reg_temp[i].flags = 0;
824 static void rcache_unlock(int hr)
827 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
828 if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr)
829 reg_temp[i].flags &= ~HRF_LOCKED;
832 static void rcache_unlock_all(void)
835 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
836 reg_temp[i].flags &= ~HRF_LOCKED;
839 static void rcache_clean(void)
844 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
845 if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) {
847 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
848 reg_temp[i].flags &= ~HRF_DIRTY;
852 static void rcache_invalidate(void)
855 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
856 reg_temp[i].type = HR_FREE;
857 reg_temp[i].flags = 0;
864 static void rcache_flush(void)
870 // ---------------------------------------------------------------
872 static int emit_get_rbase_and_offs(u32 a, u32 *offs)
878 poffs = dr_ctx_get_mem_ptr(a, &mask);
882 // XXX: could use some related reg
883 hr = rcache_get_tmp();
884 emith_ctx_read(hr, poffs);
885 emith_add_r_imm(hr, a & mask & ~0xff);
886 *offs = a & 0xff; // XXX: ARM oriented..
890 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
892 #if PROPAGATE_CONSTANTS
893 gconst_new(dst, imm);
895 int hr = rcache_get_reg(dst, RC_GR_WRITE);
896 emith_move_r_imm(hr, imm);
900 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
902 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
903 int hr_s = rcache_get_reg(src, RC_GR_READ);
905 emith_move_r_r(hr_d, hr_s);
908 // T must be clear, and comparison done just before this
909 static void emit_or_t_if_eq(int srr)
911 EMITH_SJMP_START(DCOND_NE);
912 emith_or_r_imm_c(DCOND_EQ, srr, T);
913 EMITH_SJMP_END(DCOND_NE);
916 // arguments must be ready
917 // reg cache must be clean before call
918 static int emit_memhandler_read_(int size, int ram_check)
921 host_arg2reg(arg0, 0);
925 // must writeback cycles for poll detection stuff
927 if (reg_map_g2h[SHR_SR] != -1)
928 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
930 arg1 = rcache_get_tmp_arg(1);
931 emith_move_r_r(arg1, CONTEXT_REG);
934 if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
935 int tmp = rcache_get_tmp();
936 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
937 emith_cmp_r_imm(tmp, 0x02000000);
940 EMITH_SJMP3_START(DCOND_NE);
941 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
942 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
943 EMITH_SJMP3_MID(DCOND_NE);
944 emith_call_cond(DCOND_NE, sh2_drc_read8);
948 EMITH_SJMP3_START(DCOND_NE);
949 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
950 EMITH_SJMP3_MID(DCOND_NE);
951 emith_call_cond(DCOND_NE, sh2_drc_read16);
955 EMITH_SJMP3_START(DCOND_NE);
956 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
957 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
958 EMITH_SJMP3_MID(DCOND_NE);
959 emith_call_cond(DCOND_NE, sh2_drc_read32);
969 emith_call(sh2_drc_read8);
972 emith_call(sh2_drc_read16);
975 emith_call(sh2_drc_read32);
980 // assuming arg0 and retval reg matches
981 return rcache_get_tmp_arg(0);
984 static int emit_memhandler_read(int size)
986 return emit_memhandler_read_(size, 1);
989 static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size)
991 int hr, hr2, ram_check = 1;
994 if (gconst_get(rs, &val)) {
995 hr = emit_get_rbase_and_offs(val + offs, &offs2);
997 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1000 emith_read8_r_r_offs(hr2, hr, offs2 ^ 1);
1001 emith_sext(hr2, hr2, 8);
1004 emith_read16_r_r_offs(hr2, hr, offs2);
1005 emith_sext(hr2, hr2, 16);
1008 emith_read_r_r_offs(hr2, hr, offs2);
1009 emith_ror(hr2, hr2, 16);
1012 rcache_free_tmp(hr);
1019 hr = rcache_get_reg_arg(0, rs);
1021 emith_add_r_imm(hr, offs);
1022 hr = emit_memhandler_read_(size, ram_check);
1023 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1025 emith_sext(hr2, hr, (size == 1) ? 16 : 8);
1027 emith_move_r_r(hr2, hr);
1028 rcache_free_tmp(hr);
1033 static void emit_memhandler_write(int size, u32 pc, int delay)
1036 host_arg2reg(ctxr, 2);
1039 // XXX: consider inlining sh2_drc_write8
1041 emith_call(sh2_drc_write8_slot);
1043 emit_move_r_imm32(SHR_PC, pc);
1045 emith_call(sh2_drc_write8);
1050 emith_call(sh2_drc_write16_slot);
1052 emit_move_r_imm32(SHR_PC, pc);
1054 emith_call(sh2_drc_write16);
1058 emith_move_r_r(ctxr, CONTEXT_REG);
1059 emith_call(sh2_drc_write32);
1062 rcache_invalidate();
1066 static int emit_indirect_indexed_read(int rx, int ry, int size)
1069 a0 = rcache_get_reg_arg(0, rx);
1070 t = rcache_get_reg(ry, RC_GR_READ);
1071 emith_add_r_r(a0, t);
1072 return emit_memhandler_read(size);
1076 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
1080 rcache_get_reg_arg(0, rn);
1081 tmp = emit_memhandler_read(size);
1082 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
1083 rcache_free_tmp(tmp);
1084 tmp = rcache_get_reg(rn, RC_GR_RMW);
1085 emith_add_r_imm(tmp, 1 << size);
1088 rcache_get_reg_arg(0, rm);
1089 *rmr = emit_memhandler_read(size);
1090 *rnr = rcache_get_tmp();
1091 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
1092 tmp = rcache_get_reg(rm, RC_GR_RMW);
1093 emith_add_r_imm(tmp, 1 << size);
1097 static void emit_do_static_regs(int is_write, int tmpr)
1101 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
1106 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
1107 if (reg_map_g2h[i + 1] != r + 1)
1113 // i, r point to last item
1115 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1117 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1120 emith_ctx_write(r, i * 4);
1122 emith_ctx_read(r, i * 4);
1127 static void emit_block_entry(void)
1129 int arg0, arg1, arg2;
1131 host_arg2reg(arg0, 0);
1132 host_arg2reg(arg1, 1);
1133 host_arg2reg(arg2, 2);
1135 #if (DRC_DEBUG & 8) || defined(PDB)
1136 emit_do_static_regs(1, arg2);
1137 emith_move_r_r(arg1, CONTEXT_REG);
1138 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
1139 emith_call(sh2_drc_log_entry);
1140 rcache_invalidate();
1142 emith_tst_r_r(arg0, arg0);
1143 EMITH_SJMP_START(DCOND_EQ);
1144 emith_jump_reg_c(DCOND_NE, arg0);
1145 EMITH_SJMP_END(DCOND_EQ);
1148 #define DELAYED_OP \
1151 #define DELAY_SAVE_T(sr) { \
1152 emith_bic_r_imm(sr, T_save); \
1153 emith_tst_r_imm(sr, T); \
1154 EMITH_SJMP_START(DCOND_EQ); \
1155 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
1156 EMITH_SJMP_END(DCOND_EQ); \
1157 drcf.use_saved_t = 1; \
1160 #define FLUSH_CYCLES(sr) \
1162 emith_sub_r_imm(sr, cycles << 12); \
1166 #define CHECK_UNHANDLED_BITS(mask) { \
1167 if ((op & (mask)) != 0) \
1171 #define FETCH_OP(pc) \
1172 dr_pc_base[(pc) / 2]
1174 #define FETCH32(a) \
1175 ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
1180 #define GET_Rm GET_Fx
1185 #define CHECK_FX_LT(n) \
1186 if (GET_Fx() >= n) \
1189 // op_flags: data from 1st pass
1190 #define OP_FLAGS(pc) op_flags[((pc) - base_pc) / 2]
1191 #define OF_DELAY_OP (1 << 0)
1193 static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
1195 // XXX: maybe use structs instead?
1196 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
1197 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
1198 int branch_target_blkid[MAX_LOCAL_BRANCHES];
1199 int branch_target_count = 0;
1200 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
1201 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
1202 int branch_patch_count = 0;
1203 u32 literal_addr[MAX_LITERALS];
1204 int literal_addr_count = 0;
1205 int pending_branch_cond = -1;
1206 int pending_branch_pc = 0;
1207 u8 op_flags[BLOCK_CYCLE_LIMIT + 1];
1211 u32 use_saved_t:1; // delayed op modifies T
1214 // PC of current, first, last, last_target_blk SH2 insn
1215 u32 pc, base_pc, end_pc, out_pc;
1217 block_desc *this_block;
1228 // get base/validate PC
1229 dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave);
1230 if (dr_pc_base == (void *)-1) {
1231 printf("invalid PC, aborting: %08x\n", base_pc);
1232 // FIXME: be less destructive
1236 tcache_ptr = tcache_ptrs[tcache_id];
1237 this_block = dr_add_block(base_pc, sh2->is_slave, &blkid_main);
1238 if (this_block == NULL)
1241 // predict tcache overflow
1242 tmp = tcache_ptr - tcache_bases[tcache_id];
1243 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
1244 dbg(1, "tcache %d overflow", tcache_id);
1248 block_entry = tcache_ptr;
1249 dbg(2, "== %csh2 block #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
1250 tcache_id, blkid_main, base_pc, block_entry);
1252 dr_link_blocks(tcache_ptr, base_pc, tcache_id);
1254 // 1st pass: scan forward for local branches
1255 memset(op_flags, 0, sizeof(op_flags));
1256 for (cycles = 0, pc = base_pc; cycles < BLOCK_CYCLE_LIMIT; cycles++, pc += 2) {
1258 if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR
1259 signed int offs = ((signed int)(op << 20) >> 19);
1261 OP_FLAGS(pc) |= OF_DELAY_OP;
1262 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 2,);
1265 if ((op & 0xf000) == 0) {
1267 if (op == 0x1b) // SLEEP
1269 if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) { // BRAF, BSRF, RTS, RTE
1271 OP_FLAGS(pc) |= OF_DELAY_OP;
1276 if ((op & 0xf0df) == 0x400b) { // JMP, JSR
1278 OP_FLAGS(pc) |= OF_DELAY_OP;
1281 if ((op & 0xf900) == 0x8900) { // BT(S), BF(S)
1282 signed int offs = ((signed int)(op << 24) >> 23);
1284 OP_FLAGS(pc + 2) |= OF_DELAY_OP;
1285 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc + offs + 4, break);
1287 if ((op & 0xff00) == 0xc300) // TRAPA
1293 // clean branch_targets that are not really local,
1294 // and that land on delay slots
1295 for (i = 0, tmp = 0; i < branch_target_count; i++) {
1296 pc = branch_target_pc[i];
1297 if (base_pc <= pc && pc <= end_pc && !(OP_FLAGS(pc) & OF_DELAY_OP))
1298 branch_target_pc[tmp++] = branch_target_pc[i];
1300 branch_target_count = tmp;
1301 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
1302 memset(branch_target_blkid, 0, sizeof(branch_target_blkid[0]) * branch_target_count);
1304 // -------------------------------------------------
1305 // 2nd pass: actual compilation
1308 for (cycles = 0; pc <= end_pc || drcf.delayed_op; )
1312 if (drcf.delayed_op > 0)
1317 i = find_in_array(branch_target_pc, branch_target_count, pc);
1318 if (i >= 0 || pc == base_pc)
1322 /* make "subblock" - just a mid-block entry */
1323 block_desc *subblock;
1325 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1327 // decide if to flush rcache
1328 if ((op & 0xf0ff) == 0x4010 && FETCH_OP(pc + 2) == 0x8bfd) // DT; BF #-2
1332 do_host_disasm(tcache_id);
1334 dbg(2, "-- %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
1335 tcache_id, branch_target_blkid[i], pc, tcache_ptr);
1337 subblock = dr_add_block(pc, sh2->is_slave, &branch_target_blkid[i]);
1338 if (subblock == NULL)
1341 // since we made a block entry, link any other blocks that jump to current pc
1342 dr_link_blocks(tcache_ptr, pc, tcache_id);
1345 branch_target_ptr[i] = tcache_ptr;
1348 emit_move_r_imm32(SHR_PC, pc);
1352 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1353 emith_cmp_r_imm(sr, 0);
1354 emith_jump_cond(DCOND_LE, sh2_drc_exit);
1355 do_host_disasm(tcache_id);
1356 rcache_unlock_all();
1362 DasmSH2(sh2dasm_buff, pc, op);
1363 printf("%08x %04x %s\n", pc, op, sh2dasm_buff);
1375 switch ((op >> 12) & 0x0f)
1377 /////////////////////////////////////////////
1382 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1385 case 0: // STC SR,Rn 0000nnnn00000010
1388 case 1: // STC GBR,Rn 0000nnnn00010010
1391 case 2: // STC VBR,Rn 0000nnnn00100010
1397 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
1398 emith_move_r_r(tmp, tmp3);
1400 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
1403 CHECK_UNHANDLED_BITS(0xd0);
1404 // BRAF Rm 0000mmmm00100011
1405 // BSRF Rm 0000mmmm00000011
1407 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1408 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1409 emith_move_r_r(tmp, tmp2);
1411 emith_add_r_imm(tmp, pc + 2);
1413 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
1414 emith_move_r_imm(tmp3, pc + 2);
1415 emith_add_r_r(tmp, tmp3);
1420 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
1421 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
1422 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
1424 tmp = rcache_get_reg_arg(1, GET_Rm());
1425 tmp2 = rcache_get_reg_arg(0, SHR_R0);
1426 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1427 emith_add_r_r(tmp2, tmp3);
1428 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1431 // MUL.L Rm,Rn 0000nnnnmmmm0111
1432 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1433 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1434 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1435 emith_mul(tmp3, tmp2, tmp);
1439 CHECK_UNHANDLED_BITS(0xf00);
1442 case 0: // CLRT 0000000000001000
1443 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1444 if (drcf.delayed_op)
1446 emith_bic_r_imm(sr, T);
1448 case 1: // SETT 0000000000011000
1449 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1450 if (drcf.delayed_op)
1452 emith_or_r_imm(sr, T);
1454 case 2: // CLRMAC 0000000000101000
1455 emit_move_r_imm32(SHR_MACL, 0);
1456 emit_move_r_imm32(SHR_MACH, 0);
1465 case 0: // NOP 0000000000001001
1466 CHECK_UNHANDLED_BITS(0xf00);
1468 case 1: // DIV0U 0000000000011001
1469 CHECK_UNHANDLED_BITS(0xf00);
1470 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1471 if (drcf.delayed_op)
1473 emith_bic_r_imm(sr, M|Q|T);
1475 case 2: // MOVT Rn 0000nnnn00101001
1476 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1477 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1478 emith_clear_msb(tmp2, sr, 31);
1485 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1488 case 0: // STS MACH,Rn 0000nnnn00001010
1491 case 1: // STS MACL,Rn 0000nnnn00011010
1494 case 2: // STS PR,Rn 0000nnnn00101010
1500 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1501 emith_move_r_r(tmp, tmp2);
1504 CHECK_UNHANDLED_BITS(0xf00);
1507 case 0: // RTS 0000000000001011
1509 emit_move_r_r(SHR_PC, SHR_PR);
1513 case 1: // SLEEP 0000000000011011
1514 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
1515 emith_clear_msb(tmp, tmp, 20); // clear cycles
1516 out_pc = out_pc - 2;
1519 case 2: // RTE 0000000000101011
1522 emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2);
1524 tmp = rcache_get_reg_arg(0, SHR_SP);
1525 emith_add_r_imm(tmp, 4);
1526 tmp = emit_memhandler_read(2);
1527 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1528 emith_write_sr(sr, tmp);
1529 rcache_free_tmp(tmp);
1530 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1531 emith_add_r_imm(tmp, 4*2);
1540 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1541 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1542 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1543 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1544 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1545 if ((op & 3) != 2) {
1546 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1548 emith_move_r_r(tmp2, tmp);
1549 rcache_free_tmp(tmp);
1551 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1552 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1553 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1554 /* MS 16 MAC bits unused if saturated */
1555 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1556 emith_tst_r_imm(sr, S);
1557 EMITH_SJMP_START(DCOND_EQ);
1558 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1559 EMITH_SJMP_END(DCOND_EQ);
1561 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1562 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1563 rcache_free_tmp(tmp2);
1564 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1565 emith_tst_r_imm(sr, S);
1567 EMITH_JMP_START(DCOND_EQ);
1568 emith_asr(tmp, tmp4, 15);
1569 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1570 EMITH_SJMP_START(DCOND_GE);
1571 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1572 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1573 EMITH_SJMP_END(DCOND_GE);
1574 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1575 EMITH_SJMP_START(DCOND_LE);
1576 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1577 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1578 EMITH_SJMP_END(DCOND_LE);
1579 EMITH_JMP_END(DCOND_EQ);
1581 rcache_free_tmp(tmp);
1587 /////////////////////////////////////////////
1589 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1591 tmp = rcache_get_reg_arg(0, GET_Rn());
1592 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1594 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1595 emit_memhandler_write(2, pc, drcf.delayed_op);
1601 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1602 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1603 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1605 rcache_get_reg_arg(0, GET_Rn());
1606 rcache_get_reg_arg(1, GET_Rm());
1607 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1609 case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
1610 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
1611 case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110
1612 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1613 emith_sub_r_imm(tmp, (1 << (op & 3)));
1615 rcache_get_reg_arg(0, GET_Rn());
1616 rcache_get_reg_arg(1, GET_Rm());
1617 emit_memhandler_write(op & 3, pc, drcf.delayed_op);
1619 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1620 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1621 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1622 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1623 if (drcf.delayed_op)
1625 emith_bic_r_imm(sr, M|Q|T);
1626 emith_tst_r_imm(tmp2, (1<<31));
1627 EMITH_SJMP_START(DCOND_EQ);
1628 emith_or_r_imm_c(DCOND_NE, sr, Q);
1629 EMITH_SJMP_END(DCOND_EQ);
1630 emith_tst_r_imm(tmp3, (1<<31));
1631 EMITH_SJMP_START(DCOND_EQ);
1632 emith_or_r_imm_c(DCOND_NE, sr, M);
1633 EMITH_SJMP_END(DCOND_EQ);
1634 emith_teq_r_r(tmp2, tmp3);
1635 EMITH_SJMP_START(DCOND_PL);
1636 emith_or_r_imm_c(DCOND_MI, sr, T);
1637 EMITH_SJMP_END(DCOND_PL);
1639 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1640 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1641 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1642 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1643 if (drcf.delayed_op)
1645 emith_bic_r_imm(sr, T);
1646 emith_tst_r_r(tmp2, tmp3);
1647 emit_or_t_if_eq(sr);
1649 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1650 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1651 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1652 emith_and_r_r(tmp, tmp2);
1654 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1655 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1656 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1657 emith_eor_r_r(tmp, tmp2);
1659 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1660 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1661 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1662 emith_or_r_r(tmp, tmp2);
1664 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1665 tmp = rcache_get_tmp();
1666 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1667 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1668 emith_eor_r_r_r(tmp, tmp2, tmp3);
1669 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1670 if (drcf.delayed_op)
1672 emith_bic_r_imm(sr, T);
1673 emith_tst_r_imm(tmp, 0x000000ff);
1674 emit_or_t_if_eq(tmp);
1675 emith_tst_r_imm(tmp, 0x0000ff00);
1676 emit_or_t_if_eq(tmp);
1677 emith_tst_r_imm(tmp, 0x00ff0000);
1678 emit_or_t_if_eq(tmp);
1679 emith_tst_r_imm(tmp, 0xff000000);
1680 emit_or_t_if_eq(tmp);
1681 rcache_free_tmp(tmp);
1683 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1684 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1685 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1686 emith_lsr(tmp, tmp, 16);
1687 emith_or_r_r_lsl(tmp, tmp2, 16);
1689 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1690 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1691 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1692 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1694 emith_sext(tmp, tmp2, 16);
1696 emith_clear_msb(tmp, tmp2, 16);
1697 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1698 tmp2 = rcache_get_tmp();
1700 emith_sext(tmp2, tmp3, 16);
1702 emith_clear_msb(tmp2, tmp3, 16);
1703 emith_mul(tmp, tmp, tmp2);
1704 rcache_free_tmp(tmp2);
1705 // FIXME: causes timing issues in Doom?
1711 /////////////////////////////////////////////
1715 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
1716 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
1717 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
1718 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
1719 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
1720 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1721 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1722 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1723 if (drcf.delayed_op)
1725 emith_bic_r_imm(sr, T);
1726 emith_cmp_r_r(tmp2, tmp3);
1729 case 0x00: // CMP/EQ
1730 emit_or_t_if_eq(sr);
1732 case 0x02: // CMP/HS
1733 EMITH_SJMP_START(DCOND_LO);
1734 emith_or_r_imm_c(DCOND_HS, sr, T);
1735 EMITH_SJMP_END(DCOND_LO);
1737 case 0x03: // CMP/GE
1738 EMITH_SJMP_START(DCOND_LT);
1739 emith_or_r_imm_c(DCOND_GE, sr, T);
1740 EMITH_SJMP_END(DCOND_LT);
1742 case 0x06: // CMP/HI
1743 EMITH_SJMP_START(DCOND_LS);
1744 emith_or_r_imm_c(DCOND_HI, sr, T);
1745 EMITH_SJMP_END(DCOND_LS);
1747 case 0x07: // CMP/GT
1748 EMITH_SJMP_START(DCOND_LE);
1749 emith_or_r_imm_c(DCOND_GT, sr, T);
1750 EMITH_SJMP_END(DCOND_LE);
1754 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
1755 // Q1 = carry(Rn = (Rn << 1) | T)
1757 // Q2 = carry(Rn += Rm)
1759 // Q2 = carry(Rn -= Rm)
1761 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
1762 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1763 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1764 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1765 if (drcf.delayed_op)
1767 emith_tpop_carry(sr, 0);
1768 emith_adcf_r_r(tmp2, tmp2);
1769 emith_tpush_carry(sr, 0); // keep Q1 in T for now
1770 tmp4 = rcache_get_tmp();
1771 emith_and_r_r_imm(tmp4, sr, M);
1772 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
1773 rcache_free_tmp(tmp4);
1774 // add or sub, invert T if carry to get Q1 ^ Q2
1775 // in: (Q ^ M) passed in Q, Q1 in T
1776 emith_sh2_div1_step(tmp2, tmp3, sr);
1777 emith_bic_r_imm(sr, Q);
1778 emith_tst_r_imm(sr, M);
1779 EMITH_SJMP_START(DCOND_EQ);
1780 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
1781 EMITH_SJMP_END(DCOND_EQ);
1782 emith_tst_r_imm(sr, T);
1783 EMITH_SJMP_START(DCOND_EQ);
1784 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
1785 EMITH_SJMP_END(DCOND_EQ);
1786 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
1788 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
1789 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1790 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1791 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1792 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1793 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
1795 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
1796 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
1797 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1798 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1800 emith_add_r_r(tmp, tmp2);
1802 emith_sub_r_r(tmp, tmp2);
1804 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
1805 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
1806 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1807 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1808 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1809 if (drcf.delayed_op)
1811 if (op & 4) { // adc
1812 emith_tpop_carry(sr, 0);
1813 emith_adcf_r_r(tmp, tmp2);
1814 emith_tpush_carry(sr, 0);
1816 emith_tpop_carry(sr, 1);
1817 emith_sbcf_r_r(tmp, tmp2);
1818 emith_tpush_carry(sr, 1);
1821 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
1822 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
1823 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1824 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1825 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1826 if (drcf.delayed_op)
1828 emith_bic_r_imm(sr, T);
1830 emith_addf_r_r(tmp, tmp2);
1832 emith_subf_r_r(tmp, tmp2);
1833 EMITH_SJMP_START(DCOND_VC);
1834 emith_or_r_imm_c(DCOND_VS, sr, T);
1835 EMITH_SJMP_END(DCOND_VC);
1837 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
1838 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1839 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1840 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1841 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1842 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
1847 /////////////////////////////////////////////
1854 case 0: // SHLL Rn 0100nnnn00000000
1855 case 2: // SHAL Rn 0100nnnn00100000
1856 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1857 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1858 if (drcf.delayed_op)
1860 emith_tpop_carry(sr, 0); // dummy
1861 emith_lslf(tmp, tmp, 1);
1862 emith_tpush_carry(sr, 0);
1864 case 1: // DT Rn 0100nnnn00010000
1865 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1866 if (drcf.delayed_op)
1868 if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
1869 if (gconst_get(GET_Rn(), &tmp)) {
1870 // XXX: limit burned cycles
1871 emit_move_r_imm32(GET_Rn(), 0);
1872 emith_or_r_imm(sr, T);
1873 cycles += tmp * 4 + 1; // +1 syncs with noconst version, not sure why
1877 emith_sh2_dtbf_loop();
1880 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1881 emith_bic_r_imm(sr, T);
1882 emith_subf_r_imm(tmp, 1);
1883 emit_or_t_if_eq(sr);
1890 case 0: // SHLR Rn 0100nnnn00000001
1891 case 2: // SHAR Rn 0100nnnn00100001
1892 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1893 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1894 if (drcf.delayed_op)
1896 emith_tpop_carry(sr, 0); // dummy
1898 emith_asrf(tmp, tmp, 1);
1900 emith_lsrf(tmp, tmp, 1);
1901 emith_tpush_carry(sr, 0);
1903 case 1: // CMP/PZ Rn 0100nnnn00010001
1904 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1905 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1906 if (drcf.delayed_op)
1908 emith_bic_r_imm(sr, T);
1909 emith_cmp_r_imm(tmp, 0);
1910 EMITH_SJMP_START(DCOND_LT);
1911 emith_or_r_imm_c(DCOND_GE, sr, T);
1912 EMITH_SJMP_END(DCOND_LT);
1920 case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
1923 case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
1926 case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
1929 case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
1932 case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
1935 case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
1941 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1942 emith_sub_r_imm(tmp2, 4);
1944 rcache_get_reg_arg(0, GET_Rn());
1945 tmp3 = rcache_get_reg_arg(1, tmp);
1947 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
1948 emit_memhandler_write(2, pc, drcf.delayed_op);
1954 case 0x04: // ROTL Rn 0100nnnn00000100
1955 case 0x05: // ROTR Rn 0100nnnn00000101
1956 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1957 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1958 if (drcf.delayed_op)
1960 emith_tpop_carry(sr, 0); // dummy
1962 emith_rorf(tmp, tmp, 1);
1964 emith_rolf(tmp, tmp, 1);
1965 emith_tpush_carry(sr, 0);
1967 case 0x24: // ROTCL Rn 0100nnnn00100100
1968 case 0x25: // ROTCR Rn 0100nnnn00100101
1969 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1970 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1971 if (drcf.delayed_op)
1973 emith_tpop_carry(sr, 0);
1978 emith_tpush_carry(sr, 0);
1980 case 0x15: // CMP/PL Rn 0100nnnn00010101
1981 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1982 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1983 if (drcf.delayed_op)
1985 emith_bic_r_imm(sr, T);
1986 emith_cmp_r_imm(tmp, 0);
1987 EMITH_SJMP_START(DCOND_LE);
1988 emith_or_r_imm_c(DCOND_GT, sr, T);
1989 EMITH_SJMP_END(DCOND_LE);
1997 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
2000 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
2003 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
2006 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
2009 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
2012 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
2018 rcache_get_reg_arg(0, GET_Rn());
2019 tmp2 = emit_memhandler_read(2);
2020 if (tmp == SHR_SR) {
2021 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2022 if (drcf.delayed_op)
2024 emith_write_sr(sr, tmp2);
2027 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
2028 emith_move_r_r(tmp, tmp2);
2030 rcache_free_tmp(tmp2);
2031 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2032 emith_add_r_imm(tmp, 4);
2039 // SHLL2 Rn 0100nnnn00001000
2040 // SHLR2 Rn 0100nnnn00001001
2044 // SHLL8 Rn 0100nnnn00011000
2045 // SHLR8 Rn 0100nnnn00011001
2049 // SHLL16 Rn 0100nnnn00101000
2050 // SHLR16 Rn 0100nnnn00101001
2056 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2058 emith_lsr(tmp2, tmp2, tmp);
2060 emith_lsl(tmp2, tmp2, tmp);
2065 case 0: // LDS Rm,MACH 0100mmmm00001010
2068 case 1: // LDS Rm,MACL 0100mmmm00011010
2071 case 2: // LDS Rm,PR 0100mmmm00101010
2077 emit_move_r_r(tmp2, GET_Rn());
2082 case 0: // JSR @Rm 0100mmmm00001011
2083 case 2: // JMP @Rm 0100mmmm00101011
2086 emit_move_r_imm32(SHR_PR, pc + 2);
2087 emit_move_r_r(SHR_PC, (op >> 8) & 0x0f);
2091 case 1: // TAS.B @Rn 0100nnnn00011011
2092 // XXX: is TAS working on 32X?
2093 rcache_get_reg_arg(0, GET_Rn());
2094 tmp = emit_memhandler_read(0);
2095 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2096 if (drcf.delayed_op)
2098 emith_bic_r_imm(sr, T);
2099 emith_cmp_r_imm(tmp, 0);
2100 emit_or_t_if_eq(sr);
2102 emith_or_r_imm(tmp, 0x80);
2103 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
2104 emith_move_r_r(tmp2, tmp);
2105 rcache_free_tmp(tmp);
2106 rcache_get_reg_arg(0, GET_Rn());
2107 emit_memhandler_write(0, pc, drcf.delayed_op);
2115 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2118 case 0: // LDC Rm,SR 0100mmmm00001110
2121 case 1: // LDC Rm,GBR 0100mmmm00011110
2124 case 2: // LDC Rm,VBR 0100mmmm00101110
2130 if (tmp2 == SHR_SR) {
2131 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2132 if (drcf.delayed_op)
2134 emith_write_sr(sr, tmp);
2137 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
2138 emith_move_r_r(tmp2, tmp);
2142 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
2143 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
2144 emith_sext(tmp, tmp, 16);
2145 emith_sext(tmp2, tmp2, 16);
2146 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
2147 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
2148 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
2149 rcache_free_tmp(tmp2);
2150 // XXX: MACH should be untouched when S is set?
2151 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2152 emith_tst_r_imm(sr, S);
2153 EMITH_JMP_START(DCOND_EQ);
2155 emith_asr(tmp, tmp3, 31);
2156 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
2157 EMITH_JMP_START(DCOND_EQ);
2158 emith_move_r_imm(tmp3, 0x80000000);
2159 emith_tst_r_r(tmp4, tmp4);
2160 EMITH_SJMP_START(DCOND_MI);
2161 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
2162 EMITH_SJMP_END(DCOND_MI);
2163 EMITH_JMP_END(DCOND_EQ);
2165 EMITH_JMP_END(DCOND_EQ);
2166 rcache_free_tmp(tmp);
2172 /////////////////////////////////////////////
2174 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
2175 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2);
2178 /////////////////////////////////////////////
2182 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
2183 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
2184 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
2185 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
2186 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
2187 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
2188 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), 0, op & 3);
2189 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
2190 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
2191 emith_add_r_imm(tmp, (1 << (op & 3)));
2196 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
2197 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2200 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
2201 emith_move_r_r(tmp2, tmp);
2203 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
2204 emith_mvn_r_r(tmp2, tmp);
2206 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
2209 tmp3 = rcache_get_tmp();
2210 tmp4 = rcache_get_tmp();
2211 emith_lsr(tmp3, tmp, 16);
2212 emith_or_r_r_lsl(tmp3, tmp, 24);
2213 emith_and_r_r_imm(tmp4, tmp, 0xff00);
2214 emith_or_r_r_lsl(tmp3, tmp4, 8);
2215 emith_rol(tmp2, tmp3, 16);
2216 rcache_free_tmp(tmp4);
2218 rcache_free_tmp(tmp3);
2220 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
2221 emith_rol(tmp2, tmp, 16);
2223 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
2224 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2225 if (drcf.delayed_op)
2227 emith_tpop_carry(sr, 1);
2228 emith_negcf_r_r(tmp2, tmp);
2229 emith_tpush_carry(sr, 1);
2231 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
2232 emith_neg_r_r(tmp2, tmp);
2234 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
2235 emith_clear_msb(tmp2, tmp, 24);
2237 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
2238 emith_clear_msb(tmp2, tmp, 16);
2240 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
2241 emith_sext(tmp2, tmp, 8);
2243 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
2244 emith_sext(tmp2, tmp, 16);
2251 /////////////////////////////////////////////
2253 // ADD #imm,Rn 0111nnnniiiiiiii
2254 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2255 if (op & 0x80) { // adding negative
2256 emith_sub_r_imm(tmp, -op & 0xff);
2258 emith_add_r_imm(tmp, op & 0xff);
2261 /////////////////////////////////////////////
2263 switch (op & 0x0f00)
2265 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
2266 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
2268 tmp = rcache_get_reg_arg(0, GET_Rm());
2269 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2270 tmp3 = (op & 0x100) >> 8;
2272 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
2273 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
2275 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
2276 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
2277 tmp = (op & 0x100) >> 8;
2278 emit_memhandler_read_rr(SHR_R0, GET_Rm(), (op & 0x0f) << tmp, tmp);
2280 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
2281 // XXX: could use cmn
2282 tmp = rcache_get_tmp();
2283 tmp2 = rcache_get_reg(0, RC_GR_READ);
2284 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2285 if (drcf.delayed_op)
2287 emith_move_r_imm_s8(tmp, op & 0xff);
2288 emith_bic_r_imm(sr, T);
2289 emith_cmp_r_r(tmp2, tmp);
2290 emit_or_t_if_eq(sr);
2291 rcache_free_tmp(tmp);
2293 case 0x0d00: // BT/S label 10001101dddddddd
2294 case 0x0f00: // BF/S label 10001111dddddddd
2298 case 0x0900: // BT label 10001001dddddddd
2299 case 0x0b00: // BF label 10001011dddddddd
2300 // will handle conditional branches later
2301 pending_branch_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE;
2302 i = ((signed int)(op << 24) >> 23);
2303 pending_branch_pc = pc + i + 2;
2309 /////////////////////////////////////////////
2311 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
2312 tmp = pc + (op & 0xff) * 2 + 2;
2313 #if PROPAGATE_CONSTANTS
2314 if (tmp < end_pc + MAX_LITERAL_OFFSET && literal_addr_count < MAX_LITERALS) {
2315 ADD_TO_ARRAY(literal_addr, literal_addr_count, tmp,);
2316 gconst_new(GET_Rn(), (u32)(int)(signed short)FETCH_OP(tmp));
2321 tmp2 = rcache_get_tmp_arg(0);
2322 emith_move_r_imm(tmp2, tmp);
2323 tmp2 = emit_memhandler_read(1);
2324 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2325 emith_sext(tmp3, tmp2, 16);
2326 rcache_free_tmp(tmp2);
2330 /////////////////////////////////////////////
2332 // BRA label 1010dddddddddddd
2334 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2335 tmp = ((signed int)(op << 20) >> 19);
2336 out_pc = pc + tmp + 2;
2338 emith_clear_msb(sr, sr, 20); // burn cycles
2342 /////////////////////////////////////////////
2344 // BSR label 1011dddddddddddd
2346 emit_move_r_imm32(SHR_PR, pc + 2);
2347 tmp = ((signed int)(op << 20) >> 19);
2348 out_pc = pc + tmp + 2;
2352 /////////////////////////////////////////////
2354 switch (op & 0x0f00)
2356 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
2357 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
2358 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
2360 tmp = rcache_get_reg_arg(0, SHR_GBR);
2361 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2362 tmp3 = (op & 0x300) >> 8;
2363 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
2364 emit_memhandler_write(tmp3, pc, drcf.delayed_op);
2366 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
2367 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
2368 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
2369 tmp = (op & 0x300) >> 8;
2370 emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp);
2372 case 0x0300: // TRAPA #imm 11000011iiiiiiii
2373 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2374 emith_sub_r_imm(tmp, 4*2);
2376 tmp = rcache_get_reg_arg(0, SHR_SP);
2377 emith_add_r_imm(tmp, 4);
2378 tmp = rcache_get_reg_arg(1, SHR_SR);
2379 emith_clear_msb(tmp, tmp, 22);
2380 emit_memhandler_write(2, pc, drcf.delayed_op);
2382 rcache_get_reg_arg(0, SHR_SP);
2383 tmp = rcache_get_tmp_arg(1);
2384 emith_move_r_imm(tmp, pc);
2385 emit_memhandler_write(2, pc, drcf.delayed_op);
2387 emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
2391 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
2392 emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3);
2394 case 0x0800: // TST #imm,R0 11001000iiiiiiii
2395 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
2396 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2397 if (drcf.delayed_op)
2399 emith_bic_r_imm(sr, T);
2400 emith_tst_r_imm(tmp, op & 0xff);
2401 emit_or_t_if_eq(sr);
2403 case 0x0900: // AND #imm,R0 11001001iiiiiiii
2404 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2405 emith_and_r_imm(tmp, op & 0xff);
2407 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
2408 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2409 emith_eor_r_imm(tmp, op & 0xff);
2411 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
2412 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2413 emith_or_r_imm(tmp, op & 0xff);
2415 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
2416 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2417 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2418 if (drcf.delayed_op)
2420 emith_bic_r_imm(sr, T);
2421 emith_tst_r_imm(tmp, op & 0xff);
2422 emit_or_t_if_eq(sr);
2423 rcache_free_tmp(tmp);
2426 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2427 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2428 emith_and_r_imm(tmp, op & 0xff);
2430 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2431 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2432 emith_eor_r_imm(tmp, op & 0xff);
2434 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2435 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2436 emith_or_r_imm(tmp, op & 0xff);
2438 tmp2 = rcache_get_tmp_arg(1);
2439 emith_move_r_r(tmp2, tmp);
2440 rcache_free_tmp(tmp);
2441 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2442 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2443 emith_add_r_r(tmp3, tmp4);
2444 emit_memhandler_write(0, pc, drcf.delayed_op);
2450 /////////////////////////////////////////////
2452 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
2453 tmp = (pc + (op & 0xff) * 4 + 2) & ~3;
2454 #if PROPAGATE_CONSTANTS
2455 if (tmp < end_pc + MAX_LITERAL_OFFSET && literal_addr_count < MAX_LITERALS) {
2456 ADD_TO_ARRAY(literal_addr, literal_addr_count, tmp,);
2457 gconst_new(GET_Rn(), FETCH32(tmp));
2462 tmp2 = rcache_get_tmp_arg(0);
2463 emith_move_r_imm(tmp2, tmp);
2464 tmp2 = emit_memhandler_read(2);
2465 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2466 emith_move_r_r(tmp3, tmp2);
2467 rcache_free_tmp(tmp2);
2471 /////////////////////////////////////////////
2473 // MOV #imm,Rn 1110nnnniiiiiiii
2474 emit_move_r_imm32(GET_Rn(), (u32)(signed int)(signed char)op);
2479 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
2480 sh2->is_slave ? 's' : 'm', op, pc - 2);
2481 #ifdef DRC_DEBUG_INTERP
2482 emit_move_r_imm32(SHR_PC, pc - 2);
2484 emith_pass_arg_r(0, CONTEXT_REG);
2485 emith_pass_arg_imm(1, op);
2486 emith_call(sh2_do_op);
2492 rcache_unlock_all();
2494 // conditional branch handling (with/without delay)
2495 if (pending_branch_cond != -1 && drcf.delayed_op != 2)
2497 u32 target_pc = pending_branch_pc;
2500 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2504 if (drcf.use_saved_t)
2505 emith_tst_r_imm(sr, T_save);
2507 emith_tst_r_imm(sr, T);
2510 if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0) {
2512 // XXX: jumps back can be linked already
2513 branch_patch_pc[branch_patch_count] = target_pc;
2514 branch_patch_ptr[branch_patch_count] = tcache_ptr;
2515 emith_jump_cond_patchable(pending_branch_cond, tcache_ptr);
2517 branch_patch_count++;
2518 if (branch_patch_count == MAX_LOCAL_BRANCHES) {
2519 dbg(1, "warning: too many local branches");
2526 // can't resolve branch locally, make a block exit
2527 emit_move_r_imm32(SHR_PC, target_pc);
2530 target = dr_prepare_ext_branch(target_pc, sh2, tcache_id);
2533 emith_jump_cond_patchable(pending_branch_cond, target);
2536 drcf.use_saved_t = 0;
2537 pending_branch_cond = -1;
2541 // XXX: delay slots..
2542 if (drcf.test_irq && drcf.delayed_op != 2) {
2543 if (!drcf.delayed_op)
2544 emit_move_r_imm32(SHR_PC, pc);
2545 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2548 emith_call(sh2_drc_test_irq);
2552 do_host_disasm(tcache_id);
2554 if (out_pc != 0 && drcf.delayed_op != 2)
2558 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2562 if (out_pc == (u32)-1) {
2563 // indirect jump -> back to dispatcher
2564 emith_jump(sh2_drc_dispatcher);
2569 emit_move_r_imm32(SHR_PC, out_pc);
2572 target = dr_prepare_ext_branch(out_pc, sh2, tcache_id);
2575 emith_jump_patchable(target);
2578 // link local branches
2579 for (i = 0; i < branch_patch_count; i++) {
2582 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2583 target = branch_target_ptr[t];
2584 if (target == NULL) {
2585 // flush pc and go back to dispatcher (this should no longer happen)
2586 dbg(1, "stray branch to %08x %p", branch_patch_pc[i], tcache_ptr);
2587 target = tcache_ptr;
2588 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2590 emith_jump(sh2_drc_dispatcher);
2592 emith_jump_patch(branch_patch_ptr[i], target);
2597 // mark memory blocks as containing compiled code
2598 // override any overlay blocks as they become unreachable anyway
2599 if (tcache_id != 0 || (this_block->addr & 0xc7fc0000) == 0x06000000)
2601 u16 *drc_ram_blk = NULL;
2602 u32 mask = 0, shift = 0;
2604 if (tcache_id != 0) {
2606 drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave];
2607 shift = SH2_DRCBLK_DA_SHIFT;
2610 else if ((this_block->addr & 0xc7fc0000) == 0x06000000) {
2612 drc_ram_blk = Pico32xMem->drcblk_ram;
2613 shift = SH2_DRCBLK_RAM_SHIFT;
2617 drc_ram_blk[(base_pc >> shift) & mask] = (blkid_main << 1) | 1;
2618 for (pc = base_pc + 2; pc < end_pc; pc += 2)
2619 drc_ram_blk[(pc >> shift) & mask] = blkid_main << 1;
2622 for (i = 0; i < branch_target_count; i++)
2623 if (branch_target_blkid[i] != 0)
2624 drc_ram_blk[(branch_target_pc[i] >> shift) & mask] =
2625 (branch_target_blkid[i] << 1) | 1;
2628 for (i = 0; i < literal_addr_count; i++) {
2629 tmp = literal_addr[i];
2630 drc_ram_blk[(tmp >> shift) & mask] = blkid_main << 1;
2631 if (!(tmp & 3)) // assume long
2632 drc_ram_blk[((tmp + 2) >> shift) & mask] = blkid_main << 1;
2636 tcache_ptrs[tcache_id] = tcache_ptr;
2638 host_instructions_updated(block_entry, tcache_ptr);
2640 do_host_disasm(tcache_id);
2641 dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2642 tcache_id, block_counts[tcache_id],
2643 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2644 insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled);
2645 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2646 dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2649 tcache_dsm_ptrs[tcache_id] = block_entry;
2650 do_host_disasm(tcache_id);
2661 static void sh2_generate_utils(void)
2663 int arg0, arg1, arg2, sr, tmp;
2664 void *sh2_drc_write_end, *sh2_drc_write_slot_end;
2666 sh2_drc_write32 = p32x_sh2_write32;
2667 sh2_drc_read8 = p32x_sh2_read8;
2668 sh2_drc_read16 = p32x_sh2_read16;
2669 sh2_drc_read32 = p32x_sh2_read32;
2671 host_arg2reg(arg0, 0);
2672 host_arg2reg(arg1, 1);
2673 host_arg2reg(arg2, 2);
2674 emith_move_r_r(arg0, arg0); // nop
2676 // sh2_drc_exit(void)
2677 sh2_drc_exit = (void *)tcache_ptr;
2678 emit_do_static_regs(1, arg2);
2679 emith_sh2_drc_exit();
2681 // sh2_drc_dispatcher(void)
2682 sh2_drc_dispatcher = (void *)tcache_ptr;
2683 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2684 emith_cmp_r_imm(sr, 0);
2685 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2686 rcache_invalidate();
2687 emith_ctx_read(arg0, SHR_PC * 4);
2688 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2689 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2690 emith_call(dr_lookup_block);
2692 // lookup failed, call sh2_translate()
2693 emith_move_r_r(arg0, CONTEXT_REG);
2694 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2695 emith_call(sh2_translate);
2697 // sh2_translate() failed, flush cache and retry
2698 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2699 emith_call(flush_tcache);
2700 emith_move_r_r(arg0, CONTEXT_REG);
2701 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2702 emith_call(sh2_translate);
2704 // XXX: can't translate, fail
2707 // sh2_drc_test_irq(void)
2708 // assumes it's called from main function (may jump to dispatcher)
2709 sh2_drc_test_irq = (void *)tcache_ptr;
2710 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2711 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2712 emith_lsr(arg0, sr, I_SHIFT);
2713 emith_and_r_imm(arg0, 0x0f);
2714 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2715 EMITH_SJMP_START(DCOND_GT);
2716 emith_ret_c(DCOND_LE); // nope, return
2717 EMITH_SJMP_END(DCOND_GT);
2719 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2720 emith_sub_r_imm(tmp, 4*2);
2723 tmp = rcache_get_reg_arg(0, SHR_SP);
2724 emith_add_r_imm(tmp, 4);
2725 tmp = rcache_get_reg_arg(1, SHR_SR);
2726 emith_clear_msb(tmp, tmp, 22);
2727 emith_move_r_r(arg2, CONTEXT_REG);
2728 emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
2729 rcache_invalidate();
2731 rcache_get_reg_arg(0, SHR_SP);
2732 emith_ctx_read(arg1, SHR_PC * 4);
2733 emith_move_r_r(arg2, CONTEXT_REG);
2734 emith_call(p32x_sh2_write32);
2735 rcache_invalidate();
2736 // update I, cycles, do callback
2737 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2738 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2739 emith_bic_r_imm(sr, I);
2740 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2741 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2743 emith_move_r_r(arg0, CONTEXT_REG);
2744 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2746 emith_lsl(arg0, arg0, 2);
2747 emith_ctx_read(arg1, SHR_VBR * 4);
2748 emith_add_r_r(arg0, arg1);
2749 emit_memhandler_read(2);
2750 emith_ctx_write(arg0, SHR_PC * 4);
2752 emith_add_r_imm(xSP, 4); // fix stack
2754 emith_jump(sh2_drc_dispatcher);
2755 rcache_invalidate();
2757 // sh2_drc_entry(SH2 *sh2)
2758 sh2_drc_entry = (void *)tcache_ptr;
2759 emith_sh2_drc_entry();
2760 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2761 emit_do_static_regs(0, arg2);
2762 emith_call(sh2_drc_test_irq);
2763 emith_jump(sh2_drc_dispatcher);
2765 // write-caused irq detection
2766 sh2_drc_write_end = tcache_ptr;
2767 emith_tst_r_r(arg0, arg0);
2768 EMITH_SJMP_START(DCOND_NE);
2769 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); // return
2770 EMITH_SJMP_END(DCOND_NE);
2771 emith_call(sh2_drc_test_irq);
2772 emith_jump_ctx(offsetof(SH2, drc_tmp));
2774 // write-caused irq detection for writes in delay slot
2775 sh2_drc_write_slot_end = tcache_ptr;
2776 emith_tst_r_r(arg0, arg0);
2777 EMITH_SJMP_START(DCOND_NE);
2778 emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp));
2779 EMITH_SJMP_END(DCOND_NE);
2780 // just burn cycles to get back to dispatcher after branch is handled
2781 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2782 emith_ctx_write(sr, offsetof(SH2, irq_cycles));
2783 emith_clear_msb(sr, sr, 20); // clear cycles
2785 emith_jump_ctx(offsetof(SH2, drc_tmp));
2787 // sh2_drc_write8(u32 a, u32 d)
2788 sh2_drc_write8 = (void *)tcache_ptr;
2789 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2790 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2791 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2793 // sh2_drc_write16(u32 a, u32 d)
2794 sh2_drc_write16 = (void *)tcache_ptr;
2795 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2796 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2797 emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
2799 // sh2_drc_write8_slot(u32 a, u32 d)
2800 sh2_drc_write8_slot = (void *)tcache_ptr;
2801 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2802 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2803 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2805 // sh2_drc_write16_slot(u32 a, u32 d)
2806 sh2_drc_write16_slot = (void *)tcache_ptr;
2807 emith_ret_to_ctx(offsetof(SH2, drc_tmp));
2808 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2809 emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
2813 #define MAKE_READ_WRAPPER(func) { \
2814 void *tmp = (void *)tcache_ptr; \
2817 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2818 emith_addf_r_r(arg2, arg0); \
2819 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2820 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2821 emith_adc_r_imm(arg2, 0x01000000); \
2822 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2823 emith_pop_and_ret(); \
2826 #define MAKE_WRITE_WRAPPER(func) { \
2827 void *tmp = (void *)tcache_ptr; \
2828 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2829 emith_addf_r_r(arg2, arg1); \
2830 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2831 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2832 emith_adc_r_imm(arg2, 0x01000000); \
2833 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2834 emith_move_r_r(arg2, CONTEXT_REG); \
2839 MAKE_READ_WRAPPER(sh2_drc_read8);
2840 MAKE_READ_WRAPPER(sh2_drc_read16);
2841 MAKE_READ_WRAPPER(sh2_drc_read32);
2842 MAKE_WRITE_WRAPPER(sh2_drc_write8);
2843 MAKE_WRITE_WRAPPER(sh2_drc_write8_slot);
2844 MAKE_WRITE_WRAPPER(sh2_drc_write16);
2845 MAKE_WRITE_WRAPPER(sh2_drc_write16_slot);
2846 MAKE_WRITE_WRAPPER(sh2_drc_write32);
2848 host_dasm_new_symbol(sh2_drc_read8);
2849 host_dasm_new_symbol(sh2_drc_read16);
2850 host_dasm_new_symbol(sh2_drc_read32);
2851 host_dasm_new_symbol(sh2_drc_write32);
2855 rcache_invalidate();
2857 host_dasm_new_symbol(sh2_drc_entry);
2858 host_dasm_new_symbol(sh2_drc_dispatcher);
2859 host_dasm_new_symbol(sh2_drc_exit);
2860 host_dasm_new_symbol(sh2_drc_test_irq);
2861 host_dasm_new_symbol(sh2_drc_write_end);
2862 host_dasm_new_symbol(sh2_drc_write_slot_end);
2863 host_dasm_new_symbol(sh2_drc_write8);
2864 host_dasm_new_symbol(sh2_drc_write8_slot);
2865 host_dasm_new_symbol(sh2_drc_write16);
2866 host_dasm_new_symbol(sh2_drc_write16_slot);
2870 static void *sh2_smc_rm_block_entry(block_desc *bd, int tcache_id)
2874 // XXX: kill links somehow?
2875 dbg(2, " killing entry %08x, blkid %d", bd->addr, bd - block_tables[tcache_id]);
2876 if (bd->addr == 0 || bd->tcache_ptr == NULL) {
2877 dbg(1, " killing dead block!? %08x", bd->addr);
2878 return bd->tcache_ptr;
2881 // since we never reuse space of dead blocks,
2882 // insert jump to dispatcher for blocks that are linked to this point
2883 //emith_jump_at(bd->tcache_ptr, sh2_drc_dispatcher);
2885 // attempt to handle self-modifying blocks by exiting at nearest known PC
2887 tcache_ptr = bd->tcache_ptr;
2888 emit_move_r_imm32(SHR_PC, bd->addr);
2890 emith_jump(sh2_drc_dispatcher);
2894 return bd->tcache_ptr;
2897 static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask)
2899 //block_link *bl = block_links[tcache_id];
2900 //int bl_count = block_link_counts[tcache_id];
2901 block_desc *btab = block_tables[tcache_id];
2902 u16 *p = drc_ram_blk + ((a & mask) >> shift);
2903 u16 *pmax = drc_ram_blk + (mask >> shift);
2904 void *tcache_min, *tcache_max;
2908 // Figure out what the main block is, as subblocks also have the flag set.
2909 // This relies on sub having single entry. It's possible that innocent
2910 // block might be hit, but that's not such a big deal.
2911 if ((p[0] >> 1) != (p[1] >> 1)) {
2912 for (; p > drc_ram_blk; p--)
2913 if (p[-1] == 0 || (p[-1] >> 1) == (*p >> 1))
2918 for (; p > drc_ram_blk; p--)
2923 dbg(1, "smc rm: missing block start for %08x?", a);
2930 tcache_min = tcache_max = sh2_smc_rm_block_entry(&btab[*p >> 1], tcache_id);
2933 for (p++, zeros = 0; p < pmax && zeros < MAX_LITERAL_OFFSET / 2; p++) {
2936 // there can be holes because games sometimes keep variables
2937 // directly in literal pool and we don't inline them to avoid recompile
2938 // (Star Wars Arcade)
2943 if (id == (p[1] >> 1))
2946 tcache_max = sh2_smc_rm_block_entry(&btab[id], tcache_id);
2951 host_instructions_updated(tcache_min, (void *)((char *)tcache_max + 4*4 + 4));
2954 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
2956 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
2957 sh2_smc_rm_block(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
2960 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
2962 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
2963 sh2_smc_rm_block(a, Pico32xMem->drcblk_da[cpuid],
2964 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
2967 void sh2_execute(SH2 *sh2c, int cycles)
2972 sh2c->cycles_aim += cycles;
2973 cycles = sh2c->cycles_aim - sh2c->cycles_done;
2975 // cycles are kept in SHR_SR unused bits (upper 20)
2976 // bit19 contains T saved for delay slot
2977 // others are usual SH2 flags
2979 sh2c->sr |= cycles << 12;
2980 sh2_drc_entry(sh2c);
2983 ret_cycles = (signed int)sh2c->sr >> 12;
2985 dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
2987 sh2c->cycles_done += cycles - ret_cycles;
2991 void block_stats(void)
2993 int c, b, i, total = 0;
2995 printf("block stats:\n");
2996 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
2997 for (i = 0; i < block_counts[b]; i++)
2998 if (block_tables[b][i].addr != 0)
2999 total += block_tables[b][i].refcount;
3001 for (c = 0; c < 10; c++) {
3002 block_desc *blk, *maxb = NULL;
3004 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
3005 for (i = 0; i < block_counts[b]; i++) {
3006 blk = &block_tables[b][i];
3007 if (blk->addr != 0 && blk->refcount > max) {
3008 max = blk->refcount;
3015 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
3016 (double)maxb->refcount / total * 100.0);
3020 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3021 for (i = 0; i < block_counts[b]; i++)
3022 block_tables[b][i].refcount = 0;
3025 #define block_stats()
3028 void sh2_drc_flush_all(void)
3036 void sh2_drc_mem_setup(SH2 *sh2)
3038 // fill the convenience pointers
3039 sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3040 sh2->p_da = Pico32xMem->data_array[sh2->is_slave];
3041 sh2->p_sdram = Pico32xMem->sdram;
3042 sh2->p_rom = Pico.rom;
3045 int sh2_drc_init(SH2 *sh2)
3049 if (block_tables[0] == NULL)
3051 for (i = 0; i < TCACHE_BUFFERS; i++) {
3052 block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0]));
3053 if (block_tables[i] == NULL)
3055 // max 2 block links (exits) per block
3056 block_links[i] = calloc(block_max_counts[i] * 2, sizeof(*block_links[0]));
3057 if (block_links[i] == NULL)
3060 memset(block_counts, 0, sizeof(block_counts));
3061 memset(block_link_counts, 0, sizeof(block_link_counts));
3064 tcache_ptr = tcache;
3065 sh2_generate_utils();
3066 host_instructions_updated(tcache, tcache_ptr);
3068 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
3069 for (i = 1; i < ARRAY_SIZE(tcache_bases); i++)
3070 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
3073 PicoOpt |= POPT_DIS_VDP_FIFO;
3076 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
3077 tcache_dsm_ptrs[i] = tcache_bases[i];
3079 tcache_dsm_ptrs[0] = tcache;
3083 hash_collisions = 0;
3087 if (hash_table == NULL) {
3088 hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES);
3089 if (hash_table == NULL)
3096 sh2_drc_finish(sh2);
3100 void sh2_drc_finish(SH2 *sh2)
3104 if (block_tables[0] != NULL) {
3107 for (i = 0; i < TCACHE_BUFFERS; i++) {
3109 printf("~~~ tcache %d\n", i);
3110 tcache_dsm_ptrs[i] = tcache_bases[i];
3111 tcache_ptr = tcache_ptrs[i];
3115 if (block_tables[i] != NULL)
3116 free(block_tables[i]);
3117 block_tables[i] = NULL;
3118 if (block_links[i] == NULL)
3119 free(block_links[i]);
3120 block_links[i] = NULL;
3126 if (hash_table != NULL) {
3132 // vim:shiftwidth=2:expandtab