3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * - tcache, block descriptor, link buffer overflows result in sh2_translate()
10 * failure, followed by full tcache invalidation for that region
11 * - jumps between blocks are tracked for SMC handling (in block_entry->links),
12 * except jumps between different tcaches
15 * - static register allocation
16 * - remaining register caching and tracking in temporaries
17 * - block-local branch linking
18 * - block linking (except between tcaches)
19 * - some constant propagation
22 * - better constant propagation
31 #include "../../pico/pico_int.h"
32 #include "../../pico/arm_features.h"
35 #include "../drc/cmn.h"
39 #define PROPAGATE_CONSTANTS 1
40 #define LINK_BRANCHES 1
43 #define MAX_BLOCK_SIZE (BLOCK_INSN_LIMIT * 6 * 6)
45 // max literal offset from the block end
46 #define MAX_LITERAL_OFFSET 32*2
47 #define MAX_LITERALS (BLOCK_INSN_LIMIT / 4)
48 #define MAX_LOCAL_BRANCHES 32
51 // 01 - warnings/errors
52 // 02 - block info/smc
54 // 08 - runtime block entry log
55 // 10 - smc self-check
62 #define dbg(l,...) { \
63 if ((l) & DRC_DEBUG) \
64 elprintf(EL_STATUS, ##__VA_ARGS__); \
66 #include "mame/sh2dasm.h"
67 #include <platform/libpicofe/linux/host_dasm.h>
68 static int insns_compiled, hash_collisions, host_insn_count;
77 #define FETCH_OP(pc) \
81 ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
83 #define CHECK_UNHANDLED_BITS(mask, label) { \
84 if ((op & (mask)) != 0) \
96 #define BITMASK1(v0) (1 << (v0))
97 #define BITMASK2(v0,v1) ((1 << (v0)) | (1 << (v1)))
98 #define BITMASK3(v0,v1,v2) (BITMASK2(v0,v1) | (1 << (v2)))
99 #define BITMASK4(v0,v1,v2,v3) (BITMASK3(v0,v1,v2) | (1 << (v3)))
100 #define BITMASK5(v0,v1,v2,v3,v4) (BITMASK4(v0,v1,v2,v3) | (1 << (v4)))
102 #define SHR_T SHR_SR // might make them separate someday
104 static struct op_data {
107 u8 size; // 0, 1, 2 - byte, word, long
108 s8 rm; // branch or load/store data reg
109 u32 source; // bitmask of src regs
110 u32 dest; // bitmask of dest regs
111 u32 imm; // immediate/io address/branch target
112 // (for literal - address, not value)
113 } ops[BLOCK_INSN_LIMIT];
118 OP_BRANCH_CT, // conditional, branch if T set
119 OP_BRANCH_CF, // conditional, branch if T clear
120 OP_BRANCH_R, // indirect
121 OP_BRANCH_RF, // indirect far (PC + Rm)
122 OP_SETCLRT, // T flag set/clear
123 OP_MOVE, // register move
124 OP_LOAD_POOL, // literal pool load, imm is address
132 static int literal_disabled_frames;
135 static u8 *tcache_dsm_ptrs[3];
136 static char sh2dasm_buff[64];
137 #define do_host_disasm(tcid) \
138 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
139 tcache_dsm_ptrs[tcid] = tcache_ptr
141 #define do_host_disasm(x)
144 #if (DRC_DEBUG & 8) || defined(PDB)
145 static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
148 dbg(8, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
149 sh2->pc, block, (signed int)sr >> 12);
150 pdb_step(sh2, sh2->pc);
157 #define TCACHE_BUFFERS 3
159 // we have 3 translation cache buffers, split from one drc/cmn buffer.
160 // BIOS shares tcache with data array because it's only used for init
161 // and can be discarded early
162 // XXX: need to tune sizes
163 static const int tcache_sizes[TCACHE_BUFFERS] = {
164 DRC_TCACHE_SIZE * 6 / 8, // ROM (rarely used), DRAM
165 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
166 DRC_TCACHE_SIZE / 8, // ... slave
169 static u8 *tcache_bases[TCACHE_BUFFERS];
170 static u8 *tcache_ptrs[TCACHE_BUFFERS];
172 // ptr for code emiters
173 static u8 *tcache_ptr;
175 #define MAX_BLOCK_ENTRIES (BLOCK_INSN_LIMIT / 8)
179 void *jump; // insn address
180 struct block_link *next; // either in block_entry->links or
185 void *tcache_ptr; // translated block for above PC
186 struct block_entry *next; // next block in hash_table with same pc hash
187 struct block_link *links; // links to this entry
189 struct block_desc *block;
194 u32 addr; // block start SH2 PC address
195 u16 size; // ..of recompiled insns+lit. pool
196 u16 size_nolit; // same without literals
201 struct block_entry entryp[MAX_BLOCK_ENTRIES];
204 static const int block_max_counts[TCACHE_BUFFERS] = {
209 static struct block_desc *block_tables[TCACHE_BUFFERS];
210 static int block_counts[TCACHE_BUFFERS];
212 // we have block_link_pool to avoid using mallocs
213 static const int block_link_pool_max_counts[TCACHE_BUFFERS] = {
218 static struct block_link *block_link_pool[TCACHE_BUFFERS];
219 static int block_link_pool_counts[TCACHE_BUFFERS];
220 static struct block_link *unresolved_links[TCACHE_BUFFERS];
222 // used for invalidation
223 static const int ram_sizes[TCACHE_BUFFERS] = {
228 #define INVAL_PAGE_SIZE 0x100
231 struct block_desc *block;
232 struct block_list *next;
235 // array of pointers to block_lists for RAM and 2 data arrays
236 // each array has len: sizeof(mem) / INVAL_PAGE_SIZE
237 static struct block_list **inval_lookup[TCACHE_BUFFERS];
239 static const int hash_table_sizes[TCACHE_BUFFERS] = {
244 static struct block_entry **hash_tables[TCACHE_BUFFERS];
246 #define HASH_FUNC(hash_tab, addr, mask) \
247 (hash_tab)[(((addr) >> 20) ^ ((addr) >> 2)) & (mask)]
249 // host register tracking
252 HR_CACHED, // 'val' has sh2_reg_e
253 // HR_CONST, // 'val' has a constant
254 HR_TEMP, // reg used for temp storage
258 HRF_DIRTY = 1 << 0, // reg has "dirty" value to be written to ctx
259 HRF_LOCKED = 1 << 1, // HR_CACHED can't be evicted
263 u32 hreg:5; // "host" reg
264 u32 greg:5; // "guest" reg
267 u32 stamp:16; // kind of a timestamp
270 // note: reg_temp[] must have at least the amount of
271 // registers used by handlers in worst case (currently 4)
273 #include "../drc/emit_arm.c"
277 static const int reg_map_g2h[] = {
281 -1, -1, -1, 9, // r12 .. sp
282 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
283 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
289 static const int reg_map_g2h[] = {
293 -1, -1, -1, 8, // r12 .. sp
294 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
295 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
300 static temp_reg_t reg_temp[] = {
309 #elif defined(__i386__)
310 #include "../drc/emit_x86.c"
312 static const int reg_map_g2h[] = {
321 // ax, cx, dx are usually temporaries by convention
322 static temp_reg_t reg_temp[] = {
330 #error unsupported arch
338 #define T_save 0x00000800
344 static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
345 static void (*sh2_drc_dispatcher)(void);
346 static void (*sh2_drc_exit)(void);
347 static void (*sh2_drc_test_irq)(void);
349 static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
350 static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
351 static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
352 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
353 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
354 static void REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
356 // address space stuff
357 static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
361 if ((a & ~0x7ff) == 0) {
363 poffs = offsetof(SH2, p_bios);
366 else if ((a & 0xfffff000) == 0xc0000000) {
368 // FIXME: access sh2->data_array instead
369 poffs = offsetof(SH2, p_da);
372 else if ((a & 0xc6000000) == 0x06000000) {
374 poffs = offsetof(SH2, p_sdram);
377 else if ((a & 0xc6000000) == 0x02000000) {
379 poffs = offsetof(SH2, p_rom);
386 static struct block_entry *dr_get_entry(u32 pc, int is_slave, int *tcache_id)
388 struct block_entry *be;
391 // data arrays have their own caches
392 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0)
397 mask = hash_table_sizes[tcid] - 1;
398 be = HASH_FUNC(hash_tables[tcid], pc, mask);
399 for (; be != NULL; be = be->next)
406 // ---------------------------------------------------------------
409 static void add_to_block_list(struct block_list **blist, struct block_desc *block)
411 struct block_list *added = malloc(sizeof(*added));
413 elprintf(EL_ANOMALY, "drc OOM (1)");
416 added->block = block;
417 added->next = *blist;
421 static void rm_from_block_list(struct block_list **blist, struct block_desc *block)
423 struct block_list *prev = NULL, *current = *blist;
424 for (; current != NULL; current = current->next) {
425 if (current->block == block) {
427 *blist = current->next;
429 prev->next = current->next;
435 dbg(1, "can't rm block %p (%08x-%08x)",
436 block, block->addr, block->addr + block->size);
439 static void rm_block_list(struct block_list **blist)
441 struct block_list *tmp, *current = *blist;
442 while (current != NULL) {
444 current = current->next;
450 static void REGPARM(1) flush_tcache(int tcid)
454 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
455 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
456 block_counts[tcid], block_max_counts[tcid]);
458 block_counts[tcid] = 0;
459 block_link_pool_counts[tcid] = 0;
460 unresolved_links[tcid] = NULL;
461 memset(hash_tables[tcid], 0, sizeof(*hash_tables[0]) * hash_table_sizes[tcid]);
462 tcache_ptrs[tcid] = tcache_bases[tcid];
463 if (Pico32xMem != NULL) {
464 if (tcid == 0) // ROM, RAM
465 memset(Pico32xMem->drcblk_ram, 0,
466 sizeof(Pico32xMem->drcblk_ram));
468 memset(Pico32xMem->drcblk_da[tcid - 1], 0,
469 sizeof(Pico32xMem->drcblk_da[0]));
472 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
475 for (i = 0; i < ram_sizes[tcid] / INVAL_PAGE_SIZE; i++)
476 rm_block_list(&inval_lookup[tcid][i]);
479 static void add_to_hashlist(struct block_entry *be, int tcache_id)
481 u32 tcmask = hash_table_sizes[tcache_id] - 1;
483 be->next = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
484 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be;
487 if (be->next != NULL) {
488 printf(" %08x: hash collision with %08x\n",
489 be->pc, be->next->pc);
495 static void rm_from_hashlist(struct block_entry *be, int tcache_id)
497 u32 tcmask = hash_table_sizes[tcache_id] - 1;
498 struct block_entry *cur, *prev;
500 cur = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
504 if (be == cur) { // first
505 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be->next;
509 for (prev = cur, cur = cur->next; cur != NULL; cur = cur->next) {
511 prev->next = cur->next;
517 dbg(1, "rm_from_hashlist: be %p %08x missing?", be, be->pc);
520 static void unregister_links(struct block_entry *be, int tcache_id)
522 struct block_link *bl_unresolved = unresolved_links[tcache_id];
523 struct block_link *bl, *bl_next;
525 for (bl = be->links; bl != NULL; ) {
527 bl->next = bl_unresolved;
532 unresolved_links[tcache_id] = bl_unresolved;
535 // unlike sh2_smc_rm_block, the block stays and can still be accessed
536 // by other already directly linked blocks, just not preferred
537 static void kill_block_entry(struct block_entry *be, int tcache_id)
539 rm_from_hashlist(be, tcache_id);
540 unregister_links(be, tcache_id);
543 static struct block_desc *dr_add_block(u32 addr, u16 size_lit,
544 u16 size_nolit, int is_slave, int *blk_id)
546 struct block_entry *be;
547 struct block_desc *bd;
551 // do a lookup to get tcache_id and override check
552 be = dr_get_entry(addr, is_slave, &tcache_id);
554 dbg(1, "block override for %08x, was %p", addr, be->tcache_ptr);
555 kill_block_entry(be, tcache_id);
558 bcount = &block_counts[tcache_id];
559 if (*bcount >= block_max_counts[tcache_id]) {
560 dbg(1, "bd overflow for tcache %d", tcache_id);
564 bd = &block_tables[tcache_id][*bcount];
567 bd->size_nolit = size_nolit;
570 bd->entryp[0].pc = addr;
571 bd->entryp[0].tcache_ptr = tcache_ptr;
572 bd->entryp[0].links = NULL;
574 bd->entryp[0].block = bd;
577 add_to_hashlist(&bd->entryp[0], tcache_id);
585 static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id)
587 struct block_entry *be = NULL;
590 be = dr_get_entry(pc, is_slave, tcache_id);
592 block = be->tcache_ptr;
596 be->block->refcount++;
601 static void *dr_failure(void)
603 lprintf("recompilation failed\n");
607 static void *dr_prepare_ext_branch(u32 pc, int is_slave, int tcache_id)
610 struct block_link *bl = block_link_pool[tcache_id];
611 int cnt = block_link_pool_counts[tcache_id];
612 struct block_entry *be = NULL;
613 int target_tcache_id;
616 be = dr_get_entry(pc, is_slave, &target_tcache_id);
617 if (target_tcache_id != tcache_id)
618 return sh2_drc_dispatcher;
620 // if pool has been freed, reuse
621 for (i = cnt - 1; i >= 0; i--)
622 if (bl[i].target_pc != 0)
625 if (cnt >= block_link_pool_max_counts[tcache_id]) {
626 dbg(1, "bl overflow for tcache %d", tcache_id);
630 block_link_pool_counts[tcache_id]++;
633 bl->jump = tcache_ptr;
636 dbg(2, "- early link from %p to pc %08x", bl->jump, pc);
637 bl->next = be->links;
639 return be->tcache_ptr;
642 bl->next = unresolved_links[tcache_id];
643 unresolved_links[tcache_id] = bl;
644 return sh2_drc_dispatcher;
647 return sh2_drc_dispatcher;
651 static void dr_link_blocks(struct block_entry *be, int tcache_id)
654 struct block_link *first = unresolved_links[tcache_id];
655 struct block_link *bl, *prev, *tmp;
658 for (bl = prev = first; bl != NULL; ) {
659 if (bl->target_pc == pc) {
660 dbg(2, "- link from %p to pc %08x", bl->jump, pc);
661 emith_jump_patch(bl->jump, tcache_ptr);
663 // move bl from unresolved_links to block_entry
665 bl->next = be->links;
669 first = prev = bl = tmp;
671 prev->next = bl = tmp;
677 unresolved_links[tcache_id] = first;
679 // could sync arm caches here, but that's unnecessary
683 #define ADD_TO_ARRAY(array, count, item, failcode) \
684 if (count >= ARRAY_SIZE(array)) { \
685 dbg(1, "warning: " #array " overflow"); \
688 array[count++] = item;
690 static int find_in_array(u32 *array, size_t size, u32 what)
693 for (i = 0; i < size; i++)
694 if (what == array[i])
700 // ---------------------------------------------------------------
702 // register cache / constant propagation stuff
709 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking);
711 // guest regs with constants
712 static u32 dr_gcregs[24];
713 // a mask of constant/dirty regs
714 static u32 dr_gcregs_mask;
715 static u32 dr_gcregs_dirty;
717 #if PROPAGATE_CONSTANTS
718 static void gconst_new(sh2_reg_e r, u32 val)
722 dr_gcregs_mask |= 1 << r;
723 dr_gcregs_dirty |= 1 << r;
726 // throw away old r that we might have cached
727 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
728 if ((reg_temp[i].type == HR_CACHED) &&
729 reg_temp[i].greg == r) {
730 reg_temp[i].type = HR_FREE;
731 reg_temp[i].flags = 0;
737 static int gconst_get(sh2_reg_e r, u32 *val)
739 if (dr_gcregs_mask & (1 << r)) {
746 static int gconst_check(sh2_reg_e r)
748 if ((dr_gcregs_mask | dr_gcregs_dirty) & (1 << r))
753 // update hr if dirty, else do nothing
754 static int gconst_try_read(int hr, sh2_reg_e r)
756 if (dr_gcregs_dirty & (1 << r)) {
757 emith_move_r_imm(hr, dr_gcregs[r]);
758 dr_gcregs_dirty &= ~(1 << r);
764 static void gconst_check_evict(sh2_reg_e r)
766 if (dr_gcregs_mask & (1 << r))
767 // no longer cached in reg, make dirty again
768 dr_gcregs_dirty |= 1 << r;
771 static void gconst_kill(sh2_reg_e r)
773 dr_gcregs_mask &= ~(1 << r);
774 dr_gcregs_dirty &= ~(1 << r);
777 static void gconst_clean(void)
781 for (i = 0; i < ARRAY_SIZE(dr_gcregs); i++)
782 if (dr_gcregs_dirty & (1 << i)) {
783 // using RC_GR_READ here: it will call gconst_try_read,
784 // cache the reg and mark it dirty.
785 rcache_get_reg_(i, RC_GR_READ, 0);
789 static void gconst_invalidate(void)
791 dr_gcregs_mask = dr_gcregs_dirty = 0;
794 static u16 rcache_counter;
796 static temp_reg_t *rcache_evict(void)
798 // evict reg with oldest stamp
800 u16 min_stamp = (u16)-1;
802 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
803 if (reg_temp[i].type == HR_CACHED && !(reg_temp[i].flags & HRF_LOCKED) &&
804 reg_temp[i].stamp <= min_stamp) {
805 min_stamp = reg_temp[i].stamp;
811 printf("no registers to evict, aborting\n");
816 if (reg_temp[i].type == HR_CACHED) {
817 if (reg_temp[i].flags & HRF_DIRTY)
819 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
820 gconst_check_evict(reg_temp[i].greg);
823 reg_temp[i].type = HR_FREE;
824 reg_temp[i].flags = 0;
828 static int get_reg_static(sh2_reg_e r, rc_gr_mode mode)
830 int i = reg_map_g2h[r];
832 if (mode != RC_GR_WRITE)
833 gconst_try_read(i, r);
838 // note: must not be called when doing conditional code
839 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking)
844 // maybe statically mapped?
845 ret = get_reg_static(r, mode);
851 // maybe already cached?
852 // if so, prefer against gconst (they must be in sync)
853 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
854 if (reg_temp[i].type == HR_CACHED && reg_temp[i].greg == r) {
855 reg_temp[i].stamp = rcache_counter;
856 if (mode != RC_GR_READ)
857 reg_temp[i].flags |= HRF_DIRTY;
858 ret = reg_temp[i].hreg;
864 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
865 if (reg_temp[i].type == HR_FREE) {
874 tr->type = HR_CACHED;
876 tr->flags |= HRF_LOCKED;
877 if (mode != RC_GR_READ)
878 tr->flags |= HRF_DIRTY;
880 tr->stamp = rcache_counter;
883 if (mode != RC_GR_WRITE) {
884 if (gconst_check(r)) {
885 if (gconst_try_read(ret, r))
886 tr->flags |= HRF_DIRTY;
889 emith_ctx_read(tr->hreg, r * 4);
893 if (mode != RC_GR_READ)
899 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
901 return rcache_get_reg_(r, mode, 1);
904 static int rcache_get_tmp(void)
909 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
910 if (reg_temp[i].type == HR_FREE) {
922 static int rcache_get_arg_id(int arg)
925 host_arg2reg(r, arg);
927 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
928 if (reg_temp[i].hreg == r)
931 if (i == ARRAY_SIZE(reg_temp)) // can't happen
934 if (reg_temp[i].type == HR_CACHED) {
936 if (reg_temp[i].flags & HRF_DIRTY)
937 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
938 gconst_check_evict(reg_temp[i].greg);
940 else if (reg_temp[i].type == HR_TEMP) {
941 printf("arg %d reg %d already used, aborting\n", arg, r);
945 reg_temp[i].type = HR_FREE;
946 reg_temp[i].flags = 0;
951 // get a reg to be used as function arg
952 static int rcache_get_tmp_arg(int arg)
954 int id = rcache_get_arg_id(arg);
955 reg_temp[id].type = HR_TEMP;
957 return reg_temp[id].hreg;
960 // same but caches a reg. RC_GR_READ only.
961 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
963 int i, srcr, dstr, dstid;
964 int dirty = 0, src_dirty = 0;
966 dstid = rcache_get_arg_id(arg);
967 dstr = reg_temp[dstid].hreg;
969 // maybe already statically mapped?
970 srcr = get_reg_static(r, RC_GR_READ);
974 // maybe already cached?
975 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
976 if ((reg_temp[i].type == HR_CACHED) &&
977 reg_temp[i].greg == r)
979 srcr = reg_temp[i].hreg;
980 if (reg_temp[i].flags & HRF_DIRTY)
988 if (gconst_check(r)) {
989 if (gconst_try_read(srcr, r))
993 emith_ctx_read(srcr, r * 4);
997 emith_move_r_r(dstr, srcr);
1003 // must clean, callers might want to modify the arg before call
1004 emith_ctx_write(dstr, r * 4);
1007 reg_temp[dstid].flags |= HRF_DIRTY;
1010 reg_temp[dstid].stamp = ++rcache_counter;
1011 reg_temp[dstid].type = HR_CACHED;
1012 reg_temp[dstid].greg = r;
1013 reg_temp[dstid].flags |= HRF_LOCKED;
1017 static void rcache_free_tmp(int hr)
1020 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1021 if (reg_temp[i].hreg == hr)
1024 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
1025 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
1029 reg_temp[i].type = HR_FREE;
1030 reg_temp[i].flags = 0;
1033 static void rcache_unlock(int hr)
1036 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1037 if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr)
1038 reg_temp[i].flags &= ~HRF_LOCKED;
1041 static void rcache_unlock_all(void)
1044 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1045 reg_temp[i].flags &= ~HRF_LOCKED;
1049 static u32 rcache_used_hreg_mask(void)
1054 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1055 if (reg_temp[i].type != HR_FREE)
1056 mask |= 1 << reg_temp[i].hreg;
1062 static void rcache_clean(void)
1067 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1068 if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) {
1070 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
1071 reg_temp[i].flags &= ~HRF_DIRTY;
1075 static void rcache_invalidate(void)
1078 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
1079 reg_temp[i].type = HR_FREE;
1080 reg_temp[i].flags = 0;
1084 gconst_invalidate();
1087 static void rcache_flush(void)
1090 rcache_invalidate();
1093 // ---------------------------------------------------------------
1095 static int emit_get_rbase_and_offs(u32 a, u32 *offs)
1101 poffs = dr_ctx_get_mem_ptr(a, &mask);
1105 // XXX: could use some related reg
1106 hr = rcache_get_tmp();
1107 emith_ctx_read(hr, poffs);
1108 emith_add_r_imm(hr, a & mask & ~0xff);
1109 *offs = a & 0xff; // XXX: ARM oriented..
1113 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
1115 #if PROPAGATE_CONSTANTS
1116 gconst_new(dst, imm);
1118 int hr = rcache_get_reg(dst, RC_GR_WRITE);
1119 emith_move_r_imm(hr, imm);
1123 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
1125 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
1126 int hr_s = rcache_get_reg(src, RC_GR_READ);
1128 emith_move_r_r(hr_d, hr_s);
1131 // T must be clear, and comparison done just before this
1132 static void emit_or_t_if_eq(int srr)
1134 EMITH_SJMP_START(DCOND_NE);
1135 emith_or_r_imm_c(DCOND_EQ, srr, T);
1136 EMITH_SJMP_END(DCOND_NE);
1139 // arguments must be ready
1140 // reg cache must be clean before call
1141 static int emit_memhandler_read_(int size, int ram_check)
1146 host_arg2reg(arg0, 0);
1151 // must writeback cycles for poll detection stuff
1153 if (reg_map_g2h[SHR_SR] != -1)
1154 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1156 arg1 = rcache_get_tmp_arg(1);
1157 emith_move_r_r(arg1, CONTEXT_REG);
1159 #if 0 // can't do this because of unmapped reads
1161 if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
1162 int tmp = rcache_get_tmp();
1163 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
1164 emith_cmp_r_imm(tmp, 0x02000000);
1167 EMITH_SJMP3_START(DCOND_NE);
1168 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
1169 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1170 EMITH_SJMP3_MID(DCOND_NE);
1171 emith_call_cond(DCOND_NE, sh2_drc_read8);
1175 EMITH_SJMP3_START(DCOND_NE);
1176 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1177 EMITH_SJMP3_MID(DCOND_NE);
1178 emith_call_cond(DCOND_NE, sh2_drc_read16);
1182 EMITH_SJMP3_START(DCOND_NE);
1183 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1184 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
1185 EMITH_SJMP3_MID(DCOND_NE);
1186 emith_call_cond(DCOND_NE, sh2_drc_read32);
1196 emith_call(sh2_drc_read8);
1199 emith_call(sh2_drc_read16);
1202 emith_call(sh2_drc_read32);
1206 rcache_invalidate();
1208 if (reg_map_g2h[SHR_SR] != -1)
1209 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1211 // assuming arg0 and retval reg matches
1212 return rcache_get_tmp_arg(0);
1215 static int emit_memhandler_read(int size)
1217 return emit_memhandler_read_(size, 1);
1220 static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size)
1222 int hr, hr2, ram_check = 1;
1225 if (gconst_get(rs, &val)) {
1226 hr = emit_get_rbase_and_offs(val + offs, &offs2);
1228 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1231 emith_read8_r_r_offs(hr2, hr, offs2 ^ 1);
1232 emith_sext(hr2, hr2, 8);
1235 emith_read16_r_r_offs(hr2, hr, offs2);
1236 emith_sext(hr2, hr2, 16);
1239 emith_read_r_r_offs(hr2, hr, offs2);
1240 emith_ror(hr2, hr2, 16);
1243 rcache_free_tmp(hr);
1250 hr = rcache_get_reg_arg(0, rs);
1252 emith_add_r_imm(hr, offs);
1253 hr = emit_memhandler_read_(size, ram_check);
1254 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1256 emith_sext(hr2, hr, (size == 1) ? 16 : 8);
1258 emith_move_r_r(hr2, hr);
1259 rcache_free_tmp(hr);
1264 static void emit_memhandler_write(int size)
1267 host_arg2reg(ctxr, 2);
1268 if (reg_map_g2h[SHR_SR] != -1)
1269 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1275 // XXX: consider inlining sh2_drc_write8
1276 emith_call(sh2_drc_write8);
1279 emith_call(sh2_drc_write16);
1282 emith_move_r_r(ctxr, CONTEXT_REG);
1283 emith_call(sh2_drc_write32);
1287 rcache_invalidate();
1288 if (reg_map_g2h[SHR_SR] != -1)
1289 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1293 static int emit_indirect_indexed_read(int rx, int ry, int size)
1296 a0 = rcache_get_reg_arg(0, rx);
1297 t = rcache_get_reg(ry, RC_GR_READ);
1298 emith_add_r_r(a0, t);
1299 return emit_memhandler_read(size);
1303 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
1307 rcache_get_reg_arg(0, rn);
1308 tmp = emit_memhandler_read(size);
1309 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
1310 rcache_free_tmp(tmp);
1311 tmp = rcache_get_reg(rn, RC_GR_RMW);
1312 emith_add_r_imm(tmp, 1 << size);
1315 rcache_get_reg_arg(0, rm);
1316 *rmr = emit_memhandler_read(size);
1317 *rnr = rcache_get_tmp();
1318 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
1319 tmp = rcache_get_reg(rm, RC_GR_RMW);
1320 emith_add_r_imm(tmp, 1 << size);
1324 static void emit_do_static_regs(int is_write, int tmpr)
1328 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
1333 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
1334 if (reg_map_g2h[i + 1] != r + 1)
1340 // i, r point to last item
1342 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1344 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1347 emith_ctx_write(r, i * 4);
1349 emith_ctx_read(r, i * 4);
1354 static void emit_block_entry(void)
1358 host_arg2reg(arg0, 0);
1360 #if (DRC_DEBUG & 8) || defined(PDB)
1362 host_arg2reg(arg1, 1);
1363 host_arg2reg(arg2, 2);
1365 emit_do_static_regs(1, arg2);
1366 emith_move_r_r(arg1, CONTEXT_REG);
1367 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
1368 emith_call(sh2_drc_log_entry);
1369 rcache_invalidate();
1371 emith_tst_r_r(arg0, arg0);
1372 EMITH_SJMP_START(DCOND_EQ);
1373 emith_jump_reg_c(DCOND_NE, arg0);
1374 EMITH_SJMP_END(DCOND_EQ);
1377 #define DELAY_SAVE_T(sr) { \
1378 emith_bic_r_imm(sr, T_save); \
1379 emith_tst_r_imm(sr, T); \
1380 EMITH_SJMP_START(DCOND_EQ); \
1381 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
1382 EMITH_SJMP_END(DCOND_EQ); \
1385 #define FLUSH_CYCLES(sr) \
1387 emith_sub_r_imm(sr, cycles << 12); \
1391 static void *dr_get_pc_base(u32 pc, int is_slave);
1393 static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
1395 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
1396 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
1397 int branch_target_count = 0;
1398 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
1399 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
1400 int branch_patch_count = 0;
1401 u32 literal_addr[MAX_LITERALS];
1402 int literal_addr_count = 0;
1403 u8 op_flags[BLOCK_INSN_LIMIT];
1406 u32 pending_branch_direct:1;
1407 u32 pending_branch_indirect:1;
1408 u32 literals_disabled:1;
1411 // PC of current, first, last SH2 insn
1412 u32 pc, base_pc, end_pc;
1414 void *block_entry_ptr;
1415 struct block_desc *block;
1417 struct op_data *opd;
1426 drcf.literals_disabled = literal_disabled_frames != 0;
1428 // get base/validate PC
1429 dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave);
1430 if (dr_pc_base == (void *)-1) {
1431 printf("invalid PC, aborting: %08x\n", base_pc);
1432 // FIXME: be less destructive
1436 tcache_ptr = tcache_ptrs[tcache_id];
1438 // predict tcache overflow
1439 tmp = tcache_ptr - tcache_bases[tcache_id];
1440 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
1441 dbg(1, "tcache %d overflow", tcache_id);
1445 // initial passes to disassemble and analyze the block
1446 scan_block(base_pc, sh2->is_slave, op_flags, &end_pc, &end_literals);
1448 if (drcf.literals_disabled)
1449 end_literals = end_pc;
1451 block = dr_add_block(base_pc, end_literals - base_pc,
1452 end_pc - base_pc, sh2->is_slave, &blkid_main);
1456 block_entry_ptr = tcache_ptr;
1457 dbg(2, "== %csh2 block #%d,%d %08x-%08x -> %p", sh2->is_slave ? 's' : 'm',
1458 tcache_id, blkid_main, base_pc, end_pc, block_entry_ptr);
1460 dr_link_blocks(&block->entryp[0], tcache_id);
1462 // collect branch_targets that don't land on delay slots
1463 for (pc = base_pc, i = 0; pc < end_pc; i++, pc += 2) {
1464 if (!(op_flags[i] & OF_BTARGET))
1466 if (op_flags[i] & OF_DELAY_OP) {
1467 op_flags[i] &= ~OF_BTARGET;
1470 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
1473 if (branch_target_count > 0) {
1474 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
1477 // clear stale state after compile errors
1478 rcache_invalidate();
1480 // -------------------------------------------------
1481 // 3rd pass: actual compilation
1484 for (i = 0; pc < end_pc; i++)
1486 u32 delay_dep_fw = 0, delay_dep_bk = 0;
1496 DasmSH2(sh2dasm_buff, pc, op);
1497 printf("%c%08x %04x %s\n", (op_flags[i] & OF_BTARGET) ? '*' : ' ',
1498 pc, op, sh2dasm_buff);
1501 if ((op_flags[i] & OF_BTARGET) || pc == base_pc)
1505 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1510 v = block->entry_count;
1511 if (v < ARRAY_SIZE(block->entryp))
1513 struct block_entry *be_old;
1515 block->entryp[v].pc = pc;
1516 block->entryp[v].tcache_ptr = tcache_ptr;
1517 block->entryp[v].links = NULL;
1519 block->entryp[v].block = block;
1521 be_old = dr_get_entry(pc, sh2->is_slave, &tcache_id);
1522 if (be_old != NULL) {
1523 dbg(1, "entry override for %08x, was %p", pc, be_old->tcache_ptr);
1524 kill_block_entry(be_old, tcache_id);
1527 add_to_hashlist(&block->entryp[v], tcache_id);
1528 block->entry_count++;
1530 dbg(2, "-- %csh2 block #%d,%d entry %08x -> %p",
1531 sh2->is_slave ? 's' : 'm', tcache_id, blkid_main,
1534 // since we made a block entry, link any other blocks
1535 // that jump to current pc
1536 dr_link_blocks(&block->entryp[v], tcache_id);
1539 dbg(1, "too many entryp for block #%d,%d pc=%08x",
1540 tcache_id, blkid_main, pc);
1543 do_host_disasm(tcache_id);
1546 v = find_in_array(branch_target_pc, branch_target_count, pc);
1548 branch_target_ptr[v] = tcache_ptr;
1551 emit_move_r_imm32(SHR_PC, pc);
1554 #if (DRC_DEBUG & 0x10)
1555 rcache_get_reg_arg(0, SHR_PC);
1556 tmp = emit_memhandler_read(2);
1557 tmp2 = rcache_get_tmp();
1558 tmp3 = rcache_get_tmp();
1559 emith_move_r_imm(tmp2, FETCH32(pc));
1560 emith_move_r_imm(tmp3, 0);
1561 emith_cmp_r_r(tmp, tmp2);
1562 EMITH_SJMP_START(DCOND_EQ);
1563 emith_read_r_r_offs_c(DCOND_NE, tmp3, tmp3, 0); // crash
1564 EMITH_SJMP_END(DCOND_EQ);
1565 rcache_free_tmp(tmp);
1566 rcache_free_tmp(tmp2);
1567 rcache_free_tmp(tmp3);
1571 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1572 emith_cmp_r_imm(sr, 0);
1573 emith_jump_cond(DCOND_LE, sh2_drc_exit);
1574 do_host_disasm(tcache_id);
1575 rcache_unlock_all();
1579 if (!(op_flags[i] & OF_DELAY_OP)) {
1580 emit_move_r_imm32(SHR_PC, pc);
1581 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1585 tmp = rcache_used_hreg_mask();
1586 emith_save_caller_regs(tmp);
1587 emit_do_static_regs(1, 0);
1588 emith_pass_arg_r(0, CONTEXT_REG);
1589 emith_call(do_sh2_cmp);
1590 emith_restore_caller_regs(tmp);
1601 if (op_flags[i] & OF_DELAY_OP)
1603 // handle delay slot dependencies
1604 delay_dep_fw = opd->dest & ops[i-1].source;
1605 delay_dep_bk = opd->source & ops[i-1].dest;
1606 if (delay_dep_fw & BITMASK1(SHR_T)) {
1607 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1610 if (delay_dep_bk & BITMASK1(SHR_PC)) {
1611 if (opd->op != OP_LOAD_POOL && opd->op != OP_MOVA) {
1612 // can only be those 2 really..
1613 elprintf_sh2(sh2, EL_ANOMALY,
1614 "drc: illegal slot insn %04x @ %08x?", op, pc - 2);
1617 ; // addr already resolved somehow
1619 switch (ops[i-1].op) {
1621 emit_move_r_imm32(SHR_PC, ops[i-1].imm);
1625 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1626 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1627 emith_move_r_imm(tmp, pc);
1628 emith_tst_r_imm(sr, T);
1629 tmp2 = ops[i-1].op == OP_BRANCH_CT ? DCOND_NE : DCOND_EQ;
1630 emith_move_r_imm_c(tmp2, tmp, ops[i-1].imm);
1632 // case OP_BRANCH_R OP_BRANCH_RF - PC already loaded
1636 //if (delay_dep_fw & ~BITMASK1(SHR_T))
1637 // dbg(1, "unhandled delay_dep_fw: %x", delay_dep_fw & ~BITMASK1(SHR_T));
1638 if (delay_dep_bk & ~BITMASK2(SHR_PC, SHR_PR))
1639 dbg(1, "unhandled delay_dep_bk: %x", delay_dep_bk);
1647 if (opd->dest & BITMASK1(SHR_PR))
1648 emit_move_r_imm32(SHR_PR, pc + 2);
1649 drcf.pending_branch_direct = 1;
1653 if (opd->dest & BITMASK1(SHR_PR))
1654 emit_move_r_imm32(SHR_PR, pc + 2);
1655 emit_move_r_r(SHR_PC, opd->rm);
1656 drcf.pending_branch_indirect = 1;
1660 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1661 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1662 if (opd->dest & BITMASK1(SHR_PR)) {
1663 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
1664 emith_move_r_imm(tmp3, pc + 2);
1665 emith_add_r_r_r(tmp, tmp2, tmp3);
1668 emith_move_r_r(tmp, tmp2);
1669 emith_add_r_imm(tmp, pc + 2);
1671 drcf.pending_branch_indirect = 1;
1675 printf("TODO sleep\n");
1680 emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2);
1682 tmp = rcache_get_reg_arg(0, SHR_SP);
1683 emith_add_r_imm(tmp, 4);
1684 tmp = emit_memhandler_read(2);
1685 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1686 emith_write_sr(sr, tmp);
1687 rcache_free_tmp(tmp);
1688 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1689 emith_add_r_imm(tmp, 4*2);
1691 drcf.pending_branch_indirect = 1;
1695 #if PROPAGATE_CONSTANTS
1696 if (opd->imm != 0 && opd->imm < end_literals
1697 && literal_addr_count < MAX_LITERALS)
1699 ADD_TO_ARRAY(literal_addr, literal_addr_count, opd->imm,);
1701 tmp = FETCH32(opd->imm);
1703 tmp = (u32)(int)(signed short)FETCH_OP(opd->imm);
1704 gconst_new(GET_Rn(), tmp);
1709 tmp = rcache_get_tmp_arg(0);
1711 emith_move_r_imm(tmp, opd->imm);
1713 // have to calculate read addr from PC
1714 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
1715 if (opd->size == 2) {
1716 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
1717 emith_bic_r_imm(tmp, 3);
1720 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 2);
1722 tmp2 = emit_memhandler_read(opd->size);
1723 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1725 emith_move_r_r(tmp3, tmp2);
1727 emith_sext(tmp3, tmp2, 16);
1728 rcache_free_tmp(tmp2);
1734 emit_move_r_imm32(SHR_R0, opd->imm);
1736 tmp = rcache_get_reg(SHR_R0, RC_GR_WRITE);
1737 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
1738 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
1739 emith_bic_r_imm(tmp, 3);
1744 switch ((op >> 12) & 0x0f)
1746 /////////////////////////////////////////////
1751 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1754 case 0: // STC SR,Rn 0000nnnn00000010
1757 case 1: // STC GBR,Rn 0000nnnn00010010
1760 case 2: // STC VBR,Rn 0000nnnn00100010
1766 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
1767 emith_move_r_r(tmp, tmp3);
1769 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
1771 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
1772 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
1773 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
1775 tmp = rcache_get_reg_arg(1, GET_Rm());
1776 tmp2 = rcache_get_reg_arg(0, SHR_R0);
1777 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1778 emith_add_r_r(tmp2, tmp3);
1779 emit_memhandler_write(op & 3);
1782 // MUL.L Rm,Rn 0000nnnnmmmm0111
1783 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1784 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1785 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1786 emith_mul(tmp3, tmp2, tmp);
1791 case 0: // CLRT 0000000000001000
1792 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1793 emith_bic_r_imm(sr, T);
1795 case 1: // SETT 0000000000011000
1796 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1797 emith_or_r_imm(sr, T);
1799 case 2: // CLRMAC 0000000000101000
1800 emit_move_r_imm32(SHR_MACL, 0);
1801 emit_move_r_imm32(SHR_MACH, 0);
1810 case 0: // NOP 0000000000001001
1812 case 1: // DIV0U 0000000000011001
1813 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1814 emith_bic_r_imm(sr, M|Q|T);
1816 case 2: // MOVT Rn 0000nnnn00101001
1817 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1818 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1819 emith_clear_msb(tmp2, sr, 31);
1826 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1829 case 0: // STS MACH,Rn 0000nnnn00001010
1832 case 1: // STS MACL,Rn 0000nnnn00011010
1835 case 2: // STS PR,Rn 0000nnnn00101010
1841 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1842 emith_move_r_r(tmp, tmp2);
1844 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1845 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1846 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1847 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1848 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1849 if ((op & 3) != 2) {
1850 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1852 emith_move_r_r(tmp2, tmp);
1853 rcache_free_tmp(tmp);
1855 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1856 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1857 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1858 /* MS 16 MAC bits unused if saturated */
1859 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1860 emith_tst_r_imm(sr, S);
1861 EMITH_SJMP_START(DCOND_EQ);
1862 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1863 EMITH_SJMP_END(DCOND_EQ);
1865 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1866 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1867 rcache_free_tmp(tmp2);
1868 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1869 emith_tst_r_imm(sr, S);
1871 EMITH_JMP_START(DCOND_EQ);
1872 emith_asr(tmp, tmp4, 15);
1873 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1874 EMITH_SJMP_START(DCOND_GE);
1875 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1876 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1877 EMITH_SJMP_END(DCOND_GE);
1878 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1879 EMITH_SJMP_START(DCOND_LE);
1880 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1881 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1882 EMITH_SJMP_END(DCOND_LE);
1883 EMITH_JMP_END(DCOND_EQ);
1885 rcache_free_tmp(tmp);
1890 /////////////////////////////////////////////
1892 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1894 tmp = rcache_get_reg_arg(0, GET_Rn());
1895 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1897 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1898 emit_memhandler_write(2);
1904 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1905 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1906 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1908 rcache_get_reg_arg(0, GET_Rn());
1909 rcache_get_reg_arg(1, GET_Rm());
1910 emit_memhandler_write(op & 3);
1912 case 0x04: // MOV.B Rm,@-Rn 0010nnnnmmmm0100
1913 case 0x05: // MOV.W Rm,@-Rn 0010nnnnmmmm0101
1914 case 0x06: // MOV.L Rm,@-Rn 0010nnnnmmmm0110
1915 rcache_get_reg_arg(1, GET_Rm()); // for Rm == Rn
1916 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1917 emith_sub_r_imm(tmp, (1 << (op & 3)));
1919 rcache_get_reg_arg(0, GET_Rn());
1920 emit_memhandler_write(op & 3);
1922 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1923 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1924 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1925 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1926 emith_bic_r_imm(sr, M|Q|T);
1927 emith_tst_r_imm(tmp2, (1<<31));
1928 EMITH_SJMP_START(DCOND_EQ);
1929 emith_or_r_imm_c(DCOND_NE, sr, Q);
1930 EMITH_SJMP_END(DCOND_EQ);
1931 emith_tst_r_imm(tmp3, (1<<31));
1932 EMITH_SJMP_START(DCOND_EQ);
1933 emith_or_r_imm_c(DCOND_NE, sr, M);
1934 EMITH_SJMP_END(DCOND_EQ);
1935 emith_teq_r_r(tmp2, tmp3);
1936 EMITH_SJMP_START(DCOND_PL);
1937 emith_or_r_imm_c(DCOND_MI, sr, T);
1938 EMITH_SJMP_END(DCOND_PL);
1940 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1941 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1942 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1943 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1944 emith_bic_r_imm(sr, T);
1945 emith_tst_r_r(tmp2, tmp3);
1946 emit_or_t_if_eq(sr);
1948 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1949 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1950 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1951 emith_and_r_r(tmp, tmp2);
1953 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1954 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1955 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1956 emith_eor_r_r(tmp, tmp2);
1958 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1959 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1960 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1961 emith_or_r_r(tmp, tmp2);
1963 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1964 tmp = rcache_get_tmp();
1965 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1966 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1967 emith_eor_r_r_r(tmp, tmp2, tmp3);
1968 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1969 emith_bic_r_imm(sr, T);
1970 emith_tst_r_imm(tmp, 0x000000ff);
1971 emit_or_t_if_eq(sr);
1972 emith_tst_r_imm(tmp, 0x0000ff00);
1973 emit_or_t_if_eq(sr);
1974 emith_tst_r_imm(tmp, 0x00ff0000);
1975 emit_or_t_if_eq(sr);
1976 emith_tst_r_imm(tmp, 0xff000000);
1977 emit_or_t_if_eq(sr);
1978 rcache_free_tmp(tmp);
1980 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1981 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1982 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1983 emith_lsr(tmp, tmp, 16);
1984 emith_or_r_r_lsl(tmp, tmp2, 16);
1986 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1987 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1988 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1989 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1991 emith_sext(tmp, tmp2, 16);
1993 emith_clear_msb(tmp, tmp2, 16);
1994 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1995 tmp2 = rcache_get_tmp();
1997 emith_sext(tmp2, tmp3, 16);
1999 emith_clear_msb(tmp2, tmp3, 16);
2000 emith_mul(tmp, tmp, tmp2);
2001 rcache_free_tmp(tmp2);
2006 /////////////////////////////////////////////
2010 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
2011 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
2012 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
2013 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
2014 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
2015 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2016 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
2017 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2018 emith_bic_r_imm(sr, T);
2019 emith_cmp_r_r(tmp2, tmp3);
2022 case 0x00: // CMP/EQ
2023 emit_or_t_if_eq(sr);
2025 case 0x02: // CMP/HS
2026 EMITH_SJMP_START(DCOND_LO);
2027 emith_or_r_imm_c(DCOND_HS, sr, T);
2028 EMITH_SJMP_END(DCOND_LO);
2030 case 0x03: // CMP/GE
2031 EMITH_SJMP_START(DCOND_LT);
2032 emith_or_r_imm_c(DCOND_GE, sr, T);
2033 EMITH_SJMP_END(DCOND_LT);
2035 case 0x06: // CMP/HI
2036 EMITH_SJMP_START(DCOND_LS);
2037 emith_or_r_imm_c(DCOND_HI, sr, T);
2038 EMITH_SJMP_END(DCOND_LS);
2040 case 0x07: // CMP/GT
2041 EMITH_SJMP_START(DCOND_LE);
2042 emith_or_r_imm_c(DCOND_GT, sr, T);
2043 EMITH_SJMP_END(DCOND_LE);
2047 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
2048 // Q1 = carry(Rn = (Rn << 1) | T)
2050 // Q2 = carry(Rn += Rm)
2052 // Q2 = carry(Rn -= Rm)
2054 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
2055 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2056 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2057 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2058 emith_tpop_carry(sr, 0);
2059 emith_adcf_r_r(tmp2, tmp2);
2060 emith_tpush_carry(sr, 0); // keep Q1 in T for now
2061 tmp4 = rcache_get_tmp();
2062 emith_and_r_r_imm(tmp4, sr, M);
2063 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
2064 rcache_free_tmp(tmp4);
2065 // add or sub, invert T if carry to get Q1 ^ Q2
2066 // in: (Q ^ M) passed in Q, Q1 in T
2067 emith_sh2_div1_step(tmp2, tmp3, sr);
2068 emith_bic_r_imm(sr, Q);
2069 emith_tst_r_imm(sr, M);
2070 EMITH_SJMP_START(DCOND_EQ);
2071 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
2072 EMITH_SJMP_END(DCOND_EQ);
2073 emith_tst_r_imm(sr, T);
2074 EMITH_SJMP_START(DCOND_EQ);
2075 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
2076 EMITH_SJMP_END(DCOND_EQ);
2077 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
2079 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
2080 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2081 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2082 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
2083 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
2084 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
2086 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
2087 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
2088 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2089 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2091 emith_add_r_r(tmp, tmp2);
2093 emith_sub_r_r(tmp, tmp2);
2095 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
2096 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
2097 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2098 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2099 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2100 if (op & 4) { // adc
2101 emith_tpop_carry(sr, 0);
2102 emith_adcf_r_r(tmp, tmp2);
2103 emith_tpush_carry(sr, 0);
2105 emith_tpop_carry(sr, 1);
2106 emith_sbcf_r_r(tmp, tmp2);
2107 emith_tpush_carry(sr, 1);
2110 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
2111 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
2112 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2113 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2114 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2115 emith_bic_r_imm(sr, T);
2117 emith_addf_r_r(tmp, tmp2);
2119 emith_subf_r_r(tmp, tmp2);
2120 EMITH_SJMP_START(DCOND_VC);
2121 emith_or_r_imm_c(DCOND_VS, sr, T);
2122 EMITH_SJMP_END(DCOND_VC);
2124 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
2125 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2126 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2127 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
2128 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
2129 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
2134 /////////////////////////////////////////////
2141 case 0: // SHLL Rn 0100nnnn00000000
2142 case 2: // SHAL Rn 0100nnnn00100000
2143 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2144 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2145 emith_tpop_carry(sr, 0); // dummy
2146 emith_lslf(tmp, tmp, 1);
2147 emith_tpush_carry(sr, 0);
2149 case 1: // DT Rn 0100nnnn00010000
2150 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2151 #if 0 // scheduling needs tuning
2152 if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
2153 if (gconst_get(GET_Rn(), &tmp)) {
2154 // XXX: limit burned cycles
2155 emit_move_r_imm32(GET_Rn(), 0);
2156 emith_or_r_imm(sr, T);
2157 cycles += tmp * 4 + 1; // +1 syncs with noconst version, not sure why
2161 emith_sh2_dtbf_loop();
2165 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2166 emith_bic_r_imm(sr, T);
2167 emith_subf_r_imm(tmp, 1);
2168 emit_or_t_if_eq(sr);
2175 case 0: // SHLR Rn 0100nnnn00000001
2176 case 2: // SHAR Rn 0100nnnn00100001
2177 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2178 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2179 emith_tpop_carry(sr, 0); // dummy
2181 emith_asrf(tmp, tmp, 1);
2183 emith_lsrf(tmp, tmp, 1);
2184 emith_tpush_carry(sr, 0);
2186 case 1: // CMP/PZ Rn 0100nnnn00010001
2187 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2188 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2189 emith_bic_r_imm(sr, T);
2190 emith_cmp_r_imm(tmp, 0);
2191 EMITH_SJMP_START(DCOND_LT);
2192 emith_or_r_imm_c(DCOND_GE, sr, T);
2193 EMITH_SJMP_END(DCOND_LT);
2201 case 0x02: // STS.L MACH,@-Rn 0100nnnn00000010
2204 case 0x12: // STS.L MACL,@-Rn 0100nnnn00010010
2207 case 0x22: // STS.L PR,@-Rn 0100nnnn00100010
2210 case 0x03: // STC.L SR,@-Rn 0100nnnn00000011
2213 case 0x13: // STC.L GBR,@-Rn 0100nnnn00010011
2216 case 0x23: // STC.L VBR,@-Rn 0100nnnn00100011
2222 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2223 emith_sub_r_imm(tmp2, 4);
2225 rcache_get_reg_arg(0, GET_Rn());
2226 tmp3 = rcache_get_reg_arg(1, tmp);
2228 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
2229 emit_memhandler_write(2);
2235 case 0x04: // ROTL Rn 0100nnnn00000100
2236 case 0x05: // ROTR Rn 0100nnnn00000101
2237 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2238 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2239 emith_tpop_carry(sr, 0); // dummy
2241 emith_rorf(tmp, tmp, 1);
2243 emith_rolf(tmp, tmp, 1);
2244 emith_tpush_carry(sr, 0);
2246 case 0x24: // ROTCL Rn 0100nnnn00100100
2247 case 0x25: // ROTCR Rn 0100nnnn00100101
2248 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2249 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2250 emith_tpop_carry(sr, 0);
2255 emith_tpush_carry(sr, 0);
2257 case 0x15: // CMP/PL Rn 0100nnnn00010101
2258 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2259 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2260 emith_bic_r_imm(sr, T);
2261 emith_cmp_r_imm(tmp, 0);
2262 EMITH_SJMP_START(DCOND_LE);
2263 emith_or_r_imm_c(DCOND_GT, sr, T);
2264 EMITH_SJMP_END(DCOND_LE);
2272 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
2275 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
2278 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
2281 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
2284 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
2287 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
2293 rcache_get_reg_arg(0, GET_Rn());
2294 tmp2 = emit_memhandler_read(2);
2295 if (tmp == SHR_SR) {
2296 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2297 emith_write_sr(sr, tmp2);
2300 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
2301 emith_move_r_r(tmp, tmp2);
2303 rcache_free_tmp(tmp2);
2304 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2305 emith_add_r_imm(tmp, 4);
2312 // SHLL2 Rn 0100nnnn00001000
2313 // SHLR2 Rn 0100nnnn00001001
2317 // SHLL8 Rn 0100nnnn00011000
2318 // SHLR8 Rn 0100nnnn00011001
2322 // SHLL16 Rn 0100nnnn00101000
2323 // SHLR16 Rn 0100nnnn00101001
2329 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2331 emith_lsr(tmp2, tmp2, tmp);
2333 emith_lsl(tmp2, tmp2, tmp);
2338 case 0: // LDS Rm,MACH 0100mmmm00001010
2341 case 1: // LDS Rm,MACL 0100mmmm00011010
2344 case 2: // LDS Rm,PR 0100mmmm00101010
2350 emit_move_r_r(tmp2, GET_Rn());
2355 case 1: // TAS.B @Rn 0100nnnn00011011
2356 // XXX: is TAS working on 32X?
2357 rcache_get_reg_arg(0, GET_Rn());
2358 tmp = emit_memhandler_read(0);
2359 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2360 emith_bic_r_imm(sr, T);
2361 emith_cmp_r_imm(tmp, 0);
2362 emit_or_t_if_eq(sr);
2364 emith_or_r_imm(tmp, 0x80);
2365 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
2366 emith_move_r_r(tmp2, tmp);
2367 rcache_free_tmp(tmp);
2368 rcache_get_reg_arg(0, GET_Rn());
2369 emit_memhandler_write(0);
2376 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2379 case 0: // LDC Rm,SR 0100mmmm00001110
2382 case 1: // LDC Rm,GBR 0100mmmm00011110
2385 case 2: // LDC Rm,VBR 0100mmmm00101110
2391 if (tmp2 == SHR_SR) {
2392 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2393 emith_write_sr(sr, tmp);
2396 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
2397 emith_move_r_r(tmp2, tmp);
2401 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
2402 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
2403 emith_sext(tmp, tmp, 16);
2404 emith_sext(tmp2, tmp2, 16);
2405 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
2406 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
2407 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
2408 rcache_free_tmp(tmp2);
2409 // XXX: MACH should be untouched when S is set?
2410 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2411 emith_tst_r_imm(sr, S);
2412 EMITH_JMP_START(DCOND_EQ);
2414 emith_asr(tmp, tmp3, 31);
2415 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
2416 EMITH_JMP_START(DCOND_EQ);
2417 emith_move_r_imm(tmp3, 0x80000000);
2418 emith_tst_r_r(tmp4, tmp4);
2419 EMITH_SJMP_START(DCOND_MI);
2420 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
2421 EMITH_SJMP_END(DCOND_MI);
2422 EMITH_JMP_END(DCOND_EQ);
2424 EMITH_JMP_END(DCOND_EQ);
2425 rcache_free_tmp(tmp);
2430 /////////////////////////////////////////////
2432 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
2433 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2);
2436 /////////////////////////////////////////////
2440 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
2441 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
2442 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
2443 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
2444 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
2445 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
2446 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), 0, op & 3);
2447 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
2448 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
2449 emith_add_r_imm(tmp, (1 << (op & 3)));
2454 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
2455 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2458 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
2459 emith_move_r_r(tmp2, tmp);
2461 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
2462 emith_mvn_r_r(tmp2, tmp);
2464 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
2467 tmp3 = rcache_get_tmp();
2468 tmp4 = rcache_get_tmp();
2469 emith_lsr(tmp3, tmp, 16);
2470 emith_or_r_r_lsl(tmp3, tmp, 24);
2471 emith_and_r_r_imm(tmp4, tmp, 0xff00);
2472 emith_or_r_r_lsl(tmp3, tmp4, 8);
2473 emith_rol(tmp2, tmp3, 16);
2474 rcache_free_tmp(tmp4);
2476 rcache_free_tmp(tmp3);
2478 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
2479 emith_rol(tmp2, tmp, 16);
2481 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
2482 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2483 emith_tpop_carry(sr, 1);
2484 emith_negcf_r_r(tmp2, tmp);
2485 emith_tpush_carry(sr, 1);
2487 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
2488 emith_neg_r_r(tmp2, tmp);
2490 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
2491 emith_clear_msb(tmp2, tmp, 24);
2493 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
2494 emith_clear_msb(tmp2, tmp, 16);
2496 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
2497 emith_sext(tmp2, tmp, 8);
2499 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
2500 emith_sext(tmp2, tmp, 16);
2507 /////////////////////////////////////////////
2509 // ADD #imm,Rn 0111nnnniiiiiiii
2510 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2511 if (op & 0x80) { // adding negative
2512 emith_sub_r_imm(tmp, -op & 0xff);
2514 emith_add_r_imm(tmp, op & 0xff);
2517 /////////////////////////////////////////////
2519 switch (op & 0x0f00)
2521 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
2522 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
2524 tmp = rcache_get_reg_arg(0, GET_Rm());
2525 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2526 tmp3 = (op & 0x100) >> 8;
2528 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
2529 emit_memhandler_write(tmp3);
2531 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
2532 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
2533 tmp = (op & 0x100) >> 8;
2534 emit_memhandler_read_rr(SHR_R0, GET_Rm(), (op & 0x0f) << tmp, tmp);
2536 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
2537 // XXX: could use cmn
2538 tmp = rcache_get_tmp();
2539 tmp2 = rcache_get_reg(0, RC_GR_READ);
2540 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2541 emith_move_r_imm_s8(tmp, op & 0xff);
2542 emith_bic_r_imm(sr, T);
2543 emith_cmp_r_r(tmp2, tmp);
2544 emit_or_t_if_eq(sr);
2545 rcache_free_tmp(tmp);
2550 /////////////////////////////////////////////
2552 switch (op & 0x0f00)
2554 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
2555 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
2556 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
2558 tmp = rcache_get_reg_arg(0, SHR_GBR);
2559 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2560 tmp3 = (op & 0x300) >> 8;
2561 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
2562 emit_memhandler_write(tmp3);
2564 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
2565 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
2566 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
2567 tmp = (op & 0x300) >> 8;
2568 emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp);
2570 case 0x0300: // TRAPA #imm 11000011iiiiiiii
2571 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2572 emith_sub_r_imm(tmp, 4*2);
2574 tmp = rcache_get_reg_arg(0, SHR_SP);
2575 emith_add_r_imm(tmp, 4);
2576 tmp = rcache_get_reg_arg(1, SHR_SR);
2577 emith_clear_msb(tmp, tmp, 22);
2578 emit_memhandler_write(2);
2580 rcache_get_reg_arg(0, SHR_SP);
2581 tmp = rcache_get_tmp_arg(1);
2582 emith_move_r_imm(tmp, pc);
2583 emit_memhandler_write(2);
2585 emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
2586 // indirect jump -> back to dispatcher
2588 emith_jump(sh2_drc_dispatcher);
2590 case 0x0800: // TST #imm,R0 11001000iiiiiiii
2591 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
2592 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2593 emith_bic_r_imm(sr, T);
2594 emith_tst_r_imm(tmp, op & 0xff);
2595 emit_or_t_if_eq(sr);
2597 case 0x0900: // AND #imm,R0 11001001iiiiiiii
2598 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2599 emith_and_r_imm(tmp, op & 0xff);
2601 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
2602 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2603 emith_eor_r_imm(tmp, op & 0xff);
2605 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
2606 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2607 emith_or_r_imm(tmp, op & 0xff);
2609 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
2610 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2611 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2612 emith_bic_r_imm(sr, T);
2613 emith_tst_r_imm(tmp, op & 0xff);
2614 emit_or_t_if_eq(sr);
2615 rcache_free_tmp(tmp);
2617 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2618 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2619 emith_and_r_imm(tmp, op & 0xff);
2621 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2622 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2623 emith_eor_r_imm(tmp, op & 0xff);
2625 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2626 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2627 emith_or_r_imm(tmp, op & 0xff);
2629 tmp2 = rcache_get_tmp_arg(1);
2630 emith_move_r_r(tmp2, tmp);
2631 rcache_free_tmp(tmp);
2632 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2633 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2634 emith_add_r_r(tmp3, tmp4);
2635 emit_memhandler_write(0);
2640 /////////////////////////////////////////////
2642 // MOV #imm,Rn 1110nnnniiiiiiii
2643 emit_move_r_imm32(GET_Rn(), (u32)(signed int)(signed char)op);
2648 if (!(op_flags[i] & OF_B_IN_DS))
2649 elprintf_sh2(sh2, EL_ANOMALY,
2650 "drc: illegal op %04x @ %08x", op, pc - 2);
2652 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2653 emith_sub_r_imm(tmp, 4*2);
2655 tmp = rcache_get_reg_arg(0, SHR_SP);
2656 emith_add_r_imm(tmp, 4);
2657 tmp = rcache_get_reg_arg(1, SHR_SR);
2658 emith_clear_msb(tmp, tmp, 22);
2659 emit_memhandler_write(2);
2661 rcache_get_reg_arg(0, SHR_SP);
2662 tmp = rcache_get_tmp_arg(1);
2663 if (drcf.pending_branch_indirect) {
2664 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
2665 emith_move_r_r(tmp, tmp2);
2668 emith_move_r_imm(tmp, pc - 2);
2669 emit_memhandler_write(2);
2671 v = (op_flags[i] & OF_B_IN_DS) ? 6 : 4;
2672 emit_memhandler_read_rr(SHR_PC, SHR_VBR, v * 4, 2);
2673 // indirect jump -> back to dispatcher
2675 emith_jump(sh2_drc_dispatcher);
2680 rcache_unlock_all();
2682 cycles += opd->cycles;
2684 if (op_flags[i+1] & OF_DELAY_OP) {
2685 do_host_disasm(tcache_id);
2690 if (drcf.test_irq && !drcf.pending_branch_direct) {
2691 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2693 if (!drcf.pending_branch_indirect)
2694 emit_move_r_imm32(SHR_PC, pc);
2696 emith_call(sh2_drc_test_irq);
2700 // branch handling (with/without delay)
2701 if (drcf.pending_branch_direct)
2703 struct op_data *opd_b =
2704 (op_flags[i] & OF_DELAY_OP) ? &ops[i-1] : opd;
2705 u32 target_pc = opd_b->imm;
2707 void *target = NULL;
2709 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2712 if (opd_b->op != OP_BRANCH)
2713 cond = (opd_b->op == OP_BRANCH_CF) ? DCOND_EQ : DCOND_NE;
2715 int ctaken = (op_flags[i] & OF_DELAY_OP) ? 1 : 2;
2717 if (delay_dep_fw & BITMASK1(SHR_T))
2718 emith_tst_r_imm(sr, T_save);
2720 emith_tst_r_imm(sr, T);
2722 emith_sub_r_imm_c(cond, sr, ctaken<<12);
2727 if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0)
2730 // XXX: jumps back can be linked already
2731 if (branch_patch_count < MAX_LOCAL_BRANCHES) {
2732 target = tcache_ptr;
2733 branch_patch_pc[branch_patch_count] = target_pc;
2734 branch_patch_ptr[branch_patch_count] = target;
2735 branch_patch_count++;
2738 dbg(1, "warning: too many local branches");
2744 // can't resolve branch locally, make a block exit
2745 emit_move_r_imm32(SHR_PC, target_pc);
2748 target = dr_prepare_ext_branch(target_pc, sh2->is_slave, tcache_id);
2754 emith_jump_cond_patchable(cond, target);
2756 emith_jump_patchable(target);
2757 rcache_invalidate();
2760 drcf.pending_branch_direct = 0;
2762 else if (drcf.pending_branch_indirect) {
2763 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2766 emith_jump(sh2_drc_dispatcher);
2767 drcf.pending_branch_indirect = 0;
2770 do_host_disasm(tcache_id);
2773 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2777 // check the last op
2778 if (op_flags[i-1] & OF_DELAY_OP)
2783 if (opd->op != OP_BRANCH && opd->op != OP_BRANCH_R
2784 && opd->op != OP_BRANCH_RF && opd->op != OP_RTE)
2788 emit_move_r_imm32(SHR_PC, pc);
2791 target = dr_prepare_ext_branch(pc, sh2->is_slave, tcache_id);
2794 emith_jump_patchable(target);
2797 // link local branches
2798 for (i = 0; i < branch_patch_count; i++) {
2801 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2802 target = branch_target_ptr[t];
2803 if (target == NULL) {
2804 // flush pc and go back to dispatcher (this should no longer happen)
2805 dbg(1, "stray branch to %08x %p", branch_patch_pc[i], tcache_ptr);
2806 target = tcache_ptr;
2807 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2809 emith_jump(sh2_drc_dispatcher);
2811 emith_jump_patch(branch_patch_ptr[i], target);
2814 // mark memory blocks as containing compiled code
2815 // override any overlay blocks as they become unreachable anyway
2816 if ((block->addr & 0xc7fc0000) == 0x06000000
2817 || (block->addr & 0xfffff000) == 0xc0000000)
2819 u16 *drc_ram_blk = NULL;
2820 u32 addr, mask = 0, shift = 0;
2822 if (tcache_id != 0) {
2824 drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave];
2825 shift = SH2_DRCBLK_DA_SHIFT;
2830 drc_ram_blk = Pico32xMem->drcblk_ram;
2831 shift = SH2_DRCBLK_RAM_SHIFT;
2835 // mark recompiled insns
2836 drc_ram_blk[(base_pc & mask) >> shift] = 1;
2837 for (pc = base_pc; pc < end_pc; pc += 2)
2838 drc_ram_blk[(pc & mask) >> shift] = 1;
2841 for (i = 0; i < literal_addr_count; i++) {
2842 tmp = literal_addr[i];
2843 drc_ram_blk[(tmp & mask) >> shift] = 1;
2846 // add to invalidation lookup lists
2847 addr = base_pc & ~(INVAL_PAGE_SIZE - 1);
2848 for (; addr < end_literals; addr += INVAL_PAGE_SIZE) {
2849 i = (addr & mask) / INVAL_PAGE_SIZE;
2850 add_to_block_list(&inval_lookup[tcache_id][i], block);
2854 tcache_ptrs[tcache_id] = tcache_ptr;
2856 host_instructions_updated(block_entry_ptr, tcache_ptr);
2858 do_host_disasm(tcache_id);
2860 if (drcf.literals_disabled && literal_addr_count)
2861 dbg(1, "literals_disabled && literal_addr_count?");
2862 dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2863 tcache_id, blkid_main,
2864 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2865 insns_compiled, host_insn_count, (float)host_insn_count / insns_compiled);
2866 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2867 dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2870 tcache_dsm_ptrs[tcache_id] = block_entry_ptr;
2871 do_host_disasm(tcache_id);
2879 return block_entry_ptr;
2882 static void sh2_generate_utils(void)
2884 int arg0, arg1, arg2, sr, tmp;
2886 sh2_drc_write32 = p32x_sh2_write32;
2887 sh2_drc_read8 = p32x_sh2_read8;
2888 sh2_drc_read16 = p32x_sh2_read16;
2889 sh2_drc_read32 = p32x_sh2_read32;
2891 host_arg2reg(arg0, 0);
2892 host_arg2reg(arg1, 1);
2893 host_arg2reg(arg2, 2);
2894 emith_move_r_r(arg0, arg0); // nop
2896 // sh2_drc_exit(void)
2897 sh2_drc_exit = (void *)tcache_ptr;
2898 emit_do_static_regs(1, arg2);
2899 emith_sh2_drc_exit();
2901 // sh2_drc_dispatcher(void)
2902 sh2_drc_dispatcher = (void *)tcache_ptr;
2903 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2904 emith_cmp_r_imm(sr, 0);
2905 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2906 rcache_invalidate();
2907 emith_ctx_read(arg0, SHR_PC * 4);
2908 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2909 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2910 emith_call(dr_lookup_block);
2912 // lookup failed, call sh2_translate()
2913 emith_move_r_r(arg0, CONTEXT_REG);
2914 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2915 emith_call(sh2_translate);
2917 // sh2_translate() failed, flush cache and retry
2918 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2919 emith_call(flush_tcache);
2920 emith_move_r_r(arg0, CONTEXT_REG);
2921 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2922 emith_call(sh2_translate);
2924 // XXX: can't translate, fail
2925 emith_call(dr_failure);
2927 // sh2_drc_test_irq(void)
2928 // assumes it's called from main function (may jump to dispatcher)
2929 sh2_drc_test_irq = (void *)tcache_ptr;
2930 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2931 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2932 emith_lsr(arg0, sr, I_SHIFT);
2933 emith_and_r_imm(arg0, 0x0f);
2934 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2935 EMITH_SJMP_START(DCOND_GT);
2936 emith_ret_c(DCOND_LE); // nope, return
2937 EMITH_SJMP_END(DCOND_GT);
2939 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2940 emith_sub_r_imm(tmp, 4*2);
2943 tmp = rcache_get_reg_arg(0, SHR_SP);
2944 emith_add_r_imm(tmp, 4);
2945 tmp = rcache_get_reg_arg(1, SHR_SR);
2946 emith_clear_msb(tmp, tmp, 22);
2947 emith_move_r_r(arg2, CONTEXT_REG);
2948 emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
2949 rcache_invalidate();
2951 rcache_get_reg_arg(0, SHR_SP);
2952 emith_ctx_read(arg1, SHR_PC * 4);
2953 emith_move_r_r(arg2, CONTEXT_REG);
2954 emith_call(p32x_sh2_write32);
2955 rcache_invalidate();
2956 // update I, cycles, do callback
2957 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2958 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2959 emith_bic_r_imm(sr, I);
2960 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2961 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2963 emith_move_r_r(arg0, CONTEXT_REG);
2964 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2966 emith_lsl(arg0, arg0, 2);
2967 emith_ctx_read(arg1, SHR_VBR * 4);
2968 emith_add_r_r(arg0, arg1);
2969 emit_memhandler_read(2);
2970 emith_ctx_write(arg0, SHR_PC * 4);
2972 emith_add_r_imm(xSP, 4); // fix stack
2974 emith_jump(sh2_drc_dispatcher);
2975 rcache_invalidate();
2977 // sh2_drc_entry(SH2 *sh2)
2978 sh2_drc_entry = (void *)tcache_ptr;
2979 emith_sh2_drc_entry();
2980 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2981 emit_do_static_regs(0, arg2);
2982 emith_call(sh2_drc_test_irq);
2983 emith_jump(sh2_drc_dispatcher);
2985 // sh2_drc_write8(u32 a, u32 d)
2986 sh2_drc_write8 = (void *)tcache_ptr;
2987 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2988 emith_sh2_wcall(arg0, arg2);
2990 // sh2_drc_write16(u32 a, u32 d)
2991 sh2_drc_write16 = (void *)tcache_ptr;
2992 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2993 emith_sh2_wcall(arg0, arg2);
2997 #define MAKE_READ_WRAPPER(func) { \
2998 void *tmp = (void *)tcache_ptr; \
3001 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
3002 emith_addf_r_r(arg2, arg0); \
3003 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
3004 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
3005 emith_adc_r_imm(arg2, 0x01000000); \
3006 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
3007 emith_pop_and_ret(); \
3010 #define MAKE_WRITE_WRAPPER(func) { \
3011 void *tmp = (void *)tcache_ptr; \
3012 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
3013 emith_addf_r_r(arg2, arg1); \
3014 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
3015 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
3016 emith_adc_r_imm(arg2, 0x01000000); \
3017 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
3018 emith_move_r_r(arg2, CONTEXT_REG); \
3023 MAKE_READ_WRAPPER(sh2_drc_read8);
3024 MAKE_READ_WRAPPER(sh2_drc_read16);
3025 MAKE_READ_WRAPPER(sh2_drc_read32);
3026 MAKE_WRITE_WRAPPER(sh2_drc_write8);
3027 MAKE_WRITE_WRAPPER(sh2_drc_write16);
3028 MAKE_WRITE_WRAPPER(sh2_drc_write32);
3030 host_dasm_new_symbol(sh2_drc_read8);
3031 host_dasm_new_symbol(sh2_drc_read16);
3032 host_dasm_new_symbol(sh2_drc_read32);
3033 host_dasm_new_symbol(sh2_drc_write32);
3037 rcache_invalidate();
3039 host_dasm_new_symbol(sh2_drc_entry);
3040 host_dasm_new_symbol(sh2_drc_dispatcher);
3041 host_dasm_new_symbol(sh2_drc_exit);
3042 host_dasm_new_symbol(sh2_drc_test_irq);
3043 host_dasm_new_symbol(sh2_drc_write8);
3044 host_dasm_new_symbol(sh2_drc_write16);
3048 static void sh2_smc_rm_block(struct block_desc *bd, int tcache_id, u32 ram_mask)
3050 u32 i, addr, end_addr;
3053 dbg(2, " killing block %08x-%08x-%08x, blkid %d,%d",
3054 bd->addr, bd->addr + bd->size_nolit, bd->addr + bd->size,
3055 tcache_id, bd - block_tables[tcache_id]);
3056 if (bd->addr == 0 || bd->entry_count == 0) {
3057 dbg(1, " killing dead block!? %08x", bd->addr);
3061 // remove from inval_lookup
3062 addr = bd->addr & ~(INVAL_PAGE_SIZE - 1);
3063 end_addr = bd->addr + bd->size;
3064 for (; addr < end_addr; addr += INVAL_PAGE_SIZE) {
3065 i = (addr & ram_mask) / INVAL_PAGE_SIZE;
3066 rm_from_block_list(&inval_lookup[tcache_id][i], bd);
3071 // remove from hash table, make incoming links unresolved
3072 // XXX: maybe patch branches w/flush instead?
3073 for (i = 0; i < bd->entry_count; i++) {
3074 rm_from_hashlist(&bd->entryp[i], tcache_id);
3076 // since we never reuse tcache space of dead blocks,
3077 // insert jump to dispatcher for blocks that are linked to this
3078 tcache_ptr = bd->entryp[i].tcache_ptr;
3079 emit_move_r_imm32(SHR_PC, bd->entryp[i].pc);
3081 emith_jump(sh2_drc_dispatcher);
3083 host_instructions_updated(bd->entryp[i].tcache_ptr, tcache_ptr);
3085 unregister_links(&bd->entryp[i], tcache_id);
3090 bd->addr = bd->size = bd->size_nolit = 0;
3091 bd->entry_count = 0;
3095 04205:243: == msh2 block #0,200 060017a8-060017f0 -> 0x27cb9c
3096 060017a8 d11c MOV.L @($70,PC),R1 ; @$0600181c
3098 04230:261: msh2 xsh w32 [260017a8] d225e304
3099 04230:261: msh2 smc check @260017a8
3100 04239:226: = ssh2 enter 060017a8 0x27cb9c, c=173
3102 static void sh2_smc_rm_blocks(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask)
3104 struct block_list **blist = NULL, *entry;
3105 struct block_desc *block;
3106 u32 start_addr, end_addr, taddr, i;
3107 u32 from = ~0, to = 0;
3109 // ignore cache-through
3112 blist = &inval_lookup[tcache_id][(a & mask) / INVAL_PAGE_SIZE];
3114 while (entry != NULL) {
3115 block = entry->block;
3116 start_addr = block->addr & ~0x20000000;
3117 end_addr = start_addr + block->size;
3118 if (start_addr <= a && a < end_addr) {
3119 // get addr range that includes all removed blocks
3120 if (from > start_addr)
3125 if (a >= start_addr + block->size_nolit)
3126 literal_disabled_frames = 3;
3127 sh2_smc_rm_block(block, tcache_id, mask);
3129 // entry lost, restart search
3133 entry = entry->next;
3139 // update range around a to match latest state
3140 from &= ~(INVAL_PAGE_SIZE - 1);
3141 to |= (INVAL_PAGE_SIZE - 1);
3142 for (taddr = from; taddr < to; taddr += INVAL_PAGE_SIZE) {
3143 i = (taddr & mask) / INVAL_PAGE_SIZE;
3144 entry = inval_lookup[tcache_id][i];
3146 for (; entry != NULL; entry = entry->next) {
3147 block = entry->block;
3149 start_addr = block->addr & ~0x20000000;
3150 if (start_addr > a) {
3151 if (to > start_addr)
3155 end_addr = start_addr + block->size;
3156 if (from < end_addr)
3164 u16 *p = drc_ram_blk + ((from & mask) >> shift);
3165 memset(p, 0, (to - from) >> (shift - 1));
3169 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
3171 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3172 sh2_smc_rm_blocks(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
3175 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
3177 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3178 sh2_smc_rm_blocks(a, Pico32xMem->drcblk_da[cpuid],
3179 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
3182 int sh2_execute_drc(SH2 *sh2c, int cycles)
3186 // cycles are kept in SHR_SR unused bits (upper 20)
3187 // bit11 contains T saved for delay slot
3188 // others are usual SH2 flags
3190 sh2c->sr |= cycles << 12;
3191 sh2_drc_entry(sh2c);
3194 ret_cycles = (signed int)sh2c->sr >> 12;
3196 dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
3203 void block_stats(void)
3205 int c, b, i, total = 0;
3207 printf("block stats:\n");
3208 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3209 for (i = 0; i < block_counts[b]; i++)
3210 if (block_tables[b][i].addr != 0)
3211 total += block_tables[b][i].refcount;
3213 for (c = 0; c < 10; c++) {
3214 struct block_desc *blk, *maxb = NULL;
3216 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
3217 for (i = 0; i < block_counts[b]; i++) {
3218 blk = &block_tables[b][i];
3219 if (blk->addr != 0 && blk->refcount > max) {
3220 max = blk->refcount;
3227 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
3228 (double)maxb->refcount / total * 100.0);
3232 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3233 for (i = 0; i < block_counts[b]; i++)
3234 block_tables[b][i].refcount = 0;
3237 #define block_stats()
3240 void sh2_drc_flush_all(void)
3248 void sh2_drc_mem_setup(SH2 *sh2)
3250 // fill the convenience pointers
3251 sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w;
3252 sh2->p_da = sh2->data_array;
3253 sh2->p_sdram = Pico32xMem->sdram;
3254 sh2->p_rom = Pico.rom;
3257 void sh2_drc_frame(void)
3259 if (literal_disabled_frames > 0)
3260 literal_disabled_frames--;
3263 int sh2_drc_init(SH2 *sh2)
3267 if (block_tables[0] == NULL)
3269 for (i = 0; i < TCACHE_BUFFERS; i++) {
3270 block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0]));
3271 if (block_tables[i] == NULL)
3273 // max 2 block links (exits) per block
3274 block_link_pool[i] = calloc(block_link_pool_max_counts[i],
3275 sizeof(*block_link_pool[0]));
3276 if (block_link_pool[i] == NULL)
3279 inval_lookup[i] = calloc(ram_sizes[i] / INVAL_PAGE_SIZE,
3280 sizeof(inval_lookup[0]));
3281 if (inval_lookup[i] == NULL)
3284 hash_tables[i] = calloc(hash_table_sizes[i], sizeof(*hash_tables[0]));
3285 if (hash_tables[i] == NULL)
3288 memset(block_counts, 0, sizeof(block_counts));
3289 memset(block_link_pool_counts, 0, sizeof(block_link_pool_counts));
3292 tcache_ptr = tcache;
3293 sh2_generate_utils();
3294 host_instructions_updated(tcache, tcache_ptr);
3296 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
3297 for (i = 1; i < ARRAY_SIZE(tcache_bases); i++)
3298 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
3301 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
3302 tcache_dsm_ptrs[i] = tcache_bases[i];
3304 tcache_dsm_ptrs[0] = tcache;
3308 hash_collisions = 0;
3315 sh2_drc_finish(sh2);
3319 void sh2_drc_finish(SH2 *sh2)
3323 if (block_tables[0] == NULL)
3326 sh2_drc_flush_all();
3328 for (i = 0; i < TCACHE_BUFFERS; i++) {
3330 printf("~~~ tcache %d\n", i);
3331 tcache_dsm_ptrs[i] = tcache_bases[i];
3332 tcache_ptr = tcache_ptrs[i];
3336 if (block_tables[i] != NULL)
3337 free(block_tables[i]);
3338 block_tables[i] = NULL;
3339 if (block_link_pool[i] == NULL)
3340 free(block_link_pool[i]);
3341 block_link_pool[i] = NULL;
3343 if (inval_lookup[i] == NULL)
3344 free(inval_lookup[i]);
3345 inval_lookup[i] = NULL;
3347 if (hash_tables[i] != NULL) {
3348 free(hash_tables[i]);
3349 hash_tables[i] = NULL;
3356 #endif /* DRC_SH2 */
3358 static void *dr_get_pc_base(u32 pc, int is_slave)
3363 if ((pc & ~0x7ff) == 0) {
3365 ret = is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w;
3368 else if ((pc & 0xfffff000) == 0xc0000000) {
3370 ret = sh2s[is_slave].data_array;
3373 else if ((pc & 0xc6000000) == 0x06000000) {
3375 ret = Pico32xMem->sdram;
3378 else if ((pc & 0xc6000000) == 0x02000000) {
3380 if ((pc & 0x3fffff) < Pico.romsize)
3386 return (void *)-1; // NULL is valid value
3388 return (char *)ret - (pc & ~mask);
3391 void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
3392 u32 *end_literals_out)
3396 u32 end_pc, end_literals = 0;
3397 u32 lowest_mova = 0;
3398 struct op_data *opd;
3399 int next_is_delay = 0;
3403 memset(op_flags, 0, BLOCK_INSN_LIMIT);
3405 dr_pc_base = dr_get_pc_base(base_pc, is_slave);
3407 // 1st pass: disassemble
3408 for (i = 0, pc = base_pc; ; i++, pc += 2) {
3409 // we need an ops[] entry after the last one initialized,
3410 // so do it before end_block checks
3412 opd->op = OP_UNHANDLED;
3414 opd->source = opd->dest = 0;
3418 if (next_is_delay) {
3419 op_flags[i] |= OF_DELAY_OP;
3422 else if (end_block || i >= BLOCK_INSN_LIMIT - 2)
3426 switch ((op & 0xf000) >> 12)
3428 /////////////////////////////////////////////
3435 case 0: // STC SR,Rn 0000nnnn00000010
3438 case 1: // STC GBR,Rn 0000nnnn00010010
3441 case 2: // STC VBR,Rn 0000nnnn00100010
3448 opd->source = BITMASK1(tmp);
3449 opd->dest = BITMASK1(GET_Rn());
3452 CHECK_UNHANDLED_BITS(0xd0, undefined);
3453 // BRAF Rm 0000mmmm00100011
3454 // BSRF Rm 0000mmmm00000011
3455 opd->op = OP_BRANCH_RF;
3457 opd->source = BITMASK1(opd->rm);
3458 opd->dest = BITMASK1(SHR_PC);
3460 opd->dest |= BITMASK1(SHR_PR);
3465 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
3466 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
3467 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
3468 opd->source = BITMASK3(GET_Rm(), SHR_R0, GET_Rn());
3471 // MUL.L Rm,Rn 0000nnnnmmmm0111
3472 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3473 opd->dest = BITMASK1(SHR_MACL);
3477 CHECK_UNHANDLED_BITS(0xf00, undefined);
3480 case 0: // CLRT 0000000000001000
3481 opd->op = OP_SETCLRT;
3482 opd->dest = BITMASK1(SHR_T);
3485 case 1: // SETT 0000000000011000
3486 opd->op = OP_SETCLRT;
3487 opd->dest = BITMASK1(SHR_T);
3490 case 2: // CLRMAC 0000000000101000
3491 opd->dest = BITMASK3(SHR_T, SHR_MACL, SHR_MACH);
3500 case 0: // NOP 0000000000001001
3501 CHECK_UNHANDLED_BITS(0xf00, undefined);
3503 case 1: // DIV0U 0000000000011001
3504 CHECK_UNHANDLED_BITS(0xf00, undefined);
3505 opd->dest = BITMASK2(SHR_SR, SHR_T);
3507 case 2: // MOVT Rn 0000nnnn00101001
3508 opd->source = BITMASK1(SHR_T);
3509 opd->dest = BITMASK1(GET_Rn());
3518 case 0: // STS MACH,Rn 0000nnnn00001010
3521 case 1: // STS MACL,Rn 0000nnnn00011010
3524 case 2: // STS PR,Rn 0000nnnn00101010
3531 opd->source = BITMASK1(tmp);
3532 opd->dest = BITMASK1(GET_Rn());
3535 CHECK_UNHANDLED_BITS(0xf00, undefined);
3538 case 0: // RTS 0000000000001011
3539 opd->op = OP_BRANCH_R;
3541 opd->source = BITMASK1(opd->rm);
3542 opd->dest = BITMASK1(SHR_PC);
3547 case 1: // SLEEP 0000000000011011
3551 case 2: // RTE 0000000000101011
3553 opd->source = BITMASK1(SHR_SP);
3554 opd->dest = BITMASK2(SHR_SR, SHR_PC);
3563 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
3564 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
3565 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
3566 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3567 opd->dest = BITMASK1(GET_Rn());
3569 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
3570 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3571 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3579 /////////////////////////////////////////////
3581 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
3582 opd->source = BITMASK1(GET_Rm());
3583 opd->source = BITMASK1(GET_Rn());
3584 opd->imm = (op & 0x0f) * 4;
3587 /////////////////////////////////////////////
3591 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
3592 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
3593 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
3594 opd->source = BITMASK1(GET_Rm());
3595 opd->source = BITMASK1(GET_Rn());
3597 case 0x04: // MOV.B Rm,@-Rn 0010nnnnmmmm0100
3598 case 0x05: // MOV.W Rm,@-Rn 0010nnnnmmmm0101
3599 case 0x06: // MOV.L Rm,@-Rn 0010nnnnmmmm0110
3600 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3601 opd->dest = BITMASK1(GET_Rn());
3603 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
3604 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3605 opd->dest = BITMASK1(SHR_SR);
3607 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
3608 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3609 opd->dest = BITMASK1(SHR_T);
3611 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
3612 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
3613 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
3614 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3615 opd->dest = BITMASK1(GET_Rn());
3617 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
3618 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3619 opd->dest = BITMASK1(SHR_T);
3621 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
3622 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3623 opd->dest = BITMASK1(GET_Rn());
3625 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
3626 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
3627 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3628 opd->dest = BITMASK1(SHR_MACL);
3635 /////////////////////////////////////////////
3639 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
3640 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
3641 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
3642 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
3643 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
3644 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3645 opd->dest = BITMASK1(SHR_T);
3647 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
3648 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_SR);
3649 opd->dest = BITMASK2(GET_Rn(), SHR_SR);
3651 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
3652 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
3653 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3654 opd->dest = BITMASK2(SHR_MACL, SHR_MACH);
3657 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
3658 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
3659 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3660 opd->dest = BITMASK1(GET_Rn());
3662 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
3663 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
3664 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_T);
3665 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3667 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
3668 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
3669 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3670 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3677 /////////////////////////////////////////////
3684 case 0: // SHLL Rn 0100nnnn00000000
3685 case 2: // SHAL Rn 0100nnnn00100000
3686 opd->source = BITMASK1(GET_Rn());
3687 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3689 case 1: // DT Rn 0100nnnn00010000
3690 opd->source = BITMASK1(GET_Rn());
3691 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3700 case 0: // SHLR Rn 0100nnnn00000001
3701 case 2: // SHAR Rn 0100nnnn00100001
3702 opd->source = BITMASK1(GET_Rn());
3703 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3705 case 1: // CMP/PZ Rn 0100nnnn00010001
3706 opd->source = BITMASK1(GET_Rn());
3707 opd->dest = BITMASK1(SHR_T);
3717 case 0x02: // STS.L MACH,@-Rn 0100nnnn00000010
3720 case 0x12: // STS.L MACL,@-Rn 0100nnnn00010010
3723 case 0x22: // STS.L PR,@-Rn 0100nnnn00100010
3726 case 0x03: // STC.L SR,@-Rn 0100nnnn00000011
3730 case 0x13: // STC.L GBR,@-Rn 0100nnnn00010011
3734 case 0x23: // STC.L VBR,@-Rn 0100nnnn00100011
3741 opd->source = BITMASK2(GET_Rn(), tmp);
3742 opd->dest = BITMASK1(GET_Rn());
3748 case 0x04: // ROTL Rn 0100nnnn00000100
3749 case 0x05: // ROTR Rn 0100nnnn00000101
3750 opd->source = BITMASK1(GET_Rn());
3751 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3753 case 0x24: // ROTCL Rn 0100nnnn00100100
3754 case 0x25: // ROTCR Rn 0100nnnn00100101
3755 opd->source = BITMASK2(GET_Rn(), SHR_T);
3756 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3758 case 0x15: // CMP/PL Rn 0100nnnn00010101
3759 opd->source = BITMASK1(GET_Rn());
3760 opd->dest = BITMASK1(SHR_T);
3770 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
3773 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
3776 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
3779 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
3783 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
3787 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
3794 opd->source = BITMASK1(GET_Rn());
3795 opd->dest = BITMASK2(GET_Rn(), tmp);
3802 // SHLL2 Rn 0100nnnn00001000
3803 // SHLR2 Rn 0100nnnn00001001
3806 // SHLL8 Rn 0100nnnn00011000
3807 // SHLR8 Rn 0100nnnn00011001
3810 // SHLL16 Rn 0100nnnn00101000
3811 // SHLR16 Rn 0100nnnn00101001
3816 opd->source = BITMASK1(GET_Rn());
3817 opd->dest = BITMASK1(GET_Rn());
3822 case 0: // LDS Rm,MACH 0100mmmm00001010
3825 case 1: // LDS Rm,MACL 0100mmmm00011010
3828 case 2: // LDS Rm,PR 0100mmmm00101010
3835 opd->source = BITMASK1(GET_Rn());
3836 opd->dest = BITMASK1(tmp);
3841 case 0: // JSR @Rm 0100mmmm00001011
3842 opd->dest = BITMASK1(SHR_PR);
3843 case 2: // JMP @Rm 0100mmmm00101011
3844 opd->op = OP_BRANCH_R;
3846 opd->source = BITMASK1(opd->rm);
3847 opd->dest |= BITMASK1(SHR_PC);
3852 case 1: // TAS.B @Rn 0100nnnn00011011
3853 opd->source = BITMASK1(GET_Rn());
3854 opd->dest = BITMASK1(SHR_T);
3864 case 0: // LDC Rm,SR 0100mmmm00001110
3867 case 1: // LDC Rm,GBR 0100mmmm00011110
3870 case 2: // LDC Rm,VBR 0100mmmm00101110
3877 opd->source = BITMASK1(GET_Rn());
3878 opd->dest = BITMASK1(tmp);
3881 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
3882 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3883 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3891 /////////////////////////////////////////////
3893 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
3894 opd->source = BITMASK1(GET_Rm());
3895 opd->dest = BITMASK1(GET_Rn());
3896 opd->imm = (op & 0x0f) * 4;
3899 /////////////////////////////////////////////
3903 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
3904 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
3905 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
3906 opd->dest = BITMASK1(GET_Rm());
3907 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
3908 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
3909 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
3910 opd->source = BITMASK1(GET_Rm());
3911 opd->dest |= BITMASK1(GET_Rn());
3913 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
3914 opd->source = BITMASK2(GET_Rm(), SHR_T);
3915 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3917 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
3920 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
3921 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
3922 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
3923 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
3924 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
3925 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
3926 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
3927 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
3929 opd->source = BITMASK1(GET_Rm());
3930 opd->dest = BITMASK1(GET_Rn());
3935 /////////////////////////////////////////////
3937 // ADD #imm,Rn 0111nnnniiiiiiii
3938 opd->source = opd->dest = BITMASK1(GET_Rn());
3939 opd->imm = (int)(signed char)op;
3942 /////////////////////////////////////////////
3944 switch (op & 0x0f00)
3946 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
3947 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3948 opd->imm = (op & 0x0f);
3950 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
3951 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3952 opd->imm = (op & 0x0f) * 2;
3954 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
3955 opd->source = BITMASK1(GET_Rm());
3956 opd->dest = BITMASK1(SHR_R0);
3957 opd->imm = (op & 0x0f);
3959 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
3960 opd->source = BITMASK1(GET_Rm());
3961 opd->dest = BITMASK1(SHR_R0);
3962 opd->imm = (op & 0x0f) * 2;
3964 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
3965 opd->source = BITMASK1(SHR_R0);
3966 opd->dest = BITMASK1(SHR_T);
3967 opd->imm = (int)(signed char)op;
3969 case 0x0d00: // BT/S label 10001101dddddddd
3970 case 0x0f00: // BF/S label 10001111dddddddd
3973 case 0x0900: // BT label 10001001dddddddd
3974 case 0x0b00: // BF label 10001011dddddddd
3975 opd->op = (op & 0x0200) ? OP_BRANCH_CF : OP_BRANCH_CT;
3976 opd->source = BITMASK1(SHR_T);
3977 opd->dest = BITMASK1(SHR_PC);
3978 opd->imm = ((signed int)(op << 24) >> 23);
3980 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
3981 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
3988 /////////////////////////////////////////////
3990 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
3991 opd->op = OP_LOAD_POOL;
3993 if (op_flags[i] & OF_DELAY_OP) {
3994 if (ops[i-1].op == OP_BRANCH)
3999 opd->source = BITMASK1(SHR_PC);
4000 opd->dest = BITMASK1(GET_Rn());
4002 opd->imm = tmp + 2 + (op & 0xff) * 2;
4006 /////////////////////////////////////////////
4008 // BSR label 1011dddddddddddd
4009 opd->dest = BITMASK1(SHR_PR);
4011 // BRA label 1010dddddddddddd
4012 opd->op = OP_BRANCH;
4013 opd->dest |= BITMASK1(SHR_PC);
4014 opd->imm = ((signed int)(op << 20) >> 19);
4019 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
4020 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
4023 /////////////////////////////////////////////
4025 switch (op & 0x0f00)
4027 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
4028 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
4029 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
4030 opd->source = BITMASK2(SHR_GBR, SHR_R0);
4031 opd->size = (op & 0x300) >> 8;
4032 opd->imm = (op & 0xff) << opd->size;
4034 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
4035 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
4036 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
4037 opd->source = BITMASK1(SHR_GBR);
4038 opd->dest = BITMASK1(SHR_R0);
4039 opd->size = (op & 0x300) >> 8;
4040 opd->imm = (op & 0xff) << opd->size;
4042 case 0x0300: // TRAPA #imm 11000011iiiiiiii
4043 opd->source = BITMASK2(SHR_PC, SHR_SR);
4044 opd->dest = BITMASK1(SHR_PC);
4045 opd->imm = (op & 0xff) * 4;
4047 end_block = 1; // FIXME
4049 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
4052 if (op_flags[i] & OF_DELAY_OP) {
4053 if (ops[i-1].op == OP_BRANCH)
4058 opd->dest = BITMASK1(SHR_R0);
4060 opd->imm = (tmp + 2 + (op & 0xff) * 4) & ~3;
4061 if (opd->imm >= base_pc) {
4062 if (lowest_mova == 0 || opd->imm < lowest_mova)
4063 lowest_mova = opd->imm;
4067 case 0x0800: // TST #imm,R0 11001000iiiiiiii
4068 opd->source = BITMASK1(SHR_R0);
4069 opd->dest = BITMASK1(SHR_T);
4070 opd->imm = op & 0xff;
4072 case 0x0900: // AND #imm,R0 11001001iiiiiiii
4073 opd->source = opd->dest = BITMASK1(SHR_R0);
4074 opd->imm = op & 0xff;
4076 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
4077 opd->source = opd->dest = BITMASK1(SHR_R0);
4078 opd->imm = op & 0xff;
4080 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
4081 opd->source = opd->dest = BITMASK1(SHR_R0);
4082 opd->imm = op & 0xff;
4084 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
4085 opd->source = BITMASK2(SHR_GBR, SHR_R0);
4086 opd->dest = BITMASK1(SHR_T);
4087 opd->imm = op & 0xff;
4090 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
4091 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
4092 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
4093 opd->source = BITMASK2(SHR_GBR, SHR_R0);
4094 opd->imm = op & 0xff;
4102 /////////////////////////////////////////////
4104 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
4105 opd->op = OP_LOAD_POOL;
4107 if (op_flags[i] & OF_DELAY_OP) {
4108 if (ops[i-1].op == OP_BRANCH)
4113 opd->source = BITMASK1(SHR_PC);
4114 opd->dest = BITMASK1(GET_Rn());
4116 opd->imm = (tmp + 2 + (op & 0xff) * 4) & ~3;
4120 /////////////////////////////////////////////
4122 // MOV #imm,Rn 1110nnnniiiiiiii
4123 opd->dest = BITMASK1(GET_Rn());
4124 opd->imm = (u32)(signed int)(signed char)op;
4129 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
4130 is_slave ? 's' : 'm', op, pc);
4134 if (op_flags[i] & OF_DELAY_OP) {
4141 elprintf(EL_ANOMALY, "%csh2 drc: branch in DS @ %08x",
4142 is_slave ? 's' : 'm', pc);
4143 opd->op = OP_UNHANDLED;
4144 op_flags[i] |= OF_B_IN_DS;
4153 // 2nd pass: some analysis
4154 for (i = 0; i < i_end; i++) {
4157 // propagate T (TODO: DIV0U)
4158 if ((opd->op == OP_SETCLRT && !opd->imm) || opd->op == OP_BRANCH_CT)
4159 op_flags[i + 1] |= OF_T_CLEAR;
4160 else if ((opd->op == OP_SETCLRT && opd->imm) || opd->op == OP_BRANCH_CF)
4161 op_flags[i + 1] |= OF_T_SET;
4163 if ((op_flags[i] & OF_BTARGET) || (opd->dest & BITMASK1(SHR_T)))
4164 op_flags[i] &= ~(OF_T_SET | OF_T_CLEAR);
4166 op_flags[i + 1] |= op_flags[i] & (OF_T_SET | OF_T_CLEAR);
4168 if ((opd->op == OP_BRANCH_CT && (op_flags[i] & OF_T_SET))
4169 || (opd->op == OP_BRANCH_CF && (op_flags[i] & OF_T_CLEAR)))
4171 opd->op = OP_BRANCH;
4174 if (op_flags[i + 1] & OF_DELAY_OP) {
4179 else if (opd->op == OP_LOAD_POOL)
4181 if (opd->imm < end_pc + MAX_LITERAL_OFFSET) {
4182 if (end_literals < opd->imm + opd->size * 2)
4183 end_literals = opd->imm + opd->size * 2;
4187 end_pc = base_pc + i_end * 2;
4188 if (end_literals < end_pc)
4189 end_literals = end_pc;
4191 // end_literals is used to decide to inline a literal or not
4192 // XXX: need better detection if this actually is used in write
4193 if (lowest_mova >= base_pc) {
4194 if (lowest_mova < end_literals) {
4195 dbg(1, "mova for %08x, block %08x", lowest_mova, base_pc);
4196 end_literals = end_pc;
4198 if (lowest_mova < end_pc) {
4199 dbg(1, "warning: mova inside of blk for %08x, block %08x",
4200 lowest_mova, base_pc);
4201 end_literals = end_pc;
4205 *end_pc_out = end_pc;
4206 if (end_literals_out != NULL)
4207 *end_literals_out = end_literals;
4210 // vim:shiftwidth=2:ts=2:expandtab